1 | /* |
---|---|
2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _nbio_7_0_SH_MASK_HEADER |
22 | #define _nbio_7_0_SH_MASK_HEADER |
23 | |
24 | |
25 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
26 | //NB_NBCFG0_NB_VENDOR_ID |
27 | #define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
28 | #define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
29 | //NB_NBCFG0_NB_DEVICE_ID |
30 | #define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
31 | #define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
32 | //NB_NBCFG0_NB_COMMAND |
33 | #define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
34 | #define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
35 | #define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
36 | #define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
37 | #define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
38 | #define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
39 | //NB_NBCFG0_NB_STATUS |
40 | #define NB_NBCFG0_NB_STATUS__CAP_LIST__SHIFT 0x4 |
41 | #define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
42 | #define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
43 | #define NB_NBCFG0_NB_STATUS__CAP_LIST_MASK 0x0010L |
44 | #define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
45 | #define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
46 | //NB_NBCFG0_NB_REVISION_ID |
47 | #define NB_NBCFG0_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
48 | #define NB_NBCFG0_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
49 | #define NB_NBCFG0_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
50 | #define NB_NBCFG0_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
51 | //NB_NBCFG0_NB_REGPROG_INF |
52 | #define NB_NBCFG0_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 |
53 | #define NB_NBCFG0_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL |
54 | //NB_NBCFG0_NB_SUB_CLASS |
55 | #define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
56 | #define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
57 | //NB_NBCFG0_NB_BASE_CODE |
58 | #define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
59 | #define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
60 | //NB_NBCFG0_NB_CACHE_LINE |
61 | #define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
62 | #define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
63 | //NB_NBCFG0_NB_LATENCY |
64 | #define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
65 | #define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL |
66 | //NB_NBCFG0_NB_HEADER |
67 | #define NB_NBCFG0_NB_HEADER__HEADER_TYPE__SHIFT 0x0 |
68 | #define NB_NBCFG0_NB_HEADER__DEVICE_TYPE__SHIFT 0x7 |
69 | #define NB_NBCFG0_NB_HEADER__HEADER_TYPE_MASK 0x7FL |
70 | #define NB_NBCFG0_NB_HEADER__DEVICE_TYPE_MASK 0x80L |
71 | //NB_NBCFG0_NB_ADAPTER_ID |
72 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
73 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
74 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
75 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
76 | //NB_NBCFG0_NB_CAPABILITIES_PTR |
77 | #define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
78 | #define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
79 | //NB_NBCFG0_NB_HEADER_W |
80 | #define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7 |
81 | #define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L |
82 | //NB_NBCFG0_NB_PCI_CTRL |
83 | #define NB_NBCFG0_NB_PCI_CTRL__PMEDis__SHIFT 0x4 |
84 | #define NB_NBCFG0_NB_PCI_CTRL__SErrDis__SHIFT 0x5 |
85 | #define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 |
86 | #define NB_NBCFG0_NB_PCI_CTRL__HPDis__SHIFT 0x1a |
87 | #define NB_NBCFG0_NB_PCI_CTRL__PMEDis_MASK 0x00000010L |
88 | #define NB_NBCFG0_NB_PCI_CTRL__SErrDis_MASK 0x00000020L |
89 | #define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L |
90 | #define NB_NBCFG0_NB_PCI_CTRL__HPDis_MASK 0x04000000L |
91 | //NB_NBCFG0_NB_ADAPTER_ID_W |
92 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
93 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
94 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
95 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
96 | //NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0 |
97 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0 |
98 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL |
99 | //NB_NBCFG0_NB_SMN_INDEX_0 |
100 | #define NB_NBCFG0_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0 |
101 | #define NB_NBCFG0_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL |
102 | //NB_NBCFG0_NB_SMN_DATA_0 |
103 | #define NB_NBCFG0_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0 |
104 | #define NB_NBCFG0_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL |
105 | //NB_NBCFG0_NBCFG_SCRATCH_0 |
106 | #define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 |
107 | #define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL |
108 | //NB_NBCFG0_NBCFG_SCRATCH_1 |
109 | #define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 |
110 | #define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL |
111 | //NB_NBCFG0_NBCFG_SCRATCH_2 |
112 | #define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 |
113 | #define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL |
114 | //NB_NBCFG0_NBCFG_SCRATCH_3 |
115 | #define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 |
116 | #define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL |
117 | //NB_NBCFG0_NBCFG_SCRATCH_4 |
118 | #define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 |
119 | #define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL |
120 | //NB_NBCFG0_NB_PCI_ARB |
121 | #define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
122 | #define NB_NBCFG0_NB_PCI_ARB__PMEMode__SHIFT 0x8 |
123 | #define NB_NBCFG0_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 |
124 | #define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa |
125 | #define NB_NBCFG0_NB_PCI_ARB__PMETarget__SHIFT 0x10 |
126 | #define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
127 | #define NB_NBCFG0_NB_PCI_ARB__PMEMode_MASK 0x00000100L |
128 | #define NB_NBCFG0_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L |
129 | #define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L |
130 | #define NB_NBCFG0_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L |
131 | //NB_NBCFG0_NB_DRAM_SLOT1_BASE |
132 | #define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 |
133 | #define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L |
134 | //NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1 |
135 | #define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0 |
136 | #define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
137 | #define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L |
138 | #define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
139 | //NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1 |
140 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0 |
141 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL |
142 | //NB_NBCFG0_NB_SMN_INDEX_1 |
143 | #define NB_NBCFG0_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0 |
144 | #define NB_NBCFG0_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL |
145 | //NB_NBCFG0_NB_SMN_DATA_1 |
146 | #define NB_NBCFG0_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0 |
147 | #define NB_NBCFG0_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL |
148 | //NB_NBCFG0_NB_INDEX_DATA_MUTEX0 |
149 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 |
150 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f |
151 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL |
152 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L |
153 | //NB_NBCFG0_NB_INDEX_DATA_MUTEX1 |
154 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 |
155 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f |
156 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL |
157 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L |
158 | //NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2 |
159 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0 |
160 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL |
161 | //NB_NBCFG0_NB_SMN_INDEX_2 |
162 | #define NB_NBCFG0_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0 |
163 | #define NB_NBCFG0_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL |
164 | //NB_NBCFG0_NB_SMN_DATA_2 |
165 | #define NB_NBCFG0_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0 |
166 | #define NB_NBCFG0_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL |
167 | //NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3 |
168 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0 |
169 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL |
170 | //NB_NBCFG0_NB_SMN_INDEX_3 |
171 | #define NB_NBCFG0_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0 |
172 | #define NB_NBCFG0_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL |
173 | //NB_NBCFG0_NB_SMN_DATA_3 |
174 | #define NB_NBCFG0_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0 |
175 | #define NB_NBCFG0_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL |
176 | //NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4 |
177 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0 |
178 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL |
179 | //NB_NBCFG0_NB_SMN_INDEX_4 |
180 | #define NB_NBCFG0_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0 |
181 | #define NB_NBCFG0_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL |
182 | //NB_NBCFG0_NB_SMN_DATA_4 |
183 | #define NB_NBCFG0_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0 |
184 | #define NB_NBCFG0_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL |
185 | //NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5 |
186 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0 |
187 | #define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL |
188 | //NB_NBCFG0_NB_SMN_INDEX_5 |
189 | #define NB_NBCFG0_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0 |
190 | #define NB_NBCFG0_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL |
191 | //NB_NBCFG0_NB_SMN_DATA_5 |
192 | #define NB_NBCFG0_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0 |
193 | #define NB_NBCFG0_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL |
194 | //NB_NBCFG0_NB_PERF_CNT_CTRL |
195 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0 |
196 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1 |
197 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2 |
198 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8 |
199 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf |
200 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10 |
201 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17 |
202 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L |
203 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L |
204 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L |
205 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L |
206 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L |
207 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L |
208 | #define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L |
209 | //NB_NBCFG0_NB_SMN_INDEX_6 |
210 | #define NB_NBCFG0_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0 |
211 | #define NB_NBCFG0_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL |
212 | //NB_NBCFG0_NB_SMN_DATA_6 |
213 | #define NB_NBCFG0_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0 |
214 | #define NB_NBCFG0_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL |
215 | |
216 | |
217 | // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
218 | //IOMMU_L2_0_IOMMU_VENDOR_ID |
219 | #define IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
220 | #define IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
221 | //IOMMU_L2_0_IOMMU_DEVICE_ID |
222 | #define IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
223 | #define IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
224 | //IOMMU_L2_0_IOMMU_COMMAND |
225 | #define IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
226 | #define IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
227 | #define IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
228 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved1__SHIFT 0x3 |
229 | #define IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6 |
230 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved0__SHIFT 0x7 |
231 | #define IOMMU_L2_0_IOMMU_COMMAND__SERR_EN__SHIFT 0x8 |
232 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved2__SHIFT 0x9 |
233 | #define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa |
234 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved__SHIFT 0xb |
235 | #define IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
236 | #define IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
237 | #define IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
238 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved1_MASK 0x0038L |
239 | #define IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L |
240 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved0_MASK 0x0080L |
241 | #define IOMMU_L2_0_IOMMU_COMMAND__SERR_EN_MASK 0x0100L |
242 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved2_MASK 0x0200L |
243 | #define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L |
244 | #define IOMMU_L2_0_IOMMU_COMMAND__Reserved_MASK 0xF800L |
245 | //IOMMU_L2_0_IOMMU_STATUS |
246 | #define IOMMU_L2_0_IOMMU_STATUS__Reserved__SHIFT 0x0 |
247 | #define IOMMU_L2_0_IOMMU_STATUS__INT_Status__SHIFT 0x3 |
248 | #define IOMMU_L2_0_IOMMU_STATUS__CAP_LIST__SHIFT 0x4 |
249 | #define IOMMU_L2_0_IOMMU_STATUS__Reserved1__SHIFT 0x5 |
250 | #define IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8 |
251 | #define IOMMU_L2_0_IOMMU_STATUS__Reserved2__SHIFT 0x9 |
252 | #define IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
253 | #define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
254 | #define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
255 | #define IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
256 | #define IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
257 | #define IOMMU_L2_0_IOMMU_STATUS__Reserved_MASK 0x0007L |
258 | #define IOMMU_L2_0_IOMMU_STATUS__INT_Status_MASK 0x0008L |
259 | #define IOMMU_L2_0_IOMMU_STATUS__CAP_LIST_MASK 0x0010L |
260 | #define IOMMU_L2_0_IOMMU_STATUS__Reserved1_MASK 0x00E0L |
261 | #define IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L |
262 | #define IOMMU_L2_0_IOMMU_STATUS__Reserved2_MASK 0x0600L |
263 | #define IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
264 | #define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
265 | #define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
266 | #define IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
267 | #define IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
268 | //IOMMU_L2_0_IOMMU_REVISION_ID |
269 | #define IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
270 | #define IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
271 | #define IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
272 | #define IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
273 | //IOMMU_L2_0_IOMMU_REGPROG_INF |
274 | #define IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 |
275 | #define IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL |
276 | //IOMMU_L2_0_IOMMU_SUB_CLASS |
277 | #define IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
278 | #define IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
279 | //IOMMU_L2_0_IOMMU_BASE_CODE |
280 | #define IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
281 | #define IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
282 | //IOMMU_L2_0_IOMMU_CACHE_LINE |
283 | #define IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
284 | #define IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
285 | //IOMMU_L2_0_IOMMU_LATENCY |
286 | #define IOMMU_L2_0_IOMMU_LATENCY__LATENCY__SHIFT 0x0 |
287 | #define IOMMU_L2_0_IOMMU_LATENCY__LATENCY_MASK 0xFFL |
288 | //IOMMU_L2_0_IOMMU_HEADER |
289 | #define IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0 |
290 | #define IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL |
291 | //IOMMU_L2_0_IOMMU_BIST |
292 | #define IOMMU_L2_0_IOMMU_BIST__BIST_COMP__SHIFT 0x0 |
293 | #define IOMMU_L2_0_IOMMU_BIST__BIST_STRT__SHIFT 0x6 |
294 | #define IOMMU_L2_0_IOMMU_BIST__BIST_CAP__SHIFT 0x7 |
295 | #define IOMMU_L2_0_IOMMU_BIST__BIST_COMP_MASK 0x0FL |
296 | #define IOMMU_L2_0_IOMMU_BIST__BIST_STRT_MASK 0x40L |
297 | #define IOMMU_L2_0_IOMMU_BIST__BIST_CAP_MASK 0x80L |
298 | //IOMMU_L2_0_IOMMU_ADAPTER_ID |
299 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
300 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
301 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
302 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
303 | //IOMMU_L2_0_IOMMU_CAPABILITIES_PTR |
304 | #define IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
305 | #define IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
306 | //IOMMU_L2_0_IOMMU_INTERRUPT_LINE |
307 | #define IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
308 | #define IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
309 | //IOMMU_L2_0_IOMMU_INTERRUPT_PIN |
310 | #define IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
311 | #define IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
312 | //IOMMU_L2_0_IOMMU_CAP_HEADER |
313 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0 |
314 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8 |
315 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10 |
316 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13 |
317 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18 |
318 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19 |
319 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a |
320 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b |
321 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c |
322 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d |
323 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL |
324 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L |
325 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L |
326 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L |
327 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L |
328 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L |
329 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L |
330 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L |
331 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L |
332 | #define IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L |
333 | //IOMMU_L2_0_IOMMU_CAP_BASE_LO |
334 | #define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
335 | #define IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1 |
336 | #define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 |
337 | #define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
338 | #define IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL |
339 | #define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L |
340 | //IOMMU_L2_0_IOMMU_CAP_BASE_HI |
341 | #define IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 |
342 | #define IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL |
343 | //IOMMU_L2_0_IOMMU_CAP_RANGE |
344 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0 |
345 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5 |
346 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7 |
347 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8 |
348 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10 |
349 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18 |
350 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL |
351 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L |
352 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L |
353 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L |
354 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L |
355 | #define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L |
356 | //IOMMU_L2_0_IOMMU_CAP_MISC |
357 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 |
358 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5 |
359 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8 |
360 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf |
361 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 |
362 | #define IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17 |
363 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b |
364 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL |
365 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L |
366 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L |
367 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L |
368 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L |
369 | #define IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L |
370 | #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L |
371 | //IOMMU_L2_0_IOMMU_CAP_MISC_1 |
372 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 |
373 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 |
374 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 |
375 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf |
376 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f |
377 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL |
378 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L |
379 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L |
380 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L |
381 | #define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L |
382 | //IOMMU_L2_0_IOMMU_MSI_CAP |
383 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 |
384 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 |
385 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10 |
386 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 |
387 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 |
388 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17 |
389 | #define IOMMU_L2_0_IOMMU_MSI_CAP__Reserved__SHIFT 0x18 |
390 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL |
391 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L |
392 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L |
393 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L |
394 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L |
395 | #define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L |
396 | #define IOMMU_L2_0_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L |
397 | //IOMMU_L2_0_IOMMU_MSI_ADDR_LO |
398 | #define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0 |
399 | #define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 |
400 | #define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L |
401 | #define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL |
402 | //IOMMU_L2_0_IOMMU_MSI_ADDR_HI |
403 | #define IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 |
404 | #define IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL |
405 | //IOMMU_L2_0_IOMMU_MSI_DATA |
406 | #define IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0 |
407 | #define IOMMU_L2_0_IOMMU_MSI_DATA__Reserved__SHIFT 0x10 |
408 | #define IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL |
409 | #define IOMMU_L2_0_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L |
410 | //IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP |
411 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 |
412 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 |
413 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 |
414 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 |
415 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 |
416 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b |
417 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL |
418 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L |
419 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L |
420 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L |
421 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L |
422 | #define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L |
423 | //IOMMU_L2_0_IOMMU_ADAPTER_ID_W |
424 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0 |
425 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10 |
426 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL |
427 | #define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L |
428 | //IOMMU_L2_0_IOMMU_CONTROL_W |
429 | #define IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0 |
430 | #define IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4 |
431 | #define IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 |
432 | #define IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 |
433 | #define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa |
434 | #define IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd |
435 | #define IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L |
436 | #define IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L |
437 | #define IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L |
438 | #define IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L |
439 | #define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L |
440 | #define IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L |
441 | //IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W |
442 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 |
443 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 |
444 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2 |
445 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 |
446 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 |
447 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5 |
448 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6 |
449 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 |
450 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8 |
451 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 |
452 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa |
453 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc |
454 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd |
455 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 |
456 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18 |
457 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a |
458 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c |
459 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e |
460 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L |
461 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L |
462 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L |
463 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L |
464 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L |
465 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L |
466 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L |
467 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L |
468 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L |
469 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L |
470 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L |
471 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L |
472 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L |
473 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L |
474 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L |
475 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L |
476 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L |
477 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L |
478 | //IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W |
479 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 |
480 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4 |
481 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 |
482 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8 |
483 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9 |
484 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa |
485 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb |
486 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd |
487 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe |
488 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf |
489 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 |
490 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11 |
491 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12 |
492 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13 |
493 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14 |
494 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15 |
495 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL |
496 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L |
497 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L |
498 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L |
499 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L |
500 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L |
501 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L |
502 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L |
503 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L |
504 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L |
505 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L |
506 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L |
507 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L |
508 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L |
509 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L |
510 | #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L |
511 | //IOMMU_L2_0_IOMMU_RANGE_W |
512 | #define IOMMU_L2_0_IOMMU_RANGE_W__Reserved__SHIFT 0x0 |
513 | #define IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7 |
514 | #define IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8 |
515 | #define IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10 |
516 | #define IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18 |
517 | #define IOMMU_L2_0_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL |
518 | #define IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L |
519 | #define IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L |
520 | #define IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L |
521 | #define IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L |
522 | //IOMMU_L2_0_IOMMU_DSFX_CONTROL |
523 | #define IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0 |
524 | #define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18 |
525 | #define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c |
526 | #define IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL |
527 | #define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L |
528 | #define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L |
529 | //IOMMU_L2_0_IOMMU_DSSX_DUMMY_0 |
530 | #define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0 |
531 | #define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18 |
532 | #define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL |
533 | #define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L |
534 | //IOMMU_L2_0_IOMMU_DSCX_DUMMY_0 |
535 | #define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0 |
536 | #define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18 |
537 | #define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL |
538 | #define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L |
539 | //IOMMU_L2_0_L2B_POISON_DVM_CNTRL |
540 | #define IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0 |
541 | #define IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L |
542 | //IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control |
543 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
544 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
545 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8 |
546 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe |
547 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
548 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
549 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L |
550 | #define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L |
551 | //IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control |
552 | #define IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4 |
553 | #define IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L |
554 | //IOMMU_L2_0_SMMU_MMIO_IDR0_W |
555 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0 |
556 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1 |
557 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2 |
558 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4 |
559 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5 |
560 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6 |
561 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8 |
562 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9 |
563 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa |
564 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb |
565 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc |
566 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd |
567 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe |
568 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf |
569 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10 |
570 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11 |
571 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12 |
572 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13 |
573 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14 |
574 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15 |
575 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18 |
576 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a |
577 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b |
578 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d |
579 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L |
580 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L |
581 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL |
582 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L |
583 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L |
584 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L |
585 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L |
586 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L |
587 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L |
588 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L |
589 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L |
590 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L |
591 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L |
592 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L |
593 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L |
594 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L |
595 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L |
596 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L |
597 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L |
598 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L |
599 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L |
600 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L |
601 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L |
602 | #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L |
603 | //IOMMU_L2_0_SMMU_MMIO_IDR1_W |
604 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0 |
605 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6 |
606 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb |
607 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10 |
608 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15 |
609 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a |
610 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b |
611 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c |
612 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d |
613 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e |
614 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL |
615 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L |
616 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L |
617 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L |
618 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L |
619 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L |
620 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L |
621 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L |
622 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L |
623 | #define IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L |
624 | //IOMMU_L2_0_SMMU_MMIO_IDR2_W |
625 | #define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0 |
626 | #define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa |
627 | #define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL |
628 | #define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L |
629 | //IOMMU_L2_0_SMMU_MMIO_IDR3_W |
630 | #define IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2 |
631 | #define IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L |
632 | //IOMMU_L2_0_SMMU_MMIO_IDR5_W |
633 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0 |
634 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4 |
635 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5 |
636 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6 |
637 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10 |
638 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L |
639 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L |
640 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L |
641 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L |
642 | #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L |
643 | //IOMMU_L2_0_SMMU_MMIO_IIDR_W |
644 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0 |
645 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc |
646 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10 |
647 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14 |
648 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL |
649 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L |
650 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L |
651 | #define IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L |
652 | //IOMMU_L2_0_SMMU_AIDR_W |
653 | #define IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0 |
654 | #define IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4 |
655 | #define IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL |
656 | #define IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L |
657 | |
658 | |
659 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
660 | //BIF_CFG_DEV0_RC0_VENDOR_ID |
661 | #define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
662 | #define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
663 | //BIF_CFG_DEV0_RC0_DEVICE_ID |
664 | #define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
665 | #define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
666 | //BIF_CFG_DEV0_RC0_COMMAND |
667 | #define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 |
668 | #define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 |
669 | #define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
670 | #define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
671 | #define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
672 | #define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
673 | #define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
674 | #define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 |
675 | #define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 |
676 | #define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
677 | #define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa |
678 | #define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L |
679 | #define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L |
680 | #define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
681 | #define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
682 | #define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
683 | #define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
684 | #define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
685 | #define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L |
686 | #define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L |
687 | #define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
688 | #define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L |
689 | //BIF_CFG_DEV0_RC0_STATUS |
690 | #define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 |
691 | #define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 |
692 | #define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN__SHIFT 0x5 |
693 | #define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
694 | #define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
695 | #define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
696 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
697 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
698 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
699 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
700 | #define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
701 | #define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L |
702 | #define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L |
703 | #define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN_MASK 0x0020L |
704 | #define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
705 | #define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
706 | #define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
707 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
708 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
709 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
710 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
711 | #define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
712 | //BIF_CFG_DEV0_RC0_REVISION_ID |
713 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
714 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
715 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
716 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
717 | //BIF_CFG_DEV0_RC0_PROG_INTERFACE |
718 | #define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
719 | #define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
720 | //BIF_CFG_DEV0_RC0_SUB_CLASS |
721 | #define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
722 | #define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
723 | //BIF_CFG_DEV0_RC0_BASE_CLASS |
724 | #define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
725 | #define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
726 | //BIF_CFG_DEV0_RC0_CACHE_LINE |
727 | #define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
728 | #define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
729 | //BIF_CFG_DEV0_RC0_LATENCY |
730 | #define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
731 | #define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
732 | //BIF_CFG_DEV0_RC0_HEADER |
733 | #define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 |
734 | #define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
735 | #define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL |
736 | #define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L |
737 | //BIF_CFG_DEV0_RC0_BIST |
738 | #define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 |
739 | #define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 |
740 | #define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 |
741 | #define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL |
742 | #define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L |
743 | #define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L |
744 | //BIF_CFG_DEV0_RC0_BASE_ADDR_1 |
745 | #define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
746 | #define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
747 | //BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY |
748 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
749 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
750 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
751 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
752 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
753 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
754 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
755 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
756 | //BIF_CFG_DEV0_RC0_IO_BASE_LIMIT |
757 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
758 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
759 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
760 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
761 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
762 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
763 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
764 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
765 | //BIF_CFG_DEV0_RC0_SECONDARY_STATUS |
766 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
767 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
768 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
769 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
770 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
771 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
772 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
773 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
774 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
775 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
776 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
777 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
778 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
779 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
780 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
781 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
782 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
783 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
784 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
785 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
786 | //BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT |
787 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
788 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
789 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
790 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
791 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
792 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
793 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
794 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
795 | //BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT |
796 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
797 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
798 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
799 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
800 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
801 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
802 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
803 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
804 | //BIF_CFG_DEV0_RC0_PREF_BASE_UPPER |
805 | #define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
806 | #define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
807 | //BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER |
808 | #define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
809 | #define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
810 | //BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI |
811 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
812 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
813 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
814 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
815 | //BIF_CFG_DEV0_RC0_CAP_PTR |
816 | #define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
817 | #define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
818 | //BIF_CFG_DEV0_RC0_INTERRUPT_LINE |
819 | #define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
820 | #define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
821 | //BIF_CFG_DEV0_RC0_INTERRUPT_PIN |
822 | #define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
823 | #define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
824 | //BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL |
825 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
826 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
827 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
828 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
829 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
830 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
831 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
832 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
833 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
834 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
835 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
836 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
837 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
838 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
839 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
840 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
841 | //BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL |
842 | #define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
843 | #define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
844 | //BIF_CFG_DEV0_RC0_PMI_CAP_LIST |
845 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
846 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
847 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
848 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
849 | //BIF_CFG_DEV0_RC0_PMI_CAP |
850 | #define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 |
851 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
852 | #define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
853 | #define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
854 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
855 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
856 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
857 | #define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L |
858 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
859 | #define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
860 | #define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
861 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
862 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
863 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
864 | //BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL |
865 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
866 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
867 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
868 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
869 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
870 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
871 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
872 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
873 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
874 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
875 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
876 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
877 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
878 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
879 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
880 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
881 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
882 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
883 | //BIF_CFG_DEV0_RC0_PCIE_CAP_LIST |
884 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
885 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
886 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
887 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
888 | //BIF_CFG_DEV0_RC0_PCIE_CAP |
889 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 |
890 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
891 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
892 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
893 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL |
894 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
895 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
896 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
897 | //BIF_CFG_DEV0_RC0_DEVICE_CAP |
898 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
899 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
900 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
901 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
902 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
903 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
904 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
905 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
906 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
907 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
908 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
909 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
910 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
911 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
912 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
913 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
914 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
915 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
916 | //BIF_CFG_DEV0_RC0_DEVICE_CNTL |
917 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
918 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
919 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
920 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
921 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
922 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
923 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
924 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
925 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
926 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
927 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
928 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
929 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
930 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
931 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
932 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
933 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
934 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
935 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
936 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
937 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
938 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
939 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
940 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
941 | //BIF_CFG_DEV0_RC0_DEVICE_STATUS |
942 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
943 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
944 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
945 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
946 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
947 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
948 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
949 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
950 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
951 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
952 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
953 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
954 | //BIF_CFG_DEV0_RC0_LINK_CAP |
955 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
956 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
957 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
958 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
959 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
960 | #define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
961 | #define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
962 | #define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
963 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
964 | #define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
965 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
966 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
967 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
968 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
969 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
970 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
971 | #define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
972 | #define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
973 | #define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
974 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
975 | #define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
976 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
977 | //BIF_CFG_DEV0_RC0_LINK_CNTL |
978 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
979 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
980 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
981 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
982 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
983 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
984 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
985 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
986 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
987 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
988 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
989 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
990 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
991 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
992 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
993 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
994 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
995 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
996 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
997 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
998 | //BIF_CFG_DEV0_RC0_LINK_STATUS |
999 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
1000 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
1001 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
1002 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
1003 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
1004 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
1005 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
1006 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
1007 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
1008 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
1009 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
1010 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
1011 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
1012 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
1013 | //BIF_CFG_DEV0_RC0_SLOT_CAP |
1014 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
1015 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
1016 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
1017 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
1018 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
1019 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
1020 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
1021 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
1022 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
1023 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
1024 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
1025 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
1026 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
1027 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
1028 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
1029 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
1030 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
1031 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
1032 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
1033 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
1034 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
1035 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
1036 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
1037 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
1038 | //BIF_CFG_DEV0_RC0_SLOT_CNTL |
1039 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
1040 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
1041 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
1042 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
1043 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
1044 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
1045 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
1046 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
1047 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
1048 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
1049 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
1050 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
1051 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
1052 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
1053 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
1054 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
1055 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
1056 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
1057 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
1058 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
1059 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
1060 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
1061 | //BIF_CFG_DEV0_RC0_SLOT_STATUS |
1062 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
1063 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
1064 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
1065 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
1066 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
1067 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
1068 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
1069 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
1070 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
1071 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
1072 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
1073 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
1074 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
1075 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
1076 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
1077 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
1078 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
1079 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
1080 | //BIF_CFG_DEV0_RC0_ROOT_CNTL |
1081 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
1082 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
1083 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
1084 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
1085 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
1086 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
1087 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
1088 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
1089 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
1090 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
1091 | //BIF_CFG_DEV0_RC0_ROOT_CAP |
1092 | #define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
1093 | #define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
1094 | //BIF_CFG_DEV0_RC0_ROOT_STATUS |
1095 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
1096 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
1097 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
1098 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
1099 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
1100 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
1101 | //BIF_CFG_DEV0_RC0_DEVICE_CAP2 |
1102 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
1103 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
1104 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
1105 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
1106 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
1107 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
1108 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
1109 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
1110 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
1111 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
1112 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
1113 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
1114 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
1115 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
1116 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
1117 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
1118 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
1119 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
1120 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
1121 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
1122 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
1123 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
1124 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
1125 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
1126 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
1127 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
1128 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
1129 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
1130 | //BIF_CFG_DEV0_RC0_DEVICE_CNTL2 |
1131 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
1132 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
1133 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
1134 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
1135 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
1136 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
1137 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
1138 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
1139 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
1140 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
1141 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
1142 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
1143 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
1144 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
1145 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
1146 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
1147 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
1148 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
1149 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
1150 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
1151 | //BIF_CFG_DEV0_RC0_DEVICE_STATUS2 |
1152 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
1153 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
1154 | //BIF_CFG_DEV0_RC0_LINK_CAP2 |
1155 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
1156 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
1157 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED__SHIFT 0x9 |
1158 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
1159 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
1160 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
1161 | //BIF_CFG_DEV0_RC0_LINK_CNTL2 |
1162 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
1163 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
1164 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
1165 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
1166 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
1167 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
1168 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
1169 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
1170 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
1171 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
1172 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
1173 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
1174 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
1175 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
1176 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
1177 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
1178 | //BIF_CFG_DEV0_RC0_LINK_STATUS2 |
1179 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
1180 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
1181 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
1182 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
1183 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
1184 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
1185 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
1186 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
1187 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
1188 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
1189 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
1190 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
1191 | //BIF_CFG_DEV0_RC0_SLOT_CAP2 |
1192 | #define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
1193 | #define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
1194 | //BIF_CFG_DEV0_RC0_SLOT_CNTL2 |
1195 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
1196 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
1197 | //BIF_CFG_DEV0_RC0_SLOT_STATUS2 |
1198 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
1199 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
1200 | //BIF_CFG_DEV0_RC0_MSI_CAP_LIST |
1201 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
1202 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
1203 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
1204 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
1205 | //BIF_CFG_DEV0_RC0_MSI_MSG_CNTL |
1206 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
1207 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
1208 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
1209 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
1210 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
1211 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
1212 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
1213 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
1214 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
1215 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
1216 | //BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO |
1217 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
1218 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
1219 | //BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI |
1220 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
1221 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
1222 | //BIF_CFG_DEV0_RC0_MSI_MSG_DATA |
1223 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
1224 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
1225 | //BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 |
1226 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
1227 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
1228 | //BIF_CFG_DEV0_RC0_SSID_CAP_LIST |
1229 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
1230 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
1231 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
1232 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
1233 | //BIF_CFG_DEV0_RC0_SSID_CAP |
1234 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
1235 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
1236 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
1237 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
1238 | //BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST |
1239 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
1240 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
1241 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
1242 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
1243 | //BIF_CFG_DEV0_RC0_MSI_MAP_CAP |
1244 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 |
1245 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
1246 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
1247 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK 0x0001L |
1248 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
1249 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
1250 | //BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO |
1251 | #define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
1252 | #define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
1253 | //BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI |
1254 | #define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
1255 | #define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
1256 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
1257 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1258 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1259 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1260 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1261 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1262 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1263 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR |
1264 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
1265 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
1266 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
1267 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
1268 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
1269 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
1270 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 |
1271 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
1272 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
1273 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 |
1274 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
1275 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
1276 | //BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST |
1277 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1278 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1279 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1280 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1281 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1282 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1283 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 |
1284 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
1285 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
1286 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
1287 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
1288 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
1289 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
1290 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
1291 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
1292 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 |
1293 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
1294 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
1295 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
1296 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
1297 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL |
1298 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
1299 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
1300 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
1301 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
1302 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS |
1303 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
1304 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
1305 | //BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP |
1306 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
1307 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
1308 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
1309 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
1310 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
1311 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
1312 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
1313 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
1314 | //BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL |
1315 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
1316 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
1317 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
1318 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
1319 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
1320 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
1321 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
1322 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
1323 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
1324 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
1325 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
1326 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
1327 | //BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS |
1328 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
1329 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
1330 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
1331 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
1332 | //BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP |
1333 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
1334 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
1335 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
1336 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
1337 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
1338 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
1339 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
1340 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
1341 | //BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL |
1342 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
1343 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
1344 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
1345 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
1346 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
1347 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
1348 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
1349 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
1350 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
1351 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
1352 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
1353 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
1354 | //BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS |
1355 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
1356 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
1357 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
1358 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
1359 | //BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
1360 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1361 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1362 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1363 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1364 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1365 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1366 | //BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 |
1367 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
1368 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
1369 | //BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 |
1370 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
1371 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
1372 | //BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
1373 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1374 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1375 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1376 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1377 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1378 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1379 | //BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS |
1380 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
1381 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
1382 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
1383 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
1384 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
1385 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
1386 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
1387 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
1388 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
1389 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
1390 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
1391 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
1392 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
1393 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
1394 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
1395 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
1396 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
1397 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
1398 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
1399 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
1400 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
1401 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
1402 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
1403 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
1404 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
1405 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
1406 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
1407 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
1408 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
1409 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
1410 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
1411 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
1412 | //BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK |
1413 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
1414 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
1415 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
1416 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
1417 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
1418 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
1419 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
1420 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
1421 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
1422 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
1423 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
1424 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
1425 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
1426 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
1427 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
1428 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
1429 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
1430 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
1431 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
1432 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
1433 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
1434 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
1435 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
1436 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
1437 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
1438 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
1439 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
1440 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
1441 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
1442 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
1443 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
1444 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
1445 | //BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY |
1446 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
1447 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
1448 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
1449 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
1450 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
1451 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
1452 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
1453 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
1454 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
1455 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
1456 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
1457 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
1458 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
1459 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
1460 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
1461 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
1462 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
1463 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
1464 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
1465 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
1466 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
1467 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
1468 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
1469 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
1470 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
1471 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
1472 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
1473 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
1474 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
1475 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
1476 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
1477 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
1478 | //BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS |
1479 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
1480 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
1481 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
1482 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
1483 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
1484 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
1485 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
1486 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
1487 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
1488 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
1489 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
1490 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
1491 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
1492 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
1493 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
1494 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
1495 | //BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK |
1496 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
1497 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
1498 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
1499 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
1500 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
1501 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
1502 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
1503 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
1504 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
1505 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
1506 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
1507 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
1508 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
1509 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
1510 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
1511 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
1512 | //BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL |
1513 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
1514 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
1515 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
1516 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
1517 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
1518 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
1519 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
1520 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
1521 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
1522 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
1523 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
1524 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
1525 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
1526 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
1527 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
1528 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
1529 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 |
1530 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
1531 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
1532 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 |
1533 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
1534 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
1535 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 |
1536 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
1537 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
1538 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 |
1539 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
1540 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
1541 | //BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD |
1542 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
1543 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
1544 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
1545 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
1546 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
1547 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
1548 | //BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS |
1549 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
1550 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
1551 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
1552 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
1553 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
1554 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
1555 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
1556 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
1557 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
1558 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
1559 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
1560 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
1561 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
1562 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
1563 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
1564 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
1565 | //BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID |
1566 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
1567 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
1568 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
1569 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
1570 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 |
1571 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
1572 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
1573 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 |
1574 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
1575 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
1576 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 |
1577 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
1578 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
1579 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 |
1580 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
1581 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
1582 | //BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST |
1583 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1584 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1585 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1586 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1587 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1588 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1589 | //BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 |
1590 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
1591 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
1592 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
1593 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
1594 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
1595 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
1596 | //BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS |
1597 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
1598 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
1599 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
1600 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
1601 | //BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL |
1602 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1603 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1604 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1605 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1606 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1607 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1608 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1609 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1610 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1611 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1612 | //BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL |
1613 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1614 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1615 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1616 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1617 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1618 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1619 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1620 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1621 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1622 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1623 | //BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL |
1624 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1625 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1626 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1627 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1628 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1629 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1630 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1631 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1632 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1633 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1634 | //BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL |
1635 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1636 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1637 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1638 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1639 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1640 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1641 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1642 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1643 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1644 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1645 | //BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL |
1646 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1647 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1648 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1649 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1650 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1651 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1652 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1653 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1654 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1655 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1656 | //BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL |
1657 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1658 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1659 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1660 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1661 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1662 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1663 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1664 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1665 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1666 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1667 | //BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL |
1668 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1669 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1670 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1671 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1672 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1673 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1674 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1675 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1676 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1677 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1678 | //BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL |
1679 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1680 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1681 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1682 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1683 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1684 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1685 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1686 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1687 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1688 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1689 | //BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL |
1690 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1691 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1692 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1693 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1694 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1695 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1696 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1697 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1698 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1699 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1700 | //BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL |
1701 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1702 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1703 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1704 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1705 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1706 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1707 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1708 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1709 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1710 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1711 | //BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL |
1712 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1713 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1714 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1715 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1716 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1717 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1718 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1719 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1720 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1721 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1722 | //BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL |
1723 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1724 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1725 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1726 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1727 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1728 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1729 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1730 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1731 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1732 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1733 | //BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL |
1734 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1735 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1736 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1737 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1738 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1739 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1740 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1741 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1742 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1743 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1744 | //BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL |
1745 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1746 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1747 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1748 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1749 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1750 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1751 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1752 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1753 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1754 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1755 | //BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL |
1756 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1757 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1758 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1759 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1760 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1761 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1762 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1763 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1764 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1765 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1766 | //BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL |
1767 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
1768 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
1769 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
1770 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
1771 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
1772 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
1773 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
1774 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
1775 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
1776 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
1777 | //BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST |
1778 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1779 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1780 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1781 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1782 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1783 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1784 | //BIF_CFG_DEV0_RC0_PCIE_ACS_CAP |
1785 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
1786 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
1787 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
1788 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
1789 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
1790 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
1791 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
1792 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
1793 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
1794 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
1795 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
1796 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
1797 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
1798 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
1799 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
1800 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
1801 | //BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL |
1802 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
1803 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
1804 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
1805 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
1806 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
1807 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
1808 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
1809 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
1810 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
1811 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
1812 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
1813 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
1814 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
1815 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
1816 | |
1817 | |
1818 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
1819 | //BIF_CFG_DEV1_RC0_VENDOR_ID |
1820 | #define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
1821 | #define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
1822 | //BIF_CFG_DEV1_RC0_DEVICE_ID |
1823 | #define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
1824 | #define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
1825 | //BIF_CFG_DEV1_RC0_COMMAND |
1826 | #define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT 0x0 |
1827 | #define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 |
1828 | #define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
1829 | #define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
1830 | #define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
1831 | #define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
1832 | #define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
1833 | #define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 |
1834 | #define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT 0x8 |
1835 | #define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
1836 | #define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT 0xa |
1837 | #define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK 0x0001L |
1838 | #define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK 0x0002L |
1839 | #define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
1840 | #define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
1841 | #define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
1842 | #define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
1843 | #define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
1844 | #define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK 0x0080L |
1845 | #define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK 0x0100L |
1846 | #define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
1847 | #define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK 0x0400L |
1848 | //BIF_CFG_DEV1_RC0_STATUS |
1849 | #define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT 0x3 |
1850 | #define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT 0x4 |
1851 | #define BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN__SHIFT 0x5 |
1852 | #define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
1853 | #define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
1854 | #define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
1855 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
1856 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
1857 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
1858 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
1859 | #define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
1860 | #define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK 0x0008L |
1861 | #define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK 0x0010L |
1862 | #define BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN_MASK 0x0020L |
1863 | #define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
1864 | #define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
1865 | #define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
1866 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
1867 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
1868 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
1869 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
1870 | #define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
1871 | //BIF_CFG_DEV1_RC0_REVISION_ID |
1872 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
1873 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
1874 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
1875 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
1876 | //BIF_CFG_DEV1_RC0_PROG_INTERFACE |
1877 | #define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
1878 | #define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
1879 | //BIF_CFG_DEV1_RC0_SUB_CLASS |
1880 | #define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
1881 | #define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
1882 | //BIF_CFG_DEV1_RC0_BASE_CLASS |
1883 | #define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
1884 | #define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
1885 | //BIF_CFG_DEV1_RC0_CACHE_LINE |
1886 | #define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
1887 | #define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
1888 | //BIF_CFG_DEV1_RC0_LATENCY |
1889 | #define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
1890 | #define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
1891 | //BIF_CFG_DEV1_RC0_HEADER |
1892 | #define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 |
1893 | #define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
1894 | #define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK 0x7FL |
1895 | #define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK 0x80L |
1896 | //BIF_CFG_DEV1_RC0_BIST |
1897 | #define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT 0x0 |
1898 | #define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT 0x6 |
1899 | #define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT 0x7 |
1900 | #define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK 0x0FL |
1901 | #define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK 0x40L |
1902 | #define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK 0x80L |
1903 | //BIF_CFG_DEV1_RC0_BASE_ADDR_1 |
1904 | #define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
1905 | #define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
1906 | //BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY |
1907 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
1908 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
1909 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
1910 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
1911 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
1912 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
1913 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
1914 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
1915 | //BIF_CFG_DEV1_RC0_IO_BASE_LIMIT |
1916 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
1917 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
1918 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
1919 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
1920 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
1921 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
1922 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
1923 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
1924 | //BIF_CFG_DEV1_RC0_SECONDARY_STATUS |
1925 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
1926 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
1927 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
1928 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
1929 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
1930 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
1931 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
1932 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
1933 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
1934 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
1935 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
1936 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
1937 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
1938 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
1939 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
1940 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
1941 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
1942 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
1943 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
1944 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
1945 | //BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT |
1946 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
1947 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
1948 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
1949 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
1950 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
1951 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
1952 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
1953 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
1954 | //BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT |
1955 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
1956 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
1957 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
1958 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
1959 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
1960 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
1961 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
1962 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
1963 | //BIF_CFG_DEV1_RC0_PREF_BASE_UPPER |
1964 | #define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
1965 | #define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
1966 | //BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER |
1967 | #define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
1968 | #define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
1969 | //BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI |
1970 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
1971 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
1972 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
1973 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
1974 | //BIF_CFG_DEV1_RC0_CAP_PTR |
1975 | #define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
1976 | #define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
1977 | //BIF_CFG_DEV1_RC0_INTERRUPT_LINE |
1978 | #define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
1979 | #define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
1980 | //BIF_CFG_DEV1_RC0_INTERRUPT_PIN |
1981 | #define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
1982 | #define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
1983 | //BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL |
1984 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
1985 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
1986 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
1987 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
1988 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
1989 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
1990 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
1991 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
1992 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
1993 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
1994 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
1995 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
1996 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
1997 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
1998 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
1999 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
2000 | //BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL |
2001 | #define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
2002 | #define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
2003 | //BIF_CFG_DEV1_RC0_PMI_CAP_LIST |
2004 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
2005 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2006 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
2007 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2008 | //BIF_CFG_DEV1_RC0_PMI_CAP |
2009 | #define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT 0x0 |
2010 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
2011 | #define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
2012 | #define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
2013 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
2014 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
2015 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
2016 | #define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK 0x0007L |
2017 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
2018 | #define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
2019 | #define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
2020 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
2021 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
2022 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
2023 | //BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL |
2024 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
2025 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
2026 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
2027 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
2028 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
2029 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
2030 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
2031 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
2032 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
2033 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
2034 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
2035 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
2036 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
2037 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
2038 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
2039 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
2040 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
2041 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
2042 | //BIF_CFG_DEV1_RC0_PCIE_CAP_LIST |
2043 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
2044 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2045 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
2046 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2047 | //BIF_CFG_DEV1_RC0_PCIE_CAP |
2048 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT 0x0 |
2049 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
2050 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
2051 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
2052 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK 0x000FL |
2053 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
2054 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
2055 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
2056 | //BIF_CFG_DEV1_RC0_DEVICE_CAP |
2057 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
2058 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
2059 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
2060 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
2061 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
2062 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
2063 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
2064 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
2065 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
2066 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
2067 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
2068 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
2069 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
2070 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
2071 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
2072 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
2073 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
2074 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
2075 | //BIF_CFG_DEV1_RC0_DEVICE_CNTL |
2076 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
2077 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
2078 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
2079 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
2080 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
2081 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
2082 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
2083 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
2084 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
2085 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
2086 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
2087 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
2088 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
2089 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
2090 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
2091 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
2092 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
2093 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
2094 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
2095 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
2096 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
2097 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
2098 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
2099 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
2100 | //BIF_CFG_DEV1_RC0_DEVICE_STATUS |
2101 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
2102 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
2103 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
2104 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
2105 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
2106 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
2107 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
2108 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
2109 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
2110 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
2111 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
2112 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
2113 | //BIF_CFG_DEV1_RC0_LINK_CAP |
2114 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
2115 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
2116 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
2117 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
2118 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
2119 | #define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
2120 | #define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
2121 | #define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
2122 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
2123 | #define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
2124 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
2125 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
2126 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
2127 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
2128 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
2129 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
2130 | #define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
2131 | #define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
2132 | #define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
2133 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
2134 | #define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
2135 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
2136 | //BIF_CFG_DEV1_RC0_LINK_CNTL |
2137 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
2138 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
2139 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
2140 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
2141 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
2142 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
2143 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
2144 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
2145 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
2146 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
2147 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
2148 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
2149 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
2150 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
2151 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
2152 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
2153 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
2154 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
2155 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
2156 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
2157 | //BIF_CFG_DEV1_RC0_LINK_STATUS |
2158 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
2159 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
2160 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
2161 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
2162 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
2163 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
2164 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
2165 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
2166 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
2167 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
2168 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
2169 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
2170 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
2171 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
2172 | //BIF_CFG_DEV1_RC0_SLOT_CAP |
2173 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
2174 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
2175 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
2176 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
2177 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
2178 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
2179 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
2180 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
2181 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
2182 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
2183 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
2184 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
2185 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
2186 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
2187 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
2188 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
2189 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
2190 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
2191 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
2192 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
2193 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
2194 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
2195 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
2196 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
2197 | //BIF_CFG_DEV1_RC0_SLOT_CNTL |
2198 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
2199 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
2200 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
2201 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
2202 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
2203 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
2204 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
2205 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
2206 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
2207 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
2208 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
2209 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
2210 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
2211 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
2212 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
2213 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
2214 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
2215 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
2216 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
2217 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
2218 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
2219 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
2220 | //BIF_CFG_DEV1_RC0_SLOT_STATUS |
2221 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
2222 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
2223 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
2224 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
2225 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
2226 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
2227 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
2228 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
2229 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
2230 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
2231 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
2232 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
2233 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
2234 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
2235 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
2236 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
2237 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
2238 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
2239 | //BIF_CFG_DEV1_RC0_ROOT_CNTL |
2240 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
2241 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
2242 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
2243 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
2244 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
2245 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
2246 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
2247 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
2248 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
2249 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
2250 | //BIF_CFG_DEV1_RC0_ROOT_CAP |
2251 | #define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
2252 | #define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
2253 | //BIF_CFG_DEV1_RC0_ROOT_STATUS |
2254 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
2255 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
2256 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
2257 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
2258 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
2259 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
2260 | //BIF_CFG_DEV1_RC0_DEVICE_CAP2 |
2261 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
2262 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
2263 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
2264 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
2265 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
2266 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
2267 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
2268 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
2269 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
2270 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
2271 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
2272 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
2273 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
2274 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
2275 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
2276 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
2277 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
2278 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
2279 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
2280 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
2281 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
2282 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
2283 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
2284 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
2285 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
2286 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
2287 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
2288 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
2289 | //BIF_CFG_DEV1_RC0_DEVICE_CNTL2 |
2290 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
2291 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
2292 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
2293 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
2294 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
2295 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
2296 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
2297 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
2298 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
2299 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
2300 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
2301 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
2302 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
2303 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
2304 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
2305 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
2306 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
2307 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
2308 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
2309 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
2310 | //BIF_CFG_DEV1_RC0_DEVICE_STATUS2 |
2311 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
2312 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
2313 | //BIF_CFG_DEV1_RC0_LINK_CAP2 |
2314 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
2315 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
2316 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED__SHIFT 0x9 |
2317 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
2318 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
2319 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
2320 | //BIF_CFG_DEV1_RC0_LINK_CNTL2 |
2321 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
2322 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
2323 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
2324 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
2325 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
2326 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
2327 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
2328 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
2329 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
2330 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
2331 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
2332 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
2333 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
2334 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
2335 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
2336 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
2337 | //BIF_CFG_DEV1_RC0_LINK_STATUS2 |
2338 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
2339 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
2340 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
2341 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
2342 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
2343 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
2344 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
2345 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
2346 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
2347 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
2348 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
2349 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
2350 | //BIF_CFG_DEV1_RC0_SLOT_CAP2 |
2351 | #define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
2352 | #define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
2353 | //BIF_CFG_DEV1_RC0_SLOT_CNTL2 |
2354 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
2355 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
2356 | //BIF_CFG_DEV1_RC0_SLOT_STATUS2 |
2357 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
2358 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
2359 | //BIF_CFG_DEV1_RC0_MSI_CAP_LIST |
2360 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
2361 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2362 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
2363 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2364 | //BIF_CFG_DEV1_RC0_MSI_MSG_CNTL |
2365 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
2366 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
2367 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
2368 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
2369 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
2370 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
2371 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
2372 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
2373 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
2374 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
2375 | //BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO |
2376 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
2377 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
2378 | //BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI |
2379 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
2380 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
2381 | //BIF_CFG_DEV1_RC0_MSI_MSG_DATA |
2382 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
2383 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
2384 | //BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 |
2385 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
2386 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
2387 | //BIF_CFG_DEV1_RC0_SSID_CAP_LIST |
2388 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
2389 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2390 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
2391 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2392 | //BIF_CFG_DEV1_RC0_SSID_CAP |
2393 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
2394 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
2395 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
2396 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
2397 | //BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST |
2398 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
2399 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2400 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
2401 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2402 | //BIF_CFG_DEV1_RC0_MSI_MAP_CAP |
2403 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 |
2404 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
2405 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
2406 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK 0x0001L |
2407 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
2408 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
2409 | //BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO |
2410 | #define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
2411 | #define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
2412 | //BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI |
2413 | #define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
2414 | #define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
2415 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
2416 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2417 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2418 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2419 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2420 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2421 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2422 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR |
2423 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
2424 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
2425 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
2426 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
2427 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
2428 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
2429 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 |
2430 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
2431 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
2432 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 |
2433 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
2434 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
2435 | //BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST |
2436 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2437 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2438 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2439 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2440 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2441 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2442 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 |
2443 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
2444 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
2445 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
2446 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
2447 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
2448 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
2449 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
2450 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
2451 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 |
2452 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
2453 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
2454 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
2455 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
2456 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL |
2457 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
2458 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
2459 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
2460 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
2461 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS |
2462 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
2463 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
2464 | //BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP |
2465 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
2466 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
2467 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
2468 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
2469 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
2470 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
2471 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
2472 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
2473 | //BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL |
2474 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
2475 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
2476 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
2477 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
2478 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
2479 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
2480 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
2481 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
2482 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
2483 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
2484 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
2485 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
2486 | //BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS |
2487 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
2488 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
2489 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
2490 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
2491 | //BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP |
2492 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
2493 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
2494 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
2495 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
2496 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
2497 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
2498 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
2499 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
2500 | //BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL |
2501 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
2502 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
2503 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
2504 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
2505 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
2506 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
2507 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
2508 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
2509 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
2510 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
2511 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
2512 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
2513 | //BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS |
2514 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
2515 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
2516 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
2517 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
2518 | //BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
2519 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2520 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2521 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2522 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2523 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2524 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2525 | //BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 |
2526 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
2527 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
2528 | //BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 |
2529 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
2530 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
2531 | //BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
2532 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2533 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2534 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2535 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2536 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2537 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2538 | //BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS |
2539 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
2540 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
2541 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
2542 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
2543 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
2544 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
2545 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
2546 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
2547 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
2548 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
2549 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
2550 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
2551 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
2552 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
2553 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
2554 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
2555 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
2556 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
2557 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
2558 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
2559 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
2560 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
2561 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
2562 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
2563 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
2564 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
2565 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
2566 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
2567 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
2568 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
2569 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
2570 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
2571 | //BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK |
2572 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
2573 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
2574 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
2575 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
2576 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
2577 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
2578 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
2579 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
2580 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
2581 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
2582 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
2583 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
2584 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
2585 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
2586 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
2587 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
2588 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
2589 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
2590 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
2591 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
2592 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
2593 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
2594 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
2595 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
2596 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
2597 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
2598 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
2599 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
2600 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
2601 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
2602 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
2603 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
2604 | //BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY |
2605 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
2606 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
2607 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
2608 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
2609 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
2610 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
2611 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
2612 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
2613 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
2614 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
2615 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
2616 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
2617 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
2618 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
2619 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
2620 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
2621 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
2622 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
2623 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
2624 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
2625 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
2626 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
2627 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
2628 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
2629 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
2630 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
2631 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
2632 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
2633 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
2634 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
2635 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
2636 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
2637 | //BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS |
2638 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
2639 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
2640 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
2641 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
2642 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
2643 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
2644 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
2645 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
2646 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
2647 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
2648 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
2649 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
2650 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
2651 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
2652 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
2653 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
2654 | //BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK |
2655 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
2656 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
2657 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
2658 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
2659 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
2660 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
2661 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
2662 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
2663 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
2664 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
2665 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
2666 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
2667 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
2668 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
2669 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
2670 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
2671 | //BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL |
2672 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
2673 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
2674 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
2675 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
2676 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
2677 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
2678 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
2679 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
2680 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
2681 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
2682 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
2683 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
2684 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
2685 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
2686 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
2687 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
2688 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 |
2689 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
2690 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
2691 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 |
2692 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
2693 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
2694 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 |
2695 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
2696 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
2697 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 |
2698 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
2699 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
2700 | //BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD |
2701 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
2702 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
2703 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
2704 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
2705 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
2706 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
2707 | //BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS |
2708 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
2709 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
2710 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
2711 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
2712 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
2713 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
2714 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
2715 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
2716 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
2717 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
2718 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
2719 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
2720 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
2721 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
2722 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
2723 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
2724 | //BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID |
2725 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
2726 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
2727 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
2728 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
2729 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 |
2730 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
2731 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
2732 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 |
2733 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
2734 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
2735 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 |
2736 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
2737 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
2738 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 |
2739 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
2740 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
2741 | //BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST |
2742 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2743 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2744 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2745 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2746 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2747 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2748 | //BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 |
2749 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
2750 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
2751 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
2752 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
2753 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
2754 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
2755 | //BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS |
2756 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
2757 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
2758 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
2759 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
2760 | //BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL |
2761 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2762 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2763 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2764 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2765 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2766 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2767 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2768 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2769 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2770 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2771 | //BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL |
2772 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2773 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2774 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2775 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2776 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2777 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2778 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2779 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2780 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2781 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2782 | //BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL |
2783 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2784 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2785 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2786 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2787 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2788 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2789 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2790 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2791 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2792 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2793 | //BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL |
2794 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2795 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2796 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2797 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2798 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2799 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2800 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2801 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2802 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2803 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2804 | //BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL |
2805 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2806 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2807 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2808 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2809 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2810 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2811 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2812 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2813 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2814 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2815 | //BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL |
2816 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2817 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2818 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2819 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2820 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2821 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2822 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2823 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2824 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2825 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2826 | //BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL |
2827 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2828 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2829 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2830 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2831 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2832 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2833 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2834 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2835 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2836 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2837 | //BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL |
2838 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2839 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2840 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2841 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2842 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2843 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2844 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2845 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2846 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2847 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2848 | //BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL |
2849 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2850 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2851 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2852 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2853 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2854 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2855 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2856 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2857 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2858 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2859 | //BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL |
2860 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2861 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2862 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2863 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2864 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2865 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2866 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2867 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2868 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2869 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2870 | //BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL |
2871 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2872 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2873 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2874 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2875 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2876 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2877 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2878 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2879 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2880 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2881 | //BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL |
2882 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2883 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2884 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2885 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2886 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2887 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2888 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2889 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2890 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2891 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2892 | //BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL |
2893 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2894 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2895 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2896 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2897 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2898 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2899 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2900 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2901 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2902 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2903 | //BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL |
2904 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2905 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2906 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2907 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2908 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2909 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2910 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2911 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2912 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2913 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2914 | //BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL |
2915 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2916 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2917 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2918 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2919 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2920 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2921 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2922 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2923 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2924 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2925 | //BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL |
2926 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
2927 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
2928 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
2929 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
2930 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
2931 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
2932 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
2933 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
2934 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
2935 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
2936 | //BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST |
2937 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2938 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2939 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2940 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2941 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2942 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2943 | //BIF_CFG_DEV1_RC0_PCIE_ACS_CAP |
2944 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
2945 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
2946 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
2947 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
2948 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
2949 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
2950 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
2951 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
2952 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
2953 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
2954 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
2955 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
2956 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
2957 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
2958 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
2959 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
2960 | //BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL |
2961 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
2962 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
2963 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
2964 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
2965 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
2966 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
2967 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
2968 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
2969 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
2970 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
2971 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
2972 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
2973 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
2974 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
2975 | |
2976 | |
2977 | // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
2978 | //NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID |
2979 | #define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
2980 | #define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 |
2981 | #define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL |
2982 | #define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L |
2983 | //NB_PCIEDUMMY0_0_STATUS_COMMAND |
2984 | #define NB_PCIEDUMMY0_0_STATUS_COMMAND__COMMAND__SHIFT 0x0 |
2985 | #define NB_PCIEDUMMY0_0_STATUS_COMMAND__STATUS__SHIFT 0x10 |
2986 | #define NB_PCIEDUMMY0_0_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL |
2987 | #define NB_PCIEDUMMY0_0_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L |
2988 | //NB_PCIEDUMMY0_0_CLASS_CODE_REVID |
2989 | #define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__REVID__SHIFT 0x0 |
2990 | #define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 |
2991 | #define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__REVID_MASK 0x000000FFL |
2992 | #define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L |
2993 | //NB_PCIEDUMMY0_0_HEADER_TYPE |
2994 | #define NB_PCIEDUMMY0_0_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 |
2995 | #define NB_PCIEDUMMY0_0_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 |
2996 | #define NB_PCIEDUMMY0_0_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L |
2997 | #define NB_PCIEDUMMY0_0_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L |
2998 | //NB_PCIEDUMMY0_0_HEADER_TYPE_W |
2999 | #define NB_PCIEDUMMY0_0_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 |
3000 | #define NB_PCIEDUMMY0_0_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L |
3001 | |
3002 | |
3003 | // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
3004 | //NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID |
3005 | #define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
3006 | #define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 |
3007 | #define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL |
3008 | #define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L |
3009 | //NB_PCIEDUMMY1_0_STATUS_COMMAND |
3010 | #define NB_PCIEDUMMY1_0_STATUS_COMMAND__COMMAND__SHIFT 0x0 |
3011 | #define NB_PCIEDUMMY1_0_STATUS_COMMAND__STATUS__SHIFT 0x10 |
3012 | #define NB_PCIEDUMMY1_0_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL |
3013 | #define NB_PCIEDUMMY1_0_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L |
3014 | //NB_PCIEDUMMY1_0_CLASS_CODE_REVID |
3015 | #define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__REVID__SHIFT 0x0 |
3016 | #define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 |
3017 | #define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__REVID_MASK 0x000000FFL |
3018 | #define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L |
3019 | //NB_PCIEDUMMY1_0_HEADER_TYPE |
3020 | #define NB_PCIEDUMMY1_0_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 |
3021 | #define NB_PCIEDUMMY1_0_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 |
3022 | #define NB_PCIEDUMMY1_0_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L |
3023 | #define NB_PCIEDUMMY1_0_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L |
3024 | //NB_PCIEDUMMY1_0_HEADER_TYPE_W |
3025 | #define NB_PCIEDUMMY1_0_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 |
3026 | #define NB_PCIEDUMMY1_0_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L |
3027 | |
3028 | |
3029 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
3030 | //VENDOR_ID |
3031 | #define VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
3032 | #define VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
3033 | //DEVICE_ID |
3034 | #define DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
3035 | #define DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
3036 | //COMMAND |
3037 | #define COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
3038 | #define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
3039 | #define COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
3040 | #define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
3041 | #define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
3042 | #define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
3043 | #define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
3044 | #define COMMAND__AD_STEPPING__SHIFT 0x7 |
3045 | #define COMMAND__SERR_EN__SHIFT 0x8 |
3046 | #define COMMAND__FAST_B2B_EN__SHIFT 0x9 |
3047 | #define COMMAND__INT_DIS__SHIFT 0xa |
3048 | #define COMMAND__IO_ACCESS_EN_MASK 0x0001L |
3049 | #define COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
3050 | #define COMMAND__BUS_MASTER_EN_MASK 0x0004L |
3051 | #define COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
3052 | #define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
3053 | #define COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
3054 | #define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
3055 | #define COMMAND__AD_STEPPING_MASK 0x0080L |
3056 | #define COMMAND__SERR_EN_MASK 0x0100L |
3057 | #define COMMAND__FAST_B2B_EN_MASK 0x0200L |
3058 | #define COMMAND__INT_DIS_MASK 0x0400L |
3059 | //STATUS |
3060 | #define STATUS__INT_STATUS__SHIFT 0x3 |
3061 | #define STATUS__CAP_LIST__SHIFT 0x4 |
3062 | #define STATUS__PCI_66_EN__SHIFT 0x5 |
3063 | #define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
3064 | #define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
3065 | #define STATUS__DEVSEL_TIMING__SHIFT 0x9 |
3066 | #define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
3067 | #define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
3068 | #define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
3069 | #define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
3070 | #define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
3071 | #define STATUS__INT_STATUS_MASK 0x0008L |
3072 | #define STATUS__CAP_LIST_MASK 0x0010L |
3073 | #define STATUS__PCI_66_EN_MASK 0x0020L |
3074 | #define STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
3075 | #define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
3076 | #define STATUS__DEVSEL_TIMING_MASK 0x0600L |
3077 | #define STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
3078 | #define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
3079 | #define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
3080 | #define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
3081 | #define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
3082 | //REVISION_ID |
3083 | #define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
3084 | #define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
3085 | #define REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
3086 | #define REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
3087 | //PROG_INTERFACE |
3088 | #define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
3089 | #define PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
3090 | //SUB_CLASS |
3091 | #define SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
3092 | #define SUB_CLASS__SUB_CLASS_MASK 0xFFL |
3093 | //BASE_CLASS |
3094 | #define BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
3095 | #define BASE_CLASS__BASE_CLASS_MASK 0xFFL |
3096 | //CACHE_LINE |
3097 | #define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
3098 | #define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
3099 | //LATENCY |
3100 | #define LATENCY__LATENCY_TIMER__SHIFT 0x0 |
3101 | #define LATENCY__LATENCY_TIMER_MASK 0xFFL |
3102 | //HEADER |
3103 | #define HEADER__HEADER_TYPE__SHIFT 0x0 |
3104 | #define HEADER__DEVICE_TYPE__SHIFT 0x7 |
3105 | #define HEADER__HEADER_TYPE_MASK 0x7FL |
3106 | #define HEADER__DEVICE_TYPE_MASK 0x80L |
3107 | //BIST |
3108 | #define BIST__BIST_COMP__SHIFT 0x0 |
3109 | #define BIST__BIST_STRT__SHIFT 0x6 |
3110 | #define BIST__BIST_CAP__SHIFT 0x7 |
3111 | #define BIST__BIST_COMP_MASK 0x0FL |
3112 | #define BIST__BIST_STRT_MASK 0x40L |
3113 | #define BIST__BIST_CAP_MASK 0x80L |
3114 | //BASE_ADDR_1 |
3115 | #define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
3116 | #define BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
3117 | //BASE_ADDR_2 |
3118 | #define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
3119 | #define BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
3120 | //BASE_ADDR_3 |
3121 | #define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
3122 | #define BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
3123 | //BASE_ADDR_4 |
3124 | #define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
3125 | #define BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
3126 | //BASE_ADDR_5 |
3127 | #define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
3128 | #define BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
3129 | //BASE_ADDR_6 |
3130 | #define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
3131 | #define BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
3132 | //ADAPTER_ID |
3133 | #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
3134 | #define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
3135 | #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
3136 | #define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
3137 | //ROM_BASE_ADDR |
3138 | #define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
3139 | #define ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
3140 | //CAP_PTR |
3141 | #define CAP_PTR__CAP_PTR__SHIFT 0x0 |
3142 | #define CAP_PTR__CAP_PTR_MASK 0x000000FFL |
3143 | //INTERRUPT_LINE |
3144 | #define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
3145 | #define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
3146 | //INTERRUPT_PIN |
3147 | #define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
3148 | #define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
3149 | //MIN_GRANT |
3150 | #define MIN_GRANT__MIN_GNT__SHIFT 0x0 |
3151 | #define MIN_GRANT__MIN_GNT_MASK 0xFFL |
3152 | //MAX_LATENCY |
3153 | #define MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
3154 | #define MAX_LATENCY__MAX_LAT_MASK 0xFFL |
3155 | //VENDOR_CAP_LIST |
3156 | #define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
3157 | #define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3158 | #define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
3159 | #define VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
3160 | #define VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
3161 | #define VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
3162 | //ADAPTER_ID_W |
3163 | #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
3164 | #define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
3165 | #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
3166 | #define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
3167 | //PMI_CAP_LIST |
3168 | #define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
3169 | #define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3170 | #define PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
3171 | #define PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3172 | //PMI_CAP |
3173 | #define PMI_CAP__VERSION__SHIFT 0x0 |
3174 | #define PMI_CAP__PME_CLOCK__SHIFT 0x3 |
3175 | #define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
3176 | #define PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
3177 | #define PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
3178 | #define PMI_CAP__D2_SUPPORT__SHIFT 0xa |
3179 | #define PMI_CAP__PME_SUPPORT__SHIFT 0xb |
3180 | #define PMI_CAP__VERSION_MASK 0x0007L |
3181 | #define PMI_CAP__PME_CLOCK_MASK 0x0008L |
3182 | #define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
3183 | #define PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
3184 | #define PMI_CAP__D1_SUPPORT_MASK 0x0200L |
3185 | #define PMI_CAP__D2_SUPPORT_MASK 0x0400L |
3186 | #define PMI_CAP__PME_SUPPORT_MASK 0xF800L |
3187 | //PMI_STATUS_CNTL |
3188 | #define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
3189 | #define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
3190 | #define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
3191 | #define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
3192 | #define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
3193 | #define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
3194 | #define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
3195 | #define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
3196 | #define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
3197 | #define PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
3198 | #define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
3199 | #define PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
3200 | #define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
3201 | #define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
3202 | #define PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
3203 | #define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
3204 | #define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
3205 | #define PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
3206 | //PCIE_CAP_LIST |
3207 | #define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
3208 | #define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3209 | #define PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
3210 | #define PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3211 | //PCIE_CAP |
3212 | #define PCIE_CAP__VERSION__SHIFT 0x0 |
3213 | #define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
3214 | #define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
3215 | #define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
3216 | #define PCIE_CAP__VERSION_MASK 0x000FL |
3217 | #define PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
3218 | #define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
3219 | #define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
3220 | //DEVICE_CAP |
3221 | #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
3222 | #define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
3223 | #define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
3224 | #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
3225 | #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
3226 | #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
3227 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
3228 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
3229 | #define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
3230 | #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
3231 | #define DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
3232 | #define DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
3233 | #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
3234 | #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
3235 | #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
3236 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
3237 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
3238 | #define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
3239 | //DEVICE_CNTL |
3240 | #define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
3241 | #define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
3242 | #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
3243 | #define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
3244 | #define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
3245 | #define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
3246 | #define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
3247 | #define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
3248 | #define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
3249 | #define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
3250 | #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
3251 | #define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
3252 | #define DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
3253 | #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
3254 | #define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
3255 | #define DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
3256 | #define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
3257 | #define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
3258 | #define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
3259 | #define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
3260 | #define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
3261 | #define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
3262 | #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
3263 | #define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
3264 | //DEVICE_STATUS |
3265 | #define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
3266 | #define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
3267 | #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
3268 | #define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
3269 | #define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
3270 | #define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
3271 | #define DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
3272 | #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
3273 | #define DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
3274 | #define DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
3275 | #define DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
3276 | #define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
3277 | //LINK_CAP |
3278 | #define LINK_CAP__LINK_SPEED__SHIFT 0x0 |
3279 | #define LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
3280 | #define LINK_CAP__PM_SUPPORT__SHIFT 0xa |
3281 | #define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
3282 | #define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
3283 | #define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
3284 | #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
3285 | #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
3286 | #define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
3287 | #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
3288 | #define LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
3289 | #define LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
3290 | #define LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
3291 | #define LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
3292 | #define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
3293 | #define LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
3294 | #define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
3295 | #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
3296 | #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
3297 | #define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
3298 | #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
3299 | #define LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
3300 | //LINK_CNTL |
3301 | #define LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
3302 | #define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
3303 | #define LINK_CNTL__LINK_DIS__SHIFT 0x4 |
3304 | #define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
3305 | #define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
3306 | #define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
3307 | #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
3308 | #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
3309 | #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
3310 | #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
3311 | #define LINK_CNTL__PM_CONTROL_MASK 0x0003L |
3312 | #define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
3313 | #define LINK_CNTL__LINK_DIS_MASK 0x0010L |
3314 | #define LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
3315 | #define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
3316 | #define LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
3317 | #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
3318 | #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
3319 | #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
3320 | #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
3321 | //LINK_STATUS |
3322 | #define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
3323 | #define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
3324 | #define LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
3325 | #define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
3326 | #define LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
3327 | #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
3328 | #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
3329 | #define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
3330 | #define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
3331 | #define LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
3332 | #define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
3333 | #define LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
3334 | #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
3335 | #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
3336 | //DEVICE_CAP2 |
3337 | #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
3338 | #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
3339 | #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
3340 | #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
3341 | #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
3342 | #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
3343 | #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
3344 | #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
3345 | #define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
3346 | #define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
3347 | #define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
3348 | #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
3349 | #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
3350 | #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
3351 | #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
3352 | #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
3353 | #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
3354 | #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
3355 | #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
3356 | #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
3357 | #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
3358 | #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
3359 | #define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
3360 | #define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
3361 | #define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
3362 | #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
3363 | #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
3364 | #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
3365 | //DEVICE_CNTL2 |
3366 | #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
3367 | #define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
3368 | #define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
3369 | #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
3370 | #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
3371 | #define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
3372 | #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
3373 | #define DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
3374 | #define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
3375 | #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
3376 | #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
3377 | #define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
3378 | #define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
3379 | #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
3380 | #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
3381 | #define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
3382 | #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
3383 | #define DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
3384 | #define DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
3385 | #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
3386 | //DEVICE_STATUS2 |
3387 | #define DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
3388 | #define DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
3389 | //LINK_CAP2 |
3390 | #define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
3391 | #define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
3392 | #define LINK_CAP2__RESERVED__SHIFT 0x9 |
3393 | #define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
3394 | #define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
3395 | #define LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
3396 | //LINK_CNTL2 |
3397 | #define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
3398 | #define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
3399 | #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
3400 | #define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
3401 | #define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
3402 | #define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
3403 | #define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
3404 | #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
3405 | #define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
3406 | #define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
3407 | #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
3408 | #define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
3409 | #define LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
3410 | #define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
3411 | #define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
3412 | #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
3413 | //LINK_STATUS2 |
3414 | #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
3415 | #define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
3416 | #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
3417 | #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
3418 | #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
3419 | #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
3420 | #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
3421 | #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
3422 | #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
3423 | #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
3424 | #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
3425 | #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
3426 | //SLOT_CAP2 |
3427 | #define SLOT_CAP2__RESERVED__SHIFT 0x0 |
3428 | #define SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
3429 | //SLOT_CNTL2 |
3430 | #define SLOT_CNTL2__RESERVED__SHIFT 0x0 |
3431 | #define SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
3432 | //SLOT_STATUS2 |
3433 | #define SLOT_STATUS2__RESERVED__SHIFT 0x0 |
3434 | #define SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
3435 | //MSI_CAP_LIST |
3436 | #define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
3437 | #define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3438 | #define MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
3439 | #define MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3440 | //MSI_MSG_CNTL |
3441 | #define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
3442 | #define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
3443 | #define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
3444 | #define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
3445 | #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
3446 | #define MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
3447 | #define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
3448 | #define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
3449 | #define MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
3450 | #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
3451 | //MSI_MSG_ADDR_LO |
3452 | #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
3453 | #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
3454 | //MSI_MSG_ADDR_HI |
3455 | #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
3456 | #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
3457 | //MSI_MSG_DATA |
3458 | #define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
3459 | #define MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
3460 | //MSI_MASK |
3461 | #define MSI_MASK__MSI_MASK__SHIFT 0x0 |
3462 | #define MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
3463 | //MSI_MSG_DATA_64 |
3464 | #define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
3465 | #define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
3466 | //MSI_MASK_64 |
3467 | #define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
3468 | #define MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
3469 | //MSI_PENDING |
3470 | #define MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
3471 | #define MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
3472 | //MSI_PENDING_64 |
3473 | #define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
3474 | #define MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
3475 | //MSIX_CAP_LIST |
3476 | #define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
3477 | #define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3478 | #define MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
3479 | #define MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3480 | //MSIX_MSG_CNTL |
3481 | #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
3482 | #define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
3483 | #define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
3484 | #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
3485 | #define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
3486 | #define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
3487 | //MSIX_TABLE |
3488 | #define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
3489 | #define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
3490 | #define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
3491 | #define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
3492 | //MSIX_PBA |
3493 | #define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
3494 | #define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
3495 | #define MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
3496 | #define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
3497 | //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
3498 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3499 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3500 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3501 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3502 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3503 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3504 | //PCIE_VENDOR_SPECIFIC_HDR |
3505 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
3506 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
3507 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
3508 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
3509 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
3510 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
3511 | //PCIE_VENDOR_SPECIFIC1 |
3512 | #define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
3513 | #define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
3514 | //PCIE_VENDOR_SPECIFIC2 |
3515 | #define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
3516 | #define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
3517 | //PCIE_VC_ENH_CAP_LIST |
3518 | #define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3519 | #define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3520 | #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3521 | #define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3522 | #define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3523 | #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3524 | //PCIE_PORT_VC_CAP_REG1 |
3525 | #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
3526 | #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
3527 | #define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
3528 | #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
3529 | #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
3530 | #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
3531 | #define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
3532 | #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
3533 | //PCIE_PORT_VC_CAP_REG2 |
3534 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
3535 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
3536 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
3537 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
3538 | //PCIE_PORT_VC_CNTL |
3539 | #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
3540 | #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
3541 | #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
3542 | #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
3543 | //PCIE_PORT_VC_STATUS |
3544 | #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
3545 | #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
3546 | //PCIE_VC0_RESOURCE_CAP |
3547 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
3548 | #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
3549 | #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
3550 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
3551 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
3552 | #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
3553 | #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
3554 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
3555 | //PCIE_VC0_RESOURCE_CNTL |
3556 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
3557 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
3558 | #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
3559 | #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
3560 | #define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
3561 | #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
3562 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
3563 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
3564 | #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
3565 | #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
3566 | #define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
3567 | #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
3568 | //PCIE_VC0_RESOURCE_STATUS |
3569 | #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
3570 | #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
3571 | #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
3572 | #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
3573 | //PCIE_VC1_RESOURCE_CAP |
3574 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
3575 | #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
3576 | #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
3577 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
3578 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
3579 | #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
3580 | #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
3581 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
3582 | //PCIE_VC1_RESOURCE_CNTL |
3583 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
3584 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
3585 | #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
3586 | #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
3587 | #define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
3588 | #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
3589 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
3590 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
3591 | #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
3592 | #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
3593 | #define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
3594 | #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
3595 | //PCIE_VC1_RESOURCE_STATUS |
3596 | #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
3597 | #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
3598 | #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
3599 | #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
3600 | //PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
3601 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3602 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3603 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3604 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3605 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3606 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3607 | //PCIE_DEV_SERIAL_NUM_DW1 |
3608 | #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
3609 | #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
3610 | //PCIE_DEV_SERIAL_NUM_DW2 |
3611 | #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
3612 | #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
3613 | //PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
3614 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3615 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3616 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3617 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3618 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3619 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3620 | //PCIE_UNCORR_ERR_STATUS |
3621 | #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
3622 | #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
3623 | #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
3624 | #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
3625 | #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
3626 | #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
3627 | #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
3628 | #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
3629 | #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
3630 | #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
3631 | #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
3632 | #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
3633 | #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
3634 | #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
3635 | #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
3636 | #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
3637 | #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
3638 | #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
3639 | #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
3640 | #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
3641 | #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
3642 | #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
3643 | #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
3644 | #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
3645 | #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
3646 | #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
3647 | #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
3648 | #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
3649 | #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
3650 | #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
3651 | #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
3652 | #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
3653 | //PCIE_UNCORR_ERR_MASK |
3654 | #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
3655 | #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
3656 | #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
3657 | #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
3658 | #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
3659 | #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
3660 | #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
3661 | #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
3662 | #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
3663 | #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
3664 | #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
3665 | #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
3666 | #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
3667 | #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
3668 | #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
3669 | #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
3670 | #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
3671 | #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
3672 | #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
3673 | #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
3674 | #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
3675 | #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
3676 | #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
3677 | #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
3678 | #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
3679 | #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
3680 | #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
3681 | #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
3682 | #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
3683 | #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
3684 | #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
3685 | #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
3686 | //PCIE_UNCORR_ERR_SEVERITY |
3687 | #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
3688 | #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
3689 | #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
3690 | #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
3691 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
3692 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
3693 | #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
3694 | #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
3695 | #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
3696 | #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
3697 | #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
3698 | #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
3699 | #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
3700 | #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
3701 | #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
3702 | #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
3703 | #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
3704 | #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
3705 | #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
3706 | #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
3707 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
3708 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
3709 | #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
3710 | #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
3711 | #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
3712 | #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
3713 | #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
3714 | #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
3715 | #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
3716 | #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
3717 | #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
3718 | #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
3719 | //PCIE_CORR_ERR_STATUS |
3720 | #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
3721 | #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
3722 | #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
3723 | #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
3724 | #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
3725 | #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
3726 | #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
3727 | #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
3728 | #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
3729 | #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
3730 | #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
3731 | #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
3732 | #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
3733 | #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
3734 | #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
3735 | #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
3736 | //PCIE_CORR_ERR_MASK |
3737 | #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
3738 | #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
3739 | #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
3740 | #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
3741 | #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
3742 | #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
3743 | #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
3744 | #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
3745 | #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
3746 | #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
3747 | #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
3748 | #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
3749 | #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
3750 | #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
3751 | #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
3752 | #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
3753 | //PCIE_ADV_ERR_CAP_CNTL |
3754 | #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
3755 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
3756 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
3757 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
3758 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
3759 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
3760 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
3761 | #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
3762 | #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
3763 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
3764 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
3765 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
3766 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
3767 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
3768 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
3769 | #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
3770 | //PCIE_HDR_LOG0 |
3771 | #define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
3772 | #define PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
3773 | //PCIE_HDR_LOG1 |
3774 | #define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
3775 | #define PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
3776 | //PCIE_HDR_LOG2 |
3777 | #define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
3778 | #define PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
3779 | //PCIE_HDR_LOG3 |
3780 | #define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
3781 | #define PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
3782 | //PCIE_TLP_PREFIX_LOG0 |
3783 | #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
3784 | #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
3785 | //PCIE_TLP_PREFIX_LOG1 |
3786 | #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
3787 | #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
3788 | //PCIE_TLP_PREFIX_LOG2 |
3789 | #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
3790 | #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
3791 | //PCIE_TLP_PREFIX_LOG3 |
3792 | #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
3793 | #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
3794 | //PCIE_BAR_ENH_CAP_LIST |
3795 | #define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3796 | #define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3797 | #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3798 | #define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3799 | #define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3800 | #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3801 | //PCIE_BAR1_CAP |
3802 | #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
3803 | #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
3804 | //PCIE_BAR1_CNTL |
3805 | #define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
3806 | #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
3807 | #define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
3808 | #define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
3809 | #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
3810 | #define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
3811 | //PCIE_BAR2_CAP |
3812 | #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
3813 | #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
3814 | //PCIE_BAR2_CNTL |
3815 | #define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
3816 | #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
3817 | #define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
3818 | #define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
3819 | #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
3820 | #define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
3821 | //PCIE_BAR3_CAP |
3822 | #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
3823 | #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
3824 | //PCIE_BAR3_CNTL |
3825 | #define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
3826 | #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
3827 | #define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
3828 | #define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
3829 | #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
3830 | #define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
3831 | //PCIE_BAR4_CAP |
3832 | #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
3833 | #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
3834 | //PCIE_BAR4_CNTL |
3835 | #define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
3836 | #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
3837 | #define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
3838 | #define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
3839 | #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
3840 | #define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
3841 | //PCIE_BAR5_CAP |
3842 | #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
3843 | #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
3844 | //PCIE_BAR5_CNTL |
3845 | #define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
3846 | #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
3847 | #define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
3848 | #define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
3849 | #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
3850 | #define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
3851 | //PCIE_BAR6_CAP |
3852 | #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
3853 | #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
3854 | //PCIE_BAR6_CNTL |
3855 | #define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
3856 | #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
3857 | #define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
3858 | #define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
3859 | #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
3860 | #define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
3861 | //PCIE_PWR_BUDGET_ENH_CAP_LIST |
3862 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3863 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3864 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3865 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3866 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3867 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3868 | //PCIE_PWR_BUDGET_DATA_SELECT |
3869 | #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
3870 | #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
3871 | //PCIE_PWR_BUDGET_DATA |
3872 | #define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
3873 | #define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
3874 | #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
3875 | #define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
3876 | #define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
3877 | #define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
3878 | #define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
3879 | #define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
3880 | #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
3881 | #define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
3882 | #define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
3883 | #define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
3884 | //PCIE_PWR_BUDGET_CAP |
3885 | #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
3886 | #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
3887 | //PCIE_DPA_ENH_CAP_LIST |
3888 | #define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3889 | #define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3890 | #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3891 | #define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3892 | #define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3893 | #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3894 | //PCIE_DPA_CAP |
3895 | #define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
3896 | #define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
3897 | #define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
3898 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
3899 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
3900 | #define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
3901 | #define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
3902 | #define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
3903 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
3904 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
3905 | //PCIE_DPA_LATENCY_INDICATOR |
3906 | #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
3907 | #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
3908 | //PCIE_DPA_STATUS |
3909 | #define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
3910 | #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
3911 | #define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
3912 | #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
3913 | //PCIE_DPA_CNTL |
3914 | #define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
3915 | #define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
3916 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
3917 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3918 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3919 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
3920 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3921 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3922 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
3923 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3924 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3925 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
3926 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3927 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3928 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
3929 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3930 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3931 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
3932 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3933 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3934 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
3935 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3936 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3937 | //PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
3938 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
3939 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
3940 | //PCIE_SECONDARY_ENH_CAP_LIST |
3941 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3942 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3943 | #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3944 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3945 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3946 | #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3947 | //PCIE_LINK_CNTL3 |
3948 | #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
3949 | #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
3950 | #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
3951 | #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
3952 | #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
3953 | #define PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
3954 | //PCIE_LANE_ERROR_STATUS |
3955 | #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
3956 | #define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
3957 | #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
3958 | #define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
3959 | //PCIE_LANE_0_EQUALIZATION_CNTL |
3960 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
3961 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
3962 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
3963 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
3964 | #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
3965 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
3966 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
3967 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
3968 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
3969 | #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
3970 | //PCIE_LANE_1_EQUALIZATION_CNTL |
3971 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
3972 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
3973 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
3974 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
3975 | #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
3976 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
3977 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
3978 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
3979 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
3980 | #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
3981 | //PCIE_LANE_2_EQUALIZATION_CNTL |
3982 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
3983 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
3984 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
3985 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
3986 | #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
3987 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
3988 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
3989 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
3990 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
3991 | #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
3992 | //PCIE_LANE_3_EQUALIZATION_CNTL |
3993 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
3994 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
3995 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
3996 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
3997 | #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
3998 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
3999 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4000 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4001 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4002 | #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4003 | //PCIE_LANE_4_EQUALIZATION_CNTL |
4004 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4005 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4006 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4007 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4008 | #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4009 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4010 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4011 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4012 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4013 | #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4014 | //PCIE_LANE_5_EQUALIZATION_CNTL |
4015 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4016 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4017 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4018 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4019 | #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4020 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4021 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4022 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4023 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4024 | #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4025 | //PCIE_LANE_6_EQUALIZATION_CNTL |
4026 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4027 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4028 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4029 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4030 | #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4031 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4032 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4033 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4034 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4035 | #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4036 | //PCIE_LANE_7_EQUALIZATION_CNTL |
4037 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4038 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4039 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4040 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4041 | #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4042 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4043 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4044 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4045 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4046 | #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4047 | //PCIE_LANE_8_EQUALIZATION_CNTL |
4048 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4049 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4050 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4051 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4052 | #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4053 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4054 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4055 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4056 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4057 | #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4058 | //PCIE_LANE_9_EQUALIZATION_CNTL |
4059 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4060 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4061 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4062 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4063 | #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4064 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4065 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4066 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4067 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4068 | #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4069 | //PCIE_LANE_10_EQUALIZATION_CNTL |
4070 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4071 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4072 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4073 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4074 | #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4075 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4076 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4077 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4078 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4079 | #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4080 | //PCIE_LANE_11_EQUALIZATION_CNTL |
4081 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4082 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4083 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4084 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4085 | #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4086 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4087 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4088 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4089 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4090 | #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4091 | //PCIE_LANE_12_EQUALIZATION_CNTL |
4092 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4093 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4094 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4095 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4096 | #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4097 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4098 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4099 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4100 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4101 | #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4102 | //PCIE_LANE_13_EQUALIZATION_CNTL |
4103 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4104 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4105 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4106 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4107 | #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4108 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4109 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4110 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4111 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4112 | #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4113 | //PCIE_LANE_14_EQUALIZATION_CNTL |
4114 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4115 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4116 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4117 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4118 | #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4119 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4120 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4121 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4122 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4123 | #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4124 | //PCIE_LANE_15_EQUALIZATION_CNTL |
4125 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
4126 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
4127 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
4128 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
4129 | #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
4130 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
4131 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
4132 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
4133 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
4134 | #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
4135 | //PCIE_ACS_ENH_CAP_LIST |
4136 | #define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4137 | #define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4138 | #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4139 | #define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4140 | #define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4141 | #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4142 | //PCIE_ACS_CAP |
4143 | #define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
4144 | #define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
4145 | #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
4146 | #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
4147 | #define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
4148 | #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
4149 | #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
4150 | #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
4151 | #define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
4152 | #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
4153 | #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
4154 | #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
4155 | #define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
4156 | #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
4157 | #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
4158 | #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
4159 | //PCIE_ACS_CNTL |
4160 | #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
4161 | #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
4162 | #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
4163 | #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
4164 | #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
4165 | #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
4166 | #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
4167 | #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
4168 | #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
4169 | #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
4170 | #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
4171 | #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
4172 | #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
4173 | #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
4174 | //PCIE_ATS_ENH_CAP_LIST |
4175 | #define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4176 | #define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4177 | #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4178 | #define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4179 | #define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4180 | #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4181 | //PCIE_ATS_CAP |
4182 | #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
4183 | #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
4184 | #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
4185 | #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
4186 | #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
4187 | #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
4188 | //PCIE_ATS_CNTL |
4189 | #define PCIE_ATS_CNTL__STU__SHIFT 0x0 |
4190 | #define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
4191 | #define PCIE_ATS_CNTL__STU_MASK 0x001FL |
4192 | #define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
4193 | //PCIE_PAGE_REQ_ENH_CAP_LIST |
4194 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4195 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4196 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4197 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4198 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4199 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4200 | //PCIE_PAGE_REQ_CNTL |
4201 | #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
4202 | #define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
4203 | #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
4204 | #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
4205 | //PCIE_PAGE_REQ_STATUS |
4206 | #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
4207 | #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
4208 | #define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
4209 | #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
4210 | #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
4211 | #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
4212 | #define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
4213 | #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
4214 | //PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
4215 | #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
4216 | #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
4217 | //PCIE_OUTSTAND_PAGE_REQ_ALLOC |
4218 | #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
4219 | #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
4220 | //PCIE_PASID_ENH_CAP_LIST |
4221 | #define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4222 | #define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4223 | #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4224 | #define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4225 | #define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4226 | #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4227 | //PCIE_PASID_CAP |
4228 | #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
4229 | #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
4230 | #define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
4231 | #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
4232 | #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
4233 | #define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
4234 | //PCIE_PASID_CNTL |
4235 | #define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
4236 | #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
4237 | #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
4238 | #define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
4239 | #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
4240 | #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
4241 | //PCIE_TPH_REQR_ENH_CAP_LIST |
4242 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4243 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4244 | #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4245 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4246 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4247 | #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4248 | //PCIE_TPH_REQR_CAP |
4249 | #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
4250 | #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
4251 | #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
4252 | #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
4253 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
4254 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
4255 | #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
4256 | #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
4257 | #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
4258 | #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
4259 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
4260 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
4261 | //PCIE_TPH_REQR_CNTL |
4262 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
4263 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
4264 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
4265 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
4266 | //PCIE_MC_ENH_CAP_LIST |
4267 | #define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4268 | #define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4269 | #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4270 | #define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4271 | #define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4272 | #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4273 | //PCIE_MC_CAP |
4274 | #define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
4275 | #define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
4276 | #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
4277 | #define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
4278 | #define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
4279 | #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
4280 | //PCIE_MC_CNTL |
4281 | #define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
4282 | #define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
4283 | #define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
4284 | #define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
4285 | //PCIE_MC_ADDR0 |
4286 | #define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
4287 | #define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
4288 | #define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
4289 | #define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
4290 | //PCIE_MC_ADDR1 |
4291 | #define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
4292 | #define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
4293 | //PCIE_MC_RCV0 |
4294 | #define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
4295 | #define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
4296 | //PCIE_MC_RCV1 |
4297 | #define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
4298 | #define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
4299 | //PCIE_MC_BLOCK_ALL0 |
4300 | #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
4301 | #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
4302 | //PCIE_MC_BLOCK_ALL1 |
4303 | #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
4304 | #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
4305 | //PCIE_MC_BLOCK_UNTRANSLATED_0 |
4306 | #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
4307 | #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
4308 | //PCIE_MC_BLOCK_UNTRANSLATED_1 |
4309 | #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
4310 | #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
4311 | //PCIE_LTR_ENH_CAP_LIST |
4312 | #define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4313 | #define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4314 | #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4315 | #define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4316 | #define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4317 | #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4318 | //PCIE_LTR_CAP |
4319 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
4320 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
4321 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
4322 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
4323 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
4324 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
4325 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
4326 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
4327 | //PCIE_ARI_ENH_CAP_LIST |
4328 | #define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4329 | #define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4330 | #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4331 | #define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4332 | #define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4333 | #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4334 | //PCIE_ARI_CAP |
4335 | #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
4336 | #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
4337 | #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
4338 | #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
4339 | #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
4340 | #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
4341 | //PCIE_ARI_CNTL |
4342 | #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
4343 | #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
4344 | #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
4345 | #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
4346 | #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
4347 | #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
4348 | //PCIE_SRIOV_ENH_CAP_LIST |
4349 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4350 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4351 | #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4352 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4353 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4354 | #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4355 | //PCIE_SRIOV_CAP |
4356 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
4357 | #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
4358 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
4359 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
4360 | #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
4361 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
4362 | //PCIE_SRIOV_CONTROL |
4363 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
4364 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
4365 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
4366 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
4367 | #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
4368 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
4369 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
4370 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
4371 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
4372 | #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
4373 | //PCIE_SRIOV_STATUS |
4374 | #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
4375 | #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
4376 | //PCIE_SRIOV_INITIAL_VFS |
4377 | #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
4378 | #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
4379 | //PCIE_SRIOV_TOTAL_VFS |
4380 | #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
4381 | #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
4382 | //PCIE_SRIOV_NUM_VFS |
4383 | #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
4384 | #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
4385 | //PCIE_SRIOV_FUNC_DEP_LINK |
4386 | #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
4387 | #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
4388 | //PCIE_SRIOV_FIRST_VF_OFFSET |
4389 | #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
4390 | #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
4391 | //PCIE_SRIOV_VF_STRIDE |
4392 | #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
4393 | #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
4394 | //PCIE_SRIOV_VF_DEVICE_ID |
4395 | #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
4396 | #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
4397 | //PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
4398 | #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
4399 | #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
4400 | //PCIE_SRIOV_SYSTEM_PAGE_SIZE |
4401 | #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
4402 | #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
4403 | //PCIE_SRIOV_VF_BASE_ADDR_0 |
4404 | #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
4405 | #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
4406 | //PCIE_SRIOV_VF_BASE_ADDR_1 |
4407 | #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
4408 | #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
4409 | //PCIE_SRIOV_VF_BASE_ADDR_2 |
4410 | #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
4411 | #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
4412 | //PCIE_SRIOV_VF_BASE_ADDR_3 |
4413 | #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
4414 | #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
4415 | //PCIE_SRIOV_VF_BASE_ADDR_4 |
4416 | #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
4417 | #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
4418 | //PCIE_SRIOV_VF_BASE_ADDR_5 |
4419 | #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
4420 | #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
4421 | //PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
4422 | #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
4423 | #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
4424 | #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
4425 | #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
4426 | //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
4427 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
4428 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
4429 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
4430 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
4431 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
4432 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
4433 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
4434 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
4435 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
4436 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
4437 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
4438 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
4439 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
4440 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
4441 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
4442 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
4443 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
4444 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
4445 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
4446 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
4447 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
4448 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
4449 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
4450 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
4451 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
4452 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
4453 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
4454 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
4455 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
4456 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
4457 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
4458 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
4459 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
4460 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
4461 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
4462 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
4463 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
4464 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
4465 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
4466 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
4467 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
4468 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
4469 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
4470 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
4471 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
4472 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
4473 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
4474 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
4475 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
4476 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
4477 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
4478 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
4479 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
4480 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
4481 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
4482 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
4483 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
4484 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
4485 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
4486 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
4487 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
4488 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
4489 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
4490 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
4491 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
4492 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
4493 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
4494 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
4495 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
4496 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
4497 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
4498 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
4499 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
4500 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
4501 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
4502 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
4503 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
4504 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
4505 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
4506 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
4507 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
4508 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
4509 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
4510 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
4511 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
4512 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
4513 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
4514 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
4515 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
4516 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
4517 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
4518 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
4519 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
4520 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
4521 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
4522 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
4523 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
4524 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
4525 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
4526 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
4527 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
4528 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
4529 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
4530 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
4531 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
4532 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
4533 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
4534 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
4535 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
4536 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
4537 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
4538 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
4539 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
4540 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
4541 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
4542 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
4543 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
4544 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
4545 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
4546 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
4547 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
4548 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
4549 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
4550 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
4551 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
4552 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
4553 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
4554 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
4555 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
4556 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
4557 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
4558 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
4559 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
4560 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
4561 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
4562 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
4563 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
4564 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
4565 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
4566 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
4567 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
4568 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
4569 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
4570 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
4571 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
4572 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
4573 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
4574 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
4575 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
4576 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
4577 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
4578 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
4579 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
4580 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
4581 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
4582 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
4583 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
4584 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
4585 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
4586 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
4587 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
4588 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
4589 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
4590 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
4591 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
4592 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
4593 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
4594 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
4595 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
4596 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
4597 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
4598 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
4599 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
4600 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
4601 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
4602 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
4603 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
4604 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
4605 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
4606 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
4607 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
4608 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
4609 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
4610 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
4611 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
4612 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
4613 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
4614 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
4615 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
4616 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
4617 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
4618 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
4619 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
4620 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
4621 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
4622 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
4623 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
4624 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
4625 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
4626 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
4627 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
4628 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
4629 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
4630 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
4631 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
4632 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
4633 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
4634 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
4635 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
4636 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
4637 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
4638 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
4639 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
4640 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
4641 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
4642 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
4643 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
4644 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
4645 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
4646 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
4647 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
4648 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
4649 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
4650 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
4651 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
4652 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
4653 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
4654 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
4655 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
4656 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
4657 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
4658 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
4659 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
4660 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
4661 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
4662 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
4663 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
4664 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
4665 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
4666 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
4667 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
4668 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
4669 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
4670 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
4671 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
4672 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
4673 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
4674 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
4675 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
4676 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
4677 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
4678 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
4679 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
4680 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
4681 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
4682 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
4683 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
4684 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
4685 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
4686 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
4687 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
4688 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
4689 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
4690 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
4691 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
4692 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
4693 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
4694 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
4695 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
4696 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
4697 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
4698 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
4699 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
4700 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
4701 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
4702 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
4703 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
4704 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
4705 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
4706 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
4707 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
4708 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
4709 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
4710 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
4711 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
4712 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
4713 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
4714 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
4715 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
4716 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
4717 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
4718 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
4719 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
4720 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
4721 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
4722 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
4723 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
4724 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
4725 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
4726 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
4727 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
4728 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
4729 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
4730 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
4731 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
4732 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
4733 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
4734 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
4735 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
4736 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
4737 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
4738 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
4739 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
4740 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
4741 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
4742 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
4743 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
4744 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
4745 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
4746 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
4747 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
4748 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
4749 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
4750 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
4751 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
4752 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
4753 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
4754 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
4755 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
4756 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
4757 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
4758 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
4759 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
4760 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
4761 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
4762 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
4763 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
4764 | //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
4765 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
4766 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
4767 | |
4768 | |
4769 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
4770 | //BIF_CFG_DEV0_EPF1_0_VENDOR_ID |
4771 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
4772 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
4773 | //BIF_CFG_DEV0_EPF1_0_DEVICE_ID |
4774 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
4775 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
4776 | //BIF_CFG_DEV0_EPF1_0_COMMAND |
4777 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
4778 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
4779 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
4780 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
4781 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
4782 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
4783 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
4784 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
4785 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
4786 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
4787 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
4788 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
4789 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
4790 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
4791 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
4792 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
4793 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
4794 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
4795 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
4796 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
4797 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
4798 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
4799 | //BIF_CFG_DEV0_EPF1_0_STATUS |
4800 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
4801 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
4802 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5 |
4803 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
4804 | #define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
4805 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
4806 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
4807 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
4808 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
4809 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
4810 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
4811 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
4812 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
4813 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L |
4814 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
4815 | #define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
4816 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
4817 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
4818 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
4819 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
4820 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
4821 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
4822 | //BIF_CFG_DEV0_EPF1_0_REVISION_ID |
4823 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
4824 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
4825 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
4826 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
4827 | //BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE |
4828 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
4829 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
4830 | //BIF_CFG_DEV0_EPF1_0_SUB_CLASS |
4831 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
4832 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
4833 | //BIF_CFG_DEV0_EPF1_0_BASE_CLASS |
4834 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
4835 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
4836 | //BIF_CFG_DEV0_EPF1_0_CACHE_LINE |
4837 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
4838 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
4839 | //BIF_CFG_DEV0_EPF1_0_LATENCY |
4840 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
4841 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
4842 | //BIF_CFG_DEV0_EPF1_0_HEADER |
4843 | #define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
4844 | #define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
4845 | #define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL |
4846 | #define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L |
4847 | //BIF_CFG_DEV0_EPF1_0_BIST |
4848 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
4849 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
4850 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
4851 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
4852 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
4853 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
4854 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 |
4855 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
4856 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
4857 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 |
4858 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
4859 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
4860 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 |
4861 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
4862 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
4863 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 |
4864 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
4865 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
4866 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 |
4867 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
4868 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
4869 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 |
4870 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
4871 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
4872 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID |
4873 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
4874 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
4875 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
4876 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
4877 | //BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR |
4878 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
4879 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
4880 | //BIF_CFG_DEV0_EPF1_0_CAP_PTR |
4881 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
4882 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
4883 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE |
4884 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
4885 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
4886 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN |
4887 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
4888 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
4889 | //BIF_CFG_DEV0_EPF1_0_MIN_GRANT |
4890 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
4891 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
4892 | //BIF_CFG_DEV0_EPF1_0_MAX_LATENCY |
4893 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
4894 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
4895 | //BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST |
4896 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
4897 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
4898 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
4899 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
4900 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
4901 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
4902 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W |
4903 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
4904 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
4905 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
4906 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
4907 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST |
4908 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
4909 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
4910 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
4911 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
4912 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP |
4913 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
4914 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
4915 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
4916 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
4917 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
4918 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
4919 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
4920 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
4921 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
4922 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
4923 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
4924 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
4925 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
4926 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
4927 | //BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL |
4928 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
4929 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
4930 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
4931 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
4932 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
4933 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
4934 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
4935 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
4936 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
4937 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
4938 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
4939 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
4940 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
4941 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
4942 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
4943 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
4944 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
4945 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
4946 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST |
4947 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
4948 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
4949 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
4950 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
4951 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP |
4952 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
4953 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
4954 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
4955 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
4956 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
4957 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
4958 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
4959 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
4960 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP |
4961 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
4962 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
4963 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
4964 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
4965 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
4966 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
4967 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
4968 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
4969 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
4970 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
4971 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
4972 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
4973 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
4974 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
4975 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
4976 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
4977 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
4978 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
4979 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL |
4980 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
4981 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
4982 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
4983 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
4984 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
4985 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
4986 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
4987 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
4988 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
4989 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
4990 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
4991 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
4992 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
4993 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
4994 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
4995 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
4996 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
4997 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
4998 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
4999 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
5000 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
5001 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
5002 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
5003 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
5004 | //BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS |
5005 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
5006 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
5007 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
5008 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
5009 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
5010 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
5011 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
5012 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
5013 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
5014 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
5015 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
5016 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
5017 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP |
5018 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
5019 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
5020 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
5021 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
5022 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
5023 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
5024 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
5025 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
5026 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
5027 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
5028 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
5029 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
5030 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
5031 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
5032 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
5033 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
5034 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
5035 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
5036 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
5037 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
5038 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
5039 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
5040 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL |
5041 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
5042 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
5043 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
5044 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
5045 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
5046 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
5047 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
5048 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
5049 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
5050 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
5051 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
5052 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
5053 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
5054 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
5055 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
5056 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
5057 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
5058 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
5059 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
5060 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
5061 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS |
5062 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
5063 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
5064 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
5065 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
5066 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
5067 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
5068 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
5069 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
5070 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
5071 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
5072 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
5073 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
5074 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
5075 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
5076 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 |
5077 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
5078 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
5079 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
5080 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
5081 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
5082 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
5083 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
5084 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
5085 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
5086 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
5087 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
5088 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
5089 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
5090 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
5091 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
5092 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
5093 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
5094 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
5095 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
5096 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
5097 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
5098 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
5099 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
5100 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
5101 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
5102 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
5103 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
5104 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
5105 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 |
5106 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
5107 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
5108 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
5109 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
5110 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
5111 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
5112 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
5113 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
5114 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
5115 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
5116 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
5117 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
5118 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
5119 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
5120 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
5121 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
5122 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
5123 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
5124 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
5125 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
5126 | //BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 |
5127 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
5128 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
5129 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP2 |
5130 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
5131 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
5132 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
5133 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
5134 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
5135 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
5136 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 |
5137 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
5138 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
5139 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
5140 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
5141 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
5142 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
5143 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
5144 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
5145 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
5146 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
5147 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
5148 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
5149 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
5150 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
5151 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
5152 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
5153 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 |
5154 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
5155 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
5156 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
5157 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
5158 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
5159 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
5160 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
5161 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
5162 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
5163 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
5164 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
5165 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
5166 | //BIF_CFG_DEV0_EPF1_0_SLOT_CAP2 |
5167 | #define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
5168 | #define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
5169 | //BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 |
5170 | #define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
5171 | #define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
5172 | //BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 |
5173 | #define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
5174 | #define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
5175 | //BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST |
5176 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
5177 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5178 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
5179 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
5180 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL |
5181 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
5182 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
5183 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
5184 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
5185 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
5186 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
5187 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
5188 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
5189 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
5190 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
5191 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO |
5192 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
5193 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
5194 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI |
5195 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
5196 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
5197 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA |
5198 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
5199 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
5200 | //BIF_CFG_DEV0_EPF1_0_MSI_MASK |
5201 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
5202 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
5203 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 |
5204 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
5205 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
5206 | //BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 |
5207 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
5208 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
5209 | //BIF_CFG_DEV0_EPF1_0_MSI_PENDING |
5210 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
5211 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
5212 | //BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 |
5213 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
5214 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
5215 | //BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST |
5216 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
5217 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5218 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
5219 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
5220 | //BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL |
5221 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
5222 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
5223 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
5224 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
5225 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
5226 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
5227 | //BIF_CFG_DEV0_EPF1_0_MSIX_TABLE |
5228 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
5229 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
5230 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
5231 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
5232 | //BIF_CFG_DEV0_EPF1_0_MSIX_PBA |
5233 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
5234 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
5235 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
5236 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
5237 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
5238 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5239 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5240 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5241 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5242 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5243 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5244 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR |
5245 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
5246 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
5247 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
5248 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
5249 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
5250 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
5251 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 |
5252 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
5253 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
5254 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 |
5255 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
5256 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
5257 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST |
5258 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5259 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5260 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5261 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5262 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5263 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5264 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 |
5265 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
5266 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
5267 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
5268 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
5269 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
5270 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
5271 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
5272 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
5273 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 |
5274 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
5275 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
5276 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
5277 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
5278 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL |
5279 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
5280 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
5281 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
5282 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
5283 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS |
5284 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
5285 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
5286 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP |
5287 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
5288 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
5289 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
5290 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
5291 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
5292 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
5293 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
5294 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
5295 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL |
5296 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
5297 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
5298 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
5299 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
5300 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
5301 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
5302 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
5303 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
5304 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
5305 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
5306 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
5307 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
5308 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS |
5309 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
5310 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
5311 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
5312 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
5313 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP |
5314 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
5315 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
5316 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
5317 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
5318 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
5319 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
5320 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
5321 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
5322 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL |
5323 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
5324 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
5325 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
5326 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
5327 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
5328 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
5329 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
5330 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
5331 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
5332 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
5333 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
5334 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
5335 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS |
5336 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
5337 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
5338 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
5339 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
5340 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
5341 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5342 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5343 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5344 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5345 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5346 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5347 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 |
5348 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
5349 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
5350 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 |
5351 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
5352 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
5353 | //BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
5354 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5355 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5356 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5357 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5358 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5359 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5360 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS |
5361 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
5362 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
5363 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
5364 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
5365 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
5366 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
5367 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
5368 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
5369 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
5370 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
5371 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
5372 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
5373 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
5374 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
5375 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
5376 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
5377 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
5378 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
5379 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
5380 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
5381 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
5382 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
5383 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
5384 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
5385 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
5386 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
5387 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
5388 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
5389 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
5390 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
5391 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
5392 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
5393 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK |
5394 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
5395 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
5396 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
5397 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
5398 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
5399 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
5400 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
5401 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
5402 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
5403 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
5404 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
5405 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
5406 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
5407 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
5408 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
5409 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
5410 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
5411 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
5412 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
5413 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
5414 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
5415 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
5416 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
5417 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
5418 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
5419 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
5420 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
5421 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
5422 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
5423 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
5424 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
5425 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
5426 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY |
5427 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
5428 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
5429 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
5430 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
5431 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
5432 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
5433 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
5434 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
5435 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
5436 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
5437 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
5438 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
5439 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
5440 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
5441 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
5442 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
5443 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
5444 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
5445 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
5446 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
5447 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
5448 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
5449 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
5450 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
5451 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
5452 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
5453 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
5454 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
5455 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
5456 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
5457 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
5458 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
5459 | //BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS |
5460 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
5461 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
5462 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
5463 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
5464 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
5465 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
5466 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
5467 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
5468 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
5469 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
5470 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
5471 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
5472 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
5473 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
5474 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
5475 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
5476 | //BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK |
5477 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
5478 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
5479 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
5480 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
5481 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
5482 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
5483 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
5484 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
5485 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
5486 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
5487 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
5488 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
5489 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
5490 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
5491 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
5492 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
5493 | //BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL |
5494 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
5495 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
5496 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
5497 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
5498 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
5499 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
5500 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
5501 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
5502 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
5503 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
5504 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
5505 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
5506 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
5507 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
5508 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
5509 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
5510 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 |
5511 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
5512 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
5513 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 |
5514 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
5515 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
5516 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 |
5517 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
5518 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
5519 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 |
5520 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
5521 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
5522 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 |
5523 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
5524 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
5525 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 |
5526 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
5527 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
5528 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 |
5529 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
5530 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
5531 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 |
5532 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
5533 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
5534 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST |
5535 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5536 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5537 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5538 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5539 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5540 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5541 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP |
5542 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5543 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
5544 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL |
5545 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
5546 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5547 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
5548 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
5549 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
5550 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
5551 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP |
5552 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5553 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
5554 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL |
5555 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
5556 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5557 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
5558 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
5559 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
5560 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
5561 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP |
5562 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5563 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
5564 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL |
5565 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
5566 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5567 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
5568 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
5569 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
5570 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
5571 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP |
5572 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5573 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
5574 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL |
5575 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
5576 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5577 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
5578 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
5579 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
5580 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
5581 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP |
5582 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5583 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
5584 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL |
5585 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
5586 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5587 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
5588 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
5589 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
5590 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
5591 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP |
5592 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5593 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
5594 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL |
5595 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
5596 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5597 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
5598 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
5599 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
5600 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
5601 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
5602 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5603 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5604 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5605 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5606 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5607 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5608 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT |
5609 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
5610 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
5611 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA |
5612 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
5613 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
5614 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
5615 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
5616 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
5617 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
5618 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
5619 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
5620 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
5621 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
5622 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
5623 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
5624 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP |
5625 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
5626 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
5627 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST |
5628 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5629 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5630 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5631 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5632 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5633 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5634 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP |
5635 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
5636 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
5637 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
5638 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
5639 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
5640 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
5641 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
5642 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
5643 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
5644 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
5645 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR |
5646 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
5647 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
5648 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS |
5649 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
5650 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
5651 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
5652 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
5653 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL |
5654 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
5655 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
5656 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
5657 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5658 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5659 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
5660 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5661 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5662 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
5663 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5664 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5665 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
5666 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5667 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5668 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
5669 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5670 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5671 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
5672 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5673 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5674 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
5675 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5676 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5677 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
5678 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5679 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5680 | //BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST |
5681 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5682 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5683 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5684 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5685 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5686 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5687 | //BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 |
5688 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
5689 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
5690 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
5691 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
5692 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
5693 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
5694 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS |
5695 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
5696 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
5697 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
5698 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
5699 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL |
5700 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5701 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5702 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5703 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5704 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5705 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5706 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5707 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5708 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5709 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5710 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL |
5711 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5712 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5713 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5714 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5715 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5716 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5717 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5718 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5719 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5720 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5721 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL |
5722 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5723 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5724 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5725 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5726 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5727 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5728 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5729 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5730 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5731 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5732 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL |
5733 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5734 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5735 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5736 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5737 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5738 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5739 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5740 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5741 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5742 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5743 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL |
5744 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5745 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5746 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5747 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5748 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5749 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5750 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5751 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5752 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5753 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5754 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL |
5755 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5756 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5757 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5758 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5759 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5760 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5761 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5762 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5763 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5764 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5765 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL |
5766 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5767 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5768 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5769 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5770 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5771 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5772 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5773 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5774 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5775 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5776 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL |
5777 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5778 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5779 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5780 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5781 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5782 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5783 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5784 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5785 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5786 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5787 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL |
5788 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5789 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5790 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5791 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5792 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5793 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5794 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5795 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5796 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5797 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5798 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL |
5799 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5800 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5801 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5802 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5803 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5804 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5805 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5806 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5807 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5808 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5809 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL |
5810 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5811 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5812 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5813 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5814 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5815 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5816 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5817 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5818 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5819 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5820 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL |
5821 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5822 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5823 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5824 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5825 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5826 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5827 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5828 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5829 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5830 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5831 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL |
5832 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5833 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5834 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5835 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5836 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5837 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5838 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5839 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5840 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5841 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5842 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL |
5843 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5844 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5845 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5846 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5847 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5848 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5849 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5850 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5851 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5852 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5853 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL |
5854 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5855 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5856 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5857 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5858 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5859 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5860 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5861 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5862 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5863 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5864 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL |
5865 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
5866 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
5867 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
5868 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
5869 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
5870 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
5871 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
5872 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
5873 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
5874 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
5875 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST |
5876 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5877 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5878 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5879 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5880 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5881 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5882 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP |
5883 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
5884 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
5885 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
5886 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
5887 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
5888 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
5889 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
5890 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
5891 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
5892 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
5893 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
5894 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
5895 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
5896 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
5897 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
5898 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
5899 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL |
5900 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
5901 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
5902 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
5903 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
5904 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
5905 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
5906 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
5907 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
5908 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
5909 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
5910 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
5911 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
5912 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
5913 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
5914 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST |
5915 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5916 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5917 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5918 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5919 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5920 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5921 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP |
5922 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
5923 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
5924 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
5925 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
5926 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
5927 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
5928 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL |
5929 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
5930 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
5931 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
5932 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
5933 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST |
5934 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5935 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5936 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5937 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5938 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5939 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5940 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL |
5941 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
5942 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
5943 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
5944 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
5945 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS |
5946 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
5947 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
5948 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
5949 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
5950 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
5951 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
5952 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
5953 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
5954 | //BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
5955 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
5956 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
5957 | //BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
5958 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
5959 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
5960 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST |
5961 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5962 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5963 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5964 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5965 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5966 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5967 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP |
5968 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
5969 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
5970 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
5971 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
5972 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
5973 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
5974 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL |
5975 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
5976 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
5977 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
5978 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
5979 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
5980 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
5981 | //BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST |
5982 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5983 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5984 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5985 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5986 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5987 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5988 | //BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP |
5989 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
5990 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
5991 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
5992 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
5993 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
5994 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
5995 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
5996 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
5997 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
5998 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
5999 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
6000 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
6001 | //BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL |
6002 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
6003 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
6004 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
6005 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
6006 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST |
6007 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6008 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6009 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6010 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6011 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6012 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6013 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP |
6014 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
6015 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
6016 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
6017 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
6018 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
6019 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
6020 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL |
6021 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
6022 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
6023 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
6024 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
6025 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 |
6026 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
6027 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
6028 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
6029 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
6030 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 |
6031 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
6032 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
6033 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 |
6034 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
6035 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
6036 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 |
6037 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
6038 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
6039 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 |
6040 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
6041 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
6042 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 |
6043 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
6044 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
6045 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
6046 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
6047 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
6048 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
6049 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
6050 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
6051 | //BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST |
6052 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6053 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6054 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6055 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6056 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6057 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6058 | //BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP |
6059 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
6060 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
6061 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
6062 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
6063 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
6064 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
6065 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
6066 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
6067 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST |
6068 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6069 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6070 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6071 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6072 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6073 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6074 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP |
6075 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
6076 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
6077 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
6078 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
6079 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
6080 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
6081 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL |
6082 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
6083 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
6084 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
6085 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
6086 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
6087 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
6088 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST |
6089 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6090 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6091 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6092 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6093 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6094 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6095 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP |
6096 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
6097 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
6098 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
6099 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
6100 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
6101 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
6102 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL |
6103 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
6104 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
6105 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
6106 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
6107 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
6108 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
6109 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
6110 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
6111 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
6112 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
6113 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS |
6114 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
6115 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
6116 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS |
6117 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
6118 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
6119 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS |
6120 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
6121 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
6122 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS |
6123 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
6124 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
6125 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK |
6126 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
6127 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
6128 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET |
6129 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
6130 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
6131 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE |
6132 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
6133 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
6134 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID |
6135 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
6136 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
6137 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
6138 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
6139 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
6140 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
6141 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
6142 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
6143 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
6144 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
6145 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6146 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
6147 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
6148 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6149 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
6150 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
6151 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6152 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
6153 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
6154 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6155 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
6156 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
6157 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6158 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
6159 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
6160 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6161 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
6162 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
6163 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
6164 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
6165 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
6166 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
6167 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
6168 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
6169 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
6170 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
6171 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
6172 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
6173 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
6174 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
6175 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
6176 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
6177 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
6178 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
6179 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
6180 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
6181 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
6182 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
6183 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
6184 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
6185 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
6186 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
6187 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
6188 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
6189 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
6190 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
6191 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
6192 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
6193 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
6194 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
6195 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
6196 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
6197 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
6198 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
6199 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
6200 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
6201 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
6202 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
6203 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
6204 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
6205 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
6206 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
6207 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
6208 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
6209 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
6210 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
6211 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
6212 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
6213 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
6214 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
6215 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
6216 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
6217 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
6218 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
6219 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
6220 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
6221 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
6222 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
6223 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
6224 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
6225 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
6226 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
6227 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
6228 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
6229 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
6230 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
6231 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
6232 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
6233 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
6234 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
6235 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
6236 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
6237 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
6238 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
6239 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
6240 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
6241 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
6242 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
6243 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
6244 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
6245 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
6246 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
6247 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
6248 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
6249 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
6250 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
6251 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
6252 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
6253 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
6254 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
6255 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
6256 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
6257 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
6258 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
6259 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
6260 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
6261 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
6262 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
6263 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
6264 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
6265 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
6266 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
6267 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
6268 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
6269 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
6270 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
6271 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
6272 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
6273 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
6274 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
6275 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
6276 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
6277 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
6278 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
6279 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
6280 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
6281 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
6282 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
6283 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
6284 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
6285 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
6286 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
6287 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
6288 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
6289 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
6290 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
6291 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
6292 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
6293 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
6294 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
6295 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
6296 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
6297 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
6298 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
6299 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
6300 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
6301 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
6302 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
6303 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
6304 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
6305 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
6306 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
6307 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
6308 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
6309 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
6310 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
6311 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
6312 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
6313 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
6314 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
6315 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
6316 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
6317 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
6318 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
6319 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
6320 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
6321 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
6322 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
6323 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
6324 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
6325 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
6326 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
6327 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
6328 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
6329 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
6330 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
6331 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
6332 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
6333 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
6334 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
6335 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
6336 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
6337 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
6338 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
6339 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
6340 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
6341 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
6342 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
6343 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
6344 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
6345 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
6346 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
6347 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
6348 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
6349 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
6350 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
6351 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
6352 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
6353 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
6354 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
6355 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
6356 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
6357 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
6358 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
6359 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
6360 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
6361 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
6362 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
6363 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
6364 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
6365 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
6366 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
6367 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
6368 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
6369 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
6370 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
6371 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
6372 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
6373 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
6374 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
6375 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
6376 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
6377 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
6378 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
6379 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
6380 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
6381 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
6382 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
6383 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
6384 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
6385 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
6386 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
6387 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
6388 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
6389 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
6390 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
6391 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
6392 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
6393 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
6394 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
6395 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
6396 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
6397 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
6398 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
6399 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
6400 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
6401 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
6402 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
6403 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
6404 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
6405 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
6406 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
6407 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
6408 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
6409 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
6410 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
6411 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
6412 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
6413 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
6414 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
6415 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
6416 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
6417 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
6418 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
6419 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
6420 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
6421 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
6422 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
6423 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
6424 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
6425 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
6426 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
6427 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
6428 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
6429 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
6430 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
6431 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
6432 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
6433 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
6434 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
6435 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
6436 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
6437 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
6438 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
6439 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
6440 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
6441 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
6442 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
6443 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
6444 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
6445 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
6446 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
6447 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
6448 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
6449 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
6450 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
6451 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
6452 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
6453 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
6454 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
6455 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
6456 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
6457 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
6458 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
6459 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
6460 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
6461 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
6462 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
6463 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
6464 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
6465 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
6466 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
6467 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
6468 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
6469 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
6470 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
6471 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
6472 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
6473 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
6474 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
6475 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
6476 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
6477 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
6478 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
6479 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
6480 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
6481 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
6482 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
6483 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
6484 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
6485 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
6486 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
6487 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
6488 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
6489 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
6490 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
6491 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
6492 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
6493 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
6494 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
6495 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
6496 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
6497 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
6498 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
6499 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
6500 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
6501 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
6502 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
6503 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
6504 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
6505 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
6506 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
6507 | |
6508 | |
6509 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
6510 | //BIF_CFG_DEV0_EPF2_0_VENDOR_ID |
6511 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
6512 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
6513 | //BIF_CFG_DEV0_EPF2_0_DEVICE_ID |
6514 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
6515 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
6516 | //BIF_CFG_DEV0_EPF2_0_COMMAND |
6517 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
6518 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
6519 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
6520 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
6521 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
6522 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
6523 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
6524 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
6525 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 |
6526 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
6527 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa |
6528 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
6529 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
6530 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
6531 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
6532 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
6533 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
6534 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
6535 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
6536 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L |
6537 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
6538 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L |
6539 | //BIF_CFG_DEV0_EPF2_0_STATUS |
6540 | #define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 |
6541 | #define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 |
6542 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN__SHIFT 0x5 |
6543 | #define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
6544 | #define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
6545 | #define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
6546 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
6547 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
6548 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
6549 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
6550 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
6551 | #define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L |
6552 | #define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L |
6553 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN_MASK 0x0020L |
6554 | #define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
6555 | #define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
6556 | #define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
6557 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
6558 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
6559 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
6560 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
6561 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
6562 | //BIF_CFG_DEV0_EPF2_0_REVISION_ID |
6563 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
6564 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
6565 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
6566 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
6567 | //BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE |
6568 | #define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
6569 | #define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
6570 | //BIF_CFG_DEV0_EPF2_0_SUB_CLASS |
6571 | #define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
6572 | #define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
6573 | //BIF_CFG_DEV0_EPF2_0_BASE_CLASS |
6574 | #define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
6575 | #define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
6576 | //BIF_CFG_DEV0_EPF2_0_CACHE_LINE |
6577 | #define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
6578 | #define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
6579 | //BIF_CFG_DEV0_EPF2_0_LATENCY |
6580 | #define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
6581 | #define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
6582 | //BIF_CFG_DEV0_EPF2_0_HEADER |
6583 | #define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
6584 | #define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
6585 | #define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL |
6586 | #define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L |
6587 | //BIF_CFG_DEV0_EPF2_0_BIST |
6588 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 |
6589 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 |
6590 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 |
6591 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL |
6592 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L |
6593 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L |
6594 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 |
6595 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
6596 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
6597 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 |
6598 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
6599 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
6600 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 |
6601 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
6602 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
6603 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 |
6604 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
6605 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
6606 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 |
6607 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
6608 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
6609 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 |
6610 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
6611 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
6612 | //BIF_CFG_DEV0_EPF2_0_ADAPTER_ID |
6613 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
6614 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
6615 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
6616 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
6617 | //BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR |
6618 | #define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
6619 | #define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
6620 | //BIF_CFG_DEV0_EPF2_0_CAP_PTR |
6621 | #define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
6622 | #define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
6623 | //BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE |
6624 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
6625 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
6626 | //BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN |
6627 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
6628 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
6629 | //BIF_CFG_DEV0_EPF2_0_MIN_GRANT |
6630 | #define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
6631 | #define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
6632 | //BIF_CFG_DEV0_EPF2_0_MAX_LATENCY |
6633 | #define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
6634 | #define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
6635 | //BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST |
6636 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
6637 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
6638 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
6639 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
6640 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
6641 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
6642 | //BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W |
6643 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
6644 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
6645 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
6646 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
6647 | //BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST |
6648 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
6649 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
6650 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
6651 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
6652 | //BIF_CFG_DEV0_EPF2_0_PMI_CAP |
6653 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 |
6654 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
6655 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
6656 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
6657 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
6658 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
6659 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
6660 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L |
6661 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
6662 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
6663 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
6664 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
6665 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
6666 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
6667 | //BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL |
6668 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
6669 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
6670 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
6671 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
6672 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
6673 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
6674 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
6675 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
6676 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
6677 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
6678 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
6679 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
6680 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
6681 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
6682 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
6683 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
6684 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
6685 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
6686 | //BIF_CFG_DEV0_EPF2_0_SBRN |
6687 | #define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0 |
6688 | #define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL |
6689 | //BIF_CFG_DEV0_EPF2_0_FLADJ |
6690 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 |
6691 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL |
6692 | //BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD |
6693 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
6694 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
6695 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
6696 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
6697 | //BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST |
6698 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
6699 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
6700 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
6701 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
6702 | //BIF_CFG_DEV0_EPF2_0_PCIE_CAP |
6703 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
6704 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
6705 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
6706 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
6707 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL |
6708 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
6709 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
6710 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
6711 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CAP |
6712 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
6713 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
6714 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
6715 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
6716 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
6717 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
6718 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
6719 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
6720 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
6721 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
6722 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
6723 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
6724 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
6725 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
6726 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
6727 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
6728 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
6729 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
6730 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL |
6731 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
6732 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
6733 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
6734 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
6735 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
6736 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
6737 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
6738 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
6739 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
6740 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
6741 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
6742 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
6743 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
6744 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
6745 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
6746 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
6747 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
6748 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
6749 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
6750 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
6751 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
6752 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
6753 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
6754 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
6755 | //BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS |
6756 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
6757 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
6758 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
6759 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
6760 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
6761 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
6762 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
6763 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
6764 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
6765 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
6766 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
6767 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
6768 | //BIF_CFG_DEV0_EPF2_0_LINK_CAP |
6769 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
6770 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
6771 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
6772 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
6773 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
6774 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
6775 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
6776 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
6777 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
6778 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
6779 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
6780 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
6781 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
6782 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
6783 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
6784 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
6785 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
6786 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
6787 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
6788 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
6789 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
6790 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
6791 | //BIF_CFG_DEV0_EPF2_0_LINK_CNTL |
6792 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
6793 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
6794 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
6795 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
6796 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
6797 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
6798 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
6799 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
6800 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
6801 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
6802 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
6803 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
6804 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
6805 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
6806 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
6807 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
6808 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
6809 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
6810 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
6811 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
6812 | //BIF_CFG_DEV0_EPF2_0_LINK_STATUS |
6813 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
6814 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
6815 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
6816 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
6817 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
6818 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
6819 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
6820 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
6821 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
6822 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
6823 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
6824 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
6825 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
6826 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
6827 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 |
6828 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
6829 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
6830 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
6831 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
6832 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
6833 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
6834 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
6835 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
6836 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
6837 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
6838 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
6839 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
6840 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
6841 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
6842 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
6843 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
6844 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
6845 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
6846 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
6847 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
6848 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
6849 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
6850 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
6851 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
6852 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
6853 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
6854 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
6855 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
6856 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 |
6857 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
6858 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
6859 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
6860 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
6861 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
6862 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
6863 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
6864 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
6865 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
6866 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
6867 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
6868 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
6869 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
6870 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
6871 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
6872 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
6873 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
6874 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
6875 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
6876 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
6877 | //BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 |
6878 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
6879 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
6880 | //BIF_CFG_DEV0_EPF2_0_LINK_CAP2 |
6881 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
6882 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
6883 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
6884 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
6885 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
6886 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
6887 | //BIF_CFG_DEV0_EPF2_0_LINK_CNTL2 |
6888 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
6889 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
6890 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
6891 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
6892 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
6893 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
6894 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
6895 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
6896 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
6897 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
6898 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
6899 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
6900 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
6901 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
6902 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
6903 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
6904 | //BIF_CFG_DEV0_EPF2_0_LINK_STATUS2 |
6905 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
6906 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
6907 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
6908 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
6909 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
6910 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
6911 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
6912 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
6913 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
6914 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
6915 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
6916 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
6917 | //BIF_CFG_DEV0_EPF2_0_SLOT_CAP2 |
6918 | #define BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
6919 | #define BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
6920 | //BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2 |
6921 | #define BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
6922 | #define BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
6923 | //BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2 |
6924 | #define BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
6925 | #define BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
6926 | //BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST |
6927 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
6928 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
6929 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
6930 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
6931 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL |
6932 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
6933 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
6934 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
6935 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
6936 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
6937 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
6938 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
6939 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
6940 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
6941 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
6942 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO |
6943 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
6944 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
6945 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI |
6946 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
6947 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
6948 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA |
6949 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
6950 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
6951 | //BIF_CFG_DEV0_EPF2_0_MSI_MASK |
6952 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
6953 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
6954 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 |
6955 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
6956 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
6957 | //BIF_CFG_DEV0_EPF2_0_MSI_MASK_64 |
6958 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
6959 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
6960 | //BIF_CFG_DEV0_EPF2_0_MSI_PENDING |
6961 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
6962 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
6963 | //BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 |
6964 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
6965 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
6966 | //BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST |
6967 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
6968 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
6969 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
6970 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
6971 | //BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL |
6972 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
6973 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
6974 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
6975 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
6976 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
6977 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
6978 | //BIF_CFG_DEV0_EPF2_0_MSIX_TABLE |
6979 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
6980 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
6981 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
6982 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
6983 | //BIF_CFG_DEV0_EPF2_0_MSIX_PBA |
6984 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
6985 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
6986 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
6987 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
6988 | //BIF_CFG_DEV0_EPF2_0_SATA_CAP_0 |
6989 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
6990 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
6991 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
6992 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
6993 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
6994 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
6995 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
6996 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
6997 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
6998 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
6999 | //BIF_CFG_DEV0_EPF2_0_SATA_CAP_1 |
7000 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
7001 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
7002 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
7003 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
7004 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
7005 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
7006 | //BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX |
7007 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
7008 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
7009 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
7010 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
7011 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
7012 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
7013 | //BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA |
7014 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
7015 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
7016 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
7017 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7018 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7019 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7020 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7021 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7022 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7023 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR |
7024 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
7025 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
7026 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
7027 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
7028 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
7029 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
7030 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 |
7031 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
7032 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
7033 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 |
7034 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
7035 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
7036 | //BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
7037 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7038 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7039 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7040 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7041 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7042 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7043 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS |
7044 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
7045 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
7046 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
7047 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
7048 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
7049 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
7050 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
7051 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
7052 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
7053 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
7054 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
7055 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
7056 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
7057 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
7058 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
7059 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
7060 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
7061 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
7062 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
7063 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
7064 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
7065 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
7066 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
7067 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
7068 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
7069 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
7070 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
7071 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
7072 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
7073 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
7074 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
7075 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
7076 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK |
7077 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
7078 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
7079 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
7080 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
7081 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
7082 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
7083 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
7084 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
7085 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
7086 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
7087 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
7088 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
7089 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
7090 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
7091 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
7092 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
7093 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
7094 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
7095 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
7096 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
7097 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
7098 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
7099 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
7100 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
7101 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
7102 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
7103 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
7104 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
7105 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
7106 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
7107 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
7108 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
7109 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY |
7110 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
7111 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
7112 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
7113 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
7114 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
7115 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
7116 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
7117 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
7118 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
7119 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
7120 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
7121 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
7122 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
7123 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
7124 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
7125 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
7126 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
7127 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
7128 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
7129 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
7130 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
7131 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
7132 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
7133 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
7134 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
7135 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
7136 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
7137 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
7138 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
7139 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
7140 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
7141 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
7142 | //BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS |
7143 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
7144 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
7145 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
7146 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
7147 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
7148 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
7149 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
7150 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
7151 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
7152 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
7153 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
7154 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
7155 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
7156 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
7157 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
7158 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
7159 | //BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK |
7160 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
7161 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
7162 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
7163 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
7164 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
7165 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
7166 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
7167 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
7168 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
7169 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
7170 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
7171 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
7172 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
7173 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
7174 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
7175 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
7176 | //BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL |
7177 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
7178 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
7179 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
7180 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
7181 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
7182 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
7183 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
7184 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
7185 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
7186 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
7187 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
7188 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
7189 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
7190 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
7191 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
7192 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
7193 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 |
7194 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
7195 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
7196 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 |
7197 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
7198 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
7199 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 |
7200 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
7201 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
7202 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 |
7203 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
7204 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
7205 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 |
7206 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
7207 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
7208 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 |
7209 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
7210 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
7211 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 |
7212 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
7213 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
7214 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 |
7215 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
7216 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
7217 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST |
7218 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7219 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7220 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7221 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7222 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7223 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7224 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP |
7225 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7226 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
7227 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL |
7228 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
7229 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7230 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
7231 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
7232 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
7233 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
7234 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP |
7235 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7236 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
7237 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL |
7238 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
7239 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7240 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
7241 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
7242 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
7243 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
7244 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP |
7245 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7246 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
7247 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL |
7248 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
7249 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7250 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
7251 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
7252 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
7253 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
7254 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP |
7255 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7256 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
7257 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL |
7258 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
7259 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7260 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
7261 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
7262 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
7263 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
7264 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP |
7265 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7266 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
7267 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL |
7268 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
7269 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7270 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
7271 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
7272 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
7273 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
7274 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP |
7275 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7276 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
7277 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL |
7278 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
7279 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7280 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
7281 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
7282 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
7283 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
7284 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
7285 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7286 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7287 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7288 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7289 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7290 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7291 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT |
7292 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
7293 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
7294 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA |
7295 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
7296 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
7297 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
7298 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
7299 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
7300 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
7301 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
7302 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
7303 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
7304 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
7305 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
7306 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
7307 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP |
7308 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
7309 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
7310 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST |
7311 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7312 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7313 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7314 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7315 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7316 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7317 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP |
7318 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
7319 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
7320 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
7321 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
7322 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
7323 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
7324 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
7325 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
7326 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
7327 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
7328 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR |
7329 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
7330 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
7331 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS |
7332 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
7333 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
7334 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
7335 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
7336 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL |
7337 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
7338 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
7339 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
7340 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7341 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7342 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
7343 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7344 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7345 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
7346 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7347 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7348 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
7349 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7350 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7351 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
7352 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7353 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7354 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
7355 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7356 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7357 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
7358 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7359 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7360 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
7361 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7362 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7363 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST |
7364 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7365 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7366 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7367 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7368 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7369 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7370 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP |
7371 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
7372 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
7373 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
7374 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
7375 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
7376 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
7377 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
7378 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
7379 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
7380 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
7381 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
7382 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
7383 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
7384 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
7385 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
7386 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
7387 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL |
7388 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
7389 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
7390 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
7391 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
7392 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
7393 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
7394 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
7395 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
7396 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
7397 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
7398 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
7399 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
7400 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
7401 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
7402 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST |
7403 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7404 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7405 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7406 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7407 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7408 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7409 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP |
7410 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
7411 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
7412 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
7413 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
7414 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
7415 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
7416 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL |
7417 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
7418 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
7419 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
7420 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
7421 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
7422 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
7423 | |
7424 | |
7425 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
7426 | //BIF_CFG_DEV0_EPF3_0_VENDOR_ID |
7427 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
7428 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
7429 | //BIF_CFG_DEV0_EPF3_0_DEVICE_ID |
7430 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
7431 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
7432 | //BIF_CFG_DEV0_EPF3_0_COMMAND |
7433 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
7434 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
7435 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
7436 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
7437 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
7438 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
7439 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
7440 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
7441 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8 |
7442 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
7443 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa |
7444 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
7445 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
7446 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
7447 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
7448 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
7449 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
7450 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
7451 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L |
7452 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L |
7453 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
7454 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L |
7455 | //BIF_CFG_DEV0_EPF3_0_STATUS |
7456 | #define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3 |
7457 | #define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4 |
7458 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN__SHIFT 0x5 |
7459 | #define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
7460 | #define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
7461 | #define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
7462 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
7463 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
7464 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
7465 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
7466 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
7467 | #define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L |
7468 | #define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L |
7469 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN_MASK 0x0020L |
7470 | #define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
7471 | #define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
7472 | #define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
7473 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
7474 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
7475 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
7476 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
7477 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
7478 | //BIF_CFG_DEV0_EPF3_0_REVISION_ID |
7479 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
7480 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
7481 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
7482 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
7483 | //BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE |
7484 | #define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
7485 | #define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
7486 | //BIF_CFG_DEV0_EPF3_0_SUB_CLASS |
7487 | #define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
7488 | #define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
7489 | //BIF_CFG_DEV0_EPF3_0_BASE_CLASS |
7490 | #define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
7491 | #define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
7492 | //BIF_CFG_DEV0_EPF3_0_CACHE_LINE |
7493 | #define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
7494 | #define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
7495 | //BIF_CFG_DEV0_EPF3_0_LATENCY |
7496 | #define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
7497 | #define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
7498 | //BIF_CFG_DEV0_EPF3_0_HEADER |
7499 | #define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
7500 | #define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
7501 | #define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK 0x7FL |
7502 | #define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK 0x80L |
7503 | //BIF_CFG_DEV0_EPF3_0_BIST |
7504 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0 |
7505 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6 |
7506 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7 |
7507 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL |
7508 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L |
7509 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L |
7510 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 |
7511 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
7512 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
7513 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 |
7514 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
7515 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
7516 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 |
7517 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
7518 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
7519 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 |
7520 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
7521 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
7522 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 |
7523 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
7524 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
7525 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 |
7526 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
7527 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
7528 | //BIF_CFG_DEV0_EPF3_0_ADAPTER_ID |
7529 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
7530 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
7531 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
7532 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
7533 | //BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR |
7534 | #define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
7535 | #define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
7536 | //BIF_CFG_DEV0_EPF3_0_CAP_PTR |
7537 | #define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
7538 | #define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
7539 | //BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE |
7540 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
7541 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
7542 | //BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN |
7543 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
7544 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
7545 | //BIF_CFG_DEV0_EPF3_0_MIN_GRANT |
7546 | #define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
7547 | #define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
7548 | //BIF_CFG_DEV0_EPF3_0_MAX_LATENCY |
7549 | #define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
7550 | #define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
7551 | //BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST |
7552 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
7553 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7554 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
7555 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
7556 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
7557 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
7558 | //BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W |
7559 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
7560 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
7561 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
7562 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
7563 | //BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST |
7564 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
7565 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7566 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
7567 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7568 | //BIF_CFG_DEV0_EPF3_0_PMI_CAP |
7569 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0 |
7570 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
7571 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
7572 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
7573 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
7574 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
7575 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
7576 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L |
7577 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
7578 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
7579 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
7580 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
7581 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
7582 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
7583 | //BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL |
7584 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
7585 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
7586 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
7587 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
7588 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
7589 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
7590 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
7591 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
7592 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
7593 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
7594 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
7595 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
7596 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
7597 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
7598 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
7599 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
7600 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
7601 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
7602 | //BIF_CFG_DEV0_EPF3_0_SBRN |
7603 | #define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0 |
7604 | #define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL |
7605 | //BIF_CFG_DEV0_EPF3_0_FLADJ |
7606 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0 |
7607 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL |
7608 | //BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD |
7609 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
7610 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
7611 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
7612 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
7613 | //BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST |
7614 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
7615 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7616 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
7617 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7618 | //BIF_CFG_DEV0_EPF3_0_PCIE_CAP |
7619 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0 |
7620 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
7621 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
7622 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
7623 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL |
7624 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
7625 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
7626 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
7627 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CAP |
7628 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
7629 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
7630 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
7631 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
7632 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
7633 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
7634 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
7635 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
7636 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
7637 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
7638 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
7639 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
7640 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
7641 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
7642 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
7643 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
7644 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
7645 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
7646 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL |
7647 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
7648 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
7649 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
7650 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
7651 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
7652 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
7653 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
7654 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
7655 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
7656 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
7657 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
7658 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
7659 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
7660 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
7661 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
7662 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
7663 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
7664 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
7665 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
7666 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
7667 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
7668 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
7669 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
7670 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
7671 | //BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS |
7672 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
7673 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
7674 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
7675 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
7676 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
7677 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
7678 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
7679 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
7680 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
7681 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
7682 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
7683 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
7684 | //BIF_CFG_DEV0_EPF3_0_LINK_CAP |
7685 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
7686 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
7687 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
7688 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
7689 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
7690 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
7691 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
7692 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
7693 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
7694 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
7695 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
7696 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
7697 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
7698 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
7699 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
7700 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
7701 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
7702 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
7703 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
7704 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
7705 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
7706 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
7707 | //BIF_CFG_DEV0_EPF3_0_LINK_CNTL |
7708 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
7709 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
7710 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
7711 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
7712 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
7713 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
7714 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
7715 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
7716 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
7717 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
7718 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
7719 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
7720 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
7721 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
7722 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
7723 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
7724 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
7725 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
7726 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
7727 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
7728 | //BIF_CFG_DEV0_EPF3_0_LINK_STATUS |
7729 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
7730 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
7731 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
7732 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
7733 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
7734 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
7735 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
7736 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
7737 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
7738 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
7739 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
7740 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
7741 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
7742 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
7743 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 |
7744 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
7745 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
7746 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
7747 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
7748 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
7749 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
7750 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
7751 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
7752 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
7753 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
7754 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
7755 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
7756 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
7757 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
7758 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
7759 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
7760 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
7761 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
7762 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
7763 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
7764 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
7765 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
7766 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
7767 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
7768 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
7769 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
7770 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
7771 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
7772 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 |
7773 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
7774 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
7775 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
7776 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
7777 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
7778 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
7779 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
7780 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
7781 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
7782 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
7783 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
7784 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
7785 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
7786 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
7787 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
7788 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
7789 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
7790 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
7791 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
7792 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
7793 | //BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 |
7794 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
7795 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
7796 | //BIF_CFG_DEV0_EPF3_0_LINK_CAP2 |
7797 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
7798 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
7799 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
7800 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
7801 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
7802 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
7803 | //BIF_CFG_DEV0_EPF3_0_LINK_CNTL2 |
7804 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
7805 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
7806 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
7807 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
7808 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
7809 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
7810 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
7811 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
7812 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
7813 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
7814 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
7815 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
7816 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
7817 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
7818 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
7819 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
7820 | //BIF_CFG_DEV0_EPF3_0_LINK_STATUS2 |
7821 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
7822 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
7823 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
7824 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
7825 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
7826 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
7827 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
7828 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
7829 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
7830 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
7831 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
7832 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
7833 | //BIF_CFG_DEV0_EPF3_0_SLOT_CAP2 |
7834 | #define BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
7835 | #define BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
7836 | //BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2 |
7837 | #define BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
7838 | #define BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
7839 | //BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2 |
7840 | #define BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
7841 | #define BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
7842 | //BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST |
7843 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
7844 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7845 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
7846 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7847 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL |
7848 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
7849 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
7850 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
7851 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
7852 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
7853 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
7854 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
7855 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
7856 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
7857 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
7858 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO |
7859 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
7860 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
7861 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI |
7862 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
7863 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
7864 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA |
7865 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
7866 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
7867 | //BIF_CFG_DEV0_EPF3_0_MSI_MASK |
7868 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
7869 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
7870 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 |
7871 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
7872 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
7873 | //BIF_CFG_DEV0_EPF3_0_MSI_MASK_64 |
7874 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
7875 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
7876 | //BIF_CFG_DEV0_EPF3_0_MSI_PENDING |
7877 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
7878 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
7879 | //BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 |
7880 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
7881 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
7882 | //BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST |
7883 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
7884 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7885 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
7886 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7887 | //BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL |
7888 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
7889 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
7890 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
7891 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
7892 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
7893 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
7894 | //BIF_CFG_DEV0_EPF3_0_MSIX_TABLE |
7895 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
7896 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
7897 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
7898 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
7899 | //BIF_CFG_DEV0_EPF3_0_MSIX_PBA |
7900 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
7901 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
7902 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
7903 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
7904 | //BIF_CFG_DEV0_EPF3_0_SATA_CAP_0 |
7905 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
7906 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
7907 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
7908 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
7909 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
7910 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
7911 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
7912 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
7913 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
7914 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
7915 | //BIF_CFG_DEV0_EPF3_0_SATA_CAP_1 |
7916 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
7917 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
7918 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
7919 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
7920 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
7921 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
7922 | //BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX |
7923 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
7924 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
7925 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
7926 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
7927 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
7928 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
7929 | //BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA |
7930 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
7931 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
7932 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
7933 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7934 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7935 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7936 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7937 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7938 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7939 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR |
7940 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
7941 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
7942 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
7943 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
7944 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
7945 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
7946 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 |
7947 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
7948 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
7949 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 |
7950 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
7951 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
7952 | //BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
7953 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7954 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7955 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7956 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7957 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7958 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7959 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS |
7960 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
7961 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
7962 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
7963 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
7964 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
7965 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
7966 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
7967 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
7968 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
7969 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
7970 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
7971 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
7972 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
7973 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
7974 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
7975 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
7976 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
7977 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
7978 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
7979 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
7980 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
7981 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
7982 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
7983 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
7984 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
7985 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
7986 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
7987 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
7988 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
7989 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
7990 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
7991 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
7992 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK |
7993 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
7994 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
7995 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
7996 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
7997 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
7998 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
7999 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
8000 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
8001 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
8002 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
8003 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
8004 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
8005 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
8006 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
8007 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
8008 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
8009 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
8010 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
8011 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
8012 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
8013 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
8014 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
8015 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
8016 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
8017 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
8018 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
8019 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
8020 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
8021 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
8022 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
8023 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
8024 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
8025 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY |
8026 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
8027 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
8028 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
8029 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
8030 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
8031 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
8032 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
8033 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
8034 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
8035 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
8036 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
8037 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
8038 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
8039 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
8040 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
8041 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
8042 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
8043 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
8044 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
8045 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
8046 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
8047 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
8048 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
8049 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
8050 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
8051 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
8052 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
8053 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
8054 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
8055 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
8056 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
8057 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
8058 | //BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS |
8059 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
8060 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
8061 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
8062 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
8063 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
8064 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
8065 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
8066 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
8067 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
8068 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
8069 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
8070 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
8071 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
8072 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
8073 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
8074 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
8075 | //BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK |
8076 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
8077 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
8078 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
8079 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
8080 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
8081 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
8082 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
8083 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
8084 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
8085 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
8086 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
8087 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
8088 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
8089 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
8090 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
8091 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
8092 | //BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL |
8093 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
8094 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
8095 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
8096 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
8097 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
8098 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
8099 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
8100 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
8101 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
8102 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
8103 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
8104 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
8105 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
8106 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
8107 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
8108 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
8109 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 |
8110 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
8111 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
8112 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 |
8113 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
8114 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
8115 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 |
8116 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
8117 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
8118 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 |
8119 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
8120 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
8121 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 |
8122 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
8123 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
8124 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 |
8125 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
8126 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
8127 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 |
8128 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
8129 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
8130 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 |
8131 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
8132 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
8133 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST |
8134 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8135 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8136 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8137 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8138 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8139 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8140 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP |
8141 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8142 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
8143 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL |
8144 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
8145 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
8146 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
8147 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
8148 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
8149 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
8150 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP |
8151 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8152 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
8153 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL |
8154 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
8155 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
8156 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
8157 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
8158 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
8159 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
8160 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP |
8161 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8162 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
8163 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL |
8164 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
8165 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
8166 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
8167 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
8168 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
8169 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
8170 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP |
8171 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8172 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
8173 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL |
8174 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
8175 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
8176 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
8177 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
8178 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
8179 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
8180 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP |
8181 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8182 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
8183 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL |
8184 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
8185 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
8186 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
8187 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
8188 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
8189 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
8190 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP |
8191 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8192 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
8193 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL |
8194 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
8195 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
8196 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
8197 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
8198 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
8199 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
8200 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
8201 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8202 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8203 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8204 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8205 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8206 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8207 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT |
8208 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
8209 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
8210 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA |
8211 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
8212 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
8213 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
8214 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
8215 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
8216 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
8217 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
8218 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
8219 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
8220 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
8221 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
8222 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
8223 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP |
8224 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
8225 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
8226 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST |
8227 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8228 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8229 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8230 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8231 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8232 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8233 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP |
8234 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
8235 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
8236 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
8237 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
8238 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
8239 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
8240 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
8241 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
8242 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
8243 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
8244 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR |
8245 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
8246 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
8247 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS |
8248 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
8249 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
8250 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
8251 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
8252 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL |
8253 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
8254 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
8255 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
8256 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8257 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8258 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
8259 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8260 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8261 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
8262 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8263 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8264 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
8265 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8266 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8267 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
8268 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8269 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8270 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
8271 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8272 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8273 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
8274 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8275 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8276 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
8277 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
8278 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
8279 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST |
8280 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8281 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8282 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8283 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8284 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8285 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8286 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP |
8287 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
8288 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
8289 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
8290 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
8291 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
8292 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
8293 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
8294 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
8295 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
8296 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
8297 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
8298 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
8299 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
8300 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
8301 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
8302 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
8303 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL |
8304 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
8305 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
8306 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
8307 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
8308 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
8309 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
8310 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
8311 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
8312 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
8313 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
8314 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
8315 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
8316 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
8317 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
8318 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST |
8319 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8320 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8321 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8322 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8323 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8324 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8325 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP |
8326 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
8327 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
8328 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
8329 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
8330 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
8331 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
8332 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL |
8333 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
8334 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
8335 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
8336 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
8337 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
8338 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
8339 | |
8340 | |
8341 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
8342 | //BIF_CFG_DEV0_EPF4_0_VENDOR_ID |
8343 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
8344 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
8345 | //BIF_CFG_DEV0_EPF4_0_DEVICE_ID |
8346 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
8347 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
8348 | //BIF_CFG_DEV0_EPF4_0_COMMAND |
8349 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
8350 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
8351 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
8352 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
8353 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
8354 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
8355 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
8356 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
8357 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT 0x8 |
8358 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
8359 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT 0xa |
8360 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
8361 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
8362 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
8363 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
8364 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
8365 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
8366 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
8367 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK 0x0080L |
8368 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK 0x0100L |
8369 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
8370 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK 0x0400L |
8371 | //BIF_CFG_DEV0_EPF4_0_STATUS |
8372 | #define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT 0x3 |
8373 | #define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT 0x4 |
8374 | #define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN__SHIFT 0x5 |
8375 | #define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
8376 | #define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
8377 | #define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
8378 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
8379 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
8380 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
8381 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
8382 | #define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
8383 | #define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK 0x0008L |
8384 | #define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK 0x0010L |
8385 | #define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN_MASK 0x0020L |
8386 | #define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
8387 | #define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
8388 | #define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
8389 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
8390 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
8391 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
8392 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
8393 | #define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
8394 | //BIF_CFG_DEV0_EPF4_0_REVISION_ID |
8395 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
8396 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
8397 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
8398 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
8399 | //BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE |
8400 | #define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
8401 | #define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
8402 | //BIF_CFG_DEV0_EPF4_0_SUB_CLASS |
8403 | #define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
8404 | #define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
8405 | //BIF_CFG_DEV0_EPF4_0_BASE_CLASS |
8406 | #define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
8407 | #define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
8408 | //BIF_CFG_DEV0_EPF4_0_CACHE_LINE |
8409 | #define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
8410 | #define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
8411 | //BIF_CFG_DEV0_EPF4_0_LATENCY |
8412 | #define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
8413 | #define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
8414 | //BIF_CFG_DEV0_EPF4_0_HEADER |
8415 | #define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
8416 | #define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
8417 | #define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK 0x7FL |
8418 | #define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK 0x80L |
8419 | //BIF_CFG_DEV0_EPF4_0_BIST |
8420 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT 0x0 |
8421 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT 0x6 |
8422 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT 0x7 |
8423 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK 0x0FL |
8424 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK 0x40L |
8425 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK 0x80L |
8426 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 |
8427 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
8428 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
8429 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 |
8430 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
8431 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
8432 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 |
8433 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
8434 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
8435 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 |
8436 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
8437 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
8438 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 |
8439 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
8440 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
8441 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 |
8442 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
8443 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
8444 | //BIF_CFG_DEV0_EPF4_0_ADAPTER_ID |
8445 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
8446 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
8447 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
8448 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
8449 | //BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR |
8450 | #define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
8451 | #define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
8452 | //BIF_CFG_DEV0_EPF4_0_CAP_PTR |
8453 | #define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
8454 | #define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
8455 | //BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE |
8456 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
8457 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
8458 | //BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN |
8459 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
8460 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
8461 | //BIF_CFG_DEV0_EPF4_0_MIN_GRANT |
8462 | #define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
8463 | #define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
8464 | //BIF_CFG_DEV0_EPF4_0_MAX_LATENCY |
8465 | #define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
8466 | #define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
8467 | //BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST |
8468 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
8469 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8470 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
8471 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
8472 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
8473 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
8474 | //BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W |
8475 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
8476 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
8477 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
8478 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
8479 | //BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST |
8480 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
8481 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8482 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
8483 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
8484 | //BIF_CFG_DEV0_EPF4_0_PMI_CAP |
8485 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT 0x0 |
8486 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
8487 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
8488 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
8489 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
8490 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
8491 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
8492 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK 0x0007L |
8493 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
8494 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
8495 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
8496 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
8497 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
8498 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
8499 | //BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL |
8500 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
8501 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
8502 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
8503 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
8504 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
8505 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
8506 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
8507 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
8508 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
8509 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
8510 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
8511 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
8512 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
8513 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
8514 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
8515 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
8516 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
8517 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
8518 | //BIF_CFG_DEV0_EPF4_0_SBRN |
8519 | #define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT 0x0 |
8520 | #define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK 0xFFL |
8521 | //BIF_CFG_DEV0_EPF4_0_FLADJ |
8522 | #define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT 0x0 |
8523 | #define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK 0x3FL |
8524 | //BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD |
8525 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
8526 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
8527 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
8528 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
8529 | //BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST |
8530 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
8531 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8532 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
8533 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
8534 | //BIF_CFG_DEV0_EPF4_0_PCIE_CAP |
8535 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT 0x0 |
8536 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
8537 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
8538 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
8539 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK 0x000FL |
8540 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
8541 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
8542 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
8543 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CAP |
8544 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
8545 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
8546 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
8547 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
8548 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
8549 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
8550 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
8551 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
8552 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
8553 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
8554 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
8555 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
8556 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
8557 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
8558 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
8559 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
8560 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
8561 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
8562 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL |
8563 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
8564 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
8565 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
8566 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
8567 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
8568 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
8569 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
8570 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
8571 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
8572 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
8573 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
8574 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
8575 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
8576 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
8577 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
8578 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
8579 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
8580 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
8581 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
8582 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
8583 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
8584 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
8585 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
8586 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
8587 | //BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS |
8588 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
8589 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
8590 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
8591 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
8592 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
8593 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
8594 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
8595 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
8596 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
8597 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
8598 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
8599 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
8600 | //BIF_CFG_DEV0_EPF4_0_LINK_CAP |
8601 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
8602 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
8603 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
8604 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
8605 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
8606 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
8607 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
8608 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
8609 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
8610 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
8611 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
8612 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
8613 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
8614 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
8615 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
8616 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
8617 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
8618 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
8619 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
8620 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
8621 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
8622 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
8623 | //BIF_CFG_DEV0_EPF4_0_LINK_CNTL |
8624 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
8625 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
8626 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
8627 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
8628 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
8629 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
8630 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
8631 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
8632 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
8633 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
8634 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
8635 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
8636 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
8637 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
8638 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
8639 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
8640 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
8641 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
8642 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
8643 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
8644 | //BIF_CFG_DEV0_EPF4_0_LINK_STATUS |
8645 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
8646 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
8647 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
8648 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
8649 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
8650 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
8651 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
8652 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
8653 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
8654 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
8655 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
8656 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
8657 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
8658 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
8659 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 |
8660 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
8661 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
8662 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
8663 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
8664 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
8665 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
8666 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
8667 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
8668 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
8669 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
8670 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
8671 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
8672 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
8673 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
8674 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
8675 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
8676 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
8677 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
8678 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
8679 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
8680 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
8681 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
8682 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
8683 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
8684 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
8685 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
8686 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
8687 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
8688 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 |
8689 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
8690 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
8691 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
8692 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
8693 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
8694 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
8695 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
8696 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
8697 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
8698 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
8699 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
8700 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
8701 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
8702 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
8703 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
8704 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
8705 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
8706 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
8707 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
8708 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
8709 | //BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 |
8710 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
8711 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
8712 | //BIF_CFG_DEV0_EPF4_0_LINK_CAP2 |
8713 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
8714 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
8715 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
8716 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
8717 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
8718 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
8719 | //BIF_CFG_DEV0_EPF4_0_LINK_CNTL2 |
8720 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
8721 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
8722 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
8723 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
8724 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
8725 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
8726 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
8727 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
8728 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
8729 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
8730 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
8731 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
8732 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
8733 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
8734 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
8735 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
8736 | //BIF_CFG_DEV0_EPF4_0_LINK_STATUS2 |
8737 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
8738 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
8739 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
8740 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
8741 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
8742 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
8743 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
8744 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
8745 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
8746 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
8747 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
8748 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
8749 | //BIF_CFG_DEV0_EPF4_0_SLOT_CAP2 |
8750 | #define BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
8751 | #define BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
8752 | //BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2 |
8753 | #define BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
8754 | #define BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
8755 | //BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2 |
8756 | #define BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
8757 | #define BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
8758 | //BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST |
8759 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
8760 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8761 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
8762 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
8763 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL |
8764 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
8765 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
8766 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
8767 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
8768 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
8769 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
8770 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
8771 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
8772 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
8773 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
8774 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO |
8775 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
8776 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
8777 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI |
8778 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
8779 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
8780 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA |
8781 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
8782 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
8783 | //BIF_CFG_DEV0_EPF4_0_MSI_MASK |
8784 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
8785 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
8786 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 |
8787 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
8788 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
8789 | //BIF_CFG_DEV0_EPF4_0_MSI_MASK_64 |
8790 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
8791 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
8792 | //BIF_CFG_DEV0_EPF4_0_MSI_PENDING |
8793 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
8794 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
8795 | //BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 |
8796 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
8797 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
8798 | //BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST |
8799 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
8800 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8801 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
8802 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
8803 | //BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL |
8804 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
8805 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
8806 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
8807 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
8808 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
8809 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
8810 | //BIF_CFG_DEV0_EPF4_0_MSIX_TABLE |
8811 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
8812 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
8813 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
8814 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
8815 | //BIF_CFG_DEV0_EPF4_0_MSIX_PBA |
8816 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
8817 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
8818 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
8819 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
8820 | //BIF_CFG_DEV0_EPF4_0_SATA_CAP_0 |
8821 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
8822 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
8823 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
8824 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
8825 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
8826 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
8827 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
8828 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
8829 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
8830 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
8831 | //BIF_CFG_DEV0_EPF4_0_SATA_CAP_1 |
8832 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
8833 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
8834 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
8835 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
8836 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
8837 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
8838 | //BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX |
8839 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
8840 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
8841 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
8842 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
8843 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
8844 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
8845 | //BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA |
8846 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
8847 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
8848 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
8849 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8850 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8851 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8852 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8853 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8854 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8855 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR |
8856 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
8857 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
8858 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
8859 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
8860 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
8861 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
8862 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 |
8863 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
8864 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
8865 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 |
8866 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
8867 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
8868 | //BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
8869 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8870 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8871 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8872 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8873 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8874 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8875 | //BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS |
8876 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
8877 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
8878 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
8879 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
8880 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
8881 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
8882 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
8883 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
8884 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
8885 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
8886 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
8887 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
8888 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
8889 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
8890 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
8891 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
8892 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
8893 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
8894 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
8895 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
8896 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
8897 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
8898 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
8899 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
8900 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
8901 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
8902 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
8903 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
8904 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
8905 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
8906 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
8907 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
8908 | //BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK |
8909 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
8910 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
8911 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
8912 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
8913 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
8914 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
8915 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
8916 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
8917 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
8918 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
8919 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
8920 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
8921 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
8922 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
8923 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
8924 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
8925 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
8926 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
8927 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
8928 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
8929 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
8930 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
8931 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
8932 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
8933 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
8934 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
8935 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
8936 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
8937 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
8938 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
8939 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
8940 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
8941 | //BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY |
8942 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
8943 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
8944 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
8945 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
8946 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
8947 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
8948 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
8949 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
8950 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
8951 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
8952 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
8953 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
8954 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
8955 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
8956 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
8957 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
8958 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
8959 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
8960 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
8961 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
8962 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
8963 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
8964 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
8965 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
8966 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
8967 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
8968 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
8969 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
8970 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
8971 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
8972 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
8973 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
8974 | //BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS |
8975 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
8976 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
8977 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
8978 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
8979 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
8980 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
8981 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
8982 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
8983 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
8984 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
8985 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
8986 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
8987 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
8988 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
8989 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
8990 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
8991 | //BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK |
8992 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
8993 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
8994 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
8995 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
8996 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
8997 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
8998 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
8999 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
9000 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
9001 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
9002 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
9003 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
9004 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
9005 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
9006 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
9007 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
9008 | //BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL |
9009 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
9010 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
9011 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
9012 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
9013 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
9014 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
9015 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
9016 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
9017 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
9018 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
9019 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
9020 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
9021 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
9022 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
9023 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
9024 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
9025 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 |
9026 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
9027 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
9028 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 |
9029 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
9030 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
9031 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 |
9032 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
9033 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
9034 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 |
9035 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
9036 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
9037 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 |
9038 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
9039 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
9040 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 |
9041 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
9042 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
9043 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 |
9044 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
9045 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
9046 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 |
9047 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
9048 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
9049 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST |
9050 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9051 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9052 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9053 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9054 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9055 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9056 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP |
9057 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9058 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9059 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL |
9060 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
9061 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9062 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
9063 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
9064 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9065 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
9066 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP |
9067 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9068 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9069 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL |
9070 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
9071 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9072 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
9073 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
9074 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9075 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
9076 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP |
9077 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9078 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9079 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL |
9080 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
9081 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9082 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
9083 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
9084 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9085 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
9086 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP |
9087 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9088 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9089 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL |
9090 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
9091 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9092 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
9093 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
9094 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9095 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
9096 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP |
9097 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9098 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9099 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL |
9100 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
9101 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9102 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
9103 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
9104 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9105 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
9106 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP |
9107 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9108 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9109 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL |
9110 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
9111 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9112 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
9113 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
9114 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9115 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
9116 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
9117 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9118 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9119 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9120 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9121 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9122 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9123 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT |
9124 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
9125 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
9126 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA |
9127 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
9128 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
9129 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
9130 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
9131 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
9132 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
9133 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
9134 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
9135 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
9136 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
9137 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
9138 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
9139 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP |
9140 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
9141 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
9142 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST |
9143 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9144 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9145 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9146 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9147 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9148 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9149 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP |
9150 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
9151 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
9152 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
9153 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
9154 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
9155 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
9156 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
9157 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
9158 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
9159 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
9160 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR |
9161 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
9162 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
9163 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS |
9164 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
9165 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
9166 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
9167 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
9168 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL |
9169 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
9170 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
9171 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
9172 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9173 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9174 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
9175 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9176 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9177 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
9178 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9179 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9180 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
9181 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9182 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9183 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
9184 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9185 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9186 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
9187 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9188 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9189 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
9190 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9191 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9192 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
9193 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9194 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9195 | //BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST |
9196 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9197 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9198 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9199 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9200 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9201 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9202 | //BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP |
9203 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
9204 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
9205 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
9206 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
9207 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
9208 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
9209 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
9210 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
9211 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
9212 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
9213 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
9214 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
9215 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
9216 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
9217 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
9218 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
9219 | //BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL |
9220 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
9221 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
9222 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
9223 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
9224 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
9225 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
9226 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
9227 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
9228 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
9229 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
9230 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
9231 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
9232 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
9233 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
9234 | //BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST |
9235 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9236 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9237 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9238 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9239 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9240 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9241 | //BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP |
9242 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
9243 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
9244 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
9245 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
9246 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
9247 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
9248 | //BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL |
9249 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
9250 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
9251 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
9252 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
9253 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
9254 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
9255 | |
9256 | |
9257 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
9258 | //BIF_CFG_DEV0_EPF5_0_VENDOR_ID |
9259 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
9260 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
9261 | //BIF_CFG_DEV0_EPF5_0_DEVICE_ID |
9262 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
9263 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
9264 | //BIF_CFG_DEV0_EPF5_0_COMMAND |
9265 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
9266 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
9267 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
9268 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
9269 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
9270 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
9271 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
9272 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
9273 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT 0x8 |
9274 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
9275 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT 0xa |
9276 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
9277 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
9278 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
9279 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
9280 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
9281 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
9282 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
9283 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK 0x0080L |
9284 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK 0x0100L |
9285 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
9286 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK 0x0400L |
9287 | //BIF_CFG_DEV0_EPF5_0_STATUS |
9288 | #define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT 0x3 |
9289 | #define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT 0x4 |
9290 | #define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN__SHIFT 0x5 |
9291 | #define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
9292 | #define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
9293 | #define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
9294 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
9295 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
9296 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
9297 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
9298 | #define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
9299 | #define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK 0x0008L |
9300 | #define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK 0x0010L |
9301 | #define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN_MASK 0x0020L |
9302 | #define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
9303 | #define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
9304 | #define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
9305 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
9306 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
9307 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
9308 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
9309 | #define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
9310 | //BIF_CFG_DEV0_EPF5_0_REVISION_ID |
9311 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
9312 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
9313 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
9314 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
9315 | //BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE |
9316 | #define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
9317 | #define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
9318 | //BIF_CFG_DEV0_EPF5_0_SUB_CLASS |
9319 | #define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
9320 | #define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
9321 | //BIF_CFG_DEV0_EPF5_0_BASE_CLASS |
9322 | #define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
9323 | #define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
9324 | //BIF_CFG_DEV0_EPF5_0_CACHE_LINE |
9325 | #define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
9326 | #define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
9327 | //BIF_CFG_DEV0_EPF5_0_LATENCY |
9328 | #define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
9329 | #define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
9330 | //BIF_CFG_DEV0_EPF5_0_HEADER |
9331 | #define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
9332 | #define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
9333 | #define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK 0x7FL |
9334 | #define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK 0x80L |
9335 | //BIF_CFG_DEV0_EPF5_0_BIST |
9336 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT 0x0 |
9337 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT 0x6 |
9338 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT 0x7 |
9339 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK 0x0FL |
9340 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK 0x40L |
9341 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK 0x80L |
9342 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 |
9343 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
9344 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
9345 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 |
9346 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
9347 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
9348 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 |
9349 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
9350 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
9351 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 |
9352 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
9353 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
9354 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 |
9355 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
9356 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
9357 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 |
9358 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
9359 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
9360 | //BIF_CFG_DEV0_EPF5_0_ADAPTER_ID |
9361 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
9362 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
9363 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
9364 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
9365 | //BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR |
9366 | #define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
9367 | #define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
9368 | //BIF_CFG_DEV0_EPF5_0_CAP_PTR |
9369 | #define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
9370 | #define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
9371 | //BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE |
9372 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
9373 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
9374 | //BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN |
9375 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
9376 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
9377 | //BIF_CFG_DEV0_EPF5_0_MIN_GRANT |
9378 | #define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
9379 | #define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
9380 | //BIF_CFG_DEV0_EPF5_0_MAX_LATENCY |
9381 | #define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
9382 | #define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
9383 | //BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST |
9384 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
9385 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9386 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
9387 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
9388 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
9389 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
9390 | //BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W |
9391 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
9392 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
9393 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
9394 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
9395 | //BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST |
9396 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
9397 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9398 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
9399 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9400 | //BIF_CFG_DEV0_EPF5_0_PMI_CAP |
9401 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT 0x0 |
9402 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
9403 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
9404 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
9405 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
9406 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
9407 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
9408 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK 0x0007L |
9409 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
9410 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
9411 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
9412 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
9413 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
9414 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
9415 | //BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL |
9416 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
9417 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
9418 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
9419 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
9420 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
9421 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
9422 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
9423 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
9424 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
9425 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
9426 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
9427 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
9428 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
9429 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
9430 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
9431 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
9432 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
9433 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
9434 | //BIF_CFG_DEV0_EPF5_0_SBRN |
9435 | #define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT 0x0 |
9436 | #define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK 0xFFL |
9437 | //BIF_CFG_DEV0_EPF5_0_FLADJ |
9438 | #define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT 0x0 |
9439 | #define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK 0x3FL |
9440 | //BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD |
9441 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
9442 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
9443 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
9444 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
9445 | //BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST |
9446 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
9447 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9448 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
9449 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9450 | //BIF_CFG_DEV0_EPF5_0_PCIE_CAP |
9451 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT 0x0 |
9452 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
9453 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
9454 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
9455 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK 0x000FL |
9456 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
9457 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
9458 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
9459 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CAP |
9460 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
9461 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
9462 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
9463 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
9464 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
9465 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
9466 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
9467 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
9468 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
9469 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
9470 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
9471 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
9472 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
9473 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
9474 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
9475 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
9476 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
9477 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
9478 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL |
9479 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
9480 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
9481 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
9482 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
9483 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
9484 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
9485 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
9486 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
9487 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
9488 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
9489 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
9490 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
9491 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
9492 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
9493 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
9494 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
9495 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
9496 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
9497 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
9498 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
9499 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
9500 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
9501 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
9502 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
9503 | //BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS |
9504 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
9505 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
9506 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
9507 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
9508 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
9509 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
9510 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
9511 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
9512 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
9513 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
9514 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
9515 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
9516 | //BIF_CFG_DEV0_EPF5_0_LINK_CAP |
9517 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
9518 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
9519 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
9520 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
9521 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
9522 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
9523 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
9524 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
9525 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
9526 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
9527 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
9528 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
9529 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
9530 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
9531 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
9532 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
9533 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
9534 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
9535 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
9536 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
9537 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
9538 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
9539 | //BIF_CFG_DEV0_EPF5_0_LINK_CNTL |
9540 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
9541 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
9542 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
9543 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
9544 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
9545 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
9546 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
9547 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
9548 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
9549 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
9550 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
9551 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
9552 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
9553 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
9554 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
9555 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
9556 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
9557 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
9558 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
9559 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
9560 | //BIF_CFG_DEV0_EPF5_0_LINK_STATUS |
9561 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
9562 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
9563 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
9564 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
9565 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
9566 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
9567 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
9568 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
9569 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
9570 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
9571 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
9572 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
9573 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
9574 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
9575 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 |
9576 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
9577 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
9578 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
9579 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
9580 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
9581 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
9582 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
9583 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
9584 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
9585 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
9586 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
9587 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
9588 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
9589 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
9590 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
9591 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
9592 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
9593 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
9594 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
9595 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
9596 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
9597 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
9598 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
9599 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
9600 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
9601 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
9602 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
9603 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
9604 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 |
9605 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
9606 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
9607 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
9608 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
9609 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
9610 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
9611 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
9612 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
9613 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
9614 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
9615 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
9616 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
9617 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
9618 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
9619 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
9620 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
9621 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
9622 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
9623 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
9624 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
9625 | //BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 |
9626 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
9627 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
9628 | //BIF_CFG_DEV0_EPF5_0_LINK_CAP2 |
9629 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
9630 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
9631 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
9632 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
9633 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
9634 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
9635 | //BIF_CFG_DEV0_EPF5_0_LINK_CNTL2 |
9636 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
9637 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
9638 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
9639 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
9640 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
9641 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
9642 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
9643 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
9644 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
9645 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
9646 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
9647 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
9648 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
9649 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
9650 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
9651 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
9652 | //BIF_CFG_DEV0_EPF5_0_LINK_STATUS2 |
9653 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
9654 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
9655 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
9656 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
9657 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
9658 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
9659 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
9660 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
9661 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
9662 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
9663 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
9664 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
9665 | //BIF_CFG_DEV0_EPF5_0_SLOT_CAP2 |
9666 | #define BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
9667 | #define BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
9668 | //BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2 |
9669 | #define BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
9670 | #define BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
9671 | //BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2 |
9672 | #define BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
9673 | #define BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
9674 | //BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST |
9675 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
9676 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9677 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
9678 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9679 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL |
9680 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
9681 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
9682 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
9683 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
9684 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
9685 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
9686 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
9687 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
9688 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
9689 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
9690 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO |
9691 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
9692 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
9693 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI |
9694 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
9695 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
9696 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA |
9697 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
9698 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
9699 | //BIF_CFG_DEV0_EPF5_0_MSI_MASK |
9700 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
9701 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
9702 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 |
9703 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
9704 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
9705 | //BIF_CFG_DEV0_EPF5_0_MSI_MASK_64 |
9706 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
9707 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
9708 | //BIF_CFG_DEV0_EPF5_0_MSI_PENDING |
9709 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
9710 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
9711 | //BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 |
9712 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
9713 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
9714 | //BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST |
9715 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
9716 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9717 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
9718 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9719 | //BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL |
9720 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
9721 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
9722 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
9723 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
9724 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
9725 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
9726 | //BIF_CFG_DEV0_EPF5_0_MSIX_TABLE |
9727 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
9728 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
9729 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
9730 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
9731 | //BIF_CFG_DEV0_EPF5_0_MSIX_PBA |
9732 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
9733 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
9734 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
9735 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
9736 | //BIF_CFG_DEV0_EPF5_0_SATA_CAP_0 |
9737 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
9738 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
9739 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
9740 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
9741 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
9742 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
9743 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
9744 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
9745 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
9746 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
9747 | //BIF_CFG_DEV0_EPF5_0_SATA_CAP_1 |
9748 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
9749 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
9750 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
9751 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
9752 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
9753 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
9754 | //BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX |
9755 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
9756 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
9757 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
9758 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
9759 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
9760 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
9761 | //BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA |
9762 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
9763 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
9764 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
9765 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9766 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9767 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9768 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9769 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9770 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9771 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR |
9772 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
9773 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
9774 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
9775 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
9776 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
9777 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
9778 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 |
9779 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
9780 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
9781 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 |
9782 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
9783 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
9784 | //BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
9785 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9786 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9787 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9788 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9789 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9790 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9791 | //BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS |
9792 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
9793 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
9794 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
9795 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
9796 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
9797 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
9798 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
9799 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
9800 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
9801 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
9802 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
9803 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
9804 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
9805 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
9806 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
9807 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
9808 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
9809 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
9810 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
9811 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
9812 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
9813 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
9814 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
9815 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
9816 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
9817 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
9818 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
9819 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
9820 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
9821 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
9822 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
9823 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
9824 | //BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK |
9825 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
9826 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
9827 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
9828 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
9829 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
9830 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
9831 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
9832 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
9833 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
9834 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
9835 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
9836 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
9837 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
9838 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
9839 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
9840 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
9841 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
9842 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
9843 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
9844 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
9845 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
9846 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
9847 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
9848 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
9849 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
9850 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
9851 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
9852 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
9853 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
9854 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
9855 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
9856 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
9857 | //BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY |
9858 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
9859 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
9860 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
9861 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
9862 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
9863 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
9864 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
9865 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
9866 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
9867 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
9868 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
9869 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
9870 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
9871 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
9872 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
9873 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
9874 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
9875 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
9876 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
9877 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
9878 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
9879 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
9880 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
9881 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
9882 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
9883 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
9884 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
9885 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
9886 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
9887 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
9888 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
9889 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
9890 | //BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS |
9891 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
9892 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
9893 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
9894 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
9895 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
9896 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
9897 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
9898 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
9899 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
9900 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
9901 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
9902 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
9903 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
9904 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
9905 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
9906 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
9907 | //BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK |
9908 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
9909 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
9910 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
9911 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
9912 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
9913 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
9914 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
9915 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
9916 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
9917 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
9918 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
9919 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
9920 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
9921 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
9922 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
9923 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
9924 | //BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL |
9925 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
9926 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
9927 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
9928 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
9929 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
9930 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
9931 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
9932 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
9933 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
9934 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
9935 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
9936 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
9937 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
9938 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
9939 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
9940 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
9941 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 |
9942 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
9943 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
9944 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 |
9945 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
9946 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
9947 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 |
9948 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
9949 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
9950 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 |
9951 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
9952 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
9953 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 |
9954 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
9955 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
9956 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 |
9957 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
9958 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
9959 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 |
9960 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
9961 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
9962 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 |
9963 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
9964 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
9965 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST |
9966 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9967 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9968 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9969 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9970 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9971 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9972 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP |
9973 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9974 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9975 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL |
9976 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
9977 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9978 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
9979 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
9980 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9981 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
9982 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP |
9983 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9984 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9985 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL |
9986 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
9987 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9988 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
9989 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
9990 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
9991 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
9992 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP |
9993 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9994 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
9995 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL |
9996 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
9997 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9998 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
9999 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
10000 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10001 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
10002 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP |
10003 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10004 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10005 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL |
10006 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
10007 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10008 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
10009 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
10010 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10011 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
10012 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP |
10013 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10014 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10015 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL |
10016 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
10017 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10018 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
10019 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
10020 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10021 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
10022 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP |
10023 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10024 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10025 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL |
10026 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
10027 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10028 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
10029 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
10030 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10031 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
10032 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
10033 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10034 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10035 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10036 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10037 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10038 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10039 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT |
10040 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
10041 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
10042 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA |
10043 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
10044 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
10045 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
10046 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
10047 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
10048 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
10049 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
10050 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
10051 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
10052 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
10053 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
10054 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
10055 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP |
10056 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
10057 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
10058 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST |
10059 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10060 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10061 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10062 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10063 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10064 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10065 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP |
10066 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
10067 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
10068 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
10069 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
10070 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
10071 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
10072 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
10073 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
10074 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
10075 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
10076 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR |
10077 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
10078 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
10079 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS |
10080 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
10081 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
10082 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
10083 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
10084 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL |
10085 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
10086 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
10087 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
10088 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10089 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10090 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
10091 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10092 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10093 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
10094 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10095 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10096 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
10097 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10098 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10099 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
10100 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10101 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10102 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
10103 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10104 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10105 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
10106 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10107 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10108 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
10109 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10110 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10111 | //BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST |
10112 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10113 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10114 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10115 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10116 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10117 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10118 | //BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP |
10119 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
10120 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
10121 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
10122 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
10123 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
10124 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
10125 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
10126 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
10127 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
10128 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
10129 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
10130 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
10131 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
10132 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
10133 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
10134 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
10135 | //BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL |
10136 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
10137 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
10138 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
10139 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
10140 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
10141 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
10142 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
10143 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
10144 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
10145 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
10146 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
10147 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
10148 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
10149 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
10150 | //BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST |
10151 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10152 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10153 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10154 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10155 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10156 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10157 | //BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP |
10158 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
10159 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
10160 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
10161 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
10162 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
10163 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
10164 | //BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL |
10165 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
10166 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
10167 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
10168 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
10169 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
10170 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
10171 | |
10172 | |
10173 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
10174 | //BIF_CFG_DEV0_EPF6_0_VENDOR_ID |
10175 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
10176 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
10177 | //BIF_CFG_DEV0_EPF6_0_DEVICE_ID |
10178 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
10179 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
10180 | //BIF_CFG_DEV0_EPF6_0_COMMAND |
10181 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
10182 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
10183 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
10184 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
10185 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
10186 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
10187 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
10188 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
10189 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT 0x8 |
10190 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
10191 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT 0xa |
10192 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
10193 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
10194 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
10195 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
10196 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
10197 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
10198 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
10199 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK 0x0080L |
10200 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK 0x0100L |
10201 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
10202 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK 0x0400L |
10203 | //BIF_CFG_DEV0_EPF6_0_STATUS |
10204 | #define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT 0x3 |
10205 | #define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT 0x4 |
10206 | #define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN__SHIFT 0x5 |
10207 | #define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
10208 | #define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
10209 | #define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
10210 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
10211 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
10212 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
10213 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
10214 | #define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
10215 | #define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK 0x0008L |
10216 | #define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK 0x0010L |
10217 | #define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN_MASK 0x0020L |
10218 | #define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
10219 | #define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
10220 | #define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
10221 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
10222 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
10223 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
10224 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
10225 | #define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
10226 | //BIF_CFG_DEV0_EPF6_0_REVISION_ID |
10227 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
10228 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
10229 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
10230 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
10231 | //BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE |
10232 | #define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
10233 | #define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
10234 | //BIF_CFG_DEV0_EPF6_0_SUB_CLASS |
10235 | #define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
10236 | #define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
10237 | //BIF_CFG_DEV0_EPF6_0_BASE_CLASS |
10238 | #define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
10239 | #define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
10240 | //BIF_CFG_DEV0_EPF6_0_CACHE_LINE |
10241 | #define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
10242 | #define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
10243 | //BIF_CFG_DEV0_EPF6_0_LATENCY |
10244 | #define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
10245 | #define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
10246 | //BIF_CFG_DEV0_EPF6_0_HEADER |
10247 | #define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
10248 | #define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
10249 | #define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK 0x7FL |
10250 | #define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK 0x80L |
10251 | //BIF_CFG_DEV0_EPF6_0_BIST |
10252 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT 0x0 |
10253 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT 0x6 |
10254 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT 0x7 |
10255 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK 0x0FL |
10256 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK 0x40L |
10257 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK 0x80L |
10258 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 |
10259 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
10260 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
10261 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 |
10262 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
10263 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
10264 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 |
10265 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
10266 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
10267 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 |
10268 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
10269 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
10270 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 |
10271 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
10272 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
10273 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 |
10274 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
10275 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
10276 | //BIF_CFG_DEV0_EPF6_0_ADAPTER_ID |
10277 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
10278 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
10279 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
10280 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
10281 | //BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR |
10282 | #define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
10283 | #define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
10284 | //BIF_CFG_DEV0_EPF6_0_CAP_PTR |
10285 | #define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
10286 | #define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
10287 | //BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE |
10288 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
10289 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
10290 | //BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN |
10291 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
10292 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
10293 | //BIF_CFG_DEV0_EPF6_0_MIN_GRANT |
10294 | #define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
10295 | #define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
10296 | //BIF_CFG_DEV0_EPF6_0_MAX_LATENCY |
10297 | #define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
10298 | #define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
10299 | //BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST |
10300 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
10301 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10302 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
10303 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
10304 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
10305 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
10306 | //BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W |
10307 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
10308 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
10309 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
10310 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
10311 | //BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST |
10312 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
10313 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10314 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
10315 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
10316 | //BIF_CFG_DEV0_EPF6_0_PMI_CAP |
10317 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT 0x0 |
10318 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
10319 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
10320 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
10321 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
10322 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
10323 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
10324 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK 0x0007L |
10325 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
10326 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
10327 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
10328 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
10329 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
10330 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
10331 | //BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL |
10332 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
10333 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
10334 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
10335 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
10336 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
10337 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
10338 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
10339 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
10340 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
10341 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
10342 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
10343 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
10344 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
10345 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
10346 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
10347 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
10348 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
10349 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
10350 | //BIF_CFG_DEV0_EPF6_0_SBRN |
10351 | #define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT 0x0 |
10352 | #define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK 0xFFL |
10353 | //BIF_CFG_DEV0_EPF6_0_FLADJ |
10354 | #define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT 0x0 |
10355 | #define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK 0x3FL |
10356 | //BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD |
10357 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
10358 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
10359 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
10360 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
10361 | //BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST |
10362 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
10363 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10364 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
10365 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
10366 | //BIF_CFG_DEV0_EPF6_0_PCIE_CAP |
10367 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT 0x0 |
10368 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
10369 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
10370 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
10371 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK 0x000FL |
10372 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
10373 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
10374 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
10375 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CAP |
10376 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
10377 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
10378 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
10379 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
10380 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
10381 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
10382 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
10383 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
10384 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
10385 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
10386 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
10387 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
10388 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
10389 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
10390 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
10391 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
10392 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
10393 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
10394 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL |
10395 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
10396 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
10397 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
10398 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
10399 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
10400 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
10401 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
10402 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
10403 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
10404 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
10405 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
10406 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
10407 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
10408 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
10409 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
10410 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
10411 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
10412 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
10413 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
10414 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
10415 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
10416 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
10417 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
10418 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
10419 | //BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS |
10420 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
10421 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
10422 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
10423 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
10424 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
10425 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
10426 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
10427 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
10428 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
10429 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
10430 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
10431 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
10432 | //BIF_CFG_DEV0_EPF6_0_LINK_CAP |
10433 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
10434 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
10435 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
10436 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
10437 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
10438 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
10439 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
10440 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
10441 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
10442 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
10443 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
10444 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
10445 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
10446 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
10447 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
10448 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
10449 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
10450 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
10451 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
10452 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
10453 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
10454 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
10455 | //BIF_CFG_DEV0_EPF6_0_LINK_CNTL |
10456 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
10457 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
10458 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
10459 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
10460 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
10461 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
10462 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
10463 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
10464 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
10465 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
10466 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
10467 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
10468 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
10469 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
10470 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
10471 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
10472 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
10473 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
10474 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
10475 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
10476 | //BIF_CFG_DEV0_EPF6_0_LINK_STATUS |
10477 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
10478 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
10479 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
10480 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
10481 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
10482 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
10483 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
10484 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
10485 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
10486 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
10487 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
10488 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
10489 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
10490 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
10491 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 |
10492 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
10493 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
10494 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
10495 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
10496 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
10497 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
10498 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
10499 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
10500 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
10501 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
10502 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
10503 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
10504 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
10505 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
10506 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
10507 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
10508 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
10509 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
10510 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
10511 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
10512 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
10513 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
10514 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
10515 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
10516 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
10517 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
10518 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
10519 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
10520 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 |
10521 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
10522 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
10523 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
10524 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
10525 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
10526 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
10527 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
10528 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
10529 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
10530 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
10531 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
10532 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
10533 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
10534 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
10535 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
10536 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
10537 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
10538 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
10539 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
10540 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
10541 | //BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 |
10542 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
10543 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
10544 | //BIF_CFG_DEV0_EPF6_0_LINK_CAP2 |
10545 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
10546 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
10547 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
10548 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
10549 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
10550 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
10551 | //BIF_CFG_DEV0_EPF6_0_LINK_CNTL2 |
10552 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
10553 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
10554 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
10555 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
10556 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
10557 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
10558 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
10559 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
10560 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
10561 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
10562 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
10563 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
10564 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
10565 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
10566 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
10567 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
10568 | //BIF_CFG_DEV0_EPF6_0_LINK_STATUS2 |
10569 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
10570 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
10571 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
10572 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
10573 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
10574 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
10575 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
10576 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
10577 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
10578 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
10579 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
10580 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
10581 | //BIF_CFG_DEV0_EPF6_0_SLOT_CAP2 |
10582 | #define BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
10583 | #define BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
10584 | //BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2 |
10585 | #define BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
10586 | #define BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
10587 | //BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2 |
10588 | #define BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
10589 | #define BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
10590 | //BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST |
10591 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
10592 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10593 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
10594 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
10595 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL |
10596 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
10597 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
10598 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
10599 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
10600 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
10601 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
10602 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
10603 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
10604 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
10605 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
10606 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO |
10607 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
10608 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
10609 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI |
10610 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
10611 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
10612 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA |
10613 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
10614 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
10615 | //BIF_CFG_DEV0_EPF6_0_MSI_MASK |
10616 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
10617 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
10618 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 |
10619 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
10620 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
10621 | //BIF_CFG_DEV0_EPF6_0_MSI_MASK_64 |
10622 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
10623 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
10624 | //BIF_CFG_DEV0_EPF6_0_MSI_PENDING |
10625 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
10626 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
10627 | //BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 |
10628 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
10629 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
10630 | //BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST |
10631 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
10632 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10633 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
10634 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
10635 | //BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL |
10636 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
10637 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
10638 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
10639 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
10640 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
10641 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
10642 | //BIF_CFG_DEV0_EPF6_0_MSIX_TABLE |
10643 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
10644 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
10645 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
10646 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
10647 | //BIF_CFG_DEV0_EPF6_0_MSIX_PBA |
10648 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
10649 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
10650 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
10651 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
10652 | //BIF_CFG_DEV0_EPF6_0_SATA_CAP_0 |
10653 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
10654 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
10655 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
10656 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
10657 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
10658 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
10659 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
10660 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
10661 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
10662 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
10663 | //BIF_CFG_DEV0_EPF6_0_SATA_CAP_1 |
10664 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
10665 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
10666 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
10667 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
10668 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
10669 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
10670 | //BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX |
10671 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
10672 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
10673 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
10674 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
10675 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
10676 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
10677 | //BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA |
10678 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
10679 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
10680 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
10681 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10682 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10683 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10684 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10685 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10686 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10687 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR |
10688 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
10689 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
10690 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
10691 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
10692 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
10693 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
10694 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 |
10695 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
10696 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
10697 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 |
10698 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
10699 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
10700 | //BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
10701 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10702 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10703 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10704 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10705 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10706 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10707 | //BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS |
10708 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
10709 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
10710 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
10711 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
10712 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
10713 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
10714 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
10715 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
10716 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
10717 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
10718 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
10719 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
10720 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
10721 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
10722 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
10723 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
10724 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
10725 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
10726 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
10727 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
10728 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
10729 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
10730 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
10731 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
10732 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
10733 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
10734 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
10735 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
10736 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
10737 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
10738 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
10739 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
10740 | //BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK |
10741 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
10742 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
10743 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
10744 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
10745 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
10746 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
10747 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
10748 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
10749 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
10750 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
10751 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
10752 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
10753 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
10754 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
10755 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
10756 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
10757 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
10758 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
10759 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
10760 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
10761 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
10762 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
10763 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
10764 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
10765 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
10766 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
10767 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
10768 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
10769 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
10770 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
10771 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
10772 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
10773 | //BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY |
10774 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
10775 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
10776 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
10777 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
10778 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
10779 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
10780 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
10781 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
10782 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
10783 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
10784 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
10785 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
10786 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
10787 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
10788 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
10789 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
10790 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
10791 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
10792 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
10793 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
10794 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
10795 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
10796 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
10797 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
10798 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
10799 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
10800 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
10801 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
10802 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
10803 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
10804 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
10805 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
10806 | //BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS |
10807 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
10808 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
10809 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
10810 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
10811 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
10812 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
10813 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
10814 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
10815 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
10816 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
10817 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
10818 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
10819 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
10820 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
10821 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
10822 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
10823 | //BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK |
10824 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
10825 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
10826 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
10827 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
10828 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
10829 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
10830 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
10831 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
10832 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
10833 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
10834 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
10835 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
10836 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
10837 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
10838 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
10839 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
10840 | //BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL |
10841 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
10842 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
10843 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
10844 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
10845 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
10846 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
10847 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
10848 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
10849 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
10850 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
10851 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
10852 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
10853 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
10854 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
10855 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
10856 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
10857 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 |
10858 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
10859 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
10860 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 |
10861 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
10862 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
10863 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 |
10864 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
10865 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
10866 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 |
10867 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
10868 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
10869 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 |
10870 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
10871 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
10872 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 |
10873 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
10874 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
10875 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 |
10876 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
10877 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
10878 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 |
10879 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
10880 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
10881 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST |
10882 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10883 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10884 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10885 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10886 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10887 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10888 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP |
10889 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10890 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10891 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL |
10892 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
10893 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10894 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
10895 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
10896 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10897 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
10898 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP |
10899 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10900 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10901 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL |
10902 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
10903 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10904 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
10905 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
10906 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10907 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
10908 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP |
10909 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10910 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10911 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL |
10912 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
10913 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10914 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
10915 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
10916 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10917 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
10918 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP |
10919 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10920 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10921 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL |
10922 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
10923 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10924 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
10925 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
10926 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10927 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
10928 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP |
10929 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10930 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10931 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL |
10932 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
10933 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10934 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
10935 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
10936 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10937 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
10938 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP |
10939 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10940 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
10941 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL |
10942 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
10943 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10944 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
10945 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
10946 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
10947 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
10948 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
10949 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10950 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10951 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10952 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10953 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10954 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10955 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT |
10956 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
10957 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
10958 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA |
10959 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
10960 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
10961 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
10962 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
10963 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
10964 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
10965 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
10966 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
10967 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
10968 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
10969 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
10970 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
10971 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP |
10972 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
10973 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
10974 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST |
10975 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10976 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10977 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10978 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10979 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10980 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10981 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP |
10982 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
10983 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
10984 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
10985 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
10986 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
10987 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
10988 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
10989 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
10990 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
10991 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
10992 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR |
10993 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
10994 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
10995 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS |
10996 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
10997 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
10998 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
10999 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
11000 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL |
11001 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
11002 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
11003 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
11004 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11005 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11006 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
11007 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11008 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11009 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
11010 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11011 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11012 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
11013 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11014 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11015 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
11016 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11017 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11018 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
11019 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11020 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11021 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
11022 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11023 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11024 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
11025 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11026 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11027 | //BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST |
11028 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11029 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11030 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11031 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11032 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11033 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11034 | //BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP |
11035 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
11036 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
11037 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
11038 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
11039 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
11040 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
11041 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
11042 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
11043 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
11044 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
11045 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
11046 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
11047 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
11048 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
11049 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
11050 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
11051 | //BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL |
11052 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
11053 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
11054 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
11055 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
11056 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
11057 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
11058 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
11059 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
11060 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
11061 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
11062 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
11063 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
11064 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
11065 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
11066 | //BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST |
11067 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11068 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11069 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11070 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11071 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11072 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11073 | //BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP |
11074 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
11075 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
11076 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
11077 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
11078 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
11079 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
11080 | //BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL |
11081 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
11082 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
11083 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
11084 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
11085 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
11086 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
11087 | |
11088 | |
11089 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
11090 | //BIF_CFG_DEV0_EPF7_0_VENDOR_ID |
11091 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
11092 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
11093 | //BIF_CFG_DEV0_EPF7_0_DEVICE_ID |
11094 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
11095 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
11096 | //BIF_CFG_DEV0_EPF7_0_COMMAND |
11097 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
11098 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
11099 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
11100 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
11101 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
11102 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
11103 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
11104 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
11105 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT 0x8 |
11106 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
11107 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT 0xa |
11108 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
11109 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
11110 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
11111 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
11112 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
11113 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
11114 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
11115 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK 0x0080L |
11116 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK 0x0100L |
11117 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
11118 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK 0x0400L |
11119 | //BIF_CFG_DEV0_EPF7_0_STATUS |
11120 | #define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT 0x3 |
11121 | #define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT 0x4 |
11122 | #define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN__SHIFT 0x5 |
11123 | #define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
11124 | #define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
11125 | #define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
11126 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
11127 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
11128 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
11129 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
11130 | #define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
11131 | #define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK 0x0008L |
11132 | #define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK 0x0010L |
11133 | #define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN_MASK 0x0020L |
11134 | #define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
11135 | #define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
11136 | #define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
11137 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
11138 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
11139 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
11140 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
11141 | #define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
11142 | //BIF_CFG_DEV0_EPF7_0_REVISION_ID |
11143 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
11144 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
11145 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
11146 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
11147 | //BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE |
11148 | #define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
11149 | #define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
11150 | //BIF_CFG_DEV0_EPF7_0_SUB_CLASS |
11151 | #define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
11152 | #define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
11153 | //BIF_CFG_DEV0_EPF7_0_BASE_CLASS |
11154 | #define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
11155 | #define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
11156 | //BIF_CFG_DEV0_EPF7_0_CACHE_LINE |
11157 | #define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
11158 | #define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
11159 | //BIF_CFG_DEV0_EPF7_0_LATENCY |
11160 | #define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
11161 | #define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
11162 | //BIF_CFG_DEV0_EPF7_0_HEADER |
11163 | #define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
11164 | #define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
11165 | #define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK 0x7FL |
11166 | #define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK 0x80L |
11167 | //BIF_CFG_DEV0_EPF7_0_BIST |
11168 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT 0x0 |
11169 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT 0x6 |
11170 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT 0x7 |
11171 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK 0x0FL |
11172 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK 0x40L |
11173 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK 0x80L |
11174 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 |
11175 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
11176 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
11177 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 |
11178 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
11179 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
11180 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 |
11181 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
11182 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
11183 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 |
11184 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
11185 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
11186 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 |
11187 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
11188 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
11189 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 |
11190 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
11191 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
11192 | //BIF_CFG_DEV0_EPF7_0_ADAPTER_ID |
11193 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
11194 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
11195 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
11196 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
11197 | //BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR |
11198 | #define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
11199 | #define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
11200 | //BIF_CFG_DEV0_EPF7_0_CAP_PTR |
11201 | #define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
11202 | #define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
11203 | //BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE |
11204 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
11205 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
11206 | //BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN |
11207 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
11208 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
11209 | //BIF_CFG_DEV0_EPF7_0_MIN_GRANT |
11210 | #define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
11211 | #define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
11212 | //BIF_CFG_DEV0_EPF7_0_MAX_LATENCY |
11213 | #define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
11214 | #define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
11215 | //BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST |
11216 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
11217 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11218 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
11219 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
11220 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
11221 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
11222 | //BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W |
11223 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
11224 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
11225 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
11226 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
11227 | //BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST |
11228 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
11229 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11230 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
11231 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11232 | //BIF_CFG_DEV0_EPF7_0_PMI_CAP |
11233 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT 0x0 |
11234 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
11235 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
11236 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
11237 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
11238 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
11239 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
11240 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK 0x0007L |
11241 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
11242 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
11243 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
11244 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
11245 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
11246 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
11247 | //BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL |
11248 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
11249 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
11250 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
11251 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
11252 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
11253 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
11254 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
11255 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
11256 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
11257 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
11258 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
11259 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
11260 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
11261 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
11262 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
11263 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
11264 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
11265 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
11266 | //BIF_CFG_DEV0_EPF7_0_SBRN |
11267 | #define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT 0x0 |
11268 | #define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK 0xFFL |
11269 | //BIF_CFG_DEV0_EPF7_0_FLADJ |
11270 | #define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT 0x0 |
11271 | #define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK 0x3FL |
11272 | //BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD |
11273 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
11274 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
11275 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
11276 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
11277 | //BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST |
11278 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
11279 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11280 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
11281 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11282 | //BIF_CFG_DEV0_EPF7_0_PCIE_CAP |
11283 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT 0x0 |
11284 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
11285 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
11286 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
11287 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK 0x000FL |
11288 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
11289 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
11290 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
11291 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CAP |
11292 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
11293 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
11294 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
11295 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
11296 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
11297 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
11298 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
11299 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
11300 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
11301 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
11302 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
11303 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
11304 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
11305 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
11306 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
11307 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
11308 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
11309 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
11310 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL |
11311 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
11312 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
11313 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
11314 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
11315 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
11316 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
11317 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
11318 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
11319 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
11320 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
11321 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
11322 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
11323 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
11324 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
11325 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
11326 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
11327 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
11328 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
11329 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
11330 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
11331 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
11332 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
11333 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
11334 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
11335 | //BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS |
11336 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
11337 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
11338 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
11339 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
11340 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
11341 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
11342 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
11343 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
11344 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
11345 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
11346 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
11347 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
11348 | //BIF_CFG_DEV0_EPF7_0_LINK_CAP |
11349 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
11350 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
11351 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
11352 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
11353 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
11354 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
11355 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
11356 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
11357 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
11358 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
11359 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
11360 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
11361 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
11362 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
11363 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
11364 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
11365 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
11366 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
11367 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
11368 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
11369 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
11370 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
11371 | //BIF_CFG_DEV0_EPF7_0_LINK_CNTL |
11372 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
11373 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
11374 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
11375 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
11376 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
11377 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
11378 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
11379 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
11380 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
11381 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
11382 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
11383 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
11384 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
11385 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
11386 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
11387 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
11388 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
11389 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
11390 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
11391 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
11392 | //BIF_CFG_DEV0_EPF7_0_LINK_STATUS |
11393 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
11394 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
11395 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
11396 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
11397 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
11398 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
11399 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
11400 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
11401 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
11402 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
11403 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
11404 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
11405 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
11406 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
11407 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 |
11408 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
11409 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
11410 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
11411 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
11412 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
11413 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
11414 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
11415 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
11416 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
11417 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
11418 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
11419 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
11420 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
11421 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
11422 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
11423 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
11424 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
11425 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
11426 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
11427 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
11428 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
11429 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
11430 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
11431 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
11432 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
11433 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
11434 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
11435 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
11436 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 |
11437 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
11438 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
11439 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
11440 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
11441 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
11442 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
11443 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
11444 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
11445 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
11446 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
11447 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
11448 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
11449 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
11450 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
11451 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
11452 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
11453 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
11454 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
11455 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
11456 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
11457 | //BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 |
11458 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
11459 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
11460 | //BIF_CFG_DEV0_EPF7_0_LINK_CAP2 |
11461 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
11462 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
11463 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
11464 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
11465 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
11466 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
11467 | //BIF_CFG_DEV0_EPF7_0_LINK_CNTL2 |
11468 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
11469 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
11470 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
11471 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
11472 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
11473 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
11474 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
11475 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
11476 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
11477 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
11478 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
11479 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
11480 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
11481 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
11482 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
11483 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
11484 | //BIF_CFG_DEV0_EPF7_0_LINK_STATUS2 |
11485 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
11486 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
11487 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
11488 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
11489 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
11490 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
11491 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
11492 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
11493 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
11494 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
11495 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
11496 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
11497 | //BIF_CFG_DEV0_EPF7_0_SLOT_CAP2 |
11498 | #define BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
11499 | #define BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
11500 | //BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2 |
11501 | #define BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
11502 | #define BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
11503 | //BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2 |
11504 | #define BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
11505 | #define BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
11506 | //BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST |
11507 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
11508 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11509 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
11510 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11511 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL |
11512 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
11513 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
11514 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
11515 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
11516 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
11517 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
11518 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
11519 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
11520 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
11521 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
11522 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO |
11523 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
11524 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
11525 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI |
11526 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
11527 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
11528 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA |
11529 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
11530 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
11531 | //BIF_CFG_DEV0_EPF7_0_MSI_MASK |
11532 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
11533 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
11534 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 |
11535 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
11536 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
11537 | //BIF_CFG_DEV0_EPF7_0_MSI_MASK_64 |
11538 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
11539 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
11540 | //BIF_CFG_DEV0_EPF7_0_MSI_PENDING |
11541 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
11542 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
11543 | //BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 |
11544 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
11545 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
11546 | //BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST |
11547 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
11548 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11549 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
11550 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11551 | //BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL |
11552 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
11553 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
11554 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
11555 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
11556 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
11557 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
11558 | //BIF_CFG_DEV0_EPF7_0_MSIX_TABLE |
11559 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
11560 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
11561 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
11562 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
11563 | //BIF_CFG_DEV0_EPF7_0_MSIX_PBA |
11564 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
11565 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
11566 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
11567 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
11568 | //BIF_CFG_DEV0_EPF7_0_SATA_CAP_0 |
11569 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
11570 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
11571 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
11572 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
11573 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
11574 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
11575 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
11576 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
11577 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
11578 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
11579 | //BIF_CFG_DEV0_EPF7_0_SATA_CAP_1 |
11580 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
11581 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
11582 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
11583 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
11584 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
11585 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
11586 | //BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX |
11587 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
11588 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
11589 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
11590 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
11591 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
11592 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
11593 | //BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA |
11594 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
11595 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
11596 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
11597 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11598 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11599 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11600 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11601 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11602 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11603 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR |
11604 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
11605 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
11606 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
11607 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
11608 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
11609 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
11610 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 |
11611 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
11612 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
11613 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 |
11614 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
11615 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
11616 | //BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
11617 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11618 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11619 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11620 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11621 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11622 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11623 | //BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS |
11624 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
11625 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
11626 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
11627 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
11628 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
11629 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
11630 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
11631 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
11632 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
11633 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
11634 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
11635 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
11636 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
11637 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
11638 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
11639 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
11640 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
11641 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
11642 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
11643 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
11644 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
11645 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
11646 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
11647 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
11648 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
11649 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
11650 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
11651 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
11652 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
11653 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
11654 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
11655 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
11656 | //BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK |
11657 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
11658 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
11659 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
11660 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
11661 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
11662 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
11663 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
11664 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
11665 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
11666 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
11667 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
11668 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
11669 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
11670 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
11671 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
11672 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
11673 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
11674 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
11675 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
11676 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
11677 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
11678 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
11679 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
11680 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
11681 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
11682 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
11683 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
11684 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
11685 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
11686 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
11687 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
11688 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
11689 | //BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY |
11690 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
11691 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
11692 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
11693 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
11694 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
11695 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
11696 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
11697 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
11698 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
11699 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
11700 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
11701 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
11702 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
11703 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
11704 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
11705 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
11706 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
11707 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
11708 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
11709 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
11710 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
11711 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
11712 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
11713 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
11714 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
11715 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
11716 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
11717 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
11718 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
11719 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
11720 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
11721 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
11722 | //BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS |
11723 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
11724 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
11725 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
11726 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
11727 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
11728 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
11729 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
11730 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
11731 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
11732 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
11733 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
11734 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
11735 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
11736 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
11737 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
11738 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
11739 | //BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK |
11740 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
11741 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
11742 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
11743 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
11744 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
11745 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
11746 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
11747 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
11748 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
11749 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
11750 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
11751 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
11752 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
11753 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
11754 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
11755 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
11756 | //BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL |
11757 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
11758 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
11759 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
11760 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
11761 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
11762 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
11763 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
11764 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
11765 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
11766 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
11767 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
11768 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
11769 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
11770 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
11771 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
11772 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
11773 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 |
11774 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
11775 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
11776 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 |
11777 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
11778 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
11779 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 |
11780 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
11781 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
11782 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 |
11783 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
11784 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
11785 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 |
11786 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
11787 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
11788 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 |
11789 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
11790 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
11791 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 |
11792 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
11793 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
11794 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 |
11795 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
11796 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
11797 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST |
11798 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11799 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11800 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11801 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11802 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11803 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11804 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP |
11805 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
11806 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
11807 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL |
11808 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
11809 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
11810 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
11811 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
11812 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
11813 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
11814 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP |
11815 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
11816 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
11817 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL |
11818 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
11819 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
11820 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
11821 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
11822 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
11823 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
11824 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP |
11825 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
11826 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
11827 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL |
11828 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
11829 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
11830 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
11831 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
11832 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
11833 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
11834 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP |
11835 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
11836 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
11837 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL |
11838 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
11839 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
11840 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
11841 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
11842 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
11843 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
11844 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP |
11845 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
11846 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
11847 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL |
11848 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
11849 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
11850 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
11851 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
11852 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
11853 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
11854 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP |
11855 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
11856 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
11857 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL |
11858 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
11859 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
11860 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
11861 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
11862 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
11863 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
11864 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
11865 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11866 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11867 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11868 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11869 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11870 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11871 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT |
11872 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
11873 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
11874 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA |
11875 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
11876 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
11877 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
11878 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
11879 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
11880 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
11881 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
11882 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
11883 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
11884 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
11885 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
11886 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
11887 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP |
11888 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
11889 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
11890 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST |
11891 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11892 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11893 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11894 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11895 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11896 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11897 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP |
11898 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
11899 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
11900 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
11901 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
11902 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
11903 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
11904 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
11905 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
11906 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
11907 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
11908 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR |
11909 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
11910 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
11911 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS |
11912 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
11913 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
11914 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
11915 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
11916 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL |
11917 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
11918 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
11919 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
11920 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11921 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11922 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
11923 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11924 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11925 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
11926 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11927 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11928 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
11929 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11930 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11931 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
11932 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11933 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11934 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
11935 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11936 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11937 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
11938 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11939 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11940 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
11941 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
11942 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
11943 | //BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST |
11944 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11945 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11946 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11947 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11948 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11949 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11950 | //BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP |
11951 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
11952 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
11953 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
11954 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
11955 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
11956 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
11957 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
11958 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
11959 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
11960 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
11961 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
11962 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
11963 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
11964 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
11965 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
11966 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
11967 | //BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL |
11968 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
11969 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
11970 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
11971 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
11972 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
11973 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
11974 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
11975 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
11976 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
11977 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
11978 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
11979 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
11980 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
11981 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
11982 | //BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST |
11983 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11984 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11985 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11986 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11987 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11988 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11989 | //BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP |
11990 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
11991 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
11992 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
11993 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
11994 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
11995 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
11996 | //BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL |
11997 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
11998 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
11999 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
12000 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
12001 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
12002 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
12003 | |
12004 | |
12005 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
12006 | //BIF_CFG_DEV1_EPF0_0_VENDOR_ID |
12007 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
12008 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
12009 | //BIF_CFG_DEV1_EPF0_0_DEVICE_ID |
12010 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
12011 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
12012 | //BIF_CFG_DEV1_EPF0_0_COMMAND |
12013 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
12014 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
12015 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
12016 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
12017 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
12018 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
12019 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
12020 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
12021 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
12022 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
12023 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa |
12024 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
12025 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
12026 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
12027 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
12028 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
12029 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
12030 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
12031 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
12032 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L |
12033 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
12034 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L |
12035 | //BIF_CFG_DEV1_EPF0_0_STATUS |
12036 | #define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
12037 | #define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
12038 | #define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN__SHIFT 0x5 |
12039 | #define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
12040 | #define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
12041 | #define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
12042 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
12043 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
12044 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
12045 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
12046 | #define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
12047 | #define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L |
12048 | #define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L |
12049 | #define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN_MASK 0x0020L |
12050 | #define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
12051 | #define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
12052 | #define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
12053 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
12054 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
12055 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
12056 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
12057 | #define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
12058 | //BIF_CFG_DEV1_EPF0_0_REVISION_ID |
12059 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
12060 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
12061 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
12062 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
12063 | //BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE |
12064 | #define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
12065 | #define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
12066 | //BIF_CFG_DEV1_EPF0_0_SUB_CLASS |
12067 | #define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
12068 | #define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
12069 | //BIF_CFG_DEV1_EPF0_0_BASE_CLASS |
12070 | #define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
12071 | #define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
12072 | //BIF_CFG_DEV1_EPF0_0_CACHE_LINE |
12073 | #define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
12074 | #define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
12075 | //BIF_CFG_DEV1_EPF0_0_LATENCY |
12076 | #define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
12077 | #define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
12078 | //BIF_CFG_DEV1_EPF0_0_HEADER |
12079 | #define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
12080 | #define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
12081 | #define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL |
12082 | #define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L |
12083 | //BIF_CFG_DEV1_EPF0_0_BIST |
12084 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 |
12085 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 |
12086 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 |
12087 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK 0x0FL |
12088 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK 0x40L |
12089 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK 0x80L |
12090 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 |
12091 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
12092 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
12093 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 |
12094 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
12095 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
12096 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 |
12097 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
12098 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
12099 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 |
12100 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
12101 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
12102 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 |
12103 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
12104 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
12105 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 |
12106 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
12107 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
12108 | //BIF_CFG_DEV1_EPF0_0_ADAPTER_ID |
12109 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
12110 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
12111 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
12112 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
12113 | //BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR |
12114 | #define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
12115 | #define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
12116 | //BIF_CFG_DEV1_EPF0_0_CAP_PTR |
12117 | #define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
12118 | #define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
12119 | //BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE |
12120 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
12121 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
12122 | //BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN |
12123 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
12124 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
12125 | //BIF_CFG_DEV1_EPF0_0_MIN_GRANT |
12126 | #define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
12127 | #define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
12128 | //BIF_CFG_DEV1_EPF0_0_MAX_LATENCY |
12129 | #define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
12130 | #define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
12131 | //BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST |
12132 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
12133 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12134 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
12135 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
12136 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
12137 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
12138 | //BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W |
12139 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
12140 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
12141 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
12142 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
12143 | //BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST |
12144 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
12145 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12146 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
12147 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12148 | //BIF_CFG_DEV1_EPF0_0_PMI_CAP |
12149 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 |
12150 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
12151 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
12152 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
12153 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
12154 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
12155 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
12156 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L |
12157 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
12158 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
12159 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
12160 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
12161 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
12162 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
12163 | //BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL |
12164 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
12165 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
12166 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
12167 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
12168 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
12169 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
12170 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
12171 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
12172 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
12173 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
12174 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
12175 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
12176 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
12177 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
12178 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
12179 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
12180 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
12181 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
12182 | //BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST |
12183 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
12184 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12185 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
12186 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12187 | //BIF_CFG_DEV1_EPF0_0_PCIE_CAP |
12188 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
12189 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
12190 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
12191 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
12192 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
12193 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
12194 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
12195 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
12196 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CAP |
12197 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
12198 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
12199 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
12200 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
12201 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
12202 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
12203 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
12204 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
12205 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
12206 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
12207 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
12208 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
12209 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
12210 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
12211 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
12212 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
12213 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
12214 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
12215 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL |
12216 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
12217 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
12218 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
12219 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
12220 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
12221 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
12222 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
12223 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
12224 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
12225 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
12226 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
12227 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
12228 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
12229 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
12230 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
12231 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
12232 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
12233 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
12234 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
12235 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
12236 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
12237 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
12238 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
12239 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
12240 | //BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS |
12241 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
12242 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
12243 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
12244 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
12245 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
12246 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
12247 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
12248 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
12249 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
12250 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
12251 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
12252 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
12253 | //BIF_CFG_DEV1_EPF0_0_LINK_CAP |
12254 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
12255 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
12256 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
12257 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
12258 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
12259 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
12260 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
12261 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
12262 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
12263 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
12264 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
12265 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
12266 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
12267 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
12268 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
12269 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
12270 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
12271 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
12272 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
12273 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
12274 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
12275 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
12276 | //BIF_CFG_DEV1_EPF0_0_LINK_CNTL |
12277 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
12278 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
12279 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
12280 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
12281 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
12282 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
12283 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
12284 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
12285 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
12286 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
12287 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
12288 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
12289 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
12290 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
12291 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
12292 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
12293 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
12294 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
12295 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
12296 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
12297 | //BIF_CFG_DEV1_EPF0_0_LINK_STATUS |
12298 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
12299 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
12300 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
12301 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
12302 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
12303 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
12304 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
12305 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
12306 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
12307 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
12308 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
12309 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
12310 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
12311 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
12312 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 |
12313 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
12314 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
12315 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
12316 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
12317 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
12318 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
12319 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
12320 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
12321 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
12322 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
12323 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
12324 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
12325 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
12326 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
12327 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
12328 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
12329 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
12330 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
12331 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
12332 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
12333 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
12334 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
12335 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
12336 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
12337 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
12338 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
12339 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
12340 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
12341 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 |
12342 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
12343 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
12344 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
12345 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
12346 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
12347 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
12348 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
12349 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
12350 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
12351 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
12352 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
12353 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
12354 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
12355 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
12356 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
12357 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
12358 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
12359 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
12360 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
12361 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
12362 | //BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 |
12363 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
12364 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
12365 | //BIF_CFG_DEV1_EPF0_0_LINK_CAP2 |
12366 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
12367 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
12368 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
12369 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
12370 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
12371 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
12372 | //BIF_CFG_DEV1_EPF0_0_LINK_CNTL2 |
12373 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
12374 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
12375 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
12376 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
12377 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
12378 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
12379 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
12380 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
12381 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
12382 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
12383 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
12384 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
12385 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
12386 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
12387 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
12388 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
12389 | //BIF_CFG_DEV1_EPF0_0_LINK_STATUS2 |
12390 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
12391 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
12392 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
12393 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
12394 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
12395 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
12396 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
12397 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
12398 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
12399 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
12400 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
12401 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
12402 | //BIF_CFG_DEV1_EPF0_0_SLOT_CAP2 |
12403 | #define BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
12404 | #define BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
12405 | //BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2 |
12406 | #define BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
12407 | #define BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
12408 | //BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2 |
12409 | #define BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
12410 | #define BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
12411 | //BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST |
12412 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
12413 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12414 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
12415 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12416 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL |
12417 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
12418 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
12419 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
12420 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
12421 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
12422 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
12423 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
12424 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
12425 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
12426 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
12427 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO |
12428 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
12429 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
12430 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI |
12431 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
12432 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
12433 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA |
12434 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
12435 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
12436 | //BIF_CFG_DEV1_EPF0_0_MSI_MASK |
12437 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
12438 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
12439 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 |
12440 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
12441 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
12442 | //BIF_CFG_DEV1_EPF0_0_MSI_MASK_64 |
12443 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
12444 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
12445 | //BIF_CFG_DEV1_EPF0_0_MSI_PENDING |
12446 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
12447 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
12448 | //BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 |
12449 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
12450 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
12451 | //BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST |
12452 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
12453 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12454 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
12455 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12456 | //BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL |
12457 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
12458 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
12459 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
12460 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
12461 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
12462 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
12463 | //BIF_CFG_DEV1_EPF0_0_MSIX_TABLE |
12464 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
12465 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
12466 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
12467 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
12468 | //BIF_CFG_DEV1_EPF0_0_MSIX_PBA |
12469 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
12470 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
12471 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
12472 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
12473 | //BIF_CFG_DEV1_EPF0_0_SATA_CAP_0 |
12474 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
12475 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
12476 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
12477 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
12478 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
12479 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
12480 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
12481 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
12482 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
12483 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
12484 | //BIF_CFG_DEV1_EPF0_0_SATA_CAP_1 |
12485 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
12486 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
12487 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
12488 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
12489 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
12490 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
12491 | //BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX |
12492 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
12493 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
12494 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
12495 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
12496 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
12497 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
12498 | //BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA |
12499 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
12500 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
12501 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
12502 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12503 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12504 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12505 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12506 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12507 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12508 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR |
12509 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
12510 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
12511 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
12512 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
12513 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
12514 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
12515 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 |
12516 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
12517 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
12518 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 |
12519 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
12520 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
12521 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST |
12522 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12523 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12524 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12525 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12526 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12527 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12528 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 |
12529 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
12530 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
12531 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
12532 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
12533 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
12534 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
12535 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
12536 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
12537 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 |
12538 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
12539 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
12540 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
12541 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
12542 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL |
12543 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
12544 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
12545 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
12546 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
12547 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS |
12548 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
12549 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
12550 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP |
12551 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
12552 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
12553 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
12554 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
12555 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
12556 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
12557 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
12558 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
12559 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL |
12560 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
12561 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
12562 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
12563 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
12564 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
12565 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
12566 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
12567 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
12568 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
12569 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
12570 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
12571 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
12572 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS |
12573 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
12574 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
12575 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
12576 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
12577 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP |
12578 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
12579 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
12580 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
12581 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
12582 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
12583 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
12584 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
12585 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
12586 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL |
12587 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
12588 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
12589 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
12590 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
12591 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
12592 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
12593 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
12594 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
12595 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
12596 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
12597 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
12598 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
12599 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS |
12600 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
12601 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
12602 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
12603 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
12604 | //BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
12605 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12606 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12607 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12608 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12609 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12610 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12611 | //BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS |
12612 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
12613 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
12614 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
12615 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
12616 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
12617 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
12618 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
12619 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
12620 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
12621 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
12622 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
12623 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
12624 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
12625 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
12626 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
12627 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
12628 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
12629 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
12630 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
12631 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
12632 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
12633 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
12634 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
12635 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
12636 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
12637 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
12638 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
12639 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
12640 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
12641 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
12642 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
12643 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
12644 | //BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK |
12645 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
12646 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
12647 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
12648 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
12649 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
12650 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
12651 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
12652 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
12653 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
12654 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
12655 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
12656 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
12657 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
12658 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
12659 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
12660 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
12661 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
12662 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
12663 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
12664 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
12665 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
12666 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
12667 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
12668 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
12669 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
12670 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
12671 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
12672 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
12673 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
12674 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
12675 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
12676 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
12677 | //BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY |
12678 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
12679 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
12680 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
12681 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
12682 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
12683 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
12684 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
12685 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
12686 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
12687 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
12688 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
12689 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
12690 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
12691 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
12692 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
12693 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
12694 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
12695 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
12696 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
12697 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
12698 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
12699 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
12700 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
12701 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
12702 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
12703 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
12704 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
12705 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
12706 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
12707 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
12708 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
12709 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
12710 | //BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS |
12711 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
12712 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
12713 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
12714 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
12715 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
12716 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
12717 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
12718 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
12719 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
12720 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
12721 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
12722 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
12723 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
12724 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
12725 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
12726 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
12727 | //BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK |
12728 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
12729 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
12730 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
12731 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
12732 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
12733 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
12734 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
12735 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
12736 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
12737 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
12738 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
12739 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
12740 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
12741 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
12742 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
12743 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
12744 | //BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL |
12745 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
12746 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
12747 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
12748 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
12749 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
12750 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
12751 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
12752 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
12753 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
12754 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
12755 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
12756 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
12757 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
12758 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
12759 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
12760 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
12761 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 |
12762 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
12763 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
12764 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 |
12765 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
12766 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
12767 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 |
12768 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
12769 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
12770 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 |
12771 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
12772 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
12773 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 |
12774 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
12775 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
12776 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 |
12777 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
12778 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
12779 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 |
12780 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
12781 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
12782 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 |
12783 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
12784 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
12785 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST |
12786 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12787 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12788 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12789 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12790 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12791 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12792 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP |
12793 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12794 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
12795 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL |
12796 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
12797 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12798 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
12799 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
12800 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
12801 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
12802 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP |
12803 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12804 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
12805 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL |
12806 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
12807 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12808 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
12809 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
12810 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
12811 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
12812 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP |
12813 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12814 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
12815 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL |
12816 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
12817 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12818 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
12819 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
12820 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
12821 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
12822 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP |
12823 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12824 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
12825 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL |
12826 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
12827 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12828 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
12829 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
12830 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
12831 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
12832 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP |
12833 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12834 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
12835 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL |
12836 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
12837 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12838 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
12839 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
12840 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
12841 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
12842 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP |
12843 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12844 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
12845 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL |
12846 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
12847 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12848 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
12849 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
12850 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
12851 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
12852 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
12853 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12854 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12855 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12856 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12857 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12858 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12859 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT |
12860 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
12861 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
12862 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA |
12863 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
12864 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
12865 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
12866 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
12867 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
12868 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
12869 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
12870 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
12871 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
12872 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
12873 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
12874 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
12875 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP |
12876 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
12877 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
12878 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST |
12879 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12880 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12881 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12882 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12883 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12884 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12885 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP |
12886 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
12887 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
12888 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
12889 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
12890 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
12891 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
12892 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
12893 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
12894 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
12895 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
12896 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR |
12897 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
12898 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
12899 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS |
12900 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
12901 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
12902 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
12903 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
12904 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL |
12905 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
12906 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
12907 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
12908 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12909 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12910 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
12911 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12912 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12913 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
12914 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12915 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12916 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
12917 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12918 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12919 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
12920 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12921 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12922 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
12923 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12924 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12925 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
12926 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12927 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12928 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
12929 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12930 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12931 | //BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST |
12932 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12933 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12934 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12935 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12936 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12937 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12938 | //BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 |
12939 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
12940 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
12941 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
12942 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
12943 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
12944 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
12945 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS |
12946 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
12947 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
12948 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
12949 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
12950 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
12951 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
12952 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
12953 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
12954 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
12955 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
12956 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
12957 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
12958 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
12959 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
12960 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
12961 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
12962 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
12963 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
12964 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
12965 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
12966 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
12967 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
12968 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
12969 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
12970 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
12971 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
12972 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
12973 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
12974 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
12975 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
12976 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
12977 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
12978 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
12979 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
12980 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
12981 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
12982 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
12983 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
12984 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
12985 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
12986 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
12987 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
12988 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
12989 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
12990 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
12991 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
12992 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
12993 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
12994 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
12995 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
12996 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
12997 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
12998 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
12999 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13000 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13001 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13002 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13003 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13004 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13005 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
13006 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13007 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13008 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13009 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13010 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13011 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13012 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13013 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13014 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13015 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13016 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
13017 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13018 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13019 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13020 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13021 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13022 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13023 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13024 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13025 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13026 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13027 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
13028 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13029 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13030 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13031 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13032 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13033 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13034 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13035 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13036 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13037 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13038 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
13039 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13040 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13041 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13042 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13043 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13044 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13045 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13046 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13047 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13048 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13049 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
13050 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13051 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13052 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13053 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13054 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13055 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13056 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13057 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13058 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13059 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13060 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
13061 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13062 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13063 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13064 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13065 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13066 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13067 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13068 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13069 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13070 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13071 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
13072 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13073 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13074 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13075 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13076 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13077 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13078 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13079 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13080 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13081 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13082 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
13083 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13084 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13085 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13086 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13087 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13088 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13089 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13090 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13091 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13092 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13093 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
13094 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13095 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13096 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13097 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13098 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13099 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13100 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13101 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13102 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13103 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13104 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
13105 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13106 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13107 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13108 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13109 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13110 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13111 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13112 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13113 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13114 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13115 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
13116 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
13117 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
13118 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
13119 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
13120 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
13121 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
13122 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
13123 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
13124 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
13125 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
13126 | //BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST |
13127 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13128 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13129 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13130 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13131 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13132 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13133 | //BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP |
13134 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
13135 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
13136 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
13137 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
13138 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
13139 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
13140 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
13141 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
13142 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
13143 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
13144 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
13145 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
13146 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
13147 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
13148 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
13149 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
13150 | //BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL |
13151 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
13152 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
13153 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
13154 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
13155 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
13156 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
13157 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
13158 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
13159 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
13160 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
13161 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
13162 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
13163 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
13164 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
13165 | //BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST |
13166 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13167 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13168 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13169 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13170 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13171 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13172 | //BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP |
13173 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
13174 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
13175 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
13176 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
13177 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
13178 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
13179 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
13180 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
13181 | //BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST |
13182 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13183 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13184 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13185 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13186 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13187 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13188 | //BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP |
13189 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
13190 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
13191 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
13192 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
13193 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
13194 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
13195 | //BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL |
13196 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
13197 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
13198 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
13199 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
13200 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
13201 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
13202 | |
13203 | |
13204 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
13205 | //BIF_CFG_DEV1_EPF1_0_VENDOR_ID |
13206 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
13207 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
13208 | //BIF_CFG_DEV1_EPF1_0_DEVICE_ID |
13209 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
13210 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
13211 | //BIF_CFG_DEV1_EPF1_0_COMMAND |
13212 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
13213 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
13214 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
13215 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
13216 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
13217 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
13218 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
13219 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
13220 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
13221 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
13222 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
13223 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
13224 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
13225 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
13226 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
13227 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
13228 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
13229 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
13230 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
13231 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
13232 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
13233 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
13234 | //BIF_CFG_DEV1_EPF1_0_STATUS |
13235 | #define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
13236 | #define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
13237 | #define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5 |
13238 | #define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
13239 | #define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
13240 | #define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
13241 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
13242 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
13243 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
13244 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
13245 | #define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
13246 | #define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
13247 | #define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
13248 | #define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L |
13249 | #define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
13250 | #define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
13251 | #define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
13252 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
13253 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
13254 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
13255 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
13256 | #define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
13257 | //BIF_CFG_DEV1_EPF1_0_REVISION_ID |
13258 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
13259 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
13260 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
13261 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
13262 | //BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE |
13263 | #define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
13264 | #define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
13265 | //BIF_CFG_DEV1_EPF1_0_SUB_CLASS |
13266 | #define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
13267 | #define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
13268 | //BIF_CFG_DEV1_EPF1_0_BASE_CLASS |
13269 | #define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
13270 | #define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
13271 | //BIF_CFG_DEV1_EPF1_0_CACHE_LINE |
13272 | #define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
13273 | #define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
13274 | //BIF_CFG_DEV1_EPF1_0_LATENCY |
13275 | #define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
13276 | #define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
13277 | //BIF_CFG_DEV1_EPF1_0_HEADER |
13278 | #define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
13279 | #define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
13280 | #define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL |
13281 | #define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L |
13282 | //BIF_CFG_DEV1_EPF1_0_BIST |
13283 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
13284 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
13285 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
13286 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
13287 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
13288 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
13289 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 |
13290 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
13291 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
13292 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 |
13293 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
13294 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
13295 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 |
13296 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
13297 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
13298 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 |
13299 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
13300 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
13301 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 |
13302 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
13303 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
13304 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 |
13305 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
13306 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
13307 | //BIF_CFG_DEV1_EPF1_0_ADAPTER_ID |
13308 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
13309 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
13310 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
13311 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
13312 | //BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR |
13313 | #define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
13314 | #define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
13315 | //BIF_CFG_DEV1_EPF1_0_CAP_PTR |
13316 | #define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
13317 | #define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
13318 | //BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE |
13319 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
13320 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
13321 | //BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN |
13322 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
13323 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
13324 | //BIF_CFG_DEV1_EPF1_0_MIN_GRANT |
13325 | #define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
13326 | #define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
13327 | //BIF_CFG_DEV1_EPF1_0_MAX_LATENCY |
13328 | #define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
13329 | #define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
13330 | //BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST |
13331 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
13332 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13333 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
13334 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
13335 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
13336 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
13337 | //BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W |
13338 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
13339 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
13340 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
13341 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
13342 | //BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST |
13343 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
13344 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13345 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
13346 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13347 | //BIF_CFG_DEV1_EPF1_0_PMI_CAP |
13348 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
13349 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
13350 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
13351 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
13352 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
13353 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
13354 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
13355 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
13356 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
13357 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
13358 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
13359 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
13360 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
13361 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
13362 | //BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL |
13363 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
13364 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
13365 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
13366 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
13367 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
13368 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
13369 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
13370 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
13371 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
13372 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
13373 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
13374 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
13375 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
13376 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
13377 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
13378 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
13379 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
13380 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
13381 | //BIF_CFG_DEV1_EPF1_0_SBRN |
13382 | #define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT 0x0 |
13383 | #define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK 0xFFL |
13384 | //BIF_CFG_DEV1_EPF1_0_FLADJ |
13385 | #define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT 0x0 |
13386 | #define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK 0x3FL |
13387 | //BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD |
13388 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
13389 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
13390 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
13391 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
13392 | //BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST |
13393 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
13394 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13395 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
13396 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13397 | //BIF_CFG_DEV1_EPF1_0_PCIE_CAP |
13398 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
13399 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
13400 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
13401 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
13402 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
13403 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
13404 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
13405 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
13406 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CAP |
13407 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
13408 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
13409 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
13410 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
13411 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
13412 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
13413 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
13414 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
13415 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
13416 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
13417 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
13418 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
13419 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
13420 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
13421 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
13422 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
13423 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
13424 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
13425 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL |
13426 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
13427 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
13428 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
13429 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
13430 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
13431 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
13432 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
13433 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
13434 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
13435 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
13436 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
13437 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
13438 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
13439 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
13440 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
13441 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
13442 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
13443 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
13444 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
13445 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
13446 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
13447 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
13448 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
13449 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
13450 | //BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS |
13451 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
13452 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
13453 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
13454 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
13455 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
13456 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
13457 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
13458 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
13459 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
13460 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
13461 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
13462 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
13463 | //BIF_CFG_DEV1_EPF1_0_LINK_CAP |
13464 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
13465 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
13466 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
13467 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
13468 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
13469 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
13470 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
13471 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
13472 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
13473 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
13474 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
13475 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
13476 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
13477 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
13478 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
13479 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
13480 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
13481 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
13482 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
13483 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
13484 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
13485 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
13486 | //BIF_CFG_DEV1_EPF1_0_LINK_CNTL |
13487 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
13488 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
13489 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
13490 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
13491 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
13492 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
13493 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
13494 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
13495 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
13496 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
13497 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
13498 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
13499 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
13500 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
13501 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
13502 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
13503 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
13504 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
13505 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
13506 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
13507 | //BIF_CFG_DEV1_EPF1_0_LINK_STATUS |
13508 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
13509 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
13510 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
13511 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
13512 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
13513 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
13514 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
13515 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
13516 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
13517 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
13518 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
13519 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
13520 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
13521 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
13522 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 |
13523 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
13524 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
13525 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
13526 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
13527 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
13528 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
13529 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
13530 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
13531 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
13532 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
13533 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
13534 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
13535 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
13536 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
13537 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
13538 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
13539 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
13540 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
13541 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
13542 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
13543 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
13544 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
13545 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
13546 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
13547 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
13548 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
13549 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
13550 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
13551 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 |
13552 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
13553 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
13554 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
13555 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
13556 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
13557 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
13558 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
13559 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
13560 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
13561 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
13562 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
13563 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
13564 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
13565 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
13566 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
13567 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
13568 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
13569 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
13570 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
13571 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
13572 | //BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 |
13573 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
13574 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
13575 | //BIF_CFG_DEV1_EPF1_0_LINK_CAP2 |
13576 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
13577 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
13578 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
13579 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
13580 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
13581 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
13582 | //BIF_CFG_DEV1_EPF1_0_LINK_CNTL2 |
13583 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
13584 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
13585 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
13586 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
13587 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
13588 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
13589 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
13590 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
13591 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
13592 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
13593 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
13594 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
13595 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
13596 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
13597 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
13598 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
13599 | //BIF_CFG_DEV1_EPF1_0_LINK_STATUS2 |
13600 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
13601 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
13602 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
13603 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
13604 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
13605 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
13606 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
13607 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
13608 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
13609 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
13610 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
13611 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
13612 | //BIF_CFG_DEV1_EPF1_0_SLOT_CAP2 |
13613 | #define BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
13614 | #define BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
13615 | //BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2 |
13616 | #define BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
13617 | #define BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
13618 | //BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2 |
13619 | #define BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
13620 | #define BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
13621 | //BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST |
13622 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
13623 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13624 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
13625 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13626 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL |
13627 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
13628 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
13629 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
13630 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
13631 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
13632 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
13633 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
13634 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
13635 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
13636 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
13637 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO |
13638 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
13639 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
13640 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI |
13641 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
13642 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
13643 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA |
13644 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
13645 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
13646 | //BIF_CFG_DEV1_EPF1_0_MSI_MASK |
13647 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
13648 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
13649 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 |
13650 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
13651 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
13652 | //BIF_CFG_DEV1_EPF1_0_MSI_MASK_64 |
13653 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
13654 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
13655 | //BIF_CFG_DEV1_EPF1_0_MSI_PENDING |
13656 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
13657 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
13658 | //BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 |
13659 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
13660 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
13661 | //BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST |
13662 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
13663 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13664 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
13665 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13666 | //BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL |
13667 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
13668 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
13669 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
13670 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
13671 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
13672 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
13673 | //BIF_CFG_DEV1_EPF1_0_MSIX_TABLE |
13674 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
13675 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
13676 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
13677 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
13678 | //BIF_CFG_DEV1_EPF1_0_MSIX_PBA |
13679 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
13680 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
13681 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
13682 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
13683 | //BIF_CFG_DEV1_EPF1_0_SATA_CAP_0 |
13684 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
13685 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
13686 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
13687 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
13688 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
13689 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
13690 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
13691 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
13692 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
13693 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
13694 | //BIF_CFG_DEV1_EPF1_0_SATA_CAP_1 |
13695 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
13696 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
13697 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
13698 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
13699 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
13700 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
13701 | //BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX |
13702 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
13703 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
13704 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
13705 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
13706 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
13707 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
13708 | //BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA |
13709 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
13710 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
13711 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
13712 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13713 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13714 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13715 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13716 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13717 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13718 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR |
13719 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
13720 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
13721 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
13722 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
13723 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
13724 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
13725 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 |
13726 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
13727 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
13728 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 |
13729 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
13730 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
13731 | //BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
13732 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13733 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13734 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13735 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13736 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13737 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13738 | //BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS |
13739 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
13740 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
13741 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
13742 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
13743 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
13744 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
13745 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
13746 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
13747 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
13748 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
13749 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
13750 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
13751 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
13752 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
13753 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
13754 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
13755 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
13756 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
13757 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
13758 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
13759 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
13760 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
13761 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
13762 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
13763 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
13764 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
13765 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
13766 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
13767 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
13768 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
13769 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
13770 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
13771 | //BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK |
13772 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
13773 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
13774 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
13775 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
13776 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
13777 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
13778 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
13779 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
13780 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
13781 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
13782 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
13783 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
13784 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
13785 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
13786 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
13787 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
13788 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
13789 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
13790 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
13791 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
13792 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
13793 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
13794 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
13795 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
13796 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
13797 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
13798 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
13799 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
13800 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
13801 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
13802 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
13803 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
13804 | //BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY |
13805 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
13806 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
13807 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
13808 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
13809 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
13810 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
13811 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
13812 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
13813 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
13814 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
13815 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
13816 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
13817 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
13818 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
13819 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
13820 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
13821 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
13822 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
13823 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
13824 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
13825 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
13826 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
13827 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
13828 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
13829 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
13830 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
13831 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
13832 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
13833 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
13834 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
13835 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
13836 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
13837 | //BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS |
13838 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
13839 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
13840 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
13841 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
13842 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
13843 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
13844 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
13845 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
13846 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
13847 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
13848 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
13849 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
13850 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
13851 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
13852 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
13853 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
13854 | //BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK |
13855 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
13856 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
13857 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
13858 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
13859 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
13860 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
13861 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
13862 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
13863 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
13864 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
13865 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
13866 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
13867 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
13868 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
13869 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
13870 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
13871 | //BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL |
13872 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
13873 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
13874 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
13875 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
13876 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
13877 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
13878 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
13879 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
13880 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
13881 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
13882 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
13883 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
13884 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
13885 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
13886 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
13887 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
13888 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 |
13889 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
13890 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
13891 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 |
13892 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
13893 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
13894 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 |
13895 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
13896 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
13897 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 |
13898 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
13899 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
13900 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 |
13901 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
13902 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
13903 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 |
13904 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
13905 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
13906 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 |
13907 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
13908 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
13909 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 |
13910 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
13911 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
13912 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST |
13913 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13914 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13915 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13916 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13917 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13918 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13919 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP |
13920 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13921 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
13922 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL |
13923 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
13924 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13925 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
13926 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
13927 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
13928 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
13929 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP |
13930 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13931 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
13932 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL |
13933 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
13934 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13935 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
13936 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
13937 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
13938 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
13939 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP |
13940 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13941 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
13942 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL |
13943 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
13944 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13945 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
13946 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
13947 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
13948 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
13949 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP |
13950 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13951 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
13952 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL |
13953 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
13954 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13955 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
13956 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
13957 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
13958 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
13959 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP |
13960 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13961 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
13962 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL |
13963 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
13964 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13965 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
13966 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
13967 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
13968 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
13969 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP |
13970 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13971 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
13972 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL |
13973 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
13974 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13975 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
13976 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
13977 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
13978 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
13979 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
13980 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13981 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13982 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13983 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13984 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13985 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13986 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT |
13987 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
13988 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
13989 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA |
13990 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
13991 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
13992 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
13993 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
13994 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
13995 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
13996 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
13997 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
13998 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
13999 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
14000 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
14001 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
14002 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP |
14003 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
14004 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
14005 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST |
14006 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14007 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14008 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14009 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14010 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14011 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14012 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP |
14013 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
14014 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
14015 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
14016 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
14017 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
14018 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
14019 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
14020 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
14021 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
14022 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
14023 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR |
14024 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
14025 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
14026 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS |
14027 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
14028 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
14029 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
14030 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
14031 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL |
14032 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
14033 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
14034 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
14035 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14036 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14037 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
14038 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14039 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14040 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
14041 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14042 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14043 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
14044 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14045 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14046 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
14047 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14048 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14049 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
14050 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14051 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14052 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
14053 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14054 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14055 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
14056 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14057 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14058 | //BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST |
14059 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14060 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14061 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14062 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14063 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14064 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14065 | //BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP |
14066 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
14067 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
14068 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
14069 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
14070 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
14071 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
14072 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
14073 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
14074 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
14075 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
14076 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
14077 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
14078 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
14079 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
14080 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
14081 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
14082 | //BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL |
14083 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
14084 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
14085 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
14086 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
14087 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
14088 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
14089 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
14090 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
14091 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
14092 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
14093 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
14094 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
14095 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
14096 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
14097 | //BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST |
14098 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14099 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14100 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14101 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14102 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14103 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14104 | //BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP |
14105 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
14106 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
14107 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
14108 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
14109 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
14110 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
14111 | //BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL |
14112 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
14113 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
14114 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
14115 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
14116 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
14117 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
14118 | |
14119 | |
14120 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
14121 | //BIF_CFG_DEV1_EPF2_0_VENDOR_ID |
14122 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
14123 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
14124 | //BIF_CFG_DEV1_EPF2_0_DEVICE_ID |
14125 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
14126 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
14127 | //BIF_CFG_DEV1_EPF2_0_COMMAND |
14128 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
14129 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
14130 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
14131 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
14132 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
14133 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
14134 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
14135 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
14136 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 |
14137 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
14138 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa |
14139 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
14140 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
14141 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
14142 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
14143 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
14144 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
14145 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
14146 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
14147 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L |
14148 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
14149 | #define BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L |
14150 | //BIF_CFG_DEV1_EPF2_0_STATUS |
14151 | #define BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 |
14152 | #define BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 |
14153 | #define BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN__SHIFT 0x5 |
14154 | #define BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
14155 | #define BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
14156 | #define BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
14157 | #define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
14158 | #define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
14159 | #define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
14160 | #define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
14161 | #define BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
14162 | #define BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L |
14163 | #define BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L |
14164 | #define BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN_MASK 0x0020L |
14165 | #define BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
14166 | #define BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
14167 | #define BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
14168 | #define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
14169 | #define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
14170 | #define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
14171 | #define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
14172 | #define BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
14173 | //BIF_CFG_DEV1_EPF2_0_REVISION_ID |
14174 | #define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
14175 | #define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
14176 | #define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
14177 | #define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
14178 | //BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE |
14179 | #define BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
14180 | #define BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
14181 | //BIF_CFG_DEV1_EPF2_0_SUB_CLASS |
14182 | #define BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
14183 | #define BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
14184 | //BIF_CFG_DEV1_EPF2_0_BASE_CLASS |
14185 | #define BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
14186 | #define BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
14187 | //BIF_CFG_DEV1_EPF2_0_CACHE_LINE |
14188 | #define BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
14189 | #define BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
14190 | //BIF_CFG_DEV1_EPF2_0_LATENCY |
14191 | #define BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
14192 | #define BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
14193 | //BIF_CFG_DEV1_EPF2_0_HEADER |
14194 | #define BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
14195 | #define BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
14196 | #define BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL |
14197 | #define BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L |
14198 | //BIF_CFG_DEV1_EPF2_0_BIST |
14199 | #define BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 |
14200 | #define BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 |
14201 | #define BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 |
14202 | #define BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP_MASK 0x0FL |
14203 | #define BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT_MASK 0x40L |
14204 | #define BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP_MASK 0x80L |
14205 | //BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1 |
14206 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
14207 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
14208 | //BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2 |
14209 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
14210 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
14211 | //BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3 |
14212 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
14213 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
14214 | //BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4 |
14215 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
14216 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
14217 | //BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5 |
14218 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
14219 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
14220 | //BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6 |
14221 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
14222 | #define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
14223 | //BIF_CFG_DEV1_EPF2_0_ADAPTER_ID |
14224 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
14225 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
14226 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
14227 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
14228 | //BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR |
14229 | #define BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
14230 | #define BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
14231 | //BIF_CFG_DEV1_EPF2_0_CAP_PTR |
14232 | #define BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
14233 | #define BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
14234 | //BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE |
14235 | #define BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
14236 | #define BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
14237 | //BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN |
14238 | #define BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
14239 | #define BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
14240 | //BIF_CFG_DEV1_EPF2_0_MIN_GRANT |
14241 | #define BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
14242 | #define BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
14243 | //BIF_CFG_DEV1_EPF2_0_MAX_LATENCY |
14244 | #define BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
14245 | #define BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
14246 | //BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST |
14247 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
14248 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14249 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
14250 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
14251 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
14252 | #define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
14253 | //BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W |
14254 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
14255 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
14256 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
14257 | #define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
14258 | //BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST |
14259 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
14260 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14261 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
14262 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14263 | //BIF_CFG_DEV1_EPF2_0_PMI_CAP |
14264 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 |
14265 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
14266 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
14267 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
14268 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
14269 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
14270 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
14271 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L |
14272 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
14273 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
14274 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
14275 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
14276 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
14277 | #define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
14278 | //BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL |
14279 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
14280 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
14281 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
14282 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
14283 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
14284 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
14285 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
14286 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
14287 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
14288 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
14289 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
14290 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
14291 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
14292 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
14293 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
14294 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
14295 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
14296 | #define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
14297 | //BIF_CFG_DEV1_EPF2_0_SBRN |
14298 | #define BIF_CFG_DEV1_EPF2_0_SBRN__SBRN__SHIFT 0x0 |
14299 | #define BIF_CFG_DEV1_EPF2_0_SBRN__SBRN_MASK 0xFFL |
14300 | //BIF_CFG_DEV1_EPF2_0_FLADJ |
14301 | #define BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 |
14302 | #define BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ_MASK 0x3FL |
14303 | //BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD |
14304 | #define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
14305 | #define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
14306 | #define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
14307 | #define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
14308 | //BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST |
14309 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
14310 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14311 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
14312 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14313 | //BIF_CFG_DEV1_EPF2_0_PCIE_CAP |
14314 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
14315 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
14316 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
14317 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
14318 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL |
14319 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
14320 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
14321 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
14322 | //BIF_CFG_DEV1_EPF2_0_DEVICE_CAP |
14323 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
14324 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
14325 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
14326 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
14327 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
14328 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
14329 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
14330 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
14331 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
14332 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
14333 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
14334 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
14335 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
14336 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
14337 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
14338 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
14339 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
14340 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
14341 | //BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL |
14342 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
14343 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
14344 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
14345 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
14346 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
14347 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
14348 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
14349 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
14350 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
14351 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
14352 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
14353 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
14354 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
14355 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
14356 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
14357 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
14358 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
14359 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
14360 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
14361 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
14362 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
14363 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
14364 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
14365 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
14366 | //BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS |
14367 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
14368 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
14369 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
14370 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
14371 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
14372 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
14373 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
14374 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
14375 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
14376 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
14377 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
14378 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
14379 | //BIF_CFG_DEV1_EPF2_0_LINK_CAP |
14380 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
14381 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
14382 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
14383 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
14384 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
14385 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
14386 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
14387 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
14388 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
14389 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
14390 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
14391 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
14392 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
14393 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
14394 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
14395 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
14396 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
14397 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
14398 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
14399 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
14400 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
14401 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
14402 | //BIF_CFG_DEV1_EPF2_0_LINK_CNTL |
14403 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
14404 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
14405 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
14406 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
14407 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
14408 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
14409 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
14410 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
14411 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
14412 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
14413 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
14414 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
14415 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
14416 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
14417 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
14418 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
14419 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
14420 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
14421 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
14422 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
14423 | //BIF_CFG_DEV1_EPF2_0_LINK_STATUS |
14424 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
14425 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
14426 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
14427 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
14428 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
14429 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
14430 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
14431 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
14432 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
14433 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
14434 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
14435 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
14436 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
14437 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
14438 | //BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2 |
14439 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
14440 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
14441 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
14442 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
14443 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
14444 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
14445 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
14446 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
14447 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
14448 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
14449 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
14450 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
14451 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
14452 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
14453 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
14454 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
14455 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
14456 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
14457 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
14458 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
14459 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
14460 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
14461 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
14462 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
14463 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
14464 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
14465 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
14466 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
14467 | //BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2 |
14468 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
14469 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
14470 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
14471 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
14472 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
14473 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
14474 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
14475 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
14476 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
14477 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
14478 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
14479 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
14480 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
14481 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
14482 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
14483 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
14484 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
14485 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
14486 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
14487 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
14488 | //BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2 |
14489 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
14490 | #define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
14491 | //BIF_CFG_DEV1_EPF2_0_LINK_CAP2 |
14492 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
14493 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
14494 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
14495 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
14496 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
14497 | #define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
14498 | //BIF_CFG_DEV1_EPF2_0_LINK_CNTL2 |
14499 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
14500 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
14501 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
14502 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
14503 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
14504 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
14505 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
14506 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
14507 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
14508 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
14509 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
14510 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
14511 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
14512 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
14513 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
14514 | #define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
14515 | //BIF_CFG_DEV1_EPF2_0_LINK_STATUS2 |
14516 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
14517 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
14518 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
14519 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
14520 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
14521 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
14522 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
14523 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
14524 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
14525 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
14526 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
14527 | #define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
14528 | //BIF_CFG_DEV1_EPF2_0_SLOT_CAP2 |
14529 | #define BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
14530 | #define BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
14531 | //BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2 |
14532 | #define BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
14533 | #define BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
14534 | //BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2 |
14535 | #define BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
14536 | #define BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
14537 | //BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST |
14538 | #define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
14539 | #define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14540 | #define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
14541 | #define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14542 | //BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL |
14543 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
14544 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
14545 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
14546 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
14547 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
14548 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
14549 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
14550 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
14551 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
14552 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
14553 | //BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO |
14554 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
14555 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
14556 | //BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI |
14557 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
14558 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
14559 | //BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA |
14560 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
14561 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
14562 | //BIF_CFG_DEV1_EPF2_0_MSI_MASK |
14563 | #define BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
14564 | #define BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
14565 | //BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64 |
14566 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
14567 | #define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
14568 | //BIF_CFG_DEV1_EPF2_0_MSI_MASK_64 |
14569 | #define BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
14570 | #define BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
14571 | //BIF_CFG_DEV1_EPF2_0_MSI_PENDING |
14572 | #define BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
14573 | #define BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
14574 | //BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64 |
14575 | #define BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
14576 | #define BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
14577 | //BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST |
14578 | #define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
14579 | #define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14580 | #define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
14581 | #define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14582 | //BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL |
14583 | #define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
14584 | #define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
14585 | #define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
14586 | #define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
14587 | #define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
14588 | #define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
14589 | //BIF_CFG_DEV1_EPF2_0_MSIX_TABLE |
14590 | #define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
14591 | #define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
14592 | #define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
14593 | #define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
14594 | //BIF_CFG_DEV1_EPF2_0_MSIX_PBA |
14595 | #define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
14596 | #define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
14597 | #define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
14598 | #define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
14599 | //BIF_CFG_DEV1_EPF2_0_SATA_CAP_0 |
14600 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
14601 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
14602 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
14603 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
14604 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
14605 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
14606 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
14607 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
14608 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
14609 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
14610 | //BIF_CFG_DEV1_EPF2_0_SATA_CAP_1 |
14611 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
14612 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
14613 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
14614 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
14615 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
14616 | #define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
14617 | //BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX |
14618 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
14619 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
14620 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
14621 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
14622 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
14623 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
14624 | //BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA |
14625 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
14626 | #define BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
14627 | //BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
14628 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14629 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14630 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14631 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14632 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14633 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14634 | //BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR |
14635 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
14636 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
14637 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
14638 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
14639 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
14640 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
14641 | //BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1 |
14642 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
14643 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
14644 | //BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2 |
14645 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
14646 | #define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
14647 | //BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
14648 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14649 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14650 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14651 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14652 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14653 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14654 | //BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS |
14655 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
14656 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
14657 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
14658 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
14659 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
14660 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
14661 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
14662 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
14663 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
14664 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
14665 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
14666 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
14667 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
14668 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
14669 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
14670 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
14671 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
14672 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
14673 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
14674 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
14675 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
14676 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
14677 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
14678 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
14679 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
14680 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
14681 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
14682 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
14683 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
14684 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
14685 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
14686 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
14687 | //BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK |
14688 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
14689 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
14690 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
14691 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
14692 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
14693 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
14694 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
14695 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
14696 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
14697 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
14698 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
14699 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
14700 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
14701 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
14702 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
14703 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
14704 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
14705 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
14706 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
14707 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
14708 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
14709 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
14710 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
14711 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
14712 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
14713 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
14714 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
14715 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
14716 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
14717 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
14718 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
14719 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
14720 | //BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY |
14721 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
14722 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
14723 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
14724 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
14725 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
14726 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
14727 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
14728 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
14729 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
14730 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
14731 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
14732 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
14733 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
14734 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
14735 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
14736 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
14737 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
14738 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
14739 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
14740 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
14741 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
14742 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
14743 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
14744 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
14745 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
14746 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
14747 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
14748 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
14749 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
14750 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
14751 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
14752 | #define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
14753 | //BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS |
14754 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
14755 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
14756 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
14757 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
14758 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
14759 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
14760 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
14761 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
14762 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
14763 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
14764 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
14765 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
14766 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
14767 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
14768 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
14769 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
14770 | //BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK |
14771 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
14772 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
14773 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
14774 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
14775 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
14776 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
14777 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
14778 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
14779 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
14780 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
14781 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
14782 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
14783 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
14784 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
14785 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
14786 | #define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
14787 | //BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL |
14788 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
14789 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
14790 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
14791 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
14792 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
14793 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
14794 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
14795 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
14796 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
14797 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
14798 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
14799 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
14800 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
14801 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
14802 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
14803 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
14804 | //BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0 |
14805 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
14806 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
14807 | //BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1 |
14808 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
14809 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
14810 | //BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2 |
14811 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
14812 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
14813 | //BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3 |
14814 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
14815 | #define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
14816 | //BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0 |
14817 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
14818 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
14819 | //BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1 |
14820 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
14821 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
14822 | //BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2 |
14823 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
14824 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
14825 | //BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3 |
14826 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
14827 | #define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
14828 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST |
14829 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14830 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14831 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14832 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14833 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14834 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14835 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP |
14836 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14837 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
14838 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL |
14839 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
14840 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14841 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
14842 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
14843 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
14844 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
14845 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP |
14846 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14847 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
14848 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL |
14849 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
14850 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14851 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
14852 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
14853 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
14854 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
14855 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP |
14856 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14857 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
14858 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL |
14859 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
14860 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14861 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
14862 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
14863 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
14864 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
14865 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP |
14866 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14867 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
14868 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL |
14869 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
14870 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14871 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
14872 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
14873 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
14874 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
14875 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP |
14876 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14877 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
14878 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL |
14879 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
14880 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14881 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
14882 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
14883 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
14884 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
14885 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP |
14886 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14887 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
14888 | //BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL |
14889 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
14890 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14891 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
14892 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
14893 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
14894 | #define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
14895 | //BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
14896 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14897 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14898 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14899 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14900 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14901 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14902 | //BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT |
14903 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
14904 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
14905 | //BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA |
14906 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
14907 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
14908 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
14909 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
14910 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
14911 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
14912 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
14913 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
14914 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
14915 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
14916 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
14917 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
14918 | //BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP |
14919 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
14920 | #define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
14921 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST |
14922 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14923 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14924 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14925 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14926 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14927 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14928 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP |
14929 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
14930 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
14931 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
14932 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
14933 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
14934 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
14935 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
14936 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
14937 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
14938 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
14939 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR |
14940 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
14941 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
14942 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS |
14943 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
14944 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
14945 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
14946 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
14947 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL |
14948 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
14949 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
14950 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
14951 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14952 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14953 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
14954 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14955 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14956 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
14957 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14958 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14959 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
14960 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14961 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14962 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
14963 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14964 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14965 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
14966 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14967 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14968 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
14969 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14970 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14971 | //BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
14972 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14973 | #define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14974 | //BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST |
14975 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14976 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14977 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14978 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14979 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14980 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14981 | //BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP |
14982 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
14983 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
14984 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
14985 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
14986 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
14987 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
14988 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
14989 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
14990 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
14991 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
14992 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
14993 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
14994 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
14995 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
14996 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
14997 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
14998 | //BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL |
14999 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
15000 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
15001 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
15002 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
15003 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
15004 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
15005 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
15006 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
15007 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
15008 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
15009 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
15010 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
15011 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
15012 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
15013 | //BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST |
15014 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15015 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15016 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15017 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15018 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15019 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15020 | //BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP |
15021 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
15022 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
15023 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
15024 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
15025 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
15026 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
15027 | //BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL |
15028 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
15029 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
15030 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
15031 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
15032 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
15033 | #define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
15034 | |
15035 | |
15036 | // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
15037 | //BIFPLR0_0_VENDOR_ID |
15038 | #define BIFPLR0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
15039 | #define BIFPLR0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
15040 | //BIFPLR0_0_DEVICE_ID |
15041 | #define BIFPLR0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
15042 | #define BIFPLR0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
15043 | //BIFPLR0_0_COMMAND |
15044 | #define BIFPLR0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
15045 | #define BIFPLR0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
15046 | #define BIFPLR0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
15047 | #define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
15048 | #define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
15049 | #define BIFPLR0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
15050 | #define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
15051 | #define BIFPLR0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
15052 | #define BIFPLR0_0_COMMAND__SERR_EN__SHIFT 0x8 |
15053 | #define BIFPLR0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
15054 | #define BIFPLR0_0_COMMAND__INT_DIS__SHIFT 0xa |
15055 | #define BIFPLR0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
15056 | #define BIFPLR0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
15057 | #define BIFPLR0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
15058 | #define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
15059 | #define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
15060 | #define BIFPLR0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
15061 | #define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
15062 | #define BIFPLR0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
15063 | #define BIFPLR0_0_COMMAND__SERR_EN_MASK 0x0100L |
15064 | #define BIFPLR0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
15065 | #define BIFPLR0_0_COMMAND__INT_DIS_MASK 0x0400L |
15066 | //BIFPLR0_0_STATUS |
15067 | #define BIFPLR0_0_STATUS__INT_STATUS__SHIFT 0x3 |
15068 | #define BIFPLR0_0_STATUS__CAP_LIST__SHIFT 0x4 |
15069 | #define BIFPLR0_0_STATUS__PCI_66_EN__SHIFT 0x5 |
15070 | #define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
15071 | #define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
15072 | #define BIFPLR0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
15073 | #define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
15074 | #define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
15075 | #define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
15076 | #define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
15077 | #define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
15078 | #define BIFPLR0_0_STATUS__INT_STATUS_MASK 0x0008L |
15079 | #define BIFPLR0_0_STATUS__CAP_LIST_MASK 0x0010L |
15080 | #define BIFPLR0_0_STATUS__PCI_66_EN_MASK 0x0020L |
15081 | #define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
15082 | #define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
15083 | #define BIFPLR0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
15084 | #define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
15085 | #define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
15086 | #define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
15087 | #define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
15088 | #define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
15089 | //BIFPLR0_0_REVISION_ID |
15090 | #define BIFPLR0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
15091 | #define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
15092 | #define BIFPLR0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
15093 | #define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
15094 | //BIFPLR0_0_PROG_INTERFACE |
15095 | #define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
15096 | #define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
15097 | //BIFPLR0_0_SUB_CLASS |
15098 | #define BIFPLR0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
15099 | #define BIFPLR0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
15100 | //BIFPLR0_0_BASE_CLASS |
15101 | #define BIFPLR0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
15102 | #define BIFPLR0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
15103 | //BIFPLR0_0_CACHE_LINE |
15104 | #define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
15105 | #define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
15106 | //BIFPLR0_0_LATENCY |
15107 | #define BIFPLR0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
15108 | #define BIFPLR0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
15109 | //BIFPLR0_0_HEADER |
15110 | #define BIFPLR0_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
15111 | #define BIFPLR0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
15112 | #define BIFPLR0_0_HEADER__HEADER_TYPE_MASK 0x7FL |
15113 | #define BIFPLR0_0_HEADER__DEVICE_TYPE_MASK 0x80L |
15114 | //BIFPLR0_0_BIST |
15115 | #define BIFPLR0_0_BIST__BIST_COMP__SHIFT 0x0 |
15116 | #define BIFPLR0_0_BIST__BIST_STRT__SHIFT 0x6 |
15117 | #define BIFPLR0_0_BIST__BIST_CAP__SHIFT 0x7 |
15118 | #define BIFPLR0_0_BIST__BIST_COMP_MASK 0x0FL |
15119 | #define BIFPLR0_0_BIST__BIST_STRT_MASK 0x40L |
15120 | #define BIFPLR0_0_BIST__BIST_CAP_MASK 0x80L |
15121 | //BIFPLR0_0_SUB_BUS_NUMBER_LATENCY |
15122 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
15123 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
15124 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
15125 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
15126 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
15127 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
15128 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
15129 | #define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
15130 | //BIFPLR0_0_IO_BASE_LIMIT |
15131 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
15132 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
15133 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
15134 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
15135 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
15136 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
15137 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
15138 | #define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
15139 | //BIFPLR0_0_SECONDARY_STATUS |
15140 | #define BIFPLR0_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
15141 | #define BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
15142 | #define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
15143 | #define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
15144 | #define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
15145 | #define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
15146 | #define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
15147 | #define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
15148 | #define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
15149 | #define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
15150 | #define BIFPLR0_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
15151 | #define BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
15152 | #define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
15153 | #define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
15154 | #define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
15155 | #define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
15156 | #define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
15157 | #define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
15158 | #define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
15159 | #define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
15160 | //BIFPLR0_0_MEM_BASE_LIMIT |
15161 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
15162 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
15163 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
15164 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
15165 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
15166 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
15167 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
15168 | #define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
15169 | //BIFPLR0_0_PREF_BASE_LIMIT |
15170 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
15171 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
15172 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
15173 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
15174 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
15175 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
15176 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
15177 | #define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
15178 | //BIFPLR0_0_PREF_BASE_UPPER |
15179 | #define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
15180 | #define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
15181 | //BIFPLR0_0_PREF_LIMIT_UPPER |
15182 | #define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
15183 | #define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
15184 | //BIFPLR0_0_IO_BASE_LIMIT_HI |
15185 | #define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
15186 | #define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
15187 | #define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
15188 | #define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
15189 | //BIFPLR0_0_CAP_PTR |
15190 | #define BIFPLR0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
15191 | #define BIFPLR0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
15192 | //BIFPLR0_0_INTERRUPT_LINE |
15193 | #define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
15194 | #define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
15195 | //BIFPLR0_0_INTERRUPT_PIN |
15196 | #define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
15197 | #define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
15198 | //BIFPLR0_0_IRQ_BRIDGE_CNTL |
15199 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
15200 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
15201 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
15202 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
15203 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
15204 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
15205 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
15206 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
15207 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
15208 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
15209 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
15210 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
15211 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
15212 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
15213 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
15214 | #define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
15215 | //BIFPLR0_0_EXT_BRIDGE_CNTL |
15216 | #define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
15217 | #define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
15218 | //BIFPLR0_0_PMI_CAP_LIST |
15219 | #define BIFPLR0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
15220 | #define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15221 | #define BIFPLR0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
15222 | #define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15223 | //BIFPLR0_0_PMI_CAP |
15224 | #define BIFPLR0_0_PMI_CAP__VERSION__SHIFT 0x0 |
15225 | #define BIFPLR0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
15226 | #define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
15227 | #define BIFPLR0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
15228 | #define BIFPLR0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
15229 | #define BIFPLR0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
15230 | #define BIFPLR0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
15231 | #define BIFPLR0_0_PMI_CAP__VERSION_MASK 0x0007L |
15232 | #define BIFPLR0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
15233 | #define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
15234 | #define BIFPLR0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
15235 | #define BIFPLR0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
15236 | #define BIFPLR0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
15237 | #define BIFPLR0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
15238 | //BIFPLR0_0_PMI_STATUS_CNTL |
15239 | #define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
15240 | #define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
15241 | #define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
15242 | #define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
15243 | #define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
15244 | #define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
15245 | #define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
15246 | #define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
15247 | #define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
15248 | #define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
15249 | #define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
15250 | #define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
15251 | #define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
15252 | #define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
15253 | #define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
15254 | #define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
15255 | #define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
15256 | #define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
15257 | //BIFPLR0_0_PCIE_CAP_LIST |
15258 | #define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
15259 | #define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15260 | #define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
15261 | #define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15262 | //BIFPLR0_0_PCIE_CAP |
15263 | #define BIFPLR0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
15264 | #define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
15265 | #define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
15266 | #define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
15267 | #define BIFPLR0_0_PCIE_CAP__VERSION_MASK 0x000FL |
15268 | #define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
15269 | #define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
15270 | #define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
15271 | //BIFPLR0_0_DEVICE_CAP |
15272 | #define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
15273 | #define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
15274 | #define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
15275 | #define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
15276 | #define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
15277 | #define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
15278 | #define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
15279 | #define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
15280 | #define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
15281 | #define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
15282 | #define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
15283 | #define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
15284 | #define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
15285 | #define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
15286 | #define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
15287 | #define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
15288 | #define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
15289 | #define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
15290 | //BIFPLR0_0_DEVICE_CNTL |
15291 | #define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
15292 | #define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
15293 | #define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
15294 | #define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
15295 | #define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
15296 | #define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
15297 | #define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
15298 | #define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
15299 | #define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
15300 | #define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
15301 | #define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
15302 | #define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
15303 | #define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
15304 | #define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
15305 | #define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
15306 | #define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
15307 | #define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
15308 | #define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
15309 | #define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
15310 | #define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
15311 | #define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
15312 | #define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
15313 | #define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
15314 | #define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
15315 | //BIFPLR0_0_DEVICE_STATUS |
15316 | #define BIFPLR0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
15317 | #define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
15318 | #define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
15319 | #define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
15320 | #define BIFPLR0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
15321 | #define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
15322 | #define BIFPLR0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
15323 | #define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
15324 | #define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
15325 | #define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
15326 | #define BIFPLR0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
15327 | #define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
15328 | //BIFPLR0_0_LINK_CAP |
15329 | #define BIFPLR0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
15330 | #define BIFPLR0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
15331 | #define BIFPLR0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
15332 | #define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
15333 | #define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
15334 | #define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
15335 | #define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
15336 | #define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
15337 | #define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
15338 | #define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
15339 | #define BIFPLR0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
15340 | #define BIFPLR0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
15341 | #define BIFPLR0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
15342 | #define BIFPLR0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
15343 | #define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
15344 | #define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
15345 | #define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
15346 | #define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
15347 | #define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
15348 | #define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
15349 | #define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
15350 | #define BIFPLR0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
15351 | //BIFPLR0_0_LINK_CNTL |
15352 | #define BIFPLR0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
15353 | #define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
15354 | #define BIFPLR0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
15355 | #define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
15356 | #define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
15357 | #define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
15358 | #define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
15359 | #define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
15360 | #define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
15361 | #define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
15362 | #define BIFPLR0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
15363 | #define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
15364 | #define BIFPLR0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
15365 | #define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
15366 | #define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
15367 | #define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
15368 | #define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
15369 | #define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
15370 | #define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
15371 | #define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
15372 | //BIFPLR0_0_LINK_STATUS |
15373 | #define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
15374 | #define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
15375 | #define BIFPLR0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
15376 | #define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
15377 | #define BIFPLR0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
15378 | #define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
15379 | #define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
15380 | #define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
15381 | #define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
15382 | #define BIFPLR0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
15383 | #define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
15384 | #define BIFPLR0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
15385 | #define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
15386 | #define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
15387 | //BIFPLR0_0_SLOT_CAP |
15388 | #define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
15389 | #define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
15390 | #define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
15391 | #define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
15392 | #define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
15393 | #define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
15394 | #define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
15395 | #define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
15396 | #define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
15397 | #define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
15398 | #define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
15399 | #define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
15400 | #define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
15401 | #define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
15402 | #define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
15403 | #define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
15404 | #define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
15405 | #define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
15406 | #define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
15407 | #define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
15408 | #define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
15409 | #define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
15410 | #define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
15411 | #define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
15412 | //BIFPLR0_0_SLOT_CNTL |
15413 | #define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
15414 | #define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
15415 | #define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
15416 | #define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
15417 | #define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
15418 | #define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
15419 | #define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
15420 | #define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
15421 | #define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
15422 | #define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
15423 | #define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
15424 | #define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
15425 | #define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
15426 | #define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
15427 | #define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
15428 | #define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
15429 | #define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
15430 | #define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
15431 | #define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
15432 | #define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
15433 | #define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
15434 | #define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
15435 | #define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
15436 | #define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
15437 | //BIFPLR0_0_SLOT_STATUS |
15438 | #define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
15439 | #define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
15440 | #define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
15441 | #define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
15442 | #define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
15443 | #define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
15444 | #define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
15445 | #define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
15446 | #define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
15447 | #define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
15448 | #define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
15449 | #define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
15450 | #define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
15451 | #define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
15452 | #define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
15453 | #define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
15454 | #define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
15455 | #define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
15456 | //BIFPLR0_0_ROOT_CNTL |
15457 | #define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
15458 | #define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
15459 | #define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
15460 | #define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
15461 | #define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
15462 | #define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
15463 | #define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
15464 | #define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
15465 | #define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
15466 | #define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
15467 | //BIFPLR0_0_ROOT_CAP |
15468 | #define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
15469 | #define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
15470 | //BIFPLR0_0_ROOT_STATUS |
15471 | #define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
15472 | #define BIFPLR0_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
15473 | #define BIFPLR0_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
15474 | #define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
15475 | #define BIFPLR0_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
15476 | #define BIFPLR0_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
15477 | //BIFPLR0_0_DEVICE_CAP2 |
15478 | #define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
15479 | #define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
15480 | #define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
15481 | #define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
15482 | #define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
15483 | #define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
15484 | #define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
15485 | #define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
15486 | #define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
15487 | #define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
15488 | #define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
15489 | #define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
15490 | #define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
15491 | #define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
15492 | #define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
15493 | #define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
15494 | #define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
15495 | #define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
15496 | #define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
15497 | #define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
15498 | #define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
15499 | #define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
15500 | #define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
15501 | #define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
15502 | #define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
15503 | #define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
15504 | #define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
15505 | #define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
15506 | //BIFPLR0_0_DEVICE_CNTL2 |
15507 | #define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
15508 | #define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
15509 | #define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
15510 | #define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
15511 | #define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
15512 | #define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
15513 | #define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
15514 | #define BIFPLR0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
15515 | #define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
15516 | #define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
15517 | #define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
15518 | #define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
15519 | #define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
15520 | #define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
15521 | #define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
15522 | #define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
15523 | #define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
15524 | #define BIFPLR0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
15525 | #define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
15526 | #define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
15527 | //BIFPLR0_0_DEVICE_STATUS2 |
15528 | #define BIFPLR0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
15529 | #define BIFPLR0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
15530 | //BIFPLR0_0_LINK_CAP2 |
15531 | #define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
15532 | #define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
15533 | #define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
15534 | #define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
15535 | #define BIFPLR0_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
15536 | #define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
15537 | #define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
15538 | #define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
15539 | #define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
15540 | #define BIFPLR0_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
15541 | //BIFPLR0_0_LINK_CNTL2 |
15542 | #define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
15543 | #define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
15544 | #define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
15545 | #define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
15546 | #define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
15547 | #define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
15548 | #define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
15549 | #define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
15550 | #define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
15551 | #define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
15552 | #define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
15553 | #define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
15554 | #define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
15555 | #define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
15556 | #define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
15557 | #define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
15558 | //BIFPLR0_0_LINK_STATUS2 |
15559 | #define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
15560 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
15561 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
15562 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
15563 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
15564 | #define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
15565 | #define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
15566 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
15567 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
15568 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
15569 | #define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
15570 | #define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
15571 | //BIFPLR0_0_SLOT_CAP2 |
15572 | #define BIFPLR0_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
15573 | #define BIFPLR0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
15574 | //BIFPLR0_0_SLOT_CNTL2 |
15575 | #define BIFPLR0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
15576 | #define BIFPLR0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
15577 | //BIFPLR0_0_SLOT_STATUS2 |
15578 | #define BIFPLR0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
15579 | #define BIFPLR0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
15580 | //BIFPLR0_0_MSI_CAP_LIST |
15581 | #define BIFPLR0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
15582 | #define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15583 | #define BIFPLR0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
15584 | #define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15585 | //BIFPLR0_0_MSI_MSG_CNTL |
15586 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
15587 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
15588 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
15589 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
15590 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
15591 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
15592 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
15593 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
15594 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
15595 | #define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
15596 | //BIFPLR0_0_MSI_MSG_ADDR_LO |
15597 | #define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
15598 | #define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
15599 | //BIFPLR0_0_MSI_MSG_ADDR_HI |
15600 | #define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
15601 | #define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
15602 | //BIFPLR0_0_MSI_MSG_DATA |
15603 | #define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
15604 | #define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
15605 | //BIFPLR0_0_MSI_MSG_DATA_64 |
15606 | #define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
15607 | #define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
15608 | //BIFPLR0_0_SSID_CAP_LIST |
15609 | #define BIFPLR0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
15610 | #define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15611 | #define BIFPLR0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
15612 | #define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15613 | //BIFPLR0_0_SSID_CAP |
15614 | #define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
15615 | #define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
15616 | #define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
15617 | #define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
15618 | //BIFPLR0_0_MSI_MAP_CAP_LIST |
15619 | #define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
15620 | #define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15621 | #define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
15622 | #define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15623 | //BIFPLR0_0_MSI_MAP_CAP |
15624 | #define BIFPLR0_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
15625 | #define BIFPLR0_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
15626 | #define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
15627 | #define BIFPLR0_0_MSI_MAP_CAP__EN_MASK 0x0001L |
15628 | #define BIFPLR0_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
15629 | #define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
15630 | //BIFPLR0_0_MSI_MAP_ADDR_LO |
15631 | #define BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
15632 | #define BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
15633 | //BIFPLR0_0_MSI_MAP_ADDR_HI |
15634 | #define BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
15635 | #define BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
15636 | //BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
15637 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15638 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15639 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15640 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15641 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15642 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15643 | //BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR |
15644 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
15645 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
15646 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
15647 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
15648 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
15649 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
15650 | //BIFPLR0_0_PCIE_VENDOR_SPECIFIC1 |
15651 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
15652 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
15653 | //BIFPLR0_0_PCIE_VENDOR_SPECIFIC2 |
15654 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
15655 | #define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
15656 | //BIFPLR0_0_PCIE_VC_ENH_CAP_LIST |
15657 | #define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15658 | #define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15659 | #define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15660 | #define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15661 | #define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15662 | #define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15663 | //BIFPLR0_0_PCIE_PORT_VC_CAP_REG1 |
15664 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
15665 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
15666 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
15667 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
15668 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
15669 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
15670 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
15671 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
15672 | //BIFPLR0_0_PCIE_PORT_VC_CAP_REG2 |
15673 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
15674 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
15675 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
15676 | #define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
15677 | //BIFPLR0_0_PCIE_PORT_VC_CNTL |
15678 | #define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
15679 | #define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
15680 | #define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
15681 | #define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
15682 | //BIFPLR0_0_PCIE_PORT_VC_STATUS |
15683 | #define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
15684 | #define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
15685 | //BIFPLR0_0_PCIE_VC0_RESOURCE_CAP |
15686 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
15687 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
15688 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
15689 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
15690 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
15691 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
15692 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
15693 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
15694 | //BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL |
15695 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
15696 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
15697 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
15698 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
15699 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
15700 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
15701 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
15702 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
15703 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
15704 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
15705 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
15706 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
15707 | //BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS |
15708 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
15709 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
15710 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
15711 | #define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
15712 | //BIFPLR0_0_PCIE_VC1_RESOURCE_CAP |
15713 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
15714 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
15715 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
15716 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
15717 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
15718 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
15719 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
15720 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
15721 | //BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL |
15722 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
15723 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
15724 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
15725 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
15726 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
15727 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
15728 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
15729 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
15730 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
15731 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
15732 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
15733 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
15734 | //BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS |
15735 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
15736 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
15737 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
15738 | #define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
15739 | //BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
15740 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15741 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15742 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15743 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15744 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15745 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15746 | //BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 |
15747 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
15748 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
15749 | //BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 |
15750 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
15751 | #define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
15752 | //BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
15753 | #define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15754 | #define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15755 | #define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15756 | #define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15757 | #define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15758 | #define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15759 | //BIFPLR0_0_PCIE_UNCORR_ERR_STATUS |
15760 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
15761 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
15762 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
15763 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
15764 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
15765 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
15766 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
15767 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
15768 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
15769 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
15770 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
15771 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
15772 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
15773 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
15774 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
15775 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
15776 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
15777 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
15778 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
15779 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
15780 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
15781 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
15782 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
15783 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
15784 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
15785 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
15786 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
15787 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
15788 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
15789 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
15790 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
15791 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
15792 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
15793 | #define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
15794 | //BIFPLR0_0_PCIE_UNCORR_ERR_MASK |
15795 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
15796 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
15797 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
15798 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
15799 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
15800 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
15801 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
15802 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
15803 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
15804 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
15805 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
15806 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
15807 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
15808 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
15809 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
15810 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
15811 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
15812 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
15813 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
15814 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
15815 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
15816 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
15817 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
15818 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
15819 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
15820 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
15821 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
15822 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
15823 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
15824 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
15825 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
15826 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
15827 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
15828 | #define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
15829 | //BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY |
15830 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
15831 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
15832 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
15833 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
15834 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
15835 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
15836 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
15837 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
15838 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
15839 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
15840 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
15841 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
15842 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
15843 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
15844 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
15845 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
15846 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
15847 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
15848 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
15849 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
15850 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
15851 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
15852 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
15853 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
15854 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
15855 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
15856 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
15857 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
15858 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
15859 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
15860 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
15861 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
15862 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
15863 | #define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
15864 | //BIFPLR0_0_PCIE_CORR_ERR_STATUS |
15865 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
15866 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
15867 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
15868 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
15869 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
15870 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
15871 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
15872 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
15873 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
15874 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
15875 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
15876 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
15877 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
15878 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
15879 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
15880 | #define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
15881 | //BIFPLR0_0_PCIE_CORR_ERR_MASK |
15882 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
15883 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
15884 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
15885 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
15886 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
15887 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
15888 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
15889 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
15890 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
15891 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
15892 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
15893 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
15894 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
15895 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
15896 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
15897 | #define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
15898 | //BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL |
15899 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
15900 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
15901 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
15902 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
15903 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
15904 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
15905 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
15906 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
15907 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
15908 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
15909 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
15910 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
15911 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
15912 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
15913 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
15914 | #define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
15915 | //BIFPLR0_0_PCIE_HDR_LOG0 |
15916 | #define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
15917 | #define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
15918 | //BIFPLR0_0_PCIE_HDR_LOG1 |
15919 | #define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
15920 | #define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
15921 | //BIFPLR0_0_PCIE_HDR_LOG2 |
15922 | #define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
15923 | #define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
15924 | //BIFPLR0_0_PCIE_HDR_LOG3 |
15925 | #define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
15926 | #define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
15927 | //BIFPLR0_0_PCIE_ROOT_ERR_CMD |
15928 | #define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
15929 | #define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
15930 | #define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
15931 | #define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
15932 | #define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
15933 | #define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
15934 | //BIFPLR0_0_PCIE_ROOT_ERR_STATUS |
15935 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
15936 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
15937 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
15938 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
15939 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
15940 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
15941 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
15942 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
15943 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
15944 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
15945 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
15946 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
15947 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
15948 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
15949 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
15950 | #define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
15951 | //BIFPLR0_0_PCIE_ERR_SRC_ID |
15952 | #define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
15953 | #define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
15954 | #define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
15955 | #define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
15956 | //BIFPLR0_0_PCIE_TLP_PREFIX_LOG0 |
15957 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
15958 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
15959 | //BIFPLR0_0_PCIE_TLP_PREFIX_LOG1 |
15960 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
15961 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
15962 | //BIFPLR0_0_PCIE_TLP_PREFIX_LOG2 |
15963 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
15964 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
15965 | //BIFPLR0_0_PCIE_TLP_PREFIX_LOG3 |
15966 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
15967 | #define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
15968 | //BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST |
15969 | #define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15970 | #define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15971 | #define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15972 | #define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15973 | #define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15974 | #define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15975 | //BIFPLR0_0_PCIE_LINK_CNTL3 |
15976 | #define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
15977 | #define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
15978 | #define BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
15979 | #define BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
15980 | #define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
15981 | #define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
15982 | #define BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
15983 | #define BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
15984 | //BIFPLR0_0_PCIE_LANE_ERROR_STATUS |
15985 | #define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
15986 | #define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
15987 | #define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
15988 | #define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
15989 | //BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
15990 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
15991 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
15992 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
15993 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
15994 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
15995 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
15996 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
15997 | #define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
15998 | //BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
15999 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16000 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16001 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16002 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16003 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16004 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16005 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16006 | #define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16007 | //BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
16008 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16009 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16010 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16011 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16012 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16013 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16014 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16015 | #define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16016 | //BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
16017 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16018 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16019 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16020 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16021 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16022 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16023 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16024 | #define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16025 | //BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
16026 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16027 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16028 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16029 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16030 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16031 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16032 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16033 | #define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16034 | //BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
16035 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16036 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16037 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16038 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16039 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16040 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16041 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16042 | #define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16043 | //BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
16044 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16045 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16046 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16047 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16048 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16049 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16050 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16051 | #define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16052 | //BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
16053 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16054 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16055 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16056 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16057 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16058 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16059 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16060 | #define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16061 | //BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
16062 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16063 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16064 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16065 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16066 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16067 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16068 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16069 | #define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16070 | //BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
16071 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16072 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16073 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16074 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16075 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16076 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16077 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16078 | #define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16079 | //BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
16080 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16081 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16082 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16083 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16084 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16085 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16086 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16087 | #define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16088 | //BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
16089 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16090 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16091 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16092 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16093 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16094 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16095 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16096 | #define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16097 | //BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
16098 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16099 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16100 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16101 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16102 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16103 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16104 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16105 | #define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16106 | //BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
16107 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16108 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16109 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16110 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16111 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16112 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16113 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16114 | #define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16115 | //BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
16116 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16117 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16118 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16119 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16120 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16121 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16122 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16123 | #define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16124 | //BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
16125 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
16126 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
16127 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
16128 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
16129 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
16130 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
16131 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
16132 | #define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
16133 | //BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST |
16134 | #define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16135 | #define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16136 | #define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16137 | #define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16138 | #define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16139 | #define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16140 | //BIFPLR0_0_PCIE_ACS_CAP |
16141 | #define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
16142 | #define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
16143 | #define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
16144 | #define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
16145 | #define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
16146 | #define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
16147 | #define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
16148 | #define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
16149 | #define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
16150 | #define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
16151 | #define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
16152 | #define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
16153 | #define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
16154 | #define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
16155 | #define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
16156 | #define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
16157 | //BIFPLR0_0_PCIE_ACS_CNTL |
16158 | #define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
16159 | #define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
16160 | #define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
16161 | #define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
16162 | #define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
16163 | #define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
16164 | #define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
16165 | #define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
16166 | #define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
16167 | #define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
16168 | #define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
16169 | #define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
16170 | #define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
16171 | #define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
16172 | //BIFPLR0_0_PCIE_MC_ENH_CAP_LIST |
16173 | #define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16174 | #define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16175 | #define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16176 | #define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16177 | #define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16178 | #define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16179 | //BIFPLR0_0_PCIE_MC_CAP |
16180 | #define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
16181 | #define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
16182 | #define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
16183 | #define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
16184 | //BIFPLR0_0_PCIE_MC_CNTL |
16185 | #define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
16186 | #define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
16187 | #define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
16188 | #define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
16189 | //BIFPLR0_0_PCIE_MC_ADDR0 |
16190 | #define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
16191 | #define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
16192 | #define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
16193 | #define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
16194 | //BIFPLR0_0_PCIE_MC_ADDR1 |
16195 | #define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
16196 | #define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
16197 | //BIFPLR0_0_PCIE_MC_RCV0 |
16198 | #define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
16199 | #define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
16200 | //BIFPLR0_0_PCIE_MC_RCV1 |
16201 | #define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
16202 | #define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
16203 | //BIFPLR0_0_PCIE_MC_BLOCK_ALL0 |
16204 | #define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
16205 | #define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
16206 | //BIFPLR0_0_PCIE_MC_BLOCK_ALL1 |
16207 | #define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
16208 | #define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
16209 | //BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
16210 | #define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
16211 | #define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
16212 | //BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
16213 | #define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
16214 | #define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
16215 | //BIFPLR0_0_PCIE_MC_OVERLAY_BAR0 |
16216 | #define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
16217 | #define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
16218 | #define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
16219 | #define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
16220 | //BIFPLR0_0_PCIE_MC_OVERLAY_BAR1 |
16221 | #define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
16222 | #define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
16223 | //BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST |
16224 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
16225 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
16226 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16227 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16228 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16229 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16230 | //BIFPLR0_0_PCIE_L1_PM_SUB_CAP |
16231 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
16232 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
16233 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
16234 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
16235 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
16236 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
16237 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
16238 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
16239 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
16240 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
16241 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
16242 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
16243 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
16244 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
16245 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
16246 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
16247 | //BIFPLR0_0_PCIE_L1_PM_SUB_CNTL |
16248 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
16249 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
16250 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
16251 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
16252 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
16253 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
16254 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
16255 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
16256 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
16257 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
16258 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
16259 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
16260 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
16261 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
16262 | //BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 |
16263 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
16264 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
16265 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
16266 | #define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
16267 | //BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST |
16268 | #define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16269 | #define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16270 | #define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16271 | #define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16272 | #define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16273 | #define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16274 | //BIFPLR0_0_PCIE_DPC_CAP_LIST |
16275 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
16276 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
16277 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
16278 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
16279 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
16280 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
16281 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
16282 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
16283 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
16284 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
16285 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
16286 | #define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
16287 | //BIFPLR0_0_PCIE_DPC_CNTL |
16288 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
16289 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
16290 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
16291 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
16292 | #define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
16293 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
16294 | #define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
16295 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
16296 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
16297 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
16298 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
16299 | #define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
16300 | #define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
16301 | #define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
16302 | //BIFPLR0_0_PCIE_DPC_STATUS |
16303 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
16304 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
16305 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
16306 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
16307 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
16308 | #define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
16309 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
16310 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
16311 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
16312 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
16313 | #define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
16314 | #define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
16315 | //BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID |
16316 | #define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
16317 | #define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
16318 | //BIFPLR0_0_PCIE_RP_PIO_STATUS |
16319 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
16320 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
16321 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
16322 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
16323 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
16324 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
16325 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
16326 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
16327 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
16328 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
16329 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
16330 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
16331 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
16332 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
16333 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
16334 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
16335 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
16336 | #define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
16337 | //BIFPLR0_0_PCIE_RP_PIO_MASK |
16338 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
16339 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
16340 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
16341 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
16342 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
16343 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
16344 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
16345 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
16346 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
16347 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
16348 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
16349 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
16350 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
16351 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
16352 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
16353 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
16354 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
16355 | #define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
16356 | //BIFPLR0_0_PCIE_RP_PIO_SEVERITY |
16357 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
16358 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
16359 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
16360 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
16361 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
16362 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
16363 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
16364 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
16365 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
16366 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
16367 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
16368 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
16369 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
16370 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
16371 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
16372 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
16373 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
16374 | #define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
16375 | //BIFPLR0_0_PCIE_RP_PIO_SYSERROR |
16376 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
16377 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
16378 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
16379 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
16380 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
16381 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
16382 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
16383 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
16384 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
16385 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
16386 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
16387 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
16388 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
16389 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
16390 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
16391 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
16392 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
16393 | #define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
16394 | //BIFPLR0_0_PCIE_RP_PIO_EXCEPTION |
16395 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
16396 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
16397 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
16398 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
16399 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
16400 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
16401 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
16402 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
16403 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
16404 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
16405 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
16406 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
16407 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
16408 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
16409 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
16410 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
16411 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
16412 | #define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
16413 | //BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 |
16414 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
16415 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
16416 | //BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 |
16417 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
16418 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
16419 | //BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 |
16420 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
16421 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
16422 | //BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 |
16423 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
16424 | #define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
16425 | //BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG |
16426 | #define BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
16427 | #define BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
16428 | //BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 |
16429 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
16430 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
16431 | //BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 |
16432 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
16433 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
16434 | //BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 |
16435 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
16436 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
16437 | //BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 |
16438 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
16439 | #define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
16440 | //BIFPLR0_0_PCIE_ESM_CAP_LIST |
16441 | #define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
16442 | #define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
16443 | #define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16444 | #define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16445 | #define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16446 | #define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16447 | //BIFPLR0_0_PCIE_ESM_HEADER_1 |
16448 | #define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
16449 | #define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
16450 | #define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
16451 | #define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
16452 | #define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
16453 | #define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
16454 | //BIFPLR0_0_PCIE_ESM_HEADER_2 |
16455 | #define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
16456 | #define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
16457 | //BIFPLR0_0_PCIE_ESM_STATUS |
16458 | #define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
16459 | #define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
16460 | #define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
16461 | #define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
16462 | //BIFPLR0_0_PCIE_ESM_CTRL |
16463 | #define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
16464 | #define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
16465 | #define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
16466 | #define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
16467 | #define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
16468 | #define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
16469 | //BIFPLR0_0_PCIE_ESM_CAP_1 |
16470 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
16471 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
16472 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
16473 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
16474 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
16475 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
16476 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
16477 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
16478 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
16479 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
16480 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
16481 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
16482 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
16483 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
16484 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
16485 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
16486 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
16487 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
16488 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
16489 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
16490 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
16491 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
16492 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
16493 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
16494 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
16495 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
16496 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
16497 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
16498 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
16499 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
16500 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
16501 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
16502 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
16503 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
16504 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
16505 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
16506 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
16507 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
16508 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
16509 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
16510 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
16511 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
16512 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
16513 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
16514 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
16515 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
16516 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
16517 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
16518 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
16519 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
16520 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
16521 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
16522 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
16523 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
16524 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
16525 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
16526 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
16527 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
16528 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
16529 | #define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
16530 | //BIFPLR0_0_PCIE_ESM_CAP_2 |
16531 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
16532 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
16533 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
16534 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
16535 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
16536 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
16537 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
16538 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
16539 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
16540 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
16541 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
16542 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
16543 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
16544 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
16545 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
16546 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
16547 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
16548 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
16549 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
16550 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
16551 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
16552 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
16553 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
16554 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
16555 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
16556 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
16557 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
16558 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
16559 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
16560 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
16561 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
16562 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
16563 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
16564 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
16565 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
16566 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
16567 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
16568 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
16569 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
16570 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
16571 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
16572 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
16573 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
16574 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
16575 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
16576 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
16577 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
16578 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
16579 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
16580 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
16581 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
16582 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
16583 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
16584 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
16585 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
16586 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
16587 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
16588 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
16589 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
16590 | #define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
16591 | //BIFPLR0_0_PCIE_ESM_CAP_3 |
16592 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
16593 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
16594 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
16595 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
16596 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
16597 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
16598 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
16599 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
16600 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
16601 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
16602 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
16603 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
16604 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
16605 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
16606 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
16607 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
16608 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
16609 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
16610 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
16611 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
16612 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
16613 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
16614 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
16615 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
16616 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
16617 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
16618 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
16619 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
16620 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
16621 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
16622 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
16623 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
16624 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
16625 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
16626 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
16627 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
16628 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
16629 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
16630 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
16631 | #define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
16632 | //BIFPLR0_0_PCIE_ESM_CAP_4 |
16633 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
16634 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
16635 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
16636 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
16637 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
16638 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
16639 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
16640 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
16641 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
16642 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
16643 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
16644 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
16645 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
16646 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
16647 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
16648 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
16649 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
16650 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
16651 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
16652 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
16653 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
16654 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
16655 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
16656 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
16657 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
16658 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
16659 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
16660 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
16661 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
16662 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
16663 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
16664 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
16665 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
16666 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
16667 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
16668 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
16669 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
16670 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
16671 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
16672 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
16673 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
16674 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
16675 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
16676 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
16677 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
16678 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
16679 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
16680 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
16681 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
16682 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
16683 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
16684 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
16685 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
16686 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
16687 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
16688 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
16689 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
16690 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
16691 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
16692 | #define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
16693 | //BIFPLR0_0_PCIE_ESM_CAP_5 |
16694 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
16695 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
16696 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
16697 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
16698 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
16699 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
16700 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
16701 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
16702 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
16703 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
16704 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
16705 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
16706 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
16707 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
16708 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
16709 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
16710 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
16711 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
16712 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
16713 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
16714 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
16715 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
16716 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
16717 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
16718 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
16719 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
16720 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
16721 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
16722 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
16723 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
16724 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
16725 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
16726 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
16727 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
16728 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
16729 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
16730 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
16731 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
16732 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
16733 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
16734 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
16735 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
16736 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
16737 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
16738 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
16739 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
16740 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
16741 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
16742 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
16743 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
16744 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
16745 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
16746 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
16747 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
16748 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
16749 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
16750 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
16751 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
16752 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
16753 | #define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
16754 | //BIFPLR0_0_PCIE_ESM_CAP_6 |
16755 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
16756 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
16757 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
16758 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
16759 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
16760 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
16761 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
16762 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
16763 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
16764 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
16765 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
16766 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
16767 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
16768 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
16769 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
16770 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
16771 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
16772 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
16773 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
16774 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
16775 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
16776 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
16777 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
16778 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
16779 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
16780 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
16781 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
16782 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
16783 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
16784 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
16785 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
16786 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
16787 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
16788 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
16789 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
16790 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
16791 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
16792 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
16793 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
16794 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
16795 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
16796 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
16797 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
16798 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
16799 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
16800 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
16801 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
16802 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
16803 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
16804 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
16805 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
16806 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
16807 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
16808 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
16809 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
16810 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
16811 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
16812 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
16813 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
16814 | #define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
16815 | //BIFPLR0_0_PCIE_ESM_CAP_7 |
16816 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
16817 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
16818 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
16819 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
16820 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
16821 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
16822 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
16823 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
16824 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
16825 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
16826 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
16827 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
16828 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
16829 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
16830 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
16831 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
16832 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
16833 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
16834 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
16835 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
16836 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
16837 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
16838 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
16839 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
16840 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
16841 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
16842 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
16843 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
16844 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
16845 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
16846 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
16847 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
16848 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
16849 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
16850 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
16851 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
16852 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
16853 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
16854 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
16855 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
16856 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
16857 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
16858 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
16859 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
16860 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
16861 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
16862 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
16863 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
16864 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
16865 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
16866 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
16867 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
16868 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
16869 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
16870 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
16871 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
16872 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
16873 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
16874 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
16875 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
16876 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
16877 | #define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
16878 | |
16879 | |
16880 | // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
16881 | //BIFPLR1_0_VENDOR_ID |
16882 | #define BIFPLR1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
16883 | #define BIFPLR1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
16884 | //BIFPLR1_0_DEVICE_ID |
16885 | #define BIFPLR1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
16886 | #define BIFPLR1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
16887 | //BIFPLR1_0_COMMAND |
16888 | #define BIFPLR1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
16889 | #define BIFPLR1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
16890 | #define BIFPLR1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
16891 | #define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
16892 | #define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
16893 | #define BIFPLR1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
16894 | #define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
16895 | #define BIFPLR1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
16896 | #define BIFPLR1_0_COMMAND__SERR_EN__SHIFT 0x8 |
16897 | #define BIFPLR1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
16898 | #define BIFPLR1_0_COMMAND__INT_DIS__SHIFT 0xa |
16899 | #define BIFPLR1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
16900 | #define BIFPLR1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
16901 | #define BIFPLR1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
16902 | #define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
16903 | #define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
16904 | #define BIFPLR1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
16905 | #define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
16906 | #define BIFPLR1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
16907 | #define BIFPLR1_0_COMMAND__SERR_EN_MASK 0x0100L |
16908 | #define BIFPLR1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
16909 | #define BIFPLR1_0_COMMAND__INT_DIS_MASK 0x0400L |
16910 | //BIFPLR1_0_STATUS |
16911 | #define BIFPLR1_0_STATUS__INT_STATUS__SHIFT 0x3 |
16912 | #define BIFPLR1_0_STATUS__CAP_LIST__SHIFT 0x4 |
16913 | #define BIFPLR1_0_STATUS__PCI_66_EN__SHIFT 0x5 |
16914 | #define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
16915 | #define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
16916 | #define BIFPLR1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
16917 | #define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
16918 | #define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
16919 | #define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
16920 | #define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
16921 | #define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
16922 | #define BIFPLR1_0_STATUS__INT_STATUS_MASK 0x0008L |
16923 | #define BIFPLR1_0_STATUS__CAP_LIST_MASK 0x0010L |
16924 | #define BIFPLR1_0_STATUS__PCI_66_EN_MASK 0x0020L |
16925 | #define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
16926 | #define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
16927 | #define BIFPLR1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
16928 | #define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
16929 | #define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
16930 | #define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
16931 | #define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
16932 | #define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
16933 | //BIFPLR1_0_REVISION_ID |
16934 | #define BIFPLR1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
16935 | #define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
16936 | #define BIFPLR1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
16937 | #define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
16938 | //BIFPLR1_0_PROG_INTERFACE |
16939 | #define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
16940 | #define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
16941 | //BIFPLR1_0_SUB_CLASS |
16942 | #define BIFPLR1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
16943 | #define BIFPLR1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
16944 | //BIFPLR1_0_BASE_CLASS |
16945 | #define BIFPLR1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
16946 | #define BIFPLR1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
16947 | //BIFPLR1_0_CACHE_LINE |
16948 | #define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
16949 | #define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
16950 | //BIFPLR1_0_LATENCY |
16951 | #define BIFPLR1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
16952 | #define BIFPLR1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
16953 | //BIFPLR1_0_HEADER |
16954 | #define BIFPLR1_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
16955 | #define BIFPLR1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
16956 | #define BIFPLR1_0_HEADER__HEADER_TYPE_MASK 0x7FL |
16957 | #define BIFPLR1_0_HEADER__DEVICE_TYPE_MASK 0x80L |
16958 | //BIFPLR1_0_BIST |
16959 | #define BIFPLR1_0_BIST__BIST_COMP__SHIFT 0x0 |
16960 | #define BIFPLR1_0_BIST__BIST_STRT__SHIFT 0x6 |
16961 | #define BIFPLR1_0_BIST__BIST_CAP__SHIFT 0x7 |
16962 | #define BIFPLR1_0_BIST__BIST_COMP_MASK 0x0FL |
16963 | #define BIFPLR1_0_BIST__BIST_STRT_MASK 0x40L |
16964 | #define BIFPLR1_0_BIST__BIST_CAP_MASK 0x80L |
16965 | //BIFPLR1_0_SUB_BUS_NUMBER_LATENCY |
16966 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
16967 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
16968 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
16969 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
16970 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
16971 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
16972 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
16973 | #define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
16974 | //BIFPLR1_0_IO_BASE_LIMIT |
16975 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
16976 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
16977 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
16978 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
16979 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
16980 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
16981 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
16982 | #define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
16983 | //BIFPLR1_0_SECONDARY_STATUS |
16984 | #define BIFPLR1_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
16985 | #define BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
16986 | #define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
16987 | #define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
16988 | #define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
16989 | #define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
16990 | #define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
16991 | #define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
16992 | #define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
16993 | #define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
16994 | #define BIFPLR1_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
16995 | #define BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
16996 | #define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
16997 | #define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
16998 | #define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
16999 | #define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
17000 | #define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
17001 | #define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
17002 | #define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
17003 | #define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
17004 | //BIFPLR1_0_MEM_BASE_LIMIT |
17005 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
17006 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
17007 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
17008 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
17009 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
17010 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
17011 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
17012 | #define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
17013 | //BIFPLR1_0_PREF_BASE_LIMIT |
17014 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
17015 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
17016 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
17017 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
17018 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
17019 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
17020 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
17021 | #define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
17022 | //BIFPLR1_0_PREF_BASE_UPPER |
17023 | #define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
17024 | #define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
17025 | //BIFPLR1_0_PREF_LIMIT_UPPER |
17026 | #define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
17027 | #define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
17028 | //BIFPLR1_0_IO_BASE_LIMIT_HI |
17029 | #define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
17030 | #define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
17031 | #define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
17032 | #define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
17033 | //BIFPLR1_0_CAP_PTR |
17034 | #define BIFPLR1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
17035 | #define BIFPLR1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
17036 | //BIFPLR1_0_INTERRUPT_LINE |
17037 | #define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
17038 | #define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
17039 | //BIFPLR1_0_INTERRUPT_PIN |
17040 | #define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
17041 | #define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
17042 | //BIFPLR1_0_IRQ_BRIDGE_CNTL |
17043 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
17044 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
17045 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
17046 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
17047 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
17048 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
17049 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
17050 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
17051 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
17052 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
17053 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
17054 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
17055 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
17056 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
17057 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
17058 | #define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
17059 | //BIFPLR1_0_EXT_BRIDGE_CNTL |
17060 | #define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
17061 | #define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
17062 | //BIFPLR1_0_PMI_CAP_LIST |
17063 | #define BIFPLR1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
17064 | #define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17065 | #define BIFPLR1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
17066 | #define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17067 | //BIFPLR1_0_PMI_CAP |
17068 | #define BIFPLR1_0_PMI_CAP__VERSION__SHIFT 0x0 |
17069 | #define BIFPLR1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
17070 | #define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
17071 | #define BIFPLR1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
17072 | #define BIFPLR1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
17073 | #define BIFPLR1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
17074 | #define BIFPLR1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
17075 | #define BIFPLR1_0_PMI_CAP__VERSION_MASK 0x0007L |
17076 | #define BIFPLR1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
17077 | #define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
17078 | #define BIFPLR1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
17079 | #define BIFPLR1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
17080 | #define BIFPLR1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
17081 | #define BIFPLR1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
17082 | //BIFPLR1_0_PMI_STATUS_CNTL |
17083 | #define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
17084 | #define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
17085 | #define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
17086 | #define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
17087 | #define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
17088 | #define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
17089 | #define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
17090 | #define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
17091 | #define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
17092 | #define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
17093 | #define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
17094 | #define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
17095 | #define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
17096 | #define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
17097 | #define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
17098 | #define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
17099 | #define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
17100 | #define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
17101 | //BIFPLR1_0_PCIE_CAP_LIST |
17102 | #define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
17103 | #define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17104 | #define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
17105 | #define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17106 | //BIFPLR1_0_PCIE_CAP |
17107 | #define BIFPLR1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
17108 | #define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
17109 | #define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
17110 | #define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
17111 | #define BIFPLR1_0_PCIE_CAP__VERSION_MASK 0x000FL |
17112 | #define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
17113 | #define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
17114 | #define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
17115 | //BIFPLR1_0_DEVICE_CAP |
17116 | #define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
17117 | #define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
17118 | #define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
17119 | #define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
17120 | #define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
17121 | #define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
17122 | #define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
17123 | #define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
17124 | #define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
17125 | #define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
17126 | #define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
17127 | #define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
17128 | #define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
17129 | #define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
17130 | #define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
17131 | #define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
17132 | #define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
17133 | #define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
17134 | //BIFPLR1_0_DEVICE_CNTL |
17135 | #define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
17136 | #define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
17137 | #define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
17138 | #define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
17139 | #define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
17140 | #define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
17141 | #define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
17142 | #define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
17143 | #define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
17144 | #define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
17145 | #define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
17146 | #define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
17147 | #define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
17148 | #define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
17149 | #define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
17150 | #define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
17151 | #define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
17152 | #define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
17153 | #define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
17154 | #define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
17155 | #define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
17156 | #define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
17157 | #define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
17158 | #define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
17159 | //BIFPLR1_0_DEVICE_STATUS |
17160 | #define BIFPLR1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
17161 | #define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
17162 | #define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
17163 | #define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
17164 | #define BIFPLR1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
17165 | #define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
17166 | #define BIFPLR1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
17167 | #define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
17168 | #define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
17169 | #define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
17170 | #define BIFPLR1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
17171 | #define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
17172 | //BIFPLR1_0_LINK_CAP |
17173 | #define BIFPLR1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
17174 | #define BIFPLR1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
17175 | #define BIFPLR1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
17176 | #define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
17177 | #define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
17178 | #define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
17179 | #define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
17180 | #define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
17181 | #define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
17182 | #define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
17183 | #define BIFPLR1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
17184 | #define BIFPLR1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
17185 | #define BIFPLR1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
17186 | #define BIFPLR1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
17187 | #define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
17188 | #define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
17189 | #define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
17190 | #define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
17191 | #define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
17192 | #define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
17193 | #define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
17194 | #define BIFPLR1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
17195 | //BIFPLR1_0_LINK_CNTL |
17196 | #define BIFPLR1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
17197 | #define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
17198 | #define BIFPLR1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
17199 | #define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
17200 | #define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
17201 | #define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
17202 | #define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
17203 | #define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
17204 | #define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
17205 | #define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
17206 | #define BIFPLR1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
17207 | #define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
17208 | #define BIFPLR1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
17209 | #define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
17210 | #define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
17211 | #define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
17212 | #define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
17213 | #define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
17214 | #define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
17215 | #define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
17216 | //BIFPLR1_0_LINK_STATUS |
17217 | #define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
17218 | #define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
17219 | #define BIFPLR1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
17220 | #define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
17221 | #define BIFPLR1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
17222 | #define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
17223 | #define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
17224 | #define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
17225 | #define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
17226 | #define BIFPLR1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
17227 | #define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
17228 | #define BIFPLR1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
17229 | #define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
17230 | #define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
17231 | //BIFPLR1_0_SLOT_CAP |
17232 | #define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
17233 | #define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
17234 | #define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
17235 | #define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
17236 | #define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
17237 | #define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
17238 | #define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
17239 | #define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
17240 | #define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
17241 | #define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
17242 | #define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
17243 | #define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
17244 | #define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
17245 | #define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
17246 | #define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
17247 | #define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
17248 | #define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
17249 | #define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
17250 | #define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
17251 | #define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
17252 | #define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
17253 | #define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
17254 | #define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
17255 | #define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
17256 | //BIFPLR1_0_SLOT_CNTL |
17257 | #define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
17258 | #define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
17259 | #define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
17260 | #define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
17261 | #define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
17262 | #define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
17263 | #define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
17264 | #define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
17265 | #define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
17266 | #define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
17267 | #define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
17268 | #define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
17269 | #define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
17270 | #define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
17271 | #define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
17272 | #define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
17273 | #define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
17274 | #define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
17275 | #define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
17276 | #define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
17277 | #define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
17278 | #define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
17279 | #define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
17280 | #define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
17281 | //BIFPLR1_0_SLOT_STATUS |
17282 | #define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
17283 | #define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
17284 | #define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
17285 | #define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
17286 | #define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
17287 | #define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
17288 | #define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
17289 | #define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
17290 | #define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
17291 | #define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
17292 | #define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
17293 | #define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
17294 | #define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
17295 | #define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
17296 | #define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
17297 | #define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
17298 | #define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
17299 | #define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
17300 | //BIFPLR1_0_ROOT_CNTL |
17301 | #define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
17302 | #define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
17303 | #define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
17304 | #define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
17305 | #define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
17306 | #define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
17307 | #define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
17308 | #define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
17309 | #define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
17310 | #define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
17311 | //BIFPLR1_0_ROOT_CAP |
17312 | #define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
17313 | #define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
17314 | //BIFPLR1_0_ROOT_STATUS |
17315 | #define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
17316 | #define BIFPLR1_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
17317 | #define BIFPLR1_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
17318 | #define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
17319 | #define BIFPLR1_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
17320 | #define BIFPLR1_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
17321 | //BIFPLR1_0_DEVICE_CAP2 |
17322 | #define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
17323 | #define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
17324 | #define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
17325 | #define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
17326 | #define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
17327 | #define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
17328 | #define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
17329 | #define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
17330 | #define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
17331 | #define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
17332 | #define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
17333 | #define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
17334 | #define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
17335 | #define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
17336 | #define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
17337 | #define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
17338 | #define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
17339 | #define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
17340 | #define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
17341 | #define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
17342 | #define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
17343 | #define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
17344 | #define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
17345 | #define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
17346 | #define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
17347 | #define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
17348 | #define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
17349 | #define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
17350 | //BIFPLR1_0_DEVICE_CNTL2 |
17351 | #define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
17352 | #define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
17353 | #define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
17354 | #define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
17355 | #define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
17356 | #define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
17357 | #define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
17358 | #define BIFPLR1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
17359 | #define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
17360 | #define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
17361 | #define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
17362 | #define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
17363 | #define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
17364 | #define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
17365 | #define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
17366 | #define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
17367 | #define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
17368 | #define BIFPLR1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
17369 | #define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
17370 | #define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
17371 | //BIFPLR1_0_DEVICE_STATUS2 |
17372 | #define BIFPLR1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
17373 | #define BIFPLR1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
17374 | //BIFPLR1_0_LINK_CAP2 |
17375 | #define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
17376 | #define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
17377 | #define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
17378 | #define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
17379 | #define BIFPLR1_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
17380 | #define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
17381 | #define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
17382 | #define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
17383 | #define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
17384 | #define BIFPLR1_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
17385 | //BIFPLR1_0_LINK_CNTL2 |
17386 | #define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
17387 | #define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
17388 | #define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
17389 | #define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
17390 | #define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
17391 | #define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
17392 | #define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
17393 | #define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
17394 | #define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
17395 | #define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
17396 | #define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
17397 | #define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
17398 | #define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
17399 | #define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
17400 | #define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
17401 | #define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
17402 | //BIFPLR1_0_LINK_STATUS2 |
17403 | #define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
17404 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
17405 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
17406 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
17407 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
17408 | #define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
17409 | #define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
17410 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
17411 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
17412 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
17413 | #define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
17414 | #define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
17415 | //BIFPLR1_0_SLOT_CAP2 |
17416 | #define BIFPLR1_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
17417 | #define BIFPLR1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
17418 | //BIFPLR1_0_SLOT_CNTL2 |
17419 | #define BIFPLR1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
17420 | #define BIFPLR1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
17421 | //BIFPLR1_0_SLOT_STATUS2 |
17422 | #define BIFPLR1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
17423 | #define BIFPLR1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
17424 | //BIFPLR1_0_MSI_CAP_LIST |
17425 | #define BIFPLR1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
17426 | #define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17427 | #define BIFPLR1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
17428 | #define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17429 | //BIFPLR1_0_MSI_MSG_CNTL |
17430 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
17431 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
17432 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
17433 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
17434 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
17435 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
17436 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
17437 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
17438 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
17439 | #define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
17440 | //BIFPLR1_0_MSI_MSG_ADDR_LO |
17441 | #define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
17442 | #define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
17443 | //BIFPLR1_0_MSI_MSG_ADDR_HI |
17444 | #define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
17445 | #define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
17446 | //BIFPLR1_0_MSI_MSG_DATA |
17447 | #define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
17448 | #define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
17449 | //BIFPLR1_0_MSI_MSG_DATA_64 |
17450 | #define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
17451 | #define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
17452 | //BIFPLR1_0_SSID_CAP_LIST |
17453 | #define BIFPLR1_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
17454 | #define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17455 | #define BIFPLR1_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
17456 | #define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17457 | //BIFPLR1_0_SSID_CAP |
17458 | #define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
17459 | #define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
17460 | #define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
17461 | #define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
17462 | //BIFPLR1_0_MSI_MAP_CAP_LIST |
17463 | #define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
17464 | #define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17465 | #define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
17466 | #define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17467 | //BIFPLR1_0_MSI_MAP_CAP |
17468 | #define BIFPLR1_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
17469 | #define BIFPLR1_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
17470 | #define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
17471 | #define BIFPLR1_0_MSI_MAP_CAP__EN_MASK 0x0001L |
17472 | #define BIFPLR1_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
17473 | #define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
17474 | //BIFPLR1_0_MSI_MAP_ADDR_LO |
17475 | #define BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
17476 | #define BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
17477 | //BIFPLR1_0_MSI_MAP_ADDR_HI |
17478 | #define BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
17479 | #define BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
17480 | //BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
17481 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17482 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17483 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17484 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17485 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17486 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17487 | //BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR |
17488 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
17489 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
17490 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
17491 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
17492 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
17493 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
17494 | //BIFPLR1_0_PCIE_VENDOR_SPECIFIC1 |
17495 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
17496 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
17497 | //BIFPLR1_0_PCIE_VENDOR_SPECIFIC2 |
17498 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
17499 | #define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
17500 | //BIFPLR1_0_PCIE_VC_ENH_CAP_LIST |
17501 | #define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17502 | #define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17503 | #define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17504 | #define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17505 | #define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17506 | #define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17507 | //BIFPLR1_0_PCIE_PORT_VC_CAP_REG1 |
17508 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
17509 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
17510 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
17511 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
17512 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
17513 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
17514 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
17515 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
17516 | //BIFPLR1_0_PCIE_PORT_VC_CAP_REG2 |
17517 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
17518 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
17519 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
17520 | #define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
17521 | //BIFPLR1_0_PCIE_PORT_VC_CNTL |
17522 | #define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
17523 | #define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
17524 | #define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
17525 | #define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
17526 | //BIFPLR1_0_PCIE_PORT_VC_STATUS |
17527 | #define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
17528 | #define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
17529 | //BIFPLR1_0_PCIE_VC0_RESOURCE_CAP |
17530 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
17531 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
17532 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
17533 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
17534 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
17535 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
17536 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
17537 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
17538 | //BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL |
17539 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
17540 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
17541 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
17542 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
17543 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
17544 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
17545 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
17546 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
17547 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
17548 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
17549 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
17550 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
17551 | //BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS |
17552 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
17553 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
17554 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
17555 | #define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
17556 | //BIFPLR1_0_PCIE_VC1_RESOURCE_CAP |
17557 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
17558 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
17559 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
17560 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
17561 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
17562 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
17563 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
17564 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
17565 | //BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL |
17566 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
17567 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
17568 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
17569 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
17570 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
17571 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
17572 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
17573 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
17574 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
17575 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
17576 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
17577 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
17578 | //BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS |
17579 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
17580 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
17581 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
17582 | #define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
17583 | //BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
17584 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17585 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17586 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17587 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17588 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17589 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17590 | //BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 |
17591 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
17592 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
17593 | //BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 |
17594 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
17595 | #define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
17596 | //BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
17597 | #define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17598 | #define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17599 | #define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17600 | #define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17601 | #define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17602 | #define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17603 | //BIFPLR1_0_PCIE_UNCORR_ERR_STATUS |
17604 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
17605 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
17606 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
17607 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
17608 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
17609 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
17610 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
17611 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
17612 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
17613 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
17614 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
17615 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
17616 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
17617 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
17618 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
17619 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
17620 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
17621 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
17622 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
17623 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
17624 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
17625 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
17626 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
17627 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
17628 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
17629 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
17630 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
17631 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
17632 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
17633 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
17634 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
17635 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
17636 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
17637 | #define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
17638 | //BIFPLR1_0_PCIE_UNCORR_ERR_MASK |
17639 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
17640 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
17641 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
17642 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
17643 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
17644 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
17645 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
17646 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
17647 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
17648 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
17649 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
17650 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
17651 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
17652 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
17653 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
17654 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
17655 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
17656 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
17657 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
17658 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
17659 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
17660 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
17661 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
17662 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
17663 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
17664 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
17665 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
17666 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
17667 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
17668 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
17669 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
17670 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
17671 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
17672 | #define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
17673 | //BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY |
17674 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
17675 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
17676 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
17677 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
17678 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
17679 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
17680 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
17681 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
17682 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
17683 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
17684 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
17685 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
17686 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
17687 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
17688 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
17689 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
17690 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
17691 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
17692 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
17693 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
17694 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
17695 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
17696 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
17697 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
17698 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
17699 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
17700 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
17701 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
17702 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
17703 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
17704 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
17705 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
17706 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
17707 | #define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
17708 | //BIFPLR1_0_PCIE_CORR_ERR_STATUS |
17709 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
17710 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
17711 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
17712 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
17713 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
17714 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
17715 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
17716 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
17717 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
17718 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
17719 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
17720 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
17721 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
17722 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
17723 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
17724 | #define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
17725 | //BIFPLR1_0_PCIE_CORR_ERR_MASK |
17726 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
17727 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
17728 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
17729 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
17730 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
17731 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
17732 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
17733 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
17734 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
17735 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
17736 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
17737 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
17738 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
17739 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
17740 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
17741 | #define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
17742 | //BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL |
17743 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
17744 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
17745 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
17746 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
17747 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
17748 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
17749 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
17750 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
17751 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
17752 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
17753 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
17754 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
17755 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
17756 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
17757 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
17758 | #define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
17759 | //BIFPLR1_0_PCIE_HDR_LOG0 |
17760 | #define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
17761 | #define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
17762 | //BIFPLR1_0_PCIE_HDR_LOG1 |
17763 | #define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
17764 | #define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
17765 | //BIFPLR1_0_PCIE_HDR_LOG2 |
17766 | #define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
17767 | #define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
17768 | //BIFPLR1_0_PCIE_HDR_LOG3 |
17769 | #define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
17770 | #define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
17771 | //BIFPLR1_0_PCIE_ROOT_ERR_CMD |
17772 | #define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
17773 | #define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
17774 | #define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
17775 | #define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
17776 | #define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
17777 | #define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
17778 | //BIFPLR1_0_PCIE_ROOT_ERR_STATUS |
17779 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
17780 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
17781 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
17782 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
17783 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
17784 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
17785 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
17786 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
17787 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
17788 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
17789 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
17790 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
17791 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
17792 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
17793 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
17794 | #define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
17795 | //BIFPLR1_0_PCIE_ERR_SRC_ID |
17796 | #define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
17797 | #define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
17798 | #define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
17799 | #define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
17800 | //BIFPLR1_0_PCIE_TLP_PREFIX_LOG0 |
17801 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
17802 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
17803 | //BIFPLR1_0_PCIE_TLP_PREFIX_LOG1 |
17804 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
17805 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
17806 | //BIFPLR1_0_PCIE_TLP_PREFIX_LOG2 |
17807 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
17808 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
17809 | //BIFPLR1_0_PCIE_TLP_PREFIX_LOG3 |
17810 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
17811 | #define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
17812 | //BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST |
17813 | #define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17814 | #define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17815 | #define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17816 | #define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17817 | #define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17818 | #define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17819 | //BIFPLR1_0_PCIE_LINK_CNTL3 |
17820 | #define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
17821 | #define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
17822 | #define BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
17823 | #define BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
17824 | #define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
17825 | #define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
17826 | #define BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
17827 | #define BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
17828 | //BIFPLR1_0_PCIE_LANE_ERROR_STATUS |
17829 | #define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
17830 | #define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
17831 | #define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
17832 | #define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
17833 | //BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL |
17834 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17835 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17836 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17837 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17838 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17839 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17840 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17841 | #define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17842 | //BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL |
17843 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17844 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17845 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17846 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17847 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17848 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17849 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17850 | #define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17851 | //BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL |
17852 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17853 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17854 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17855 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17856 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17857 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17858 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17859 | #define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17860 | //BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL |
17861 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17862 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17863 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17864 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17865 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17866 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17867 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17868 | #define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17869 | //BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL |
17870 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17871 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17872 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17873 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17874 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17875 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17876 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17877 | #define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17878 | //BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL |
17879 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17880 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17881 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17882 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17883 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17884 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17885 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17886 | #define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17887 | //BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL |
17888 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17889 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17890 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17891 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17892 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17893 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17894 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17895 | #define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17896 | //BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL |
17897 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17898 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17899 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17900 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17901 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17902 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17903 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17904 | #define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17905 | //BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL |
17906 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17907 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17908 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17909 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17910 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17911 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17912 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17913 | #define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17914 | //BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL |
17915 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17916 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17917 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17918 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17919 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17920 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17921 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17922 | #define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17923 | //BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL |
17924 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17925 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17926 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17927 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17928 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17929 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17930 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17931 | #define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17932 | //BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL |
17933 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17934 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17935 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17936 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17937 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17938 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17939 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17940 | #define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17941 | //BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL |
17942 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17943 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17944 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17945 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17946 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17947 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17948 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17949 | #define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17950 | //BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL |
17951 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17952 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17953 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17954 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17955 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17956 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17957 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17958 | #define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17959 | //BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL |
17960 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17961 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17962 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17963 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17964 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17965 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17966 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17967 | #define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17968 | //BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL |
17969 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
17970 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
17971 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
17972 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
17973 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
17974 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
17975 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
17976 | #define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
17977 | //BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST |
17978 | #define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17979 | #define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17980 | #define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17981 | #define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17982 | #define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17983 | #define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17984 | //BIFPLR1_0_PCIE_ACS_CAP |
17985 | #define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
17986 | #define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
17987 | #define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
17988 | #define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
17989 | #define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
17990 | #define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
17991 | #define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
17992 | #define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
17993 | #define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
17994 | #define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
17995 | #define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
17996 | #define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
17997 | #define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
17998 | #define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
17999 | #define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
18000 | #define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
18001 | //BIFPLR1_0_PCIE_ACS_CNTL |
18002 | #define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
18003 | #define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
18004 | #define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
18005 | #define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
18006 | #define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
18007 | #define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
18008 | #define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
18009 | #define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
18010 | #define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
18011 | #define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
18012 | #define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
18013 | #define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
18014 | #define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
18015 | #define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
18016 | //BIFPLR1_0_PCIE_MC_ENH_CAP_LIST |
18017 | #define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18018 | #define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18019 | #define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18020 | #define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18021 | #define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18022 | #define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18023 | //BIFPLR1_0_PCIE_MC_CAP |
18024 | #define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
18025 | #define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
18026 | #define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
18027 | #define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
18028 | //BIFPLR1_0_PCIE_MC_CNTL |
18029 | #define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
18030 | #define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
18031 | #define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
18032 | #define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
18033 | //BIFPLR1_0_PCIE_MC_ADDR0 |
18034 | #define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
18035 | #define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
18036 | #define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
18037 | #define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
18038 | //BIFPLR1_0_PCIE_MC_ADDR1 |
18039 | #define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
18040 | #define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
18041 | //BIFPLR1_0_PCIE_MC_RCV0 |
18042 | #define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
18043 | #define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
18044 | //BIFPLR1_0_PCIE_MC_RCV1 |
18045 | #define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
18046 | #define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
18047 | //BIFPLR1_0_PCIE_MC_BLOCK_ALL0 |
18048 | #define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
18049 | #define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
18050 | //BIFPLR1_0_PCIE_MC_BLOCK_ALL1 |
18051 | #define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
18052 | #define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
18053 | //BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
18054 | #define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
18055 | #define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
18056 | //BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
18057 | #define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
18058 | #define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
18059 | //BIFPLR1_0_PCIE_MC_OVERLAY_BAR0 |
18060 | #define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
18061 | #define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
18062 | #define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
18063 | #define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
18064 | //BIFPLR1_0_PCIE_MC_OVERLAY_BAR1 |
18065 | #define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
18066 | #define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
18067 | //BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST |
18068 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
18069 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
18070 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18071 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18072 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18073 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18074 | //BIFPLR1_0_PCIE_L1_PM_SUB_CAP |
18075 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
18076 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
18077 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
18078 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
18079 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
18080 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
18081 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
18082 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
18083 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
18084 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
18085 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
18086 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
18087 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
18088 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
18089 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
18090 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
18091 | //BIFPLR1_0_PCIE_L1_PM_SUB_CNTL |
18092 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
18093 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
18094 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
18095 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
18096 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
18097 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
18098 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
18099 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
18100 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
18101 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
18102 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
18103 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
18104 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
18105 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
18106 | //BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 |
18107 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
18108 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
18109 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
18110 | #define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
18111 | //BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST |
18112 | #define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18113 | #define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18114 | #define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18115 | #define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18116 | #define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18117 | #define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18118 | //BIFPLR1_0_PCIE_DPC_CAP_LIST |
18119 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
18120 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
18121 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
18122 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
18123 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
18124 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
18125 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
18126 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
18127 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
18128 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
18129 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
18130 | #define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
18131 | //BIFPLR1_0_PCIE_DPC_CNTL |
18132 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
18133 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
18134 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
18135 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
18136 | #define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
18137 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
18138 | #define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
18139 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
18140 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
18141 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
18142 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
18143 | #define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
18144 | #define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
18145 | #define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
18146 | //BIFPLR1_0_PCIE_DPC_STATUS |
18147 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
18148 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
18149 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
18150 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
18151 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
18152 | #define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
18153 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
18154 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
18155 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
18156 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
18157 | #define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
18158 | #define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
18159 | //BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID |
18160 | #define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
18161 | #define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
18162 | //BIFPLR1_0_PCIE_RP_PIO_STATUS |
18163 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
18164 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
18165 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
18166 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
18167 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
18168 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
18169 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
18170 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
18171 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
18172 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
18173 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
18174 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
18175 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
18176 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
18177 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
18178 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
18179 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
18180 | #define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
18181 | //BIFPLR1_0_PCIE_RP_PIO_MASK |
18182 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
18183 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
18184 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
18185 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
18186 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
18187 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
18188 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
18189 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
18190 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
18191 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
18192 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
18193 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
18194 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
18195 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
18196 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
18197 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
18198 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
18199 | #define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
18200 | //BIFPLR1_0_PCIE_RP_PIO_SEVERITY |
18201 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
18202 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
18203 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
18204 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
18205 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
18206 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
18207 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
18208 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
18209 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
18210 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
18211 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
18212 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
18213 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
18214 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
18215 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
18216 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
18217 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
18218 | #define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
18219 | //BIFPLR1_0_PCIE_RP_PIO_SYSERROR |
18220 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
18221 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
18222 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
18223 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
18224 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
18225 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
18226 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
18227 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
18228 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
18229 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
18230 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
18231 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
18232 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
18233 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
18234 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
18235 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
18236 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
18237 | #define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
18238 | //BIFPLR1_0_PCIE_RP_PIO_EXCEPTION |
18239 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
18240 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
18241 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
18242 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
18243 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
18244 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
18245 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
18246 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
18247 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
18248 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
18249 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
18250 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
18251 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
18252 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
18253 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
18254 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
18255 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
18256 | #define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
18257 | //BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 |
18258 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
18259 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
18260 | //BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 |
18261 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
18262 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
18263 | //BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 |
18264 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
18265 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
18266 | //BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 |
18267 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
18268 | #define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
18269 | //BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG |
18270 | #define BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
18271 | #define BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
18272 | //BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 |
18273 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
18274 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
18275 | //BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 |
18276 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
18277 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
18278 | //BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 |
18279 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
18280 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
18281 | //BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 |
18282 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
18283 | #define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
18284 | //BIFPLR1_0_PCIE_ESM_CAP_LIST |
18285 | #define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
18286 | #define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
18287 | #define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18288 | #define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18289 | #define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18290 | #define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18291 | //BIFPLR1_0_PCIE_ESM_HEADER_1 |
18292 | #define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
18293 | #define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
18294 | #define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
18295 | #define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
18296 | #define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
18297 | #define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
18298 | //BIFPLR1_0_PCIE_ESM_HEADER_2 |
18299 | #define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
18300 | #define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
18301 | //BIFPLR1_0_PCIE_ESM_STATUS |
18302 | #define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
18303 | #define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
18304 | #define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
18305 | #define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
18306 | //BIFPLR1_0_PCIE_ESM_CTRL |
18307 | #define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
18308 | #define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
18309 | #define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
18310 | #define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
18311 | #define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
18312 | #define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
18313 | //BIFPLR1_0_PCIE_ESM_CAP_1 |
18314 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
18315 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
18316 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
18317 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
18318 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
18319 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
18320 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
18321 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
18322 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
18323 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
18324 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
18325 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
18326 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
18327 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
18328 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
18329 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
18330 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
18331 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
18332 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
18333 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
18334 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
18335 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
18336 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
18337 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
18338 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
18339 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
18340 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
18341 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
18342 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
18343 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
18344 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
18345 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
18346 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
18347 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
18348 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
18349 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
18350 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
18351 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
18352 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
18353 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
18354 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
18355 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
18356 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
18357 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
18358 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
18359 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
18360 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
18361 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
18362 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
18363 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
18364 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
18365 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
18366 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
18367 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
18368 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
18369 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
18370 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
18371 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
18372 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
18373 | #define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
18374 | //BIFPLR1_0_PCIE_ESM_CAP_2 |
18375 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
18376 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
18377 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
18378 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
18379 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
18380 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
18381 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
18382 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
18383 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
18384 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
18385 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
18386 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
18387 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
18388 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
18389 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
18390 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
18391 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
18392 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
18393 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
18394 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
18395 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
18396 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
18397 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
18398 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
18399 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
18400 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
18401 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
18402 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
18403 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
18404 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
18405 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
18406 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
18407 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
18408 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
18409 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
18410 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
18411 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
18412 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
18413 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
18414 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
18415 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
18416 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
18417 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
18418 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
18419 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
18420 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
18421 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
18422 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
18423 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
18424 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
18425 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
18426 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
18427 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
18428 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
18429 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
18430 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
18431 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
18432 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
18433 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
18434 | #define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
18435 | //BIFPLR1_0_PCIE_ESM_CAP_3 |
18436 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
18437 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
18438 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
18439 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
18440 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
18441 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
18442 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
18443 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
18444 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
18445 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
18446 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
18447 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
18448 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
18449 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
18450 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
18451 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
18452 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
18453 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
18454 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
18455 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
18456 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
18457 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
18458 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
18459 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
18460 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
18461 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
18462 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
18463 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
18464 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
18465 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
18466 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
18467 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
18468 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
18469 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
18470 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
18471 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
18472 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
18473 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
18474 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
18475 | #define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
18476 | //BIFPLR1_0_PCIE_ESM_CAP_4 |
18477 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
18478 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
18479 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
18480 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
18481 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
18482 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
18483 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
18484 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
18485 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
18486 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
18487 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
18488 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
18489 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
18490 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
18491 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
18492 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
18493 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
18494 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
18495 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
18496 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
18497 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
18498 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
18499 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
18500 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
18501 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
18502 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
18503 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
18504 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
18505 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
18506 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
18507 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
18508 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
18509 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
18510 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
18511 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
18512 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
18513 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
18514 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
18515 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
18516 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
18517 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
18518 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
18519 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
18520 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
18521 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
18522 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
18523 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
18524 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
18525 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
18526 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
18527 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
18528 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
18529 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
18530 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
18531 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
18532 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
18533 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
18534 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
18535 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
18536 | #define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
18537 | //BIFPLR1_0_PCIE_ESM_CAP_5 |
18538 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
18539 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
18540 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
18541 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
18542 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
18543 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
18544 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
18545 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
18546 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
18547 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
18548 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
18549 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
18550 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
18551 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
18552 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
18553 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
18554 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
18555 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
18556 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
18557 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
18558 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
18559 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
18560 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
18561 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
18562 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
18563 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
18564 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
18565 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
18566 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
18567 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
18568 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
18569 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
18570 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
18571 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
18572 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
18573 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
18574 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
18575 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
18576 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
18577 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
18578 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
18579 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
18580 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
18581 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
18582 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
18583 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
18584 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
18585 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
18586 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
18587 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
18588 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
18589 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
18590 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
18591 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
18592 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
18593 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
18594 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
18595 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
18596 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
18597 | #define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
18598 | //BIFPLR1_0_PCIE_ESM_CAP_6 |
18599 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
18600 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
18601 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
18602 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
18603 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
18604 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
18605 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
18606 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
18607 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
18608 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
18609 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
18610 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
18611 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
18612 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
18613 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
18614 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
18615 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
18616 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
18617 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
18618 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
18619 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
18620 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
18621 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
18622 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
18623 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
18624 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
18625 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
18626 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
18627 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
18628 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
18629 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
18630 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
18631 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
18632 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
18633 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
18634 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
18635 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
18636 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
18637 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
18638 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
18639 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
18640 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
18641 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
18642 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
18643 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
18644 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
18645 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
18646 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
18647 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
18648 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
18649 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
18650 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
18651 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
18652 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
18653 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
18654 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
18655 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
18656 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
18657 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
18658 | #define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
18659 | //BIFPLR1_0_PCIE_ESM_CAP_7 |
18660 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
18661 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
18662 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
18663 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
18664 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
18665 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
18666 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
18667 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
18668 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
18669 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
18670 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
18671 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
18672 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
18673 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
18674 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
18675 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
18676 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
18677 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
18678 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
18679 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
18680 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
18681 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
18682 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
18683 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
18684 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
18685 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
18686 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
18687 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
18688 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
18689 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
18690 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
18691 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
18692 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
18693 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
18694 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
18695 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
18696 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
18697 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
18698 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
18699 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
18700 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
18701 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
18702 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
18703 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
18704 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
18705 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
18706 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
18707 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
18708 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
18709 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
18710 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
18711 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
18712 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
18713 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
18714 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
18715 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
18716 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
18717 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
18718 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
18719 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
18720 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
18721 | #define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
18722 | |
18723 | |
18724 | // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
18725 | //BIFPLR2_0_VENDOR_ID |
18726 | #define BIFPLR2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
18727 | #define BIFPLR2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
18728 | //BIFPLR2_0_DEVICE_ID |
18729 | #define BIFPLR2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
18730 | #define BIFPLR2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
18731 | //BIFPLR2_0_COMMAND |
18732 | #define BIFPLR2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
18733 | #define BIFPLR2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
18734 | #define BIFPLR2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
18735 | #define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
18736 | #define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
18737 | #define BIFPLR2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
18738 | #define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
18739 | #define BIFPLR2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
18740 | #define BIFPLR2_0_COMMAND__SERR_EN__SHIFT 0x8 |
18741 | #define BIFPLR2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
18742 | #define BIFPLR2_0_COMMAND__INT_DIS__SHIFT 0xa |
18743 | #define BIFPLR2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
18744 | #define BIFPLR2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
18745 | #define BIFPLR2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
18746 | #define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
18747 | #define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
18748 | #define BIFPLR2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
18749 | #define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
18750 | #define BIFPLR2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
18751 | #define BIFPLR2_0_COMMAND__SERR_EN_MASK 0x0100L |
18752 | #define BIFPLR2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
18753 | #define BIFPLR2_0_COMMAND__INT_DIS_MASK 0x0400L |
18754 | //BIFPLR2_0_STATUS |
18755 | #define BIFPLR2_0_STATUS__INT_STATUS__SHIFT 0x3 |
18756 | #define BIFPLR2_0_STATUS__CAP_LIST__SHIFT 0x4 |
18757 | #define BIFPLR2_0_STATUS__PCI_66_EN__SHIFT 0x5 |
18758 | #define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
18759 | #define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
18760 | #define BIFPLR2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
18761 | #define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
18762 | #define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
18763 | #define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
18764 | #define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
18765 | #define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
18766 | #define BIFPLR2_0_STATUS__INT_STATUS_MASK 0x0008L |
18767 | #define BIFPLR2_0_STATUS__CAP_LIST_MASK 0x0010L |
18768 | #define BIFPLR2_0_STATUS__PCI_66_EN_MASK 0x0020L |
18769 | #define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
18770 | #define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
18771 | #define BIFPLR2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
18772 | #define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
18773 | #define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
18774 | #define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
18775 | #define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
18776 | #define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
18777 | //BIFPLR2_0_REVISION_ID |
18778 | #define BIFPLR2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
18779 | #define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
18780 | #define BIFPLR2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
18781 | #define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
18782 | //BIFPLR2_0_PROG_INTERFACE |
18783 | #define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
18784 | #define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
18785 | //BIFPLR2_0_SUB_CLASS |
18786 | #define BIFPLR2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
18787 | #define BIFPLR2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
18788 | //BIFPLR2_0_BASE_CLASS |
18789 | #define BIFPLR2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
18790 | #define BIFPLR2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
18791 | //BIFPLR2_0_CACHE_LINE |
18792 | #define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
18793 | #define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
18794 | //BIFPLR2_0_LATENCY |
18795 | #define BIFPLR2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
18796 | #define BIFPLR2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
18797 | //BIFPLR2_0_HEADER |
18798 | #define BIFPLR2_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
18799 | #define BIFPLR2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
18800 | #define BIFPLR2_0_HEADER__HEADER_TYPE_MASK 0x7FL |
18801 | #define BIFPLR2_0_HEADER__DEVICE_TYPE_MASK 0x80L |
18802 | //BIFPLR2_0_BIST |
18803 | #define BIFPLR2_0_BIST__BIST_COMP__SHIFT 0x0 |
18804 | #define BIFPLR2_0_BIST__BIST_STRT__SHIFT 0x6 |
18805 | #define BIFPLR2_0_BIST__BIST_CAP__SHIFT 0x7 |
18806 | #define BIFPLR2_0_BIST__BIST_COMP_MASK 0x0FL |
18807 | #define BIFPLR2_0_BIST__BIST_STRT_MASK 0x40L |
18808 | #define BIFPLR2_0_BIST__BIST_CAP_MASK 0x80L |
18809 | //BIFPLR2_0_SUB_BUS_NUMBER_LATENCY |
18810 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
18811 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
18812 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
18813 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
18814 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
18815 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
18816 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
18817 | #define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
18818 | //BIFPLR2_0_IO_BASE_LIMIT |
18819 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
18820 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
18821 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
18822 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
18823 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
18824 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
18825 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
18826 | #define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
18827 | //BIFPLR2_0_SECONDARY_STATUS |
18828 | #define BIFPLR2_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
18829 | #define BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
18830 | #define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
18831 | #define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
18832 | #define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
18833 | #define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
18834 | #define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
18835 | #define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
18836 | #define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
18837 | #define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
18838 | #define BIFPLR2_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
18839 | #define BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
18840 | #define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
18841 | #define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
18842 | #define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
18843 | #define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
18844 | #define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
18845 | #define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
18846 | #define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
18847 | #define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
18848 | //BIFPLR2_0_MEM_BASE_LIMIT |
18849 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
18850 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
18851 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
18852 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
18853 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
18854 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
18855 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
18856 | #define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
18857 | //BIFPLR2_0_PREF_BASE_LIMIT |
18858 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
18859 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
18860 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
18861 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
18862 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
18863 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
18864 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
18865 | #define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
18866 | //BIFPLR2_0_PREF_BASE_UPPER |
18867 | #define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
18868 | #define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
18869 | //BIFPLR2_0_PREF_LIMIT_UPPER |
18870 | #define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
18871 | #define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
18872 | //BIFPLR2_0_IO_BASE_LIMIT_HI |
18873 | #define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
18874 | #define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
18875 | #define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
18876 | #define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
18877 | //BIFPLR2_0_CAP_PTR |
18878 | #define BIFPLR2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
18879 | #define BIFPLR2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
18880 | //BIFPLR2_0_INTERRUPT_LINE |
18881 | #define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
18882 | #define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
18883 | //BIFPLR2_0_INTERRUPT_PIN |
18884 | #define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
18885 | #define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
18886 | //BIFPLR2_0_IRQ_BRIDGE_CNTL |
18887 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
18888 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
18889 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
18890 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
18891 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
18892 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
18893 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
18894 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
18895 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
18896 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
18897 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
18898 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
18899 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
18900 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
18901 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
18902 | #define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
18903 | //BIFPLR2_0_EXT_BRIDGE_CNTL |
18904 | #define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
18905 | #define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
18906 | //BIFPLR2_0_PMI_CAP_LIST |
18907 | #define BIFPLR2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
18908 | #define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
18909 | #define BIFPLR2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
18910 | #define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
18911 | //BIFPLR2_0_PMI_CAP |
18912 | #define BIFPLR2_0_PMI_CAP__VERSION__SHIFT 0x0 |
18913 | #define BIFPLR2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
18914 | #define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
18915 | #define BIFPLR2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
18916 | #define BIFPLR2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
18917 | #define BIFPLR2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
18918 | #define BIFPLR2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
18919 | #define BIFPLR2_0_PMI_CAP__VERSION_MASK 0x0007L |
18920 | #define BIFPLR2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
18921 | #define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
18922 | #define BIFPLR2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
18923 | #define BIFPLR2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
18924 | #define BIFPLR2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
18925 | #define BIFPLR2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
18926 | //BIFPLR2_0_PMI_STATUS_CNTL |
18927 | #define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
18928 | #define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
18929 | #define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
18930 | #define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
18931 | #define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
18932 | #define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
18933 | #define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
18934 | #define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
18935 | #define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
18936 | #define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
18937 | #define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
18938 | #define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
18939 | #define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
18940 | #define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
18941 | #define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
18942 | #define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
18943 | #define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
18944 | #define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
18945 | //BIFPLR2_0_PCIE_CAP_LIST |
18946 | #define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
18947 | #define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
18948 | #define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
18949 | #define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
18950 | //BIFPLR2_0_PCIE_CAP |
18951 | #define BIFPLR2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
18952 | #define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
18953 | #define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
18954 | #define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
18955 | #define BIFPLR2_0_PCIE_CAP__VERSION_MASK 0x000FL |
18956 | #define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
18957 | #define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
18958 | #define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
18959 | //BIFPLR2_0_DEVICE_CAP |
18960 | #define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
18961 | #define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
18962 | #define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
18963 | #define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
18964 | #define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
18965 | #define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
18966 | #define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
18967 | #define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
18968 | #define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
18969 | #define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
18970 | #define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
18971 | #define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
18972 | #define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
18973 | #define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
18974 | #define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
18975 | #define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
18976 | #define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
18977 | #define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
18978 | //BIFPLR2_0_DEVICE_CNTL |
18979 | #define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
18980 | #define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
18981 | #define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
18982 | #define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
18983 | #define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
18984 | #define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
18985 | #define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
18986 | #define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
18987 | #define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
18988 | #define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
18989 | #define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
18990 | #define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
18991 | #define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
18992 | #define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
18993 | #define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
18994 | #define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
18995 | #define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
18996 | #define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
18997 | #define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
18998 | #define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
18999 | #define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
19000 | #define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
19001 | #define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
19002 | #define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
19003 | //BIFPLR2_0_DEVICE_STATUS |
19004 | #define BIFPLR2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
19005 | #define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
19006 | #define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
19007 | #define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
19008 | #define BIFPLR2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
19009 | #define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
19010 | #define BIFPLR2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
19011 | #define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
19012 | #define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
19013 | #define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
19014 | #define BIFPLR2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
19015 | #define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
19016 | //BIFPLR2_0_LINK_CAP |
19017 | #define BIFPLR2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
19018 | #define BIFPLR2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
19019 | #define BIFPLR2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
19020 | #define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
19021 | #define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
19022 | #define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
19023 | #define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
19024 | #define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
19025 | #define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
19026 | #define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
19027 | #define BIFPLR2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
19028 | #define BIFPLR2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
19029 | #define BIFPLR2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
19030 | #define BIFPLR2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
19031 | #define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
19032 | #define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
19033 | #define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
19034 | #define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
19035 | #define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
19036 | #define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
19037 | #define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
19038 | #define BIFPLR2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
19039 | //BIFPLR2_0_LINK_CNTL |
19040 | #define BIFPLR2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
19041 | #define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
19042 | #define BIFPLR2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
19043 | #define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
19044 | #define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
19045 | #define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
19046 | #define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
19047 | #define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
19048 | #define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
19049 | #define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
19050 | #define BIFPLR2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
19051 | #define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
19052 | #define BIFPLR2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
19053 | #define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
19054 | #define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
19055 | #define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
19056 | #define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
19057 | #define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
19058 | #define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
19059 | #define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
19060 | //BIFPLR2_0_LINK_STATUS |
19061 | #define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
19062 | #define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
19063 | #define BIFPLR2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
19064 | #define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
19065 | #define BIFPLR2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
19066 | #define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
19067 | #define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
19068 | #define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
19069 | #define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
19070 | #define BIFPLR2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
19071 | #define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
19072 | #define BIFPLR2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
19073 | #define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
19074 | #define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
19075 | //BIFPLR2_0_SLOT_CAP |
19076 | #define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
19077 | #define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
19078 | #define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
19079 | #define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
19080 | #define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
19081 | #define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
19082 | #define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
19083 | #define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
19084 | #define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
19085 | #define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
19086 | #define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
19087 | #define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
19088 | #define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
19089 | #define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
19090 | #define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
19091 | #define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
19092 | #define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
19093 | #define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
19094 | #define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
19095 | #define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
19096 | #define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
19097 | #define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
19098 | #define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
19099 | #define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
19100 | //BIFPLR2_0_SLOT_CNTL |
19101 | #define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
19102 | #define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
19103 | #define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
19104 | #define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
19105 | #define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
19106 | #define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
19107 | #define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
19108 | #define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
19109 | #define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
19110 | #define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
19111 | #define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
19112 | #define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
19113 | #define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
19114 | #define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
19115 | #define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
19116 | #define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
19117 | #define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
19118 | #define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
19119 | #define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
19120 | #define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
19121 | #define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
19122 | #define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
19123 | #define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
19124 | #define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
19125 | //BIFPLR2_0_SLOT_STATUS |
19126 | #define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
19127 | #define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
19128 | #define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
19129 | #define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
19130 | #define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
19131 | #define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
19132 | #define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
19133 | #define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
19134 | #define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
19135 | #define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
19136 | #define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
19137 | #define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
19138 | #define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
19139 | #define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
19140 | #define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
19141 | #define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
19142 | #define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
19143 | #define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
19144 | //BIFPLR2_0_ROOT_CNTL |
19145 | #define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
19146 | #define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
19147 | #define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
19148 | #define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
19149 | #define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
19150 | #define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
19151 | #define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
19152 | #define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
19153 | #define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
19154 | #define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
19155 | //BIFPLR2_0_ROOT_CAP |
19156 | #define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
19157 | #define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
19158 | //BIFPLR2_0_ROOT_STATUS |
19159 | #define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
19160 | #define BIFPLR2_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
19161 | #define BIFPLR2_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
19162 | #define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
19163 | #define BIFPLR2_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
19164 | #define BIFPLR2_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
19165 | //BIFPLR2_0_DEVICE_CAP2 |
19166 | #define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
19167 | #define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
19168 | #define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
19169 | #define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
19170 | #define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
19171 | #define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
19172 | #define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
19173 | #define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
19174 | #define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
19175 | #define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
19176 | #define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
19177 | #define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
19178 | #define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
19179 | #define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
19180 | #define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
19181 | #define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
19182 | #define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
19183 | #define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
19184 | #define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
19185 | #define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
19186 | #define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
19187 | #define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
19188 | #define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
19189 | #define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
19190 | #define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
19191 | #define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
19192 | #define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
19193 | #define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
19194 | //BIFPLR2_0_DEVICE_CNTL2 |
19195 | #define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
19196 | #define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
19197 | #define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
19198 | #define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
19199 | #define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
19200 | #define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
19201 | #define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
19202 | #define BIFPLR2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
19203 | #define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
19204 | #define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
19205 | #define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
19206 | #define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
19207 | #define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
19208 | #define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
19209 | #define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
19210 | #define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
19211 | #define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
19212 | #define BIFPLR2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
19213 | #define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
19214 | #define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
19215 | //BIFPLR2_0_DEVICE_STATUS2 |
19216 | #define BIFPLR2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
19217 | #define BIFPLR2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
19218 | //BIFPLR2_0_LINK_CAP2 |
19219 | #define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
19220 | #define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
19221 | #define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
19222 | #define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
19223 | #define BIFPLR2_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
19224 | #define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
19225 | #define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
19226 | #define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
19227 | #define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
19228 | #define BIFPLR2_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
19229 | //BIFPLR2_0_LINK_CNTL2 |
19230 | #define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
19231 | #define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
19232 | #define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
19233 | #define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
19234 | #define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
19235 | #define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
19236 | #define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
19237 | #define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
19238 | #define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
19239 | #define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
19240 | #define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
19241 | #define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
19242 | #define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
19243 | #define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
19244 | #define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
19245 | #define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
19246 | //BIFPLR2_0_LINK_STATUS2 |
19247 | #define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
19248 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
19249 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
19250 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
19251 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
19252 | #define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
19253 | #define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
19254 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
19255 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
19256 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
19257 | #define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
19258 | #define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
19259 | //BIFPLR2_0_SLOT_CAP2 |
19260 | #define BIFPLR2_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
19261 | #define BIFPLR2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
19262 | //BIFPLR2_0_SLOT_CNTL2 |
19263 | #define BIFPLR2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
19264 | #define BIFPLR2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
19265 | //BIFPLR2_0_SLOT_STATUS2 |
19266 | #define BIFPLR2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
19267 | #define BIFPLR2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
19268 | //BIFPLR2_0_MSI_CAP_LIST |
19269 | #define BIFPLR2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
19270 | #define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19271 | #define BIFPLR2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
19272 | #define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19273 | //BIFPLR2_0_MSI_MSG_CNTL |
19274 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
19275 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
19276 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
19277 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
19278 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
19279 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
19280 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
19281 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
19282 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
19283 | #define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
19284 | //BIFPLR2_0_MSI_MSG_ADDR_LO |
19285 | #define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
19286 | #define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
19287 | //BIFPLR2_0_MSI_MSG_ADDR_HI |
19288 | #define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
19289 | #define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
19290 | //BIFPLR2_0_MSI_MSG_DATA |
19291 | #define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
19292 | #define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
19293 | //BIFPLR2_0_MSI_MSG_DATA_64 |
19294 | #define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
19295 | #define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
19296 | //BIFPLR2_0_SSID_CAP_LIST |
19297 | #define BIFPLR2_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
19298 | #define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19299 | #define BIFPLR2_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
19300 | #define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19301 | //BIFPLR2_0_SSID_CAP |
19302 | #define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
19303 | #define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
19304 | #define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
19305 | #define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
19306 | //BIFPLR2_0_MSI_MAP_CAP_LIST |
19307 | #define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
19308 | #define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19309 | #define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
19310 | #define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19311 | //BIFPLR2_0_MSI_MAP_CAP |
19312 | #define BIFPLR2_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
19313 | #define BIFPLR2_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
19314 | #define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
19315 | #define BIFPLR2_0_MSI_MAP_CAP__EN_MASK 0x0001L |
19316 | #define BIFPLR2_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
19317 | #define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
19318 | //BIFPLR2_0_MSI_MAP_ADDR_LO |
19319 | #define BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
19320 | #define BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
19321 | //BIFPLR2_0_MSI_MAP_ADDR_HI |
19322 | #define BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
19323 | #define BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
19324 | //BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
19325 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19326 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19327 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19328 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19329 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19330 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19331 | //BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR |
19332 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
19333 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
19334 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
19335 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
19336 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
19337 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
19338 | //BIFPLR2_0_PCIE_VENDOR_SPECIFIC1 |
19339 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
19340 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
19341 | //BIFPLR2_0_PCIE_VENDOR_SPECIFIC2 |
19342 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
19343 | #define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
19344 | //BIFPLR2_0_PCIE_VC_ENH_CAP_LIST |
19345 | #define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19346 | #define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19347 | #define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19348 | #define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19349 | #define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19350 | #define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19351 | //BIFPLR2_0_PCIE_PORT_VC_CAP_REG1 |
19352 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
19353 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
19354 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
19355 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
19356 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
19357 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
19358 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
19359 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
19360 | //BIFPLR2_0_PCIE_PORT_VC_CAP_REG2 |
19361 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
19362 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
19363 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
19364 | #define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
19365 | //BIFPLR2_0_PCIE_PORT_VC_CNTL |
19366 | #define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
19367 | #define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
19368 | #define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
19369 | #define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
19370 | //BIFPLR2_0_PCIE_PORT_VC_STATUS |
19371 | #define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
19372 | #define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
19373 | //BIFPLR2_0_PCIE_VC0_RESOURCE_CAP |
19374 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
19375 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
19376 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
19377 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
19378 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
19379 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
19380 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
19381 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
19382 | //BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL |
19383 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
19384 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
19385 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
19386 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
19387 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
19388 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
19389 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
19390 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
19391 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
19392 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
19393 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
19394 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
19395 | //BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS |
19396 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
19397 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
19398 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
19399 | #define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
19400 | //BIFPLR2_0_PCIE_VC1_RESOURCE_CAP |
19401 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
19402 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
19403 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
19404 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
19405 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
19406 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
19407 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
19408 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
19409 | //BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL |
19410 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
19411 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
19412 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
19413 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
19414 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
19415 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
19416 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
19417 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
19418 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
19419 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
19420 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
19421 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
19422 | //BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS |
19423 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
19424 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
19425 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
19426 | #define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
19427 | //BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
19428 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19429 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19430 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19431 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19432 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19433 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19434 | //BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 |
19435 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
19436 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
19437 | //BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 |
19438 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
19439 | #define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
19440 | //BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
19441 | #define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19442 | #define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19443 | #define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19444 | #define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19445 | #define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19446 | #define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19447 | //BIFPLR2_0_PCIE_UNCORR_ERR_STATUS |
19448 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
19449 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
19450 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
19451 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
19452 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
19453 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
19454 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
19455 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
19456 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
19457 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
19458 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
19459 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
19460 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
19461 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
19462 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
19463 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
19464 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
19465 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
19466 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
19467 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
19468 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
19469 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
19470 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
19471 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
19472 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
19473 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
19474 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
19475 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
19476 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
19477 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
19478 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
19479 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
19480 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
19481 | #define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
19482 | //BIFPLR2_0_PCIE_UNCORR_ERR_MASK |
19483 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
19484 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
19485 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
19486 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
19487 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
19488 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
19489 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
19490 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
19491 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
19492 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
19493 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
19494 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
19495 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
19496 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
19497 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
19498 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
19499 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
19500 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
19501 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
19502 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
19503 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
19504 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
19505 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
19506 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
19507 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
19508 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
19509 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
19510 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
19511 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
19512 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
19513 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
19514 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
19515 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
19516 | #define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
19517 | //BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY |
19518 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
19519 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
19520 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
19521 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
19522 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
19523 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
19524 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
19525 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
19526 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
19527 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
19528 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
19529 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
19530 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
19531 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
19532 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
19533 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
19534 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
19535 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
19536 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
19537 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
19538 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
19539 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
19540 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
19541 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
19542 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
19543 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
19544 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
19545 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
19546 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
19547 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
19548 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
19549 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
19550 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
19551 | #define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
19552 | //BIFPLR2_0_PCIE_CORR_ERR_STATUS |
19553 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
19554 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
19555 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
19556 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
19557 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
19558 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
19559 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
19560 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
19561 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
19562 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
19563 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
19564 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
19565 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
19566 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
19567 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
19568 | #define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
19569 | //BIFPLR2_0_PCIE_CORR_ERR_MASK |
19570 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
19571 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
19572 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
19573 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
19574 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
19575 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
19576 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
19577 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
19578 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
19579 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
19580 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
19581 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
19582 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
19583 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
19584 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
19585 | #define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
19586 | //BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL |
19587 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
19588 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
19589 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
19590 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
19591 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
19592 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
19593 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
19594 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
19595 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
19596 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
19597 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
19598 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
19599 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
19600 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
19601 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
19602 | #define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
19603 | //BIFPLR2_0_PCIE_HDR_LOG0 |
19604 | #define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
19605 | #define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
19606 | //BIFPLR2_0_PCIE_HDR_LOG1 |
19607 | #define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
19608 | #define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
19609 | //BIFPLR2_0_PCIE_HDR_LOG2 |
19610 | #define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
19611 | #define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
19612 | //BIFPLR2_0_PCIE_HDR_LOG3 |
19613 | #define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
19614 | #define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
19615 | //BIFPLR2_0_PCIE_ROOT_ERR_CMD |
19616 | #define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
19617 | #define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
19618 | #define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
19619 | #define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
19620 | #define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
19621 | #define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
19622 | //BIFPLR2_0_PCIE_ROOT_ERR_STATUS |
19623 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
19624 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
19625 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
19626 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
19627 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
19628 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
19629 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
19630 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
19631 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
19632 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
19633 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
19634 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
19635 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
19636 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
19637 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
19638 | #define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
19639 | //BIFPLR2_0_PCIE_ERR_SRC_ID |
19640 | #define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
19641 | #define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
19642 | #define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
19643 | #define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
19644 | //BIFPLR2_0_PCIE_TLP_PREFIX_LOG0 |
19645 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
19646 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
19647 | //BIFPLR2_0_PCIE_TLP_PREFIX_LOG1 |
19648 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
19649 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
19650 | //BIFPLR2_0_PCIE_TLP_PREFIX_LOG2 |
19651 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
19652 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
19653 | //BIFPLR2_0_PCIE_TLP_PREFIX_LOG3 |
19654 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
19655 | #define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
19656 | //BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST |
19657 | #define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19658 | #define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19659 | #define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19660 | #define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19661 | #define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19662 | #define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19663 | //BIFPLR2_0_PCIE_LINK_CNTL3 |
19664 | #define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
19665 | #define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
19666 | #define BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
19667 | #define BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
19668 | #define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
19669 | #define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
19670 | #define BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
19671 | #define BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
19672 | //BIFPLR2_0_PCIE_LANE_ERROR_STATUS |
19673 | #define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
19674 | #define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
19675 | #define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
19676 | #define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
19677 | //BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL |
19678 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19679 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19680 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19681 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19682 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19683 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19684 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19685 | #define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19686 | //BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL |
19687 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19688 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19689 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19690 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19691 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19692 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19693 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19694 | #define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19695 | //BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL |
19696 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19697 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19698 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19699 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19700 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19701 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19702 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19703 | #define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19704 | //BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL |
19705 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19706 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19707 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19708 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19709 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19710 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19711 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19712 | #define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19713 | //BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL |
19714 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19715 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19716 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19717 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19718 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19719 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19720 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19721 | #define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19722 | //BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL |
19723 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19724 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19725 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19726 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19727 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19728 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19729 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19730 | #define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19731 | //BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL |
19732 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19733 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19734 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19735 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19736 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19737 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19738 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19739 | #define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19740 | //BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL |
19741 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19742 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19743 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19744 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19745 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19746 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19747 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19748 | #define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19749 | //BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL |
19750 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19751 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19752 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19753 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19754 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19755 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19756 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19757 | #define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19758 | //BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL |
19759 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19760 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19761 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19762 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19763 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19764 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19765 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19766 | #define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19767 | //BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL |
19768 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19769 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19770 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19771 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19772 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19773 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19774 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19775 | #define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19776 | //BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL |
19777 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19778 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19779 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19780 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19781 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19782 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19783 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19784 | #define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19785 | //BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL |
19786 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19787 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19788 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19789 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19790 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19791 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19792 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19793 | #define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19794 | //BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL |
19795 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19796 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19797 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19798 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19799 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19800 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19801 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19802 | #define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19803 | //BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL |
19804 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19805 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19806 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19807 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19808 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19809 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19810 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19811 | #define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19812 | //BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL |
19813 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
19814 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
19815 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
19816 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
19817 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
19818 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
19819 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
19820 | #define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
19821 | //BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST |
19822 | #define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19823 | #define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19824 | #define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19825 | #define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19826 | #define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19827 | #define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19828 | //BIFPLR2_0_PCIE_ACS_CAP |
19829 | #define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
19830 | #define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
19831 | #define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
19832 | #define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
19833 | #define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
19834 | #define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
19835 | #define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
19836 | #define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
19837 | #define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
19838 | #define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
19839 | #define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
19840 | #define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
19841 | #define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
19842 | #define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
19843 | #define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
19844 | #define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
19845 | //BIFPLR2_0_PCIE_ACS_CNTL |
19846 | #define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
19847 | #define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
19848 | #define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
19849 | #define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
19850 | #define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
19851 | #define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
19852 | #define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
19853 | #define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
19854 | #define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
19855 | #define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
19856 | #define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
19857 | #define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
19858 | #define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
19859 | #define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
19860 | //BIFPLR2_0_PCIE_MC_ENH_CAP_LIST |
19861 | #define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19862 | #define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19863 | #define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19864 | #define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19865 | #define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19866 | #define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19867 | //BIFPLR2_0_PCIE_MC_CAP |
19868 | #define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
19869 | #define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
19870 | #define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
19871 | #define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
19872 | //BIFPLR2_0_PCIE_MC_CNTL |
19873 | #define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
19874 | #define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
19875 | #define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
19876 | #define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
19877 | //BIFPLR2_0_PCIE_MC_ADDR0 |
19878 | #define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
19879 | #define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
19880 | #define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
19881 | #define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
19882 | //BIFPLR2_0_PCIE_MC_ADDR1 |
19883 | #define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
19884 | #define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
19885 | //BIFPLR2_0_PCIE_MC_RCV0 |
19886 | #define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
19887 | #define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
19888 | //BIFPLR2_0_PCIE_MC_RCV1 |
19889 | #define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
19890 | #define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
19891 | //BIFPLR2_0_PCIE_MC_BLOCK_ALL0 |
19892 | #define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
19893 | #define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
19894 | //BIFPLR2_0_PCIE_MC_BLOCK_ALL1 |
19895 | #define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
19896 | #define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
19897 | //BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
19898 | #define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
19899 | #define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
19900 | //BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
19901 | #define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
19902 | #define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
19903 | //BIFPLR2_0_PCIE_MC_OVERLAY_BAR0 |
19904 | #define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
19905 | #define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
19906 | #define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
19907 | #define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
19908 | //BIFPLR2_0_PCIE_MC_OVERLAY_BAR1 |
19909 | #define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
19910 | #define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
19911 | //BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST |
19912 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
19913 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
19914 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19915 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19916 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19917 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19918 | //BIFPLR2_0_PCIE_L1_PM_SUB_CAP |
19919 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
19920 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
19921 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
19922 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
19923 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
19924 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
19925 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
19926 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
19927 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
19928 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
19929 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
19930 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
19931 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
19932 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
19933 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
19934 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
19935 | //BIFPLR2_0_PCIE_L1_PM_SUB_CNTL |
19936 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
19937 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
19938 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
19939 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
19940 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
19941 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
19942 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
19943 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
19944 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
19945 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
19946 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
19947 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
19948 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
19949 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
19950 | //BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 |
19951 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
19952 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
19953 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
19954 | #define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
19955 | //BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST |
19956 | #define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19957 | #define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19958 | #define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19959 | #define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19960 | #define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19961 | #define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19962 | //BIFPLR2_0_PCIE_DPC_CAP_LIST |
19963 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
19964 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
19965 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
19966 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
19967 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
19968 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
19969 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
19970 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
19971 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
19972 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
19973 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
19974 | #define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
19975 | //BIFPLR2_0_PCIE_DPC_CNTL |
19976 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
19977 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
19978 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
19979 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
19980 | #define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
19981 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
19982 | #define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
19983 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
19984 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
19985 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
19986 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
19987 | #define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
19988 | #define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
19989 | #define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
19990 | //BIFPLR2_0_PCIE_DPC_STATUS |
19991 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
19992 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
19993 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
19994 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
19995 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
19996 | #define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
19997 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
19998 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
19999 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
20000 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
20001 | #define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
20002 | #define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
20003 | //BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID |
20004 | #define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
20005 | #define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
20006 | //BIFPLR2_0_PCIE_RP_PIO_STATUS |
20007 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
20008 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
20009 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
20010 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
20011 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
20012 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
20013 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
20014 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
20015 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
20016 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
20017 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
20018 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
20019 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
20020 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
20021 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
20022 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
20023 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
20024 | #define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
20025 | //BIFPLR2_0_PCIE_RP_PIO_MASK |
20026 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
20027 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
20028 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
20029 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
20030 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
20031 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
20032 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
20033 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
20034 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
20035 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
20036 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
20037 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
20038 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
20039 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
20040 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
20041 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
20042 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
20043 | #define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
20044 | //BIFPLR2_0_PCIE_RP_PIO_SEVERITY |
20045 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
20046 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
20047 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
20048 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
20049 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
20050 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
20051 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
20052 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
20053 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
20054 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
20055 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
20056 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
20057 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
20058 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
20059 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
20060 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
20061 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
20062 | #define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
20063 | //BIFPLR2_0_PCIE_RP_PIO_SYSERROR |
20064 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
20065 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
20066 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
20067 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
20068 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
20069 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
20070 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
20071 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
20072 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
20073 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
20074 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
20075 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
20076 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
20077 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
20078 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
20079 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
20080 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
20081 | #define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
20082 | //BIFPLR2_0_PCIE_RP_PIO_EXCEPTION |
20083 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
20084 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
20085 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
20086 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
20087 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
20088 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
20089 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
20090 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
20091 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
20092 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
20093 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
20094 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
20095 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
20096 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
20097 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
20098 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
20099 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
20100 | #define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
20101 | //BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 |
20102 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
20103 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
20104 | //BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 |
20105 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
20106 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
20107 | //BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 |
20108 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
20109 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
20110 | //BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 |
20111 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
20112 | #define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
20113 | //BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG |
20114 | #define BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
20115 | #define BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
20116 | //BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 |
20117 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
20118 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
20119 | //BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 |
20120 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
20121 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
20122 | //BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 |
20123 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
20124 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
20125 | //BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 |
20126 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
20127 | #define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
20128 | //BIFPLR2_0_PCIE_ESM_CAP_LIST |
20129 | #define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
20130 | #define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
20131 | #define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20132 | #define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20133 | #define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20134 | #define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20135 | //BIFPLR2_0_PCIE_ESM_HEADER_1 |
20136 | #define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
20137 | #define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
20138 | #define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
20139 | #define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
20140 | #define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
20141 | #define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
20142 | //BIFPLR2_0_PCIE_ESM_HEADER_2 |
20143 | #define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
20144 | #define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
20145 | //BIFPLR2_0_PCIE_ESM_STATUS |
20146 | #define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
20147 | #define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
20148 | #define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
20149 | #define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
20150 | //BIFPLR2_0_PCIE_ESM_CTRL |
20151 | #define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
20152 | #define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
20153 | #define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
20154 | #define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
20155 | #define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
20156 | #define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
20157 | //BIFPLR2_0_PCIE_ESM_CAP_1 |
20158 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
20159 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
20160 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
20161 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
20162 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
20163 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
20164 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
20165 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
20166 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
20167 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
20168 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
20169 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
20170 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
20171 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
20172 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
20173 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
20174 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
20175 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
20176 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
20177 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
20178 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
20179 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
20180 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
20181 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
20182 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
20183 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
20184 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
20185 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
20186 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
20187 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
20188 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
20189 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
20190 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
20191 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
20192 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
20193 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
20194 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
20195 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
20196 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
20197 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
20198 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
20199 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
20200 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
20201 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
20202 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
20203 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
20204 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
20205 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
20206 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
20207 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
20208 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
20209 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
20210 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
20211 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
20212 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
20213 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
20214 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
20215 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
20216 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
20217 | #define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
20218 | //BIFPLR2_0_PCIE_ESM_CAP_2 |
20219 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
20220 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
20221 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
20222 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
20223 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
20224 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
20225 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
20226 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
20227 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
20228 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
20229 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
20230 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
20231 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
20232 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
20233 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
20234 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
20235 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
20236 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
20237 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
20238 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
20239 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
20240 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
20241 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
20242 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
20243 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
20244 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
20245 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
20246 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
20247 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
20248 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
20249 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
20250 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
20251 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
20252 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
20253 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
20254 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
20255 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
20256 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
20257 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
20258 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
20259 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
20260 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
20261 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
20262 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
20263 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
20264 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
20265 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
20266 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
20267 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
20268 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
20269 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
20270 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
20271 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
20272 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
20273 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
20274 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
20275 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
20276 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
20277 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
20278 | #define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
20279 | //BIFPLR2_0_PCIE_ESM_CAP_3 |
20280 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
20281 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
20282 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
20283 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
20284 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
20285 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
20286 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
20287 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
20288 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
20289 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
20290 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
20291 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
20292 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
20293 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
20294 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
20295 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
20296 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
20297 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
20298 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
20299 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
20300 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
20301 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
20302 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
20303 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
20304 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
20305 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
20306 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
20307 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
20308 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
20309 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
20310 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
20311 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
20312 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
20313 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
20314 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
20315 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
20316 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
20317 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
20318 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
20319 | #define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
20320 | //BIFPLR2_0_PCIE_ESM_CAP_4 |
20321 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
20322 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
20323 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
20324 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
20325 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
20326 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
20327 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
20328 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
20329 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
20330 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
20331 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
20332 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
20333 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
20334 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
20335 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
20336 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
20337 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
20338 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
20339 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
20340 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
20341 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
20342 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
20343 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
20344 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
20345 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
20346 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
20347 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
20348 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
20349 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
20350 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
20351 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
20352 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
20353 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
20354 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
20355 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
20356 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
20357 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
20358 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
20359 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
20360 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
20361 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
20362 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
20363 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
20364 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
20365 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
20366 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
20367 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
20368 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
20369 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
20370 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
20371 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
20372 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
20373 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
20374 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
20375 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
20376 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
20377 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
20378 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
20379 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
20380 | #define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
20381 | //BIFPLR2_0_PCIE_ESM_CAP_5 |
20382 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
20383 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
20384 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
20385 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
20386 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
20387 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
20388 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
20389 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
20390 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
20391 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
20392 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
20393 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
20394 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
20395 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
20396 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
20397 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
20398 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
20399 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
20400 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
20401 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
20402 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
20403 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
20404 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
20405 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
20406 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
20407 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
20408 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
20409 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
20410 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
20411 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
20412 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
20413 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
20414 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
20415 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
20416 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
20417 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
20418 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
20419 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
20420 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
20421 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
20422 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
20423 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
20424 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
20425 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
20426 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
20427 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
20428 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
20429 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
20430 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
20431 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
20432 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
20433 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
20434 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
20435 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
20436 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
20437 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
20438 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
20439 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
20440 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
20441 | #define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
20442 | //BIFPLR2_0_PCIE_ESM_CAP_6 |
20443 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
20444 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
20445 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
20446 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
20447 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
20448 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
20449 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
20450 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
20451 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
20452 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
20453 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
20454 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
20455 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
20456 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
20457 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
20458 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
20459 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
20460 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
20461 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
20462 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
20463 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
20464 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
20465 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
20466 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
20467 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
20468 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
20469 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
20470 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
20471 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
20472 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
20473 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
20474 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
20475 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
20476 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
20477 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
20478 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
20479 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
20480 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
20481 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
20482 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
20483 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
20484 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
20485 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
20486 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
20487 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
20488 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
20489 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
20490 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
20491 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
20492 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
20493 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
20494 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
20495 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
20496 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
20497 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
20498 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
20499 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
20500 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
20501 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
20502 | #define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
20503 | //BIFPLR2_0_PCIE_ESM_CAP_7 |
20504 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
20505 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
20506 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
20507 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
20508 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
20509 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
20510 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
20511 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
20512 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
20513 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
20514 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
20515 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
20516 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
20517 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
20518 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
20519 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
20520 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
20521 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
20522 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
20523 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
20524 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
20525 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
20526 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
20527 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
20528 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
20529 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
20530 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
20531 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
20532 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
20533 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
20534 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
20535 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
20536 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
20537 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
20538 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
20539 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
20540 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
20541 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
20542 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
20543 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
20544 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
20545 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
20546 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
20547 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
20548 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
20549 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
20550 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
20551 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
20552 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
20553 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
20554 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
20555 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
20556 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
20557 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
20558 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
20559 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
20560 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
20561 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
20562 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
20563 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
20564 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
20565 | #define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
20566 | |
20567 | |
20568 | // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
20569 | //BIFPLR3_0_VENDOR_ID |
20570 | #define BIFPLR3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
20571 | #define BIFPLR3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
20572 | //BIFPLR3_0_DEVICE_ID |
20573 | #define BIFPLR3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
20574 | #define BIFPLR3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
20575 | //BIFPLR3_0_COMMAND |
20576 | #define BIFPLR3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
20577 | #define BIFPLR3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
20578 | #define BIFPLR3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
20579 | #define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
20580 | #define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
20581 | #define BIFPLR3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
20582 | #define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
20583 | #define BIFPLR3_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
20584 | #define BIFPLR3_0_COMMAND__SERR_EN__SHIFT 0x8 |
20585 | #define BIFPLR3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
20586 | #define BIFPLR3_0_COMMAND__INT_DIS__SHIFT 0xa |
20587 | #define BIFPLR3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
20588 | #define BIFPLR3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
20589 | #define BIFPLR3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
20590 | #define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
20591 | #define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
20592 | #define BIFPLR3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
20593 | #define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
20594 | #define BIFPLR3_0_COMMAND__AD_STEPPING_MASK 0x0080L |
20595 | #define BIFPLR3_0_COMMAND__SERR_EN_MASK 0x0100L |
20596 | #define BIFPLR3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
20597 | #define BIFPLR3_0_COMMAND__INT_DIS_MASK 0x0400L |
20598 | //BIFPLR3_0_STATUS |
20599 | #define BIFPLR3_0_STATUS__INT_STATUS__SHIFT 0x3 |
20600 | #define BIFPLR3_0_STATUS__CAP_LIST__SHIFT 0x4 |
20601 | #define BIFPLR3_0_STATUS__PCI_66_EN__SHIFT 0x5 |
20602 | #define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
20603 | #define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
20604 | #define BIFPLR3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
20605 | #define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
20606 | #define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
20607 | #define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
20608 | #define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
20609 | #define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
20610 | #define BIFPLR3_0_STATUS__INT_STATUS_MASK 0x0008L |
20611 | #define BIFPLR3_0_STATUS__CAP_LIST_MASK 0x0010L |
20612 | #define BIFPLR3_0_STATUS__PCI_66_EN_MASK 0x0020L |
20613 | #define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
20614 | #define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
20615 | #define BIFPLR3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
20616 | #define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
20617 | #define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
20618 | #define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
20619 | #define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
20620 | #define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
20621 | //BIFPLR3_0_REVISION_ID |
20622 | #define BIFPLR3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
20623 | #define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
20624 | #define BIFPLR3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
20625 | #define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
20626 | //BIFPLR3_0_PROG_INTERFACE |
20627 | #define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
20628 | #define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
20629 | //BIFPLR3_0_SUB_CLASS |
20630 | #define BIFPLR3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
20631 | #define BIFPLR3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
20632 | //BIFPLR3_0_BASE_CLASS |
20633 | #define BIFPLR3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
20634 | #define BIFPLR3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
20635 | //BIFPLR3_0_CACHE_LINE |
20636 | #define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
20637 | #define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
20638 | //BIFPLR3_0_LATENCY |
20639 | #define BIFPLR3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
20640 | #define BIFPLR3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
20641 | //BIFPLR3_0_HEADER |
20642 | #define BIFPLR3_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
20643 | #define BIFPLR3_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
20644 | #define BIFPLR3_0_HEADER__HEADER_TYPE_MASK 0x7FL |
20645 | #define BIFPLR3_0_HEADER__DEVICE_TYPE_MASK 0x80L |
20646 | //BIFPLR3_0_BIST |
20647 | #define BIFPLR3_0_BIST__BIST_COMP__SHIFT 0x0 |
20648 | #define BIFPLR3_0_BIST__BIST_STRT__SHIFT 0x6 |
20649 | #define BIFPLR3_0_BIST__BIST_CAP__SHIFT 0x7 |
20650 | #define BIFPLR3_0_BIST__BIST_COMP_MASK 0x0FL |
20651 | #define BIFPLR3_0_BIST__BIST_STRT_MASK 0x40L |
20652 | #define BIFPLR3_0_BIST__BIST_CAP_MASK 0x80L |
20653 | //BIFPLR3_0_SUB_BUS_NUMBER_LATENCY |
20654 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
20655 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
20656 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
20657 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
20658 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
20659 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
20660 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
20661 | #define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
20662 | //BIFPLR3_0_IO_BASE_LIMIT |
20663 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
20664 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
20665 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
20666 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
20667 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
20668 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
20669 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
20670 | #define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
20671 | //BIFPLR3_0_SECONDARY_STATUS |
20672 | #define BIFPLR3_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
20673 | #define BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
20674 | #define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
20675 | #define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
20676 | #define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
20677 | #define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
20678 | #define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
20679 | #define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
20680 | #define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
20681 | #define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
20682 | #define BIFPLR3_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
20683 | #define BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
20684 | #define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
20685 | #define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
20686 | #define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
20687 | #define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
20688 | #define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
20689 | #define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
20690 | #define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
20691 | #define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
20692 | //BIFPLR3_0_MEM_BASE_LIMIT |
20693 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
20694 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
20695 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
20696 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
20697 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
20698 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
20699 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
20700 | #define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
20701 | //BIFPLR3_0_PREF_BASE_LIMIT |
20702 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
20703 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
20704 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
20705 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
20706 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
20707 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
20708 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
20709 | #define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
20710 | //BIFPLR3_0_PREF_BASE_UPPER |
20711 | #define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
20712 | #define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
20713 | //BIFPLR3_0_PREF_LIMIT_UPPER |
20714 | #define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
20715 | #define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
20716 | //BIFPLR3_0_IO_BASE_LIMIT_HI |
20717 | #define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
20718 | #define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
20719 | #define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
20720 | #define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
20721 | //BIFPLR3_0_CAP_PTR |
20722 | #define BIFPLR3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
20723 | #define BIFPLR3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
20724 | //BIFPLR3_0_INTERRUPT_LINE |
20725 | #define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
20726 | #define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
20727 | //BIFPLR3_0_INTERRUPT_PIN |
20728 | #define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
20729 | #define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
20730 | //BIFPLR3_0_IRQ_BRIDGE_CNTL |
20731 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
20732 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
20733 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
20734 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
20735 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
20736 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
20737 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
20738 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
20739 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
20740 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
20741 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
20742 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
20743 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
20744 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
20745 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
20746 | #define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
20747 | //BIFPLR3_0_EXT_BRIDGE_CNTL |
20748 | #define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
20749 | #define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
20750 | //BIFPLR3_0_PMI_CAP_LIST |
20751 | #define BIFPLR3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
20752 | #define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20753 | #define BIFPLR3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
20754 | #define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
20755 | //BIFPLR3_0_PMI_CAP |
20756 | #define BIFPLR3_0_PMI_CAP__VERSION__SHIFT 0x0 |
20757 | #define BIFPLR3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
20758 | #define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
20759 | #define BIFPLR3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
20760 | #define BIFPLR3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
20761 | #define BIFPLR3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
20762 | #define BIFPLR3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
20763 | #define BIFPLR3_0_PMI_CAP__VERSION_MASK 0x0007L |
20764 | #define BIFPLR3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
20765 | #define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
20766 | #define BIFPLR3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
20767 | #define BIFPLR3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
20768 | #define BIFPLR3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
20769 | #define BIFPLR3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
20770 | //BIFPLR3_0_PMI_STATUS_CNTL |
20771 | #define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
20772 | #define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
20773 | #define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
20774 | #define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
20775 | #define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
20776 | #define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
20777 | #define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
20778 | #define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
20779 | #define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
20780 | #define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
20781 | #define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
20782 | #define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
20783 | #define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
20784 | #define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
20785 | #define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
20786 | #define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
20787 | #define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
20788 | #define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
20789 | //BIFPLR3_0_PCIE_CAP_LIST |
20790 | #define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
20791 | #define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20792 | #define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
20793 | #define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
20794 | //BIFPLR3_0_PCIE_CAP |
20795 | #define BIFPLR3_0_PCIE_CAP__VERSION__SHIFT 0x0 |
20796 | #define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
20797 | #define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
20798 | #define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
20799 | #define BIFPLR3_0_PCIE_CAP__VERSION_MASK 0x000FL |
20800 | #define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
20801 | #define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
20802 | #define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
20803 | //BIFPLR3_0_DEVICE_CAP |
20804 | #define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
20805 | #define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
20806 | #define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
20807 | #define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
20808 | #define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
20809 | #define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
20810 | #define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
20811 | #define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
20812 | #define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
20813 | #define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
20814 | #define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
20815 | #define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
20816 | #define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
20817 | #define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
20818 | #define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
20819 | #define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
20820 | #define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
20821 | #define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
20822 | //BIFPLR3_0_DEVICE_CNTL |
20823 | #define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
20824 | #define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
20825 | #define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
20826 | #define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
20827 | #define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
20828 | #define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
20829 | #define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
20830 | #define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
20831 | #define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
20832 | #define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
20833 | #define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
20834 | #define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
20835 | #define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
20836 | #define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
20837 | #define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
20838 | #define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
20839 | #define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
20840 | #define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
20841 | #define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
20842 | #define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
20843 | #define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
20844 | #define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
20845 | #define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
20846 | #define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
20847 | //BIFPLR3_0_DEVICE_STATUS |
20848 | #define BIFPLR3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
20849 | #define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
20850 | #define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
20851 | #define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
20852 | #define BIFPLR3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
20853 | #define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
20854 | #define BIFPLR3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
20855 | #define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
20856 | #define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
20857 | #define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
20858 | #define BIFPLR3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
20859 | #define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
20860 | //BIFPLR3_0_LINK_CAP |
20861 | #define BIFPLR3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
20862 | #define BIFPLR3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
20863 | #define BIFPLR3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
20864 | #define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
20865 | #define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
20866 | #define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
20867 | #define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
20868 | #define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
20869 | #define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
20870 | #define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
20871 | #define BIFPLR3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
20872 | #define BIFPLR3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
20873 | #define BIFPLR3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
20874 | #define BIFPLR3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
20875 | #define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
20876 | #define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
20877 | #define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
20878 | #define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
20879 | #define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
20880 | #define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
20881 | #define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
20882 | #define BIFPLR3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
20883 | //BIFPLR3_0_LINK_CNTL |
20884 | #define BIFPLR3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
20885 | #define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
20886 | #define BIFPLR3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
20887 | #define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
20888 | #define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
20889 | #define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
20890 | #define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
20891 | #define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
20892 | #define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
20893 | #define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
20894 | #define BIFPLR3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
20895 | #define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
20896 | #define BIFPLR3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
20897 | #define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
20898 | #define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
20899 | #define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
20900 | #define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
20901 | #define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
20902 | #define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
20903 | #define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
20904 | //BIFPLR3_0_LINK_STATUS |
20905 | #define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
20906 | #define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
20907 | #define BIFPLR3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
20908 | #define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
20909 | #define BIFPLR3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
20910 | #define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
20911 | #define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
20912 | #define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
20913 | #define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
20914 | #define BIFPLR3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
20915 | #define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
20916 | #define BIFPLR3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
20917 | #define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
20918 | #define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
20919 | //BIFPLR3_0_SLOT_CAP |
20920 | #define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
20921 | #define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
20922 | #define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
20923 | #define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
20924 | #define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
20925 | #define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
20926 | #define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
20927 | #define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
20928 | #define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
20929 | #define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
20930 | #define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
20931 | #define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
20932 | #define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
20933 | #define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
20934 | #define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
20935 | #define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
20936 | #define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
20937 | #define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
20938 | #define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
20939 | #define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
20940 | #define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
20941 | #define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
20942 | #define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
20943 | #define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
20944 | //BIFPLR3_0_SLOT_CNTL |
20945 | #define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
20946 | #define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
20947 | #define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
20948 | #define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
20949 | #define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
20950 | #define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
20951 | #define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
20952 | #define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
20953 | #define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
20954 | #define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
20955 | #define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
20956 | #define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
20957 | #define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
20958 | #define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
20959 | #define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
20960 | #define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
20961 | #define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
20962 | #define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
20963 | #define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
20964 | #define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
20965 | #define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
20966 | #define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
20967 | #define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
20968 | #define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
20969 | //BIFPLR3_0_SLOT_STATUS |
20970 | #define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
20971 | #define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
20972 | #define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
20973 | #define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
20974 | #define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
20975 | #define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
20976 | #define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
20977 | #define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
20978 | #define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
20979 | #define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
20980 | #define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
20981 | #define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
20982 | #define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
20983 | #define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
20984 | #define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
20985 | #define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
20986 | #define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
20987 | #define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
20988 | //BIFPLR3_0_ROOT_CNTL |
20989 | #define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
20990 | #define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
20991 | #define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
20992 | #define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
20993 | #define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
20994 | #define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
20995 | #define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
20996 | #define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
20997 | #define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
20998 | #define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
20999 | //BIFPLR3_0_ROOT_CAP |
21000 | #define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
21001 | #define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
21002 | //BIFPLR3_0_ROOT_STATUS |
21003 | #define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
21004 | #define BIFPLR3_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
21005 | #define BIFPLR3_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
21006 | #define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
21007 | #define BIFPLR3_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
21008 | #define BIFPLR3_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
21009 | //BIFPLR3_0_DEVICE_CAP2 |
21010 | #define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
21011 | #define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
21012 | #define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
21013 | #define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
21014 | #define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
21015 | #define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
21016 | #define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
21017 | #define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
21018 | #define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
21019 | #define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
21020 | #define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
21021 | #define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
21022 | #define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
21023 | #define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
21024 | #define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
21025 | #define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
21026 | #define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
21027 | #define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
21028 | #define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
21029 | #define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
21030 | #define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
21031 | #define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
21032 | #define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
21033 | #define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
21034 | #define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
21035 | #define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
21036 | #define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
21037 | #define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
21038 | //BIFPLR3_0_DEVICE_CNTL2 |
21039 | #define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
21040 | #define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
21041 | #define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
21042 | #define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
21043 | #define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
21044 | #define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
21045 | #define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
21046 | #define BIFPLR3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
21047 | #define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
21048 | #define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
21049 | #define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
21050 | #define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
21051 | #define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
21052 | #define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
21053 | #define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
21054 | #define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
21055 | #define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
21056 | #define BIFPLR3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
21057 | #define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
21058 | #define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
21059 | //BIFPLR3_0_DEVICE_STATUS2 |
21060 | #define BIFPLR3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
21061 | #define BIFPLR3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
21062 | //BIFPLR3_0_LINK_CAP2 |
21063 | #define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
21064 | #define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
21065 | #define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
21066 | #define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
21067 | #define BIFPLR3_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
21068 | #define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
21069 | #define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
21070 | #define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
21071 | #define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
21072 | #define BIFPLR3_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
21073 | //BIFPLR3_0_LINK_CNTL2 |
21074 | #define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
21075 | #define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
21076 | #define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
21077 | #define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
21078 | #define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
21079 | #define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
21080 | #define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
21081 | #define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
21082 | #define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
21083 | #define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
21084 | #define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
21085 | #define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
21086 | #define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
21087 | #define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
21088 | #define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
21089 | #define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
21090 | //BIFPLR3_0_LINK_STATUS2 |
21091 | #define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
21092 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
21093 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
21094 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
21095 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
21096 | #define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
21097 | #define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
21098 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
21099 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
21100 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
21101 | #define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
21102 | #define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
21103 | //BIFPLR3_0_SLOT_CAP2 |
21104 | #define BIFPLR3_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
21105 | #define BIFPLR3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
21106 | //BIFPLR3_0_SLOT_CNTL2 |
21107 | #define BIFPLR3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
21108 | #define BIFPLR3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
21109 | //BIFPLR3_0_SLOT_STATUS2 |
21110 | #define BIFPLR3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
21111 | #define BIFPLR3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
21112 | //BIFPLR3_0_MSI_CAP_LIST |
21113 | #define BIFPLR3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
21114 | #define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
21115 | #define BIFPLR3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
21116 | #define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
21117 | //BIFPLR3_0_MSI_MSG_CNTL |
21118 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
21119 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
21120 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
21121 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
21122 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
21123 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
21124 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
21125 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
21126 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
21127 | #define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
21128 | //BIFPLR3_0_MSI_MSG_ADDR_LO |
21129 | #define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
21130 | #define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
21131 | //BIFPLR3_0_MSI_MSG_ADDR_HI |
21132 | #define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
21133 | #define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
21134 | //BIFPLR3_0_MSI_MSG_DATA |
21135 | #define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
21136 | #define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
21137 | //BIFPLR3_0_MSI_MSG_DATA_64 |
21138 | #define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
21139 | #define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
21140 | //BIFPLR3_0_SSID_CAP_LIST |
21141 | #define BIFPLR3_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
21142 | #define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
21143 | #define BIFPLR3_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
21144 | #define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
21145 | //BIFPLR3_0_SSID_CAP |
21146 | #define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
21147 | #define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
21148 | #define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
21149 | #define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
21150 | //BIFPLR3_0_MSI_MAP_CAP_LIST |
21151 | #define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
21152 | #define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
21153 | #define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
21154 | #define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
21155 | //BIFPLR3_0_MSI_MAP_CAP |
21156 | #define BIFPLR3_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
21157 | #define BIFPLR3_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
21158 | #define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
21159 | #define BIFPLR3_0_MSI_MAP_CAP__EN_MASK 0x0001L |
21160 | #define BIFPLR3_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
21161 | #define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
21162 | //BIFPLR3_0_MSI_MAP_ADDR_LO |
21163 | #define BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
21164 | #define BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
21165 | //BIFPLR3_0_MSI_MAP_ADDR_HI |
21166 | #define BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
21167 | #define BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
21168 | //BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
21169 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21170 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21171 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21172 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21173 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21174 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21175 | //BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR |
21176 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
21177 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
21178 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
21179 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
21180 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
21181 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
21182 | //BIFPLR3_0_PCIE_VENDOR_SPECIFIC1 |
21183 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
21184 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
21185 | //BIFPLR3_0_PCIE_VENDOR_SPECIFIC2 |
21186 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
21187 | #define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
21188 | //BIFPLR3_0_PCIE_VC_ENH_CAP_LIST |
21189 | #define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21190 | #define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21191 | #define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21192 | #define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21193 | #define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21194 | #define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21195 | //BIFPLR3_0_PCIE_PORT_VC_CAP_REG1 |
21196 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
21197 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
21198 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
21199 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
21200 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
21201 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
21202 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
21203 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
21204 | //BIFPLR3_0_PCIE_PORT_VC_CAP_REG2 |
21205 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
21206 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
21207 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
21208 | #define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
21209 | //BIFPLR3_0_PCIE_PORT_VC_CNTL |
21210 | #define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
21211 | #define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
21212 | #define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
21213 | #define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
21214 | //BIFPLR3_0_PCIE_PORT_VC_STATUS |
21215 | #define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
21216 | #define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
21217 | //BIFPLR3_0_PCIE_VC0_RESOURCE_CAP |
21218 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
21219 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
21220 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
21221 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
21222 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
21223 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
21224 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
21225 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
21226 | //BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL |
21227 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
21228 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
21229 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
21230 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
21231 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
21232 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
21233 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
21234 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
21235 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
21236 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
21237 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
21238 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
21239 | //BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS |
21240 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
21241 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
21242 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
21243 | #define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
21244 | //BIFPLR3_0_PCIE_VC1_RESOURCE_CAP |
21245 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
21246 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
21247 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
21248 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
21249 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
21250 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
21251 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
21252 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
21253 | //BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL |
21254 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
21255 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
21256 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
21257 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
21258 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
21259 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
21260 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
21261 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
21262 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
21263 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
21264 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
21265 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
21266 | //BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS |
21267 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
21268 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
21269 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
21270 | #define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
21271 | //BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
21272 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21273 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21274 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21275 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21276 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21277 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21278 | //BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 |
21279 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
21280 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
21281 | //BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 |
21282 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
21283 | #define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
21284 | //BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
21285 | #define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21286 | #define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21287 | #define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21288 | #define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21289 | #define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21290 | #define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21291 | //BIFPLR3_0_PCIE_UNCORR_ERR_STATUS |
21292 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
21293 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
21294 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
21295 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
21296 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
21297 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
21298 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
21299 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
21300 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
21301 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
21302 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
21303 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
21304 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
21305 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
21306 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
21307 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
21308 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
21309 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
21310 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
21311 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
21312 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
21313 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
21314 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
21315 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
21316 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
21317 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
21318 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
21319 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
21320 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
21321 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
21322 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
21323 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
21324 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
21325 | #define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
21326 | //BIFPLR3_0_PCIE_UNCORR_ERR_MASK |
21327 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
21328 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
21329 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
21330 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
21331 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
21332 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
21333 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
21334 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
21335 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
21336 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
21337 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
21338 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
21339 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
21340 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
21341 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
21342 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
21343 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
21344 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
21345 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
21346 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
21347 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
21348 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
21349 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
21350 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
21351 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
21352 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
21353 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
21354 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
21355 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
21356 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
21357 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
21358 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
21359 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
21360 | #define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
21361 | //BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY |
21362 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
21363 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
21364 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
21365 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
21366 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
21367 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
21368 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
21369 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
21370 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
21371 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
21372 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
21373 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
21374 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
21375 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
21376 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
21377 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
21378 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
21379 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
21380 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
21381 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
21382 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
21383 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
21384 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
21385 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
21386 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
21387 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
21388 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
21389 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
21390 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
21391 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
21392 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
21393 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
21394 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
21395 | #define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
21396 | //BIFPLR3_0_PCIE_CORR_ERR_STATUS |
21397 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
21398 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
21399 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
21400 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
21401 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
21402 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
21403 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
21404 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
21405 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
21406 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
21407 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
21408 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
21409 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
21410 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
21411 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
21412 | #define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
21413 | //BIFPLR3_0_PCIE_CORR_ERR_MASK |
21414 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
21415 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
21416 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
21417 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
21418 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
21419 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
21420 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
21421 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
21422 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
21423 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
21424 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
21425 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
21426 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
21427 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
21428 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
21429 | #define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
21430 | //BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL |
21431 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
21432 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
21433 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
21434 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
21435 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
21436 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
21437 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
21438 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
21439 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
21440 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
21441 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
21442 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
21443 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
21444 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
21445 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
21446 | #define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
21447 | //BIFPLR3_0_PCIE_HDR_LOG0 |
21448 | #define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
21449 | #define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
21450 | //BIFPLR3_0_PCIE_HDR_LOG1 |
21451 | #define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
21452 | #define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
21453 | //BIFPLR3_0_PCIE_HDR_LOG2 |
21454 | #define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
21455 | #define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
21456 | //BIFPLR3_0_PCIE_HDR_LOG3 |
21457 | #define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
21458 | #define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
21459 | //BIFPLR3_0_PCIE_ROOT_ERR_CMD |
21460 | #define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
21461 | #define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
21462 | #define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
21463 | #define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
21464 | #define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
21465 | #define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
21466 | //BIFPLR3_0_PCIE_ROOT_ERR_STATUS |
21467 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
21468 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
21469 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
21470 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
21471 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
21472 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
21473 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
21474 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
21475 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
21476 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
21477 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
21478 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
21479 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
21480 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
21481 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
21482 | #define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
21483 | //BIFPLR3_0_PCIE_ERR_SRC_ID |
21484 | #define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
21485 | #define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
21486 | #define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
21487 | #define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
21488 | //BIFPLR3_0_PCIE_TLP_PREFIX_LOG0 |
21489 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
21490 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
21491 | //BIFPLR3_0_PCIE_TLP_PREFIX_LOG1 |
21492 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
21493 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
21494 | //BIFPLR3_0_PCIE_TLP_PREFIX_LOG2 |
21495 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
21496 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
21497 | //BIFPLR3_0_PCIE_TLP_PREFIX_LOG3 |
21498 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
21499 | #define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
21500 | //BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST |
21501 | #define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21502 | #define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21503 | #define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21504 | #define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21505 | #define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21506 | #define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21507 | //BIFPLR3_0_PCIE_LINK_CNTL3 |
21508 | #define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
21509 | #define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
21510 | #define BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
21511 | #define BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
21512 | #define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
21513 | #define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
21514 | #define BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
21515 | #define BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
21516 | //BIFPLR3_0_PCIE_LANE_ERROR_STATUS |
21517 | #define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
21518 | #define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
21519 | #define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
21520 | #define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
21521 | //BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL |
21522 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21523 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21524 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21525 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21526 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21527 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21528 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21529 | #define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21530 | //BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL |
21531 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21532 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21533 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21534 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21535 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21536 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21537 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21538 | #define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21539 | //BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL |
21540 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21541 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21542 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21543 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21544 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21545 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21546 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21547 | #define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21548 | //BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL |
21549 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21550 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21551 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21552 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21553 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21554 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21555 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21556 | #define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21557 | //BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL |
21558 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21559 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21560 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21561 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21562 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21563 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21564 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21565 | #define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21566 | //BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL |
21567 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21568 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21569 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21570 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21571 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21572 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21573 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21574 | #define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21575 | //BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL |
21576 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21577 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21578 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21579 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21580 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21581 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21582 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21583 | #define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21584 | //BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL |
21585 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21586 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21587 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21588 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21589 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21590 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21591 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21592 | #define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21593 | //BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL |
21594 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21595 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21596 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21597 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21598 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21599 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21600 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21601 | #define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21602 | //BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL |
21603 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21604 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21605 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21606 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21607 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21608 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21609 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21610 | #define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21611 | //BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL |
21612 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21613 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21614 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21615 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21616 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21617 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21618 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21619 | #define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21620 | //BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL |
21621 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21622 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21623 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21624 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21625 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21626 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21627 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21628 | #define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21629 | //BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL |
21630 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21631 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21632 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21633 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21634 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21635 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21636 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21637 | #define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21638 | //BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL |
21639 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21640 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21641 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21642 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21643 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21644 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21645 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21646 | #define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21647 | //BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL |
21648 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21649 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21650 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21651 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21652 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21653 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21654 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21655 | #define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21656 | //BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL |
21657 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
21658 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
21659 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
21660 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
21661 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
21662 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
21663 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
21664 | #define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
21665 | //BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST |
21666 | #define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21667 | #define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21668 | #define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21669 | #define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21670 | #define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21671 | #define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21672 | //BIFPLR3_0_PCIE_ACS_CAP |
21673 | #define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
21674 | #define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
21675 | #define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
21676 | #define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
21677 | #define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
21678 | #define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
21679 | #define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
21680 | #define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
21681 | #define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
21682 | #define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
21683 | #define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
21684 | #define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
21685 | #define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
21686 | #define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
21687 | #define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
21688 | #define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
21689 | //BIFPLR3_0_PCIE_ACS_CNTL |
21690 | #define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
21691 | #define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
21692 | #define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
21693 | #define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
21694 | #define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
21695 | #define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
21696 | #define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
21697 | #define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
21698 | #define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
21699 | #define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
21700 | #define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
21701 | #define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
21702 | #define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
21703 | #define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
21704 | //BIFPLR3_0_PCIE_MC_ENH_CAP_LIST |
21705 | #define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21706 | #define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21707 | #define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21708 | #define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21709 | #define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21710 | #define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21711 | //BIFPLR3_0_PCIE_MC_CAP |
21712 | #define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
21713 | #define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
21714 | #define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
21715 | #define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
21716 | //BIFPLR3_0_PCIE_MC_CNTL |
21717 | #define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
21718 | #define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
21719 | #define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
21720 | #define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
21721 | //BIFPLR3_0_PCIE_MC_ADDR0 |
21722 | #define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
21723 | #define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
21724 | #define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
21725 | #define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
21726 | //BIFPLR3_0_PCIE_MC_ADDR1 |
21727 | #define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
21728 | #define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
21729 | //BIFPLR3_0_PCIE_MC_RCV0 |
21730 | #define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
21731 | #define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
21732 | //BIFPLR3_0_PCIE_MC_RCV1 |
21733 | #define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
21734 | #define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
21735 | //BIFPLR3_0_PCIE_MC_BLOCK_ALL0 |
21736 | #define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
21737 | #define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
21738 | //BIFPLR3_0_PCIE_MC_BLOCK_ALL1 |
21739 | #define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
21740 | #define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
21741 | //BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
21742 | #define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
21743 | #define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
21744 | //BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
21745 | #define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
21746 | #define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
21747 | //BIFPLR3_0_PCIE_MC_OVERLAY_BAR0 |
21748 | #define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
21749 | #define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
21750 | #define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
21751 | #define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
21752 | //BIFPLR3_0_PCIE_MC_OVERLAY_BAR1 |
21753 | #define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
21754 | #define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
21755 | //BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST |
21756 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
21757 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
21758 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21759 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21760 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21761 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21762 | //BIFPLR3_0_PCIE_L1_PM_SUB_CAP |
21763 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
21764 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
21765 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
21766 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
21767 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
21768 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
21769 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
21770 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
21771 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
21772 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
21773 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
21774 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
21775 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
21776 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
21777 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
21778 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
21779 | //BIFPLR3_0_PCIE_L1_PM_SUB_CNTL |
21780 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
21781 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
21782 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
21783 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
21784 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
21785 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
21786 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
21787 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
21788 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
21789 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
21790 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
21791 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
21792 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
21793 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
21794 | //BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 |
21795 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
21796 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
21797 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
21798 | #define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
21799 | //BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST |
21800 | #define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21801 | #define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21802 | #define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21803 | #define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21804 | #define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21805 | #define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21806 | //BIFPLR3_0_PCIE_DPC_CAP_LIST |
21807 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
21808 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
21809 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
21810 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
21811 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
21812 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
21813 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
21814 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
21815 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
21816 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
21817 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
21818 | #define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
21819 | //BIFPLR3_0_PCIE_DPC_CNTL |
21820 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
21821 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
21822 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
21823 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
21824 | #define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
21825 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
21826 | #define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
21827 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
21828 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
21829 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
21830 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
21831 | #define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
21832 | #define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
21833 | #define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
21834 | //BIFPLR3_0_PCIE_DPC_STATUS |
21835 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
21836 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
21837 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
21838 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
21839 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
21840 | #define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
21841 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
21842 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
21843 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
21844 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
21845 | #define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
21846 | #define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
21847 | //BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID |
21848 | #define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
21849 | #define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
21850 | //BIFPLR3_0_PCIE_RP_PIO_STATUS |
21851 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
21852 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
21853 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
21854 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
21855 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
21856 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
21857 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
21858 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
21859 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
21860 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
21861 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
21862 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
21863 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
21864 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
21865 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
21866 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
21867 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
21868 | #define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
21869 | //BIFPLR3_0_PCIE_RP_PIO_MASK |
21870 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
21871 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
21872 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
21873 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
21874 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
21875 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
21876 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
21877 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
21878 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
21879 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
21880 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
21881 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
21882 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
21883 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
21884 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
21885 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
21886 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
21887 | #define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
21888 | //BIFPLR3_0_PCIE_RP_PIO_SEVERITY |
21889 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
21890 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
21891 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
21892 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
21893 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
21894 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
21895 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
21896 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
21897 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
21898 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
21899 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
21900 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
21901 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
21902 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
21903 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
21904 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
21905 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
21906 | #define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
21907 | //BIFPLR3_0_PCIE_RP_PIO_SYSERROR |
21908 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
21909 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
21910 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
21911 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
21912 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
21913 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
21914 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
21915 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
21916 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
21917 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
21918 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
21919 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
21920 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
21921 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
21922 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
21923 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
21924 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
21925 | #define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
21926 | //BIFPLR3_0_PCIE_RP_PIO_EXCEPTION |
21927 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
21928 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
21929 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
21930 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
21931 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
21932 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
21933 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
21934 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
21935 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
21936 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
21937 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
21938 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
21939 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
21940 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
21941 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
21942 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
21943 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
21944 | #define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
21945 | //BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 |
21946 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
21947 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
21948 | //BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 |
21949 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
21950 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
21951 | //BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 |
21952 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
21953 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
21954 | //BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 |
21955 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
21956 | #define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
21957 | //BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG |
21958 | #define BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
21959 | #define BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
21960 | //BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 |
21961 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
21962 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
21963 | //BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 |
21964 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
21965 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
21966 | //BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 |
21967 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
21968 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
21969 | //BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 |
21970 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
21971 | #define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
21972 | //BIFPLR3_0_PCIE_ESM_CAP_LIST |
21973 | #define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
21974 | #define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
21975 | #define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21976 | #define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21977 | #define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21978 | #define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21979 | //BIFPLR3_0_PCIE_ESM_HEADER_1 |
21980 | #define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
21981 | #define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
21982 | #define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
21983 | #define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
21984 | #define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
21985 | #define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
21986 | //BIFPLR3_0_PCIE_ESM_HEADER_2 |
21987 | #define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
21988 | #define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
21989 | //BIFPLR3_0_PCIE_ESM_STATUS |
21990 | #define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
21991 | #define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
21992 | #define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
21993 | #define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
21994 | //BIFPLR3_0_PCIE_ESM_CTRL |
21995 | #define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
21996 | #define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
21997 | #define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
21998 | #define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
21999 | #define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
22000 | #define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
22001 | //BIFPLR3_0_PCIE_ESM_CAP_1 |
22002 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
22003 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
22004 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
22005 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
22006 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
22007 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
22008 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
22009 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
22010 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
22011 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
22012 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
22013 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
22014 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
22015 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
22016 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
22017 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
22018 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
22019 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
22020 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
22021 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
22022 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
22023 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
22024 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
22025 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
22026 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
22027 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
22028 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
22029 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
22030 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
22031 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
22032 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
22033 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
22034 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
22035 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
22036 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
22037 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
22038 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
22039 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
22040 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
22041 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
22042 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
22043 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
22044 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
22045 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
22046 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
22047 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
22048 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
22049 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
22050 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
22051 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
22052 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
22053 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
22054 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
22055 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
22056 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
22057 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
22058 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
22059 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
22060 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
22061 | #define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
22062 | //BIFPLR3_0_PCIE_ESM_CAP_2 |
22063 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
22064 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
22065 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
22066 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
22067 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
22068 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
22069 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
22070 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
22071 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
22072 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
22073 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
22074 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
22075 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
22076 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
22077 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
22078 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
22079 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
22080 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
22081 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
22082 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
22083 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
22084 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
22085 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
22086 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
22087 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
22088 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
22089 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
22090 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
22091 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
22092 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
22093 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
22094 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
22095 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
22096 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
22097 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
22098 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
22099 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
22100 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
22101 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
22102 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
22103 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
22104 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
22105 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
22106 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
22107 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
22108 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
22109 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
22110 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
22111 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
22112 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
22113 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
22114 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
22115 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
22116 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
22117 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
22118 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
22119 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
22120 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
22121 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
22122 | #define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
22123 | //BIFPLR3_0_PCIE_ESM_CAP_3 |
22124 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
22125 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
22126 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
22127 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
22128 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
22129 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
22130 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
22131 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
22132 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
22133 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
22134 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
22135 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
22136 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
22137 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
22138 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
22139 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
22140 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
22141 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
22142 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
22143 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
22144 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
22145 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
22146 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
22147 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
22148 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
22149 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
22150 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
22151 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
22152 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
22153 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
22154 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
22155 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
22156 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
22157 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
22158 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
22159 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
22160 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
22161 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
22162 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
22163 | #define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
22164 | //BIFPLR3_0_PCIE_ESM_CAP_4 |
22165 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
22166 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
22167 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
22168 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
22169 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
22170 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
22171 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
22172 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
22173 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
22174 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
22175 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
22176 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
22177 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
22178 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
22179 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
22180 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
22181 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
22182 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
22183 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
22184 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
22185 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
22186 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
22187 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
22188 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
22189 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
22190 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
22191 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
22192 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
22193 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
22194 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
22195 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
22196 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
22197 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
22198 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
22199 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
22200 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
22201 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
22202 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
22203 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
22204 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
22205 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
22206 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
22207 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
22208 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
22209 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
22210 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
22211 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
22212 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
22213 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
22214 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
22215 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
22216 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
22217 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
22218 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
22219 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
22220 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
22221 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
22222 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
22223 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
22224 | #define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
22225 | //BIFPLR3_0_PCIE_ESM_CAP_5 |
22226 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
22227 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
22228 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
22229 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
22230 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
22231 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
22232 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
22233 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
22234 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
22235 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
22236 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
22237 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
22238 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
22239 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
22240 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
22241 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
22242 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
22243 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
22244 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
22245 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
22246 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
22247 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
22248 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
22249 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
22250 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
22251 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
22252 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
22253 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
22254 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
22255 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
22256 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
22257 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
22258 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
22259 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
22260 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
22261 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
22262 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
22263 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
22264 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
22265 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
22266 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
22267 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
22268 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
22269 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
22270 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
22271 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
22272 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
22273 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
22274 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
22275 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
22276 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
22277 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
22278 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
22279 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
22280 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
22281 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
22282 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
22283 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
22284 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
22285 | #define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
22286 | //BIFPLR3_0_PCIE_ESM_CAP_6 |
22287 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
22288 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
22289 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
22290 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
22291 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
22292 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
22293 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
22294 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
22295 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
22296 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
22297 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
22298 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
22299 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
22300 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
22301 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
22302 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
22303 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
22304 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
22305 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
22306 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
22307 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
22308 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
22309 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
22310 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
22311 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
22312 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
22313 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
22314 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
22315 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
22316 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
22317 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
22318 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
22319 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
22320 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
22321 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
22322 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
22323 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
22324 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
22325 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
22326 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
22327 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
22328 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
22329 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
22330 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
22331 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
22332 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
22333 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
22334 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
22335 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
22336 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
22337 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
22338 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
22339 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
22340 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
22341 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
22342 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
22343 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
22344 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
22345 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
22346 | #define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
22347 | //BIFPLR3_0_PCIE_ESM_CAP_7 |
22348 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
22349 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
22350 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
22351 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
22352 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
22353 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
22354 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
22355 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
22356 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
22357 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
22358 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
22359 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
22360 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
22361 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
22362 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
22363 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
22364 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
22365 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
22366 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
22367 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
22368 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
22369 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
22370 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
22371 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
22372 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
22373 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
22374 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
22375 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
22376 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
22377 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
22378 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
22379 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
22380 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
22381 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
22382 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
22383 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
22384 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
22385 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
22386 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
22387 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
22388 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
22389 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
22390 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
22391 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
22392 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
22393 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
22394 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
22395 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
22396 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
22397 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
22398 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
22399 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
22400 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
22401 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
22402 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
22403 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
22404 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
22405 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
22406 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
22407 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
22408 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
22409 | #define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
22410 | |
22411 | |
22412 | // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
22413 | //BIFPLR4_0_VENDOR_ID |
22414 | #define BIFPLR4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
22415 | #define BIFPLR4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
22416 | //BIFPLR4_0_DEVICE_ID |
22417 | #define BIFPLR4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
22418 | #define BIFPLR4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
22419 | //BIFPLR4_0_COMMAND |
22420 | #define BIFPLR4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
22421 | #define BIFPLR4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
22422 | #define BIFPLR4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
22423 | #define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
22424 | #define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
22425 | #define BIFPLR4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
22426 | #define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
22427 | #define BIFPLR4_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
22428 | #define BIFPLR4_0_COMMAND__SERR_EN__SHIFT 0x8 |
22429 | #define BIFPLR4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
22430 | #define BIFPLR4_0_COMMAND__INT_DIS__SHIFT 0xa |
22431 | #define BIFPLR4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
22432 | #define BIFPLR4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
22433 | #define BIFPLR4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
22434 | #define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
22435 | #define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
22436 | #define BIFPLR4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
22437 | #define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
22438 | #define BIFPLR4_0_COMMAND__AD_STEPPING_MASK 0x0080L |
22439 | #define BIFPLR4_0_COMMAND__SERR_EN_MASK 0x0100L |
22440 | #define BIFPLR4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
22441 | #define BIFPLR4_0_COMMAND__INT_DIS_MASK 0x0400L |
22442 | //BIFPLR4_0_STATUS |
22443 | #define BIFPLR4_0_STATUS__INT_STATUS__SHIFT 0x3 |
22444 | #define BIFPLR4_0_STATUS__CAP_LIST__SHIFT 0x4 |
22445 | #define BIFPLR4_0_STATUS__PCI_66_EN__SHIFT 0x5 |
22446 | #define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
22447 | #define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
22448 | #define BIFPLR4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
22449 | #define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
22450 | #define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
22451 | #define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
22452 | #define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
22453 | #define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
22454 | #define BIFPLR4_0_STATUS__INT_STATUS_MASK 0x0008L |
22455 | #define BIFPLR4_0_STATUS__CAP_LIST_MASK 0x0010L |
22456 | #define BIFPLR4_0_STATUS__PCI_66_EN_MASK 0x0020L |
22457 | #define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
22458 | #define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
22459 | #define BIFPLR4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
22460 | #define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
22461 | #define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
22462 | #define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
22463 | #define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
22464 | #define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
22465 | //BIFPLR4_0_REVISION_ID |
22466 | #define BIFPLR4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
22467 | #define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
22468 | #define BIFPLR4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
22469 | #define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
22470 | //BIFPLR4_0_PROG_INTERFACE |
22471 | #define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
22472 | #define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
22473 | //BIFPLR4_0_SUB_CLASS |
22474 | #define BIFPLR4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
22475 | #define BIFPLR4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
22476 | //BIFPLR4_0_BASE_CLASS |
22477 | #define BIFPLR4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
22478 | #define BIFPLR4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
22479 | //BIFPLR4_0_CACHE_LINE |
22480 | #define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
22481 | #define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
22482 | //BIFPLR4_0_LATENCY |
22483 | #define BIFPLR4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
22484 | #define BIFPLR4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
22485 | //BIFPLR4_0_HEADER |
22486 | #define BIFPLR4_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
22487 | #define BIFPLR4_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
22488 | #define BIFPLR4_0_HEADER__HEADER_TYPE_MASK 0x7FL |
22489 | #define BIFPLR4_0_HEADER__DEVICE_TYPE_MASK 0x80L |
22490 | //BIFPLR4_0_BIST |
22491 | #define BIFPLR4_0_BIST__BIST_COMP__SHIFT 0x0 |
22492 | #define BIFPLR4_0_BIST__BIST_STRT__SHIFT 0x6 |
22493 | #define BIFPLR4_0_BIST__BIST_CAP__SHIFT 0x7 |
22494 | #define BIFPLR4_0_BIST__BIST_COMP_MASK 0x0FL |
22495 | #define BIFPLR4_0_BIST__BIST_STRT_MASK 0x40L |
22496 | #define BIFPLR4_0_BIST__BIST_CAP_MASK 0x80L |
22497 | //BIFPLR4_0_SUB_BUS_NUMBER_LATENCY |
22498 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
22499 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
22500 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
22501 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
22502 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
22503 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
22504 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
22505 | #define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
22506 | //BIFPLR4_0_IO_BASE_LIMIT |
22507 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
22508 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
22509 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
22510 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
22511 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
22512 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
22513 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
22514 | #define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
22515 | //BIFPLR4_0_SECONDARY_STATUS |
22516 | #define BIFPLR4_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
22517 | #define BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
22518 | #define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
22519 | #define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
22520 | #define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
22521 | #define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
22522 | #define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
22523 | #define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
22524 | #define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
22525 | #define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
22526 | #define BIFPLR4_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
22527 | #define BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
22528 | #define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
22529 | #define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
22530 | #define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
22531 | #define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
22532 | #define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
22533 | #define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
22534 | #define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
22535 | #define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
22536 | //BIFPLR4_0_MEM_BASE_LIMIT |
22537 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
22538 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
22539 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
22540 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
22541 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
22542 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
22543 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
22544 | #define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
22545 | //BIFPLR4_0_PREF_BASE_LIMIT |
22546 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
22547 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
22548 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
22549 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
22550 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
22551 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
22552 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
22553 | #define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
22554 | //BIFPLR4_0_PREF_BASE_UPPER |
22555 | #define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
22556 | #define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
22557 | //BIFPLR4_0_PREF_LIMIT_UPPER |
22558 | #define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
22559 | #define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
22560 | //BIFPLR4_0_IO_BASE_LIMIT_HI |
22561 | #define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
22562 | #define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
22563 | #define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
22564 | #define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
22565 | //BIFPLR4_0_CAP_PTR |
22566 | #define BIFPLR4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
22567 | #define BIFPLR4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
22568 | //BIFPLR4_0_INTERRUPT_LINE |
22569 | #define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
22570 | #define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
22571 | //BIFPLR4_0_INTERRUPT_PIN |
22572 | #define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
22573 | #define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
22574 | //BIFPLR4_0_IRQ_BRIDGE_CNTL |
22575 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
22576 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
22577 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
22578 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
22579 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
22580 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
22581 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
22582 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
22583 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
22584 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
22585 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
22586 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
22587 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
22588 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
22589 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
22590 | #define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
22591 | //BIFPLR4_0_EXT_BRIDGE_CNTL |
22592 | #define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
22593 | #define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
22594 | //BIFPLR4_0_PMI_CAP_LIST |
22595 | #define BIFPLR4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
22596 | #define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
22597 | #define BIFPLR4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
22598 | #define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
22599 | //BIFPLR4_0_PMI_CAP |
22600 | #define BIFPLR4_0_PMI_CAP__VERSION__SHIFT 0x0 |
22601 | #define BIFPLR4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
22602 | #define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
22603 | #define BIFPLR4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
22604 | #define BIFPLR4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
22605 | #define BIFPLR4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
22606 | #define BIFPLR4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
22607 | #define BIFPLR4_0_PMI_CAP__VERSION_MASK 0x0007L |
22608 | #define BIFPLR4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
22609 | #define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
22610 | #define BIFPLR4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
22611 | #define BIFPLR4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
22612 | #define BIFPLR4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
22613 | #define BIFPLR4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
22614 | //BIFPLR4_0_PMI_STATUS_CNTL |
22615 | #define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
22616 | #define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
22617 | #define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
22618 | #define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
22619 | #define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
22620 | #define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
22621 | #define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
22622 | #define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
22623 | #define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
22624 | #define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
22625 | #define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
22626 | #define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
22627 | #define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
22628 | #define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
22629 | #define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
22630 | #define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
22631 | #define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
22632 | #define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
22633 | //BIFPLR4_0_PCIE_CAP_LIST |
22634 | #define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
22635 | #define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
22636 | #define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
22637 | #define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
22638 | //BIFPLR4_0_PCIE_CAP |
22639 | #define BIFPLR4_0_PCIE_CAP__VERSION__SHIFT 0x0 |
22640 | #define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
22641 | #define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
22642 | #define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
22643 | #define BIFPLR4_0_PCIE_CAP__VERSION_MASK 0x000FL |
22644 | #define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
22645 | #define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
22646 | #define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
22647 | //BIFPLR4_0_DEVICE_CAP |
22648 | #define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
22649 | #define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
22650 | #define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
22651 | #define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
22652 | #define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
22653 | #define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
22654 | #define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
22655 | #define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
22656 | #define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
22657 | #define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
22658 | #define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
22659 | #define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
22660 | #define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
22661 | #define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
22662 | #define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
22663 | #define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
22664 | #define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
22665 | #define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
22666 | //BIFPLR4_0_DEVICE_CNTL |
22667 | #define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
22668 | #define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
22669 | #define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
22670 | #define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
22671 | #define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
22672 | #define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
22673 | #define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
22674 | #define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
22675 | #define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
22676 | #define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
22677 | #define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
22678 | #define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
22679 | #define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
22680 | #define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
22681 | #define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
22682 | #define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
22683 | #define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
22684 | #define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
22685 | #define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
22686 | #define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
22687 | #define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
22688 | #define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
22689 | #define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
22690 | #define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
22691 | //BIFPLR4_0_DEVICE_STATUS |
22692 | #define BIFPLR4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
22693 | #define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
22694 | #define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
22695 | #define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
22696 | #define BIFPLR4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
22697 | #define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
22698 | #define BIFPLR4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
22699 | #define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
22700 | #define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
22701 | #define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
22702 | #define BIFPLR4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
22703 | #define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
22704 | //BIFPLR4_0_LINK_CAP |
22705 | #define BIFPLR4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
22706 | #define BIFPLR4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
22707 | #define BIFPLR4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
22708 | #define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
22709 | #define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
22710 | #define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
22711 | #define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
22712 | #define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
22713 | #define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
22714 | #define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
22715 | #define BIFPLR4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
22716 | #define BIFPLR4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
22717 | #define BIFPLR4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
22718 | #define BIFPLR4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
22719 | #define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
22720 | #define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
22721 | #define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
22722 | #define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
22723 | #define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
22724 | #define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
22725 | #define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
22726 | #define BIFPLR4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
22727 | //BIFPLR4_0_LINK_CNTL |
22728 | #define BIFPLR4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
22729 | #define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
22730 | #define BIFPLR4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
22731 | #define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
22732 | #define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
22733 | #define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
22734 | #define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
22735 | #define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
22736 | #define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
22737 | #define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
22738 | #define BIFPLR4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
22739 | #define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
22740 | #define BIFPLR4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
22741 | #define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
22742 | #define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
22743 | #define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
22744 | #define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
22745 | #define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
22746 | #define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
22747 | #define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
22748 | //BIFPLR4_0_LINK_STATUS |
22749 | #define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
22750 | #define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
22751 | #define BIFPLR4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
22752 | #define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
22753 | #define BIFPLR4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
22754 | #define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
22755 | #define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
22756 | #define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
22757 | #define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
22758 | #define BIFPLR4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
22759 | #define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
22760 | #define BIFPLR4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
22761 | #define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
22762 | #define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
22763 | //BIFPLR4_0_SLOT_CAP |
22764 | #define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
22765 | #define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
22766 | #define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
22767 | #define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
22768 | #define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
22769 | #define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
22770 | #define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
22771 | #define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
22772 | #define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
22773 | #define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
22774 | #define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
22775 | #define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
22776 | #define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
22777 | #define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
22778 | #define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
22779 | #define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
22780 | #define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
22781 | #define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
22782 | #define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
22783 | #define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
22784 | #define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
22785 | #define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
22786 | #define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
22787 | #define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
22788 | //BIFPLR4_0_SLOT_CNTL |
22789 | #define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
22790 | #define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
22791 | #define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
22792 | #define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
22793 | #define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
22794 | #define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
22795 | #define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
22796 | #define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
22797 | #define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
22798 | #define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
22799 | #define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
22800 | #define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
22801 | #define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
22802 | #define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
22803 | #define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
22804 | #define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
22805 | #define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
22806 | #define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
22807 | #define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
22808 | #define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
22809 | #define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
22810 | #define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
22811 | #define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
22812 | #define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
22813 | //BIFPLR4_0_SLOT_STATUS |
22814 | #define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
22815 | #define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
22816 | #define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
22817 | #define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
22818 | #define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
22819 | #define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
22820 | #define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
22821 | #define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
22822 | #define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
22823 | #define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
22824 | #define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
22825 | #define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
22826 | #define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
22827 | #define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
22828 | #define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
22829 | #define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
22830 | #define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
22831 | #define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
22832 | //BIFPLR4_0_ROOT_CNTL |
22833 | #define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
22834 | #define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
22835 | #define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
22836 | #define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
22837 | #define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
22838 | #define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
22839 | #define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
22840 | #define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
22841 | #define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
22842 | #define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
22843 | //BIFPLR4_0_ROOT_CAP |
22844 | #define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
22845 | #define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
22846 | //BIFPLR4_0_ROOT_STATUS |
22847 | #define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
22848 | #define BIFPLR4_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
22849 | #define BIFPLR4_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
22850 | #define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
22851 | #define BIFPLR4_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
22852 | #define BIFPLR4_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
22853 | //BIFPLR4_0_DEVICE_CAP2 |
22854 | #define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
22855 | #define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
22856 | #define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
22857 | #define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
22858 | #define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
22859 | #define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
22860 | #define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
22861 | #define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
22862 | #define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
22863 | #define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
22864 | #define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
22865 | #define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
22866 | #define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
22867 | #define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
22868 | #define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
22869 | #define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
22870 | #define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
22871 | #define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
22872 | #define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
22873 | #define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
22874 | #define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
22875 | #define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
22876 | #define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
22877 | #define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
22878 | #define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
22879 | #define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
22880 | #define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
22881 | #define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
22882 | //BIFPLR4_0_DEVICE_CNTL2 |
22883 | #define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
22884 | #define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
22885 | #define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
22886 | #define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
22887 | #define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
22888 | #define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
22889 | #define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
22890 | #define BIFPLR4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
22891 | #define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
22892 | #define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
22893 | #define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
22894 | #define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
22895 | #define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
22896 | #define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
22897 | #define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
22898 | #define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
22899 | #define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
22900 | #define BIFPLR4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
22901 | #define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
22902 | #define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
22903 | //BIFPLR4_0_DEVICE_STATUS2 |
22904 | #define BIFPLR4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
22905 | #define BIFPLR4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
22906 | //BIFPLR4_0_LINK_CAP2 |
22907 | #define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
22908 | #define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
22909 | #define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
22910 | #define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
22911 | #define BIFPLR4_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
22912 | #define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
22913 | #define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
22914 | #define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
22915 | #define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
22916 | #define BIFPLR4_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
22917 | //BIFPLR4_0_LINK_CNTL2 |
22918 | #define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
22919 | #define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
22920 | #define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
22921 | #define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
22922 | #define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
22923 | #define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
22924 | #define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
22925 | #define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
22926 | #define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
22927 | #define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
22928 | #define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
22929 | #define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
22930 | #define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
22931 | #define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
22932 | #define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
22933 | #define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
22934 | //BIFPLR4_0_LINK_STATUS2 |
22935 | #define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
22936 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
22937 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
22938 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
22939 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
22940 | #define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
22941 | #define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
22942 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
22943 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
22944 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
22945 | #define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
22946 | #define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
22947 | //BIFPLR4_0_SLOT_CAP2 |
22948 | #define BIFPLR4_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
22949 | #define BIFPLR4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
22950 | //BIFPLR4_0_SLOT_CNTL2 |
22951 | #define BIFPLR4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
22952 | #define BIFPLR4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
22953 | //BIFPLR4_0_SLOT_STATUS2 |
22954 | #define BIFPLR4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
22955 | #define BIFPLR4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
22956 | //BIFPLR4_0_MSI_CAP_LIST |
22957 | #define BIFPLR4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
22958 | #define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
22959 | #define BIFPLR4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
22960 | #define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
22961 | //BIFPLR4_0_MSI_MSG_CNTL |
22962 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
22963 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
22964 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
22965 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
22966 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
22967 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
22968 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
22969 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
22970 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
22971 | #define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
22972 | //BIFPLR4_0_MSI_MSG_ADDR_LO |
22973 | #define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
22974 | #define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
22975 | //BIFPLR4_0_MSI_MSG_ADDR_HI |
22976 | #define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
22977 | #define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
22978 | //BIFPLR4_0_MSI_MSG_DATA |
22979 | #define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
22980 | #define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
22981 | //BIFPLR4_0_MSI_MSG_DATA_64 |
22982 | #define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
22983 | #define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
22984 | //BIFPLR4_0_SSID_CAP_LIST |
22985 | #define BIFPLR4_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
22986 | #define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
22987 | #define BIFPLR4_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
22988 | #define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
22989 | //BIFPLR4_0_SSID_CAP |
22990 | #define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
22991 | #define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
22992 | #define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
22993 | #define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
22994 | //BIFPLR4_0_MSI_MAP_CAP_LIST |
22995 | #define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
22996 | #define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
22997 | #define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
22998 | #define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
22999 | //BIFPLR4_0_MSI_MAP_CAP |
23000 | #define BIFPLR4_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
23001 | #define BIFPLR4_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
23002 | #define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
23003 | #define BIFPLR4_0_MSI_MAP_CAP__EN_MASK 0x0001L |
23004 | #define BIFPLR4_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
23005 | #define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
23006 | //BIFPLR4_0_MSI_MAP_ADDR_LO |
23007 | #define BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
23008 | #define BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
23009 | //BIFPLR4_0_MSI_MAP_ADDR_HI |
23010 | #define BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
23011 | #define BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
23012 | //BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
23013 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23014 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23015 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23016 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23017 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23018 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23019 | //BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR |
23020 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
23021 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
23022 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
23023 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
23024 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
23025 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
23026 | //BIFPLR4_0_PCIE_VENDOR_SPECIFIC1 |
23027 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
23028 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
23029 | //BIFPLR4_0_PCIE_VENDOR_SPECIFIC2 |
23030 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
23031 | #define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
23032 | //BIFPLR4_0_PCIE_VC_ENH_CAP_LIST |
23033 | #define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23034 | #define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23035 | #define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23036 | #define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23037 | #define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23038 | #define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23039 | //BIFPLR4_0_PCIE_PORT_VC_CAP_REG1 |
23040 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
23041 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
23042 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
23043 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
23044 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
23045 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
23046 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
23047 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
23048 | //BIFPLR4_0_PCIE_PORT_VC_CAP_REG2 |
23049 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
23050 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
23051 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
23052 | #define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
23053 | //BIFPLR4_0_PCIE_PORT_VC_CNTL |
23054 | #define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
23055 | #define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
23056 | #define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
23057 | #define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
23058 | //BIFPLR4_0_PCIE_PORT_VC_STATUS |
23059 | #define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
23060 | #define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
23061 | //BIFPLR4_0_PCIE_VC0_RESOURCE_CAP |
23062 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
23063 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
23064 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
23065 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
23066 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
23067 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
23068 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
23069 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
23070 | //BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL |
23071 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
23072 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
23073 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
23074 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
23075 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
23076 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
23077 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
23078 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
23079 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
23080 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
23081 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
23082 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
23083 | //BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS |
23084 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
23085 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
23086 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
23087 | #define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
23088 | //BIFPLR4_0_PCIE_VC1_RESOURCE_CAP |
23089 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
23090 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
23091 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
23092 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
23093 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
23094 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
23095 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
23096 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
23097 | //BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL |
23098 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
23099 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
23100 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
23101 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
23102 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
23103 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
23104 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
23105 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
23106 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
23107 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
23108 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
23109 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
23110 | //BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS |
23111 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
23112 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
23113 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
23114 | #define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
23115 | //BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
23116 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23117 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23118 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23119 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23120 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23121 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23122 | //BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 |
23123 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
23124 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
23125 | //BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 |
23126 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
23127 | #define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
23128 | //BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
23129 | #define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23130 | #define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23131 | #define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23132 | #define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23133 | #define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23134 | #define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23135 | //BIFPLR4_0_PCIE_UNCORR_ERR_STATUS |
23136 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
23137 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
23138 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
23139 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
23140 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
23141 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
23142 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
23143 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
23144 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
23145 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
23146 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
23147 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
23148 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
23149 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
23150 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
23151 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
23152 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
23153 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
23154 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
23155 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
23156 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
23157 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
23158 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
23159 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
23160 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
23161 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
23162 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
23163 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
23164 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
23165 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
23166 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
23167 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
23168 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
23169 | #define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
23170 | //BIFPLR4_0_PCIE_UNCORR_ERR_MASK |
23171 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
23172 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
23173 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
23174 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
23175 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
23176 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
23177 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
23178 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
23179 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
23180 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
23181 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
23182 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
23183 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
23184 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
23185 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
23186 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
23187 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
23188 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
23189 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
23190 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
23191 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
23192 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
23193 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
23194 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
23195 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
23196 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
23197 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
23198 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
23199 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
23200 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
23201 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
23202 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
23203 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
23204 | #define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
23205 | //BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY |
23206 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
23207 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
23208 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
23209 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
23210 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
23211 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
23212 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
23213 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
23214 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
23215 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
23216 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
23217 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
23218 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
23219 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
23220 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
23221 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
23222 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
23223 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
23224 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
23225 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
23226 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
23227 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
23228 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
23229 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
23230 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
23231 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
23232 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
23233 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
23234 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
23235 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
23236 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
23237 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
23238 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
23239 | #define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
23240 | //BIFPLR4_0_PCIE_CORR_ERR_STATUS |
23241 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
23242 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
23243 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
23244 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
23245 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
23246 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
23247 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
23248 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
23249 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
23250 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
23251 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
23252 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
23253 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
23254 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
23255 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
23256 | #define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
23257 | //BIFPLR4_0_PCIE_CORR_ERR_MASK |
23258 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
23259 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
23260 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
23261 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
23262 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
23263 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
23264 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
23265 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
23266 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
23267 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
23268 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
23269 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
23270 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
23271 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
23272 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
23273 | #define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
23274 | //BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL |
23275 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
23276 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
23277 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
23278 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
23279 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
23280 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
23281 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
23282 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
23283 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
23284 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
23285 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
23286 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
23287 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
23288 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
23289 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
23290 | #define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
23291 | //BIFPLR4_0_PCIE_HDR_LOG0 |
23292 | #define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
23293 | #define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
23294 | //BIFPLR4_0_PCIE_HDR_LOG1 |
23295 | #define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
23296 | #define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
23297 | //BIFPLR4_0_PCIE_HDR_LOG2 |
23298 | #define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
23299 | #define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
23300 | //BIFPLR4_0_PCIE_HDR_LOG3 |
23301 | #define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
23302 | #define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
23303 | //BIFPLR4_0_PCIE_ROOT_ERR_CMD |
23304 | #define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
23305 | #define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
23306 | #define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
23307 | #define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
23308 | #define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
23309 | #define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
23310 | //BIFPLR4_0_PCIE_ROOT_ERR_STATUS |
23311 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
23312 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
23313 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
23314 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
23315 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
23316 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
23317 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
23318 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
23319 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
23320 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
23321 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
23322 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
23323 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
23324 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
23325 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
23326 | #define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
23327 | //BIFPLR4_0_PCIE_ERR_SRC_ID |
23328 | #define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
23329 | #define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
23330 | #define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
23331 | #define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
23332 | //BIFPLR4_0_PCIE_TLP_PREFIX_LOG0 |
23333 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
23334 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
23335 | //BIFPLR4_0_PCIE_TLP_PREFIX_LOG1 |
23336 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
23337 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
23338 | //BIFPLR4_0_PCIE_TLP_PREFIX_LOG2 |
23339 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
23340 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
23341 | //BIFPLR4_0_PCIE_TLP_PREFIX_LOG3 |
23342 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
23343 | #define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
23344 | //BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST |
23345 | #define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23346 | #define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23347 | #define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23348 | #define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23349 | #define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23350 | #define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23351 | //BIFPLR4_0_PCIE_LINK_CNTL3 |
23352 | #define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
23353 | #define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
23354 | #define BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
23355 | #define BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
23356 | #define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
23357 | #define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
23358 | #define BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
23359 | #define BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
23360 | //BIFPLR4_0_PCIE_LANE_ERROR_STATUS |
23361 | #define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
23362 | #define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
23363 | #define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
23364 | #define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
23365 | //BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL |
23366 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23367 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23368 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23369 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23370 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23371 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23372 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23373 | #define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23374 | //BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL |
23375 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23376 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23377 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23378 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23379 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23380 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23381 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23382 | #define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23383 | //BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL |
23384 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23385 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23386 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23387 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23388 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23389 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23390 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23391 | #define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23392 | //BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL |
23393 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23394 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23395 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23396 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23397 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23398 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23399 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23400 | #define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23401 | //BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL |
23402 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23403 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23404 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23405 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23406 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23407 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23408 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23409 | #define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23410 | //BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL |
23411 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23412 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23413 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23414 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23415 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23416 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23417 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23418 | #define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23419 | //BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL |
23420 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23421 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23422 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23423 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23424 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23425 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23426 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23427 | #define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23428 | //BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL |
23429 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23430 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23431 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23432 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23433 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23434 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23435 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23436 | #define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23437 | //BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL |
23438 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23439 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23440 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23441 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23442 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23443 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23444 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23445 | #define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23446 | //BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL |
23447 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23448 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23449 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23450 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23451 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23452 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23453 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23454 | #define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23455 | //BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL |
23456 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23457 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23458 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23459 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23460 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23461 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23462 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23463 | #define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23464 | //BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL |
23465 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23466 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23467 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23468 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23469 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23470 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23471 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23472 | #define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23473 | //BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL |
23474 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23475 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23476 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23477 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23478 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23479 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23480 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23481 | #define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23482 | //BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL |
23483 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23484 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23485 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23486 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23487 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23488 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23489 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23490 | #define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23491 | //BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL |
23492 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23493 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23494 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23495 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23496 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23497 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23498 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23499 | #define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23500 | //BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL |
23501 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
23502 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
23503 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
23504 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
23505 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
23506 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
23507 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
23508 | #define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
23509 | //BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST |
23510 | #define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23511 | #define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23512 | #define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23513 | #define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23514 | #define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23515 | #define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23516 | //BIFPLR4_0_PCIE_ACS_CAP |
23517 | #define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
23518 | #define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
23519 | #define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
23520 | #define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
23521 | #define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
23522 | #define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
23523 | #define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
23524 | #define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
23525 | #define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
23526 | #define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
23527 | #define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
23528 | #define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
23529 | #define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
23530 | #define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
23531 | #define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
23532 | #define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
23533 | //BIFPLR4_0_PCIE_ACS_CNTL |
23534 | #define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
23535 | #define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
23536 | #define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
23537 | #define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
23538 | #define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
23539 | #define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
23540 | #define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
23541 | #define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
23542 | #define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
23543 | #define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
23544 | #define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
23545 | #define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
23546 | #define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
23547 | #define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
23548 | //BIFPLR4_0_PCIE_MC_ENH_CAP_LIST |
23549 | #define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23550 | #define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23551 | #define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23552 | #define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23553 | #define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23554 | #define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23555 | //BIFPLR4_0_PCIE_MC_CAP |
23556 | #define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
23557 | #define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
23558 | #define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
23559 | #define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
23560 | //BIFPLR4_0_PCIE_MC_CNTL |
23561 | #define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
23562 | #define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
23563 | #define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
23564 | #define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
23565 | //BIFPLR4_0_PCIE_MC_ADDR0 |
23566 | #define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
23567 | #define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
23568 | #define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
23569 | #define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
23570 | //BIFPLR4_0_PCIE_MC_ADDR1 |
23571 | #define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
23572 | #define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
23573 | //BIFPLR4_0_PCIE_MC_RCV0 |
23574 | #define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
23575 | #define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
23576 | //BIFPLR4_0_PCIE_MC_RCV1 |
23577 | #define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
23578 | #define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
23579 | //BIFPLR4_0_PCIE_MC_BLOCK_ALL0 |
23580 | #define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
23581 | #define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
23582 | //BIFPLR4_0_PCIE_MC_BLOCK_ALL1 |
23583 | #define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
23584 | #define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
23585 | //BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
23586 | #define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
23587 | #define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
23588 | //BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
23589 | #define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
23590 | #define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
23591 | //BIFPLR4_0_PCIE_MC_OVERLAY_BAR0 |
23592 | #define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
23593 | #define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
23594 | #define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
23595 | #define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
23596 | //BIFPLR4_0_PCIE_MC_OVERLAY_BAR1 |
23597 | #define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
23598 | #define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
23599 | //BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST |
23600 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
23601 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
23602 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23603 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23604 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23605 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23606 | //BIFPLR4_0_PCIE_L1_PM_SUB_CAP |
23607 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
23608 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
23609 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
23610 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
23611 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
23612 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
23613 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
23614 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
23615 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
23616 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
23617 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
23618 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
23619 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
23620 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
23621 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
23622 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
23623 | //BIFPLR4_0_PCIE_L1_PM_SUB_CNTL |
23624 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
23625 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
23626 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
23627 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
23628 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
23629 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
23630 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
23631 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
23632 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
23633 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
23634 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
23635 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
23636 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
23637 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
23638 | //BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 |
23639 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
23640 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
23641 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
23642 | #define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
23643 | //BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST |
23644 | #define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
23645 | #define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
23646 | #define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23647 | #define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23648 | #define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23649 | #define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23650 | //BIFPLR4_0_PCIE_DPC_CAP_LIST |
23651 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
23652 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
23653 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
23654 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
23655 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
23656 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
23657 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
23658 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
23659 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
23660 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
23661 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
23662 | #define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
23663 | //BIFPLR4_0_PCIE_DPC_CNTL |
23664 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
23665 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
23666 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
23667 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
23668 | #define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
23669 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
23670 | #define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
23671 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
23672 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
23673 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
23674 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
23675 | #define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
23676 | #define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
23677 | #define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
23678 | //BIFPLR4_0_PCIE_DPC_STATUS |
23679 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
23680 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
23681 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
23682 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
23683 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
23684 | #define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
23685 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
23686 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
23687 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
23688 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
23689 | #define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
23690 | #define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
23691 | //BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID |
23692 | #define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
23693 | #define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
23694 | //BIFPLR4_0_PCIE_RP_PIO_STATUS |
23695 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
23696 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
23697 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
23698 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
23699 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
23700 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
23701 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
23702 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
23703 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
23704 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
23705 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
23706 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
23707 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
23708 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
23709 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
23710 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
23711 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
23712 | #define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
23713 | //BIFPLR4_0_PCIE_RP_PIO_MASK |
23714 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
23715 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
23716 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
23717 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
23718 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
23719 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
23720 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
23721 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
23722 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
23723 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
23724 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
23725 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
23726 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
23727 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
23728 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
23729 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
23730 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
23731 | #define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
23732 | //BIFPLR4_0_PCIE_RP_PIO_SEVERITY |
23733 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
23734 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
23735 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
23736 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
23737 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
23738 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
23739 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
23740 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
23741 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
23742 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
23743 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
23744 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
23745 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
23746 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
23747 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
23748 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
23749 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
23750 | #define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
23751 | //BIFPLR4_0_PCIE_RP_PIO_SYSERROR |
23752 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
23753 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
23754 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
23755 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
23756 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
23757 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
23758 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
23759 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
23760 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
23761 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
23762 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
23763 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
23764 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
23765 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
23766 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
23767 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
23768 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
23769 | #define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
23770 | //BIFPLR4_0_PCIE_RP_PIO_EXCEPTION |
23771 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
23772 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
23773 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
23774 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
23775 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
23776 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
23777 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
23778 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
23779 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
23780 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
23781 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
23782 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
23783 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
23784 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
23785 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
23786 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
23787 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
23788 | #define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
23789 | //BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 |
23790 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
23791 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
23792 | //BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 |
23793 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
23794 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
23795 | //BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 |
23796 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
23797 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
23798 | //BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 |
23799 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
23800 | #define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
23801 | //BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG |
23802 | #define BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
23803 | #define BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
23804 | //BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 |
23805 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
23806 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
23807 | //BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 |
23808 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
23809 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
23810 | //BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 |
23811 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
23812 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
23813 | //BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 |
23814 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
23815 | #define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
23816 | //BIFPLR4_0_PCIE_ESM_CAP_LIST |
23817 | #define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
23818 | #define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
23819 | #define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
23820 | #define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
23821 | #define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
23822 | #define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
23823 | //BIFPLR4_0_PCIE_ESM_HEADER_1 |
23824 | #define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
23825 | #define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
23826 | #define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
23827 | #define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
23828 | #define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
23829 | #define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
23830 | //BIFPLR4_0_PCIE_ESM_HEADER_2 |
23831 | #define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
23832 | #define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
23833 | //BIFPLR4_0_PCIE_ESM_STATUS |
23834 | #define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
23835 | #define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
23836 | #define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
23837 | #define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
23838 | //BIFPLR4_0_PCIE_ESM_CTRL |
23839 | #define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
23840 | #define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
23841 | #define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
23842 | #define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
23843 | #define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
23844 | #define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
23845 | //BIFPLR4_0_PCIE_ESM_CAP_1 |
23846 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
23847 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
23848 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
23849 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
23850 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
23851 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
23852 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
23853 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
23854 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
23855 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
23856 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
23857 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
23858 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
23859 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
23860 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
23861 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
23862 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
23863 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
23864 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
23865 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
23866 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
23867 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
23868 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
23869 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
23870 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
23871 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
23872 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
23873 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
23874 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
23875 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
23876 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
23877 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
23878 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
23879 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
23880 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
23881 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
23882 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
23883 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
23884 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
23885 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
23886 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
23887 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
23888 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
23889 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
23890 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
23891 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
23892 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
23893 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
23894 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
23895 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
23896 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
23897 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
23898 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
23899 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
23900 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
23901 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
23902 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
23903 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
23904 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
23905 | #define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
23906 | //BIFPLR4_0_PCIE_ESM_CAP_2 |
23907 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
23908 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
23909 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
23910 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
23911 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
23912 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
23913 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
23914 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
23915 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
23916 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
23917 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
23918 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
23919 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
23920 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
23921 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
23922 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
23923 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
23924 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
23925 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
23926 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
23927 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
23928 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
23929 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
23930 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
23931 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
23932 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
23933 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
23934 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
23935 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
23936 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
23937 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
23938 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
23939 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
23940 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
23941 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
23942 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
23943 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
23944 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
23945 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
23946 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
23947 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
23948 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
23949 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
23950 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
23951 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
23952 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
23953 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
23954 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
23955 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
23956 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
23957 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
23958 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
23959 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
23960 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
23961 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
23962 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
23963 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
23964 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
23965 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
23966 | #define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
23967 | //BIFPLR4_0_PCIE_ESM_CAP_3 |
23968 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
23969 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
23970 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
23971 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
23972 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
23973 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
23974 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
23975 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
23976 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
23977 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
23978 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
23979 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
23980 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
23981 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
23982 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
23983 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
23984 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
23985 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
23986 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
23987 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
23988 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
23989 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
23990 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
23991 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
23992 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
23993 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
23994 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
23995 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
23996 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
23997 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
23998 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
23999 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
24000 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
24001 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
24002 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
24003 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
24004 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
24005 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
24006 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
24007 | #define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
24008 | //BIFPLR4_0_PCIE_ESM_CAP_4 |
24009 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
24010 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
24011 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
24012 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
24013 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
24014 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
24015 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
24016 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
24017 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
24018 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
24019 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
24020 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
24021 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
24022 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
24023 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
24024 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
24025 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
24026 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
24027 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
24028 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
24029 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
24030 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
24031 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
24032 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
24033 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
24034 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
24035 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
24036 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
24037 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
24038 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
24039 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
24040 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
24041 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
24042 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
24043 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
24044 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
24045 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
24046 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
24047 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
24048 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
24049 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
24050 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
24051 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
24052 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
24053 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
24054 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
24055 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
24056 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
24057 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
24058 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
24059 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
24060 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
24061 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
24062 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
24063 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
24064 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
24065 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
24066 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
24067 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
24068 | #define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
24069 | //BIFPLR4_0_PCIE_ESM_CAP_5 |
24070 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
24071 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
24072 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
24073 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
24074 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
24075 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
24076 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
24077 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
24078 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
24079 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
24080 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
24081 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
24082 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
24083 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
24084 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
24085 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
24086 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
24087 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
24088 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
24089 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
24090 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
24091 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
24092 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
24093 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
24094 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
24095 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
24096 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
24097 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
24098 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
24099 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
24100 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
24101 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
24102 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
24103 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
24104 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
24105 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
24106 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
24107 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
24108 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
24109 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
24110 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
24111 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
24112 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
24113 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
24114 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
24115 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
24116 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
24117 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
24118 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
24119 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
24120 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
24121 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
24122 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
24123 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
24124 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
24125 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
24126 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
24127 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
24128 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
24129 | #define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
24130 | //BIFPLR4_0_PCIE_ESM_CAP_6 |
24131 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
24132 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
24133 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
24134 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
24135 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
24136 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
24137 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
24138 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
24139 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
24140 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
24141 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
24142 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
24143 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
24144 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
24145 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
24146 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
24147 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
24148 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
24149 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
24150 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
24151 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
24152 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
24153 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
24154 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
24155 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
24156 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
24157 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
24158 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
24159 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
24160 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
24161 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
24162 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
24163 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
24164 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
24165 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
24166 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
24167 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
24168 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
24169 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
24170 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
24171 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
24172 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
24173 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
24174 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
24175 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
24176 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
24177 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
24178 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
24179 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
24180 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
24181 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
24182 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
24183 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
24184 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
24185 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
24186 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
24187 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
24188 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
24189 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
24190 | #define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
24191 | //BIFPLR4_0_PCIE_ESM_CAP_7 |
24192 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
24193 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
24194 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
24195 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
24196 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
24197 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
24198 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
24199 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
24200 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
24201 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
24202 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
24203 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
24204 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
24205 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
24206 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
24207 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
24208 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
24209 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
24210 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
24211 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
24212 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
24213 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
24214 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
24215 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
24216 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
24217 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
24218 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
24219 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
24220 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
24221 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
24222 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
24223 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
24224 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
24225 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
24226 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
24227 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
24228 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
24229 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
24230 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
24231 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
24232 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
24233 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
24234 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
24235 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
24236 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
24237 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
24238 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
24239 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
24240 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
24241 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
24242 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
24243 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
24244 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
24245 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
24246 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
24247 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
24248 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
24249 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
24250 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
24251 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
24252 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
24253 | #define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
24254 | |
24255 | |
24256 | // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
24257 | //BIFPLR5_0_VENDOR_ID |
24258 | #define BIFPLR5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
24259 | #define BIFPLR5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
24260 | //BIFPLR5_0_DEVICE_ID |
24261 | #define BIFPLR5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
24262 | #define BIFPLR5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
24263 | //BIFPLR5_0_COMMAND |
24264 | #define BIFPLR5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
24265 | #define BIFPLR5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
24266 | #define BIFPLR5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
24267 | #define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
24268 | #define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
24269 | #define BIFPLR5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
24270 | #define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
24271 | #define BIFPLR5_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
24272 | #define BIFPLR5_0_COMMAND__SERR_EN__SHIFT 0x8 |
24273 | #define BIFPLR5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
24274 | #define BIFPLR5_0_COMMAND__INT_DIS__SHIFT 0xa |
24275 | #define BIFPLR5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
24276 | #define BIFPLR5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
24277 | #define BIFPLR5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
24278 | #define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
24279 | #define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
24280 | #define BIFPLR5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
24281 | #define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
24282 | #define BIFPLR5_0_COMMAND__AD_STEPPING_MASK 0x0080L |
24283 | #define BIFPLR5_0_COMMAND__SERR_EN_MASK 0x0100L |
24284 | #define BIFPLR5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
24285 | #define BIFPLR5_0_COMMAND__INT_DIS_MASK 0x0400L |
24286 | //BIFPLR5_0_STATUS |
24287 | #define BIFPLR5_0_STATUS__INT_STATUS__SHIFT 0x3 |
24288 | #define BIFPLR5_0_STATUS__CAP_LIST__SHIFT 0x4 |
24289 | #define BIFPLR5_0_STATUS__PCI_66_EN__SHIFT 0x5 |
24290 | #define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
24291 | #define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
24292 | #define BIFPLR5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
24293 | #define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
24294 | #define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
24295 | #define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
24296 | #define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
24297 | #define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
24298 | #define BIFPLR5_0_STATUS__INT_STATUS_MASK 0x0008L |
24299 | #define BIFPLR5_0_STATUS__CAP_LIST_MASK 0x0010L |
24300 | #define BIFPLR5_0_STATUS__PCI_66_EN_MASK 0x0020L |
24301 | #define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
24302 | #define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
24303 | #define BIFPLR5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
24304 | #define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
24305 | #define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
24306 | #define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
24307 | #define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
24308 | #define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
24309 | //BIFPLR5_0_REVISION_ID |
24310 | #define BIFPLR5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
24311 | #define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
24312 | #define BIFPLR5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
24313 | #define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
24314 | //BIFPLR5_0_PROG_INTERFACE |
24315 | #define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
24316 | #define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
24317 | //BIFPLR5_0_SUB_CLASS |
24318 | #define BIFPLR5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
24319 | #define BIFPLR5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
24320 | //BIFPLR5_0_BASE_CLASS |
24321 | #define BIFPLR5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
24322 | #define BIFPLR5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
24323 | //BIFPLR5_0_CACHE_LINE |
24324 | #define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
24325 | #define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
24326 | //BIFPLR5_0_LATENCY |
24327 | #define BIFPLR5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
24328 | #define BIFPLR5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
24329 | //BIFPLR5_0_HEADER |
24330 | #define BIFPLR5_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
24331 | #define BIFPLR5_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
24332 | #define BIFPLR5_0_HEADER__HEADER_TYPE_MASK 0x7FL |
24333 | #define BIFPLR5_0_HEADER__DEVICE_TYPE_MASK 0x80L |
24334 | //BIFPLR5_0_BIST |
24335 | #define BIFPLR5_0_BIST__BIST_COMP__SHIFT 0x0 |
24336 | #define BIFPLR5_0_BIST__BIST_STRT__SHIFT 0x6 |
24337 | #define BIFPLR5_0_BIST__BIST_CAP__SHIFT 0x7 |
24338 | #define BIFPLR5_0_BIST__BIST_COMP_MASK 0x0FL |
24339 | #define BIFPLR5_0_BIST__BIST_STRT_MASK 0x40L |
24340 | #define BIFPLR5_0_BIST__BIST_CAP_MASK 0x80L |
24341 | //BIFPLR5_0_SUB_BUS_NUMBER_LATENCY |
24342 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
24343 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
24344 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
24345 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
24346 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
24347 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
24348 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
24349 | #define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
24350 | //BIFPLR5_0_IO_BASE_LIMIT |
24351 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
24352 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
24353 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
24354 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
24355 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
24356 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
24357 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
24358 | #define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
24359 | //BIFPLR5_0_SECONDARY_STATUS |
24360 | #define BIFPLR5_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
24361 | #define BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
24362 | #define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
24363 | #define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
24364 | #define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
24365 | #define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
24366 | #define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
24367 | #define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
24368 | #define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
24369 | #define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
24370 | #define BIFPLR5_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
24371 | #define BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
24372 | #define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
24373 | #define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
24374 | #define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
24375 | #define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
24376 | #define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
24377 | #define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
24378 | #define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
24379 | #define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
24380 | //BIFPLR5_0_MEM_BASE_LIMIT |
24381 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
24382 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
24383 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
24384 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
24385 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
24386 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
24387 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
24388 | #define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
24389 | //BIFPLR5_0_PREF_BASE_LIMIT |
24390 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
24391 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
24392 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
24393 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
24394 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
24395 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
24396 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
24397 | #define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
24398 | //BIFPLR5_0_PREF_BASE_UPPER |
24399 | #define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
24400 | #define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
24401 | //BIFPLR5_0_PREF_LIMIT_UPPER |
24402 | #define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
24403 | #define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
24404 | //BIFPLR5_0_IO_BASE_LIMIT_HI |
24405 | #define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
24406 | #define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
24407 | #define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
24408 | #define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
24409 | //BIFPLR5_0_CAP_PTR |
24410 | #define BIFPLR5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
24411 | #define BIFPLR5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
24412 | //BIFPLR5_0_INTERRUPT_LINE |
24413 | #define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
24414 | #define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
24415 | //BIFPLR5_0_INTERRUPT_PIN |
24416 | #define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
24417 | #define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
24418 | //BIFPLR5_0_IRQ_BRIDGE_CNTL |
24419 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
24420 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
24421 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
24422 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
24423 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
24424 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
24425 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
24426 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
24427 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
24428 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
24429 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
24430 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
24431 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
24432 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
24433 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
24434 | #define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
24435 | //BIFPLR5_0_EXT_BRIDGE_CNTL |
24436 | #define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
24437 | #define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
24438 | //BIFPLR5_0_PMI_CAP_LIST |
24439 | #define BIFPLR5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
24440 | #define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24441 | #define BIFPLR5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
24442 | #define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24443 | //BIFPLR5_0_PMI_CAP |
24444 | #define BIFPLR5_0_PMI_CAP__VERSION__SHIFT 0x0 |
24445 | #define BIFPLR5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
24446 | #define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
24447 | #define BIFPLR5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
24448 | #define BIFPLR5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
24449 | #define BIFPLR5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
24450 | #define BIFPLR5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
24451 | #define BIFPLR5_0_PMI_CAP__VERSION_MASK 0x0007L |
24452 | #define BIFPLR5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
24453 | #define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
24454 | #define BIFPLR5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
24455 | #define BIFPLR5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
24456 | #define BIFPLR5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
24457 | #define BIFPLR5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
24458 | //BIFPLR5_0_PMI_STATUS_CNTL |
24459 | #define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
24460 | #define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
24461 | #define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
24462 | #define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
24463 | #define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
24464 | #define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
24465 | #define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
24466 | #define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
24467 | #define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
24468 | #define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
24469 | #define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
24470 | #define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
24471 | #define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
24472 | #define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
24473 | #define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
24474 | #define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
24475 | #define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
24476 | #define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
24477 | //BIFPLR5_0_PCIE_CAP_LIST |
24478 | #define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
24479 | #define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24480 | #define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
24481 | #define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24482 | //BIFPLR5_0_PCIE_CAP |
24483 | #define BIFPLR5_0_PCIE_CAP__VERSION__SHIFT 0x0 |
24484 | #define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
24485 | #define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
24486 | #define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
24487 | #define BIFPLR5_0_PCIE_CAP__VERSION_MASK 0x000FL |
24488 | #define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
24489 | #define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
24490 | #define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
24491 | //BIFPLR5_0_DEVICE_CAP |
24492 | #define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
24493 | #define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
24494 | #define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
24495 | #define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
24496 | #define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
24497 | #define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
24498 | #define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
24499 | #define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
24500 | #define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
24501 | #define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
24502 | #define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
24503 | #define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
24504 | #define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
24505 | #define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
24506 | #define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
24507 | #define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
24508 | #define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
24509 | #define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
24510 | //BIFPLR5_0_DEVICE_CNTL |
24511 | #define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
24512 | #define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
24513 | #define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
24514 | #define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
24515 | #define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
24516 | #define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
24517 | #define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
24518 | #define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
24519 | #define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
24520 | #define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
24521 | #define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
24522 | #define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
24523 | #define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
24524 | #define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
24525 | #define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
24526 | #define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
24527 | #define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
24528 | #define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
24529 | #define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
24530 | #define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
24531 | #define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
24532 | #define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
24533 | #define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
24534 | #define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
24535 | //BIFPLR5_0_DEVICE_STATUS |
24536 | #define BIFPLR5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
24537 | #define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
24538 | #define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
24539 | #define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
24540 | #define BIFPLR5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
24541 | #define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
24542 | #define BIFPLR5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
24543 | #define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
24544 | #define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
24545 | #define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
24546 | #define BIFPLR5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
24547 | #define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
24548 | //BIFPLR5_0_LINK_CAP |
24549 | #define BIFPLR5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
24550 | #define BIFPLR5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
24551 | #define BIFPLR5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
24552 | #define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
24553 | #define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
24554 | #define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
24555 | #define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
24556 | #define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
24557 | #define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
24558 | #define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
24559 | #define BIFPLR5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
24560 | #define BIFPLR5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
24561 | #define BIFPLR5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
24562 | #define BIFPLR5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
24563 | #define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
24564 | #define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
24565 | #define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
24566 | #define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
24567 | #define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
24568 | #define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
24569 | #define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
24570 | #define BIFPLR5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
24571 | //BIFPLR5_0_LINK_CNTL |
24572 | #define BIFPLR5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
24573 | #define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
24574 | #define BIFPLR5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
24575 | #define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
24576 | #define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
24577 | #define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
24578 | #define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
24579 | #define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
24580 | #define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
24581 | #define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
24582 | #define BIFPLR5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
24583 | #define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
24584 | #define BIFPLR5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
24585 | #define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
24586 | #define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
24587 | #define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
24588 | #define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
24589 | #define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
24590 | #define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
24591 | #define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
24592 | //BIFPLR5_0_LINK_STATUS |
24593 | #define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
24594 | #define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
24595 | #define BIFPLR5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
24596 | #define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
24597 | #define BIFPLR5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
24598 | #define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
24599 | #define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
24600 | #define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
24601 | #define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
24602 | #define BIFPLR5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
24603 | #define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
24604 | #define BIFPLR5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
24605 | #define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
24606 | #define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
24607 | //BIFPLR5_0_SLOT_CAP |
24608 | #define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
24609 | #define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
24610 | #define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
24611 | #define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
24612 | #define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
24613 | #define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
24614 | #define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
24615 | #define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
24616 | #define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
24617 | #define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
24618 | #define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
24619 | #define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
24620 | #define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
24621 | #define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
24622 | #define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
24623 | #define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
24624 | #define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
24625 | #define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
24626 | #define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
24627 | #define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
24628 | #define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
24629 | #define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
24630 | #define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
24631 | #define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
24632 | //BIFPLR5_0_SLOT_CNTL |
24633 | #define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
24634 | #define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
24635 | #define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
24636 | #define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
24637 | #define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
24638 | #define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
24639 | #define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
24640 | #define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
24641 | #define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
24642 | #define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
24643 | #define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
24644 | #define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
24645 | #define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
24646 | #define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
24647 | #define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
24648 | #define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
24649 | #define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
24650 | #define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
24651 | #define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
24652 | #define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
24653 | #define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
24654 | #define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
24655 | #define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
24656 | #define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
24657 | //BIFPLR5_0_SLOT_STATUS |
24658 | #define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
24659 | #define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
24660 | #define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
24661 | #define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
24662 | #define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
24663 | #define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
24664 | #define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
24665 | #define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
24666 | #define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
24667 | #define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
24668 | #define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
24669 | #define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
24670 | #define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
24671 | #define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
24672 | #define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
24673 | #define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
24674 | #define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
24675 | #define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
24676 | //BIFPLR5_0_ROOT_CNTL |
24677 | #define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
24678 | #define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
24679 | #define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
24680 | #define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
24681 | #define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
24682 | #define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
24683 | #define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
24684 | #define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
24685 | #define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
24686 | #define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
24687 | //BIFPLR5_0_ROOT_CAP |
24688 | #define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
24689 | #define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
24690 | //BIFPLR5_0_ROOT_STATUS |
24691 | #define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
24692 | #define BIFPLR5_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
24693 | #define BIFPLR5_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
24694 | #define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
24695 | #define BIFPLR5_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
24696 | #define BIFPLR5_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
24697 | //BIFPLR5_0_DEVICE_CAP2 |
24698 | #define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
24699 | #define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
24700 | #define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
24701 | #define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
24702 | #define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
24703 | #define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
24704 | #define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
24705 | #define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
24706 | #define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
24707 | #define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
24708 | #define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
24709 | #define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
24710 | #define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
24711 | #define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
24712 | #define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
24713 | #define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
24714 | #define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
24715 | #define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
24716 | #define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
24717 | #define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
24718 | #define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
24719 | #define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
24720 | #define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
24721 | #define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
24722 | #define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
24723 | #define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
24724 | #define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
24725 | #define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
24726 | //BIFPLR5_0_DEVICE_CNTL2 |
24727 | #define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
24728 | #define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
24729 | #define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
24730 | #define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
24731 | #define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
24732 | #define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
24733 | #define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
24734 | #define BIFPLR5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
24735 | #define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
24736 | #define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
24737 | #define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
24738 | #define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
24739 | #define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
24740 | #define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
24741 | #define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
24742 | #define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
24743 | #define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
24744 | #define BIFPLR5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
24745 | #define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
24746 | #define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
24747 | //BIFPLR5_0_DEVICE_STATUS2 |
24748 | #define BIFPLR5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
24749 | #define BIFPLR5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
24750 | //BIFPLR5_0_LINK_CAP2 |
24751 | #define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
24752 | #define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
24753 | #define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
24754 | #define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
24755 | #define BIFPLR5_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
24756 | #define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
24757 | #define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
24758 | #define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
24759 | #define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
24760 | #define BIFPLR5_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
24761 | //BIFPLR5_0_LINK_CNTL2 |
24762 | #define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
24763 | #define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
24764 | #define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
24765 | #define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
24766 | #define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
24767 | #define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
24768 | #define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
24769 | #define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
24770 | #define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
24771 | #define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
24772 | #define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
24773 | #define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
24774 | #define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
24775 | #define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
24776 | #define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
24777 | #define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
24778 | //BIFPLR5_0_LINK_STATUS2 |
24779 | #define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
24780 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
24781 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
24782 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
24783 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
24784 | #define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
24785 | #define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
24786 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
24787 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
24788 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
24789 | #define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
24790 | #define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
24791 | //BIFPLR5_0_SLOT_CAP2 |
24792 | #define BIFPLR5_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
24793 | #define BIFPLR5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
24794 | //BIFPLR5_0_SLOT_CNTL2 |
24795 | #define BIFPLR5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
24796 | #define BIFPLR5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
24797 | //BIFPLR5_0_SLOT_STATUS2 |
24798 | #define BIFPLR5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
24799 | #define BIFPLR5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
24800 | //BIFPLR5_0_MSI_CAP_LIST |
24801 | #define BIFPLR5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
24802 | #define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24803 | #define BIFPLR5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
24804 | #define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24805 | //BIFPLR5_0_MSI_MSG_CNTL |
24806 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
24807 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
24808 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
24809 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
24810 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
24811 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
24812 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
24813 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
24814 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
24815 | #define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
24816 | //BIFPLR5_0_MSI_MSG_ADDR_LO |
24817 | #define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
24818 | #define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
24819 | //BIFPLR5_0_MSI_MSG_ADDR_HI |
24820 | #define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
24821 | #define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
24822 | //BIFPLR5_0_MSI_MSG_DATA |
24823 | #define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
24824 | #define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
24825 | //BIFPLR5_0_MSI_MSG_DATA_64 |
24826 | #define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
24827 | #define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
24828 | //BIFPLR5_0_SSID_CAP_LIST |
24829 | #define BIFPLR5_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
24830 | #define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24831 | #define BIFPLR5_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
24832 | #define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24833 | //BIFPLR5_0_SSID_CAP |
24834 | #define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
24835 | #define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
24836 | #define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
24837 | #define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
24838 | //BIFPLR5_0_MSI_MAP_CAP_LIST |
24839 | #define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
24840 | #define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24841 | #define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
24842 | #define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24843 | //BIFPLR5_0_MSI_MAP_CAP |
24844 | #define BIFPLR5_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
24845 | #define BIFPLR5_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
24846 | #define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
24847 | #define BIFPLR5_0_MSI_MAP_CAP__EN_MASK 0x0001L |
24848 | #define BIFPLR5_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
24849 | #define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
24850 | //BIFPLR5_0_MSI_MAP_ADDR_LO |
24851 | #define BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
24852 | #define BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
24853 | //BIFPLR5_0_MSI_MAP_ADDR_HI |
24854 | #define BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
24855 | #define BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
24856 | //BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
24857 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
24858 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
24859 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
24860 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
24861 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
24862 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
24863 | //BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR |
24864 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
24865 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
24866 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
24867 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
24868 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
24869 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
24870 | //BIFPLR5_0_PCIE_VENDOR_SPECIFIC1 |
24871 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
24872 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
24873 | //BIFPLR5_0_PCIE_VENDOR_SPECIFIC2 |
24874 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
24875 | #define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
24876 | //BIFPLR5_0_PCIE_VC_ENH_CAP_LIST |
24877 | #define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
24878 | #define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
24879 | #define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
24880 | #define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
24881 | #define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
24882 | #define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
24883 | //BIFPLR5_0_PCIE_PORT_VC_CAP_REG1 |
24884 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
24885 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
24886 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
24887 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
24888 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
24889 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
24890 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
24891 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
24892 | //BIFPLR5_0_PCIE_PORT_VC_CAP_REG2 |
24893 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
24894 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
24895 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
24896 | #define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
24897 | //BIFPLR5_0_PCIE_PORT_VC_CNTL |
24898 | #define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
24899 | #define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
24900 | #define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
24901 | #define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
24902 | //BIFPLR5_0_PCIE_PORT_VC_STATUS |
24903 | #define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
24904 | #define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
24905 | //BIFPLR5_0_PCIE_VC0_RESOURCE_CAP |
24906 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
24907 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
24908 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
24909 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
24910 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
24911 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
24912 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
24913 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
24914 | //BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL |
24915 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
24916 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
24917 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
24918 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
24919 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
24920 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
24921 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
24922 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
24923 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
24924 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
24925 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
24926 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
24927 | //BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS |
24928 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
24929 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
24930 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
24931 | #define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
24932 | //BIFPLR5_0_PCIE_VC1_RESOURCE_CAP |
24933 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
24934 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
24935 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
24936 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
24937 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
24938 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
24939 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
24940 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
24941 | //BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL |
24942 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
24943 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
24944 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
24945 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
24946 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
24947 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
24948 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
24949 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
24950 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
24951 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
24952 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
24953 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
24954 | //BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS |
24955 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
24956 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
24957 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
24958 | #define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
24959 | //BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
24960 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
24961 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
24962 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
24963 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
24964 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
24965 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
24966 | //BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 |
24967 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
24968 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
24969 | //BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 |
24970 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
24971 | #define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
24972 | //BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
24973 | #define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
24974 | #define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
24975 | #define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
24976 | #define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
24977 | #define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
24978 | #define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
24979 | //BIFPLR5_0_PCIE_UNCORR_ERR_STATUS |
24980 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
24981 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
24982 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
24983 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
24984 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
24985 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
24986 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
24987 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
24988 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
24989 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
24990 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
24991 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
24992 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
24993 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
24994 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
24995 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
24996 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
24997 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
24998 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
24999 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
25000 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
25001 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
25002 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
25003 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
25004 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
25005 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
25006 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
25007 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
25008 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
25009 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
25010 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
25011 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
25012 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
25013 | #define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
25014 | //BIFPLR5_0_PCIE_UNCORR_ERR_MASK |
25015 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
25016 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
25017 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
25018 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
25019 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
25020 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
25021 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
25022 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
25023 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
25024 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
25025 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
25026 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
25027 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
25028 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
25029 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
25030 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
25031 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
25032 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
25033 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
25034 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
25035 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
25036 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
25037 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
25038 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
25039 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
25040 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
25041 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
25042 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
25043 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
25044 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
25045 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
25046 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
25047 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
25048 | #define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
25049 | //BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY |
25050 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
25051 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
25052 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
25053 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
25054 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
25055 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
25056 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
25057 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
25058 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
25059 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
25060 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
25061 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
25062 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
25063 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
25064 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
25065 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
25066 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
25067 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
25068 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
25069 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
25070 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
25071 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
25072 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
25073 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
25074 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
25075 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
25076 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
25077 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
25078 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
25079 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
25080 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
25081 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
25082 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
25083 | #define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
25084 | //BIFPLR5_0_PCIE_CORR_ERR_STATUS |
25085 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
25086 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
25087 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
25088 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
25089 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
25090 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
25091 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
25092 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
25093 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
25094 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
25095 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
25096 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
25097 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
25098 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
25099 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
25100 | #define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
25101 | //BIFPLR5_0_PCIE_CORR_ERR_MASK |
25102 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
25103 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
25104 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
25105 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
25106 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
25107 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
25108 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
25109 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
25110 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
25111 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
25112 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
25113 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
25114 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
25115 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
25116 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
25117 | #define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
25118 | //BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL |
25119 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
25120 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
25121 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
25122 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
25123 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
25124 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
25125 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
25126 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
25127 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
25128 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
25129 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
25130 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
25131 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
25132 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
25133 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
25134 | #define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
25135 | //BIFPLR5_0_PCIE_HDR_LOG0 |
25136 | #define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
25137 | #define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
25138 | //BIFPLR5_0_PCIE_HDR_LOG1 |
25139 | #define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
25140 | #define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
25141 | //BIFPLR5_0_PCIE_HDR_LOG2 |
25142 | #define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
25143 | #define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
25144 | //BIFPLR5_0_PCIE_HDR_LOG3 |
25145 | #define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
25146 | #define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
25147 | //BIFPLR5_0_PCIE_ROOT_ERR_CMD |
25148 | #define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
25149 | #define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
25150 | #define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
25151 | #define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
25152 | #define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
25153 | #define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
25154 | //BIFPLR5_0_PCIE_ROOT_ERR_STATUS |
25155 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
25156 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
25157 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
25158 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
25159 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
25160 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
25161 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
25162 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
25163 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
25164 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
25165 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
25166 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
25167 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
25168 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
25169 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
25170 | #define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
25171 | //BIFPLR5_0_PCIE_ERR_SRC_ID |
25172 | #define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
25173 | #define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
25174 | #define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
25175 | #define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
25176 | //BIFPLR5_0_PCIE_TLP_PREFIX_LOG0 |
25177 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
25178 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
25179 | //BIFPLR5_0_PCIE_TLP_PREFIX_LOG1 |
25180 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
25181 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
25182 | //BIFPLR5_0_PCIE_TLP_PREFIX_LOG2 |
25183 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
25184 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
25185 | //BIFPLR5_0_PCIE_TLP_PREFIX_LOG3 |
25186 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
25187 | #define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
25188 | //BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST |
25189 | #define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25190 | #define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25191 | #define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25192 | #define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25193 | #define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25194 | #define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25195 | //BIFPLR5_0_PCIE_LINK_CNTL3 |
25196 | #define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
25197 | #define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
25198 | #define BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
25199 | #define BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
25200 | #define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
25201 | #define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
25202 | #define BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
25203 | #define BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
25204 | //BIFPLR5_0_PCIE_LANE_ERROR_STATUS |
25205 | #define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
25206 | #define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
25207 | #define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
25208 | #define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
25209 | //BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL |
25210 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25211 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25212 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25213 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25214 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25215 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25216 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25217 | #define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25218 | //BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL |
25219 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25220 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25221 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25222 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25223 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25224 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25225 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25226 | #define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25227 | //BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL |
25228 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25229 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25230 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25231 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25232 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25233 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25234 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25235 | #define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25236 | //BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL |
25237 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25238 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25239 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25240 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25241 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25242 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25243 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25244 | #define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25245 | //BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL |
25246 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25247 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25248 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25249 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25250 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25251 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25252 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25253 | #define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25254 | //BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL |
25255 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25256 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25257 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25258 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25259 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25260 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25261 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25262 | #define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25263 | //BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL |
25264 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25265 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25266 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25267 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25268 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25269 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25270 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25271 | #define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25272 | //BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL |
25273 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25274 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25275 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25276 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25277 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25278 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25279 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25280 | #define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25281 | //BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL |
25282 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25283 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25284 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25285 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25286 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25287 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25288 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25289 | #define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25290 | //BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL |
25291 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25292 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25293 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25294 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25295 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25296 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25297 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25298 | #define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25299 | //BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL |
25300 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25301 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25302 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25303 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25304 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25305 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25306 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25307 | #define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25308 | //BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL |
25309 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25310 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25311 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25312 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25313 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25314 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25315 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25316 | #define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25317 | //BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL |
25318 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25319 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25320 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25321 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25322 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25323 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25324 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25325 | #define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25326 | //BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL |
25327 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25328 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25329 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25330 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25331 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25332 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25333 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25334 | #define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25335 | //BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL |
25336 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25337 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25338 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25339 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25340 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25341 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25342 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25343 | #define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25344 | //BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL |
25345 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
25346 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
25347 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
25348 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
25349 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
25350 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
25351 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
25352 | #define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
25353 | //BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST |
25354 | #define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25355 | #define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25356 | #define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25357 | #define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25358 | #define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25359 | #define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25360 | //BIFPLR5_0_PCIE_ACS_CAP |
25361 | #define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
25362 | #define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
25363 | #define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
25364 | #define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
25365 | #define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
25366 | #define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
25367 | #define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
25368 | #define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
25369 | #define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
25370 | #define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
25371 | #define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
25372 | #define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
25373 | #define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
25374 | #define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
25375 | #define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
25376 | #define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
25377 | //BIFPLR5_0_PCIE_ACS_CNTL |
25378 | #define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
25379 | #define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
25380 | #define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
25381 | #define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
25382 | #define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
25383 | #define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
25384 | #define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
25385 | #define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
25386 | #define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
25387 | #define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
25388 | #define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
25389 | #define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
25390 | #define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
25391 | #define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
25392 | //BIFPLR5_0_PCIE_MC_ENH_CAP_LIST |
25393 | #define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25394 | #define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25395 | #define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25396 | #define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25397 | #define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25398 | #define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25399 | //BIFPLR5_0_PCIE_MC_CAP |
25400 | #define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
25401 | #define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
25402 | #define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
25403 | #define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
25404 | //BIFPLR5_0_PCIE_MC_CNTL |
25405 | #define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
25406 | #define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
25407 | #define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
25408 | #define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
25409 | //BIFPLR5_0_PCIE_MC_ADDR0 |
25410 | #define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
25411 | #define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
25412 | #define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
25413 | #define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
25414 | //BIFPLR5_0_PCIE_MC_ADDR1 |
25415 | #define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
25416 | #define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
25417 | //BIFPLR5_0_PCIE_MC_RCV0 |
25418 | #define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
25419 | #define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
25420 | //BIFPLR5_0_PCIE_MC_RCV1 |
25421 | #define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
25422 | #define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
25423 | //BIFPLR5_0_PCIE_MC_BLOCK_ALL0 |
25424 | #define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
25425 | #define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
25426 | //BIFPLR5_0_PCIE_MC_BLOCK_ALL1 |
25427 | #define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
25428 | #define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
25429 | //BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
25430 | #define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
25431 | #define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
25432 | //BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
25433 | #define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
25434 | #define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
25435 | //BIFPLR5_0_PCIE_MC_OVERLAY_BAR0 |
25436 | #define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
25437 | #define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
25438 | #define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
25439 | #define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
25440 | //BIFPLR5_0_PCIE_MC_OVERLAY_BAR1 |
25441 | #define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
25442 | #define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
25443 | //BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST |
25444 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
25445 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
25446 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25447 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25448 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25449 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25450 | //BIFPLR5_0_PCIE_L1_PM_SUB_CAP |
25451 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
25452 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
25453 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
25454 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
25455 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
25456 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
25457 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
25458 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
25459 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
25460 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
25461 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
25462 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
25463 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
25464 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
25465 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
25466 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
25467 | //BIFPLR5_0_PCIE_L1_PM_SUB_CNTL |
25468 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
25469 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
25470 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
25471 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
25472 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
25473 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
25474 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
25475 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
25476 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
25477 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
25478 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
25479 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
25480 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
25481 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
25482 | //BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 |
25483 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
25484 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
25485 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
25486 | #define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
25487 | //BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST |
25488 | #define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25489 | #define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25490 | #define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25491 | #define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25492 | #define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25493 | #define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25494 | //BIFPLR5_0_PCIE_DPC_CAP_LIST |
25495 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
25496 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
25497 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
25498 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
25499 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
25500 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
25501 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
25502 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
25503 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
25504 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
25505 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
25506 | #define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
25507 | //BIFPLR5_0_PCIE_DPC_CNTL |
25508 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
25509 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
25510 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
25511 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
25512 | #define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
25513 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
25514 | #define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
25515 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
25516 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
25517 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
25518 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
25519 | #define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
25520 | #define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
25521 | #define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
25522 | //BIFPLR5_0_PCIE_DPC_STATUS |
25523 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
25524 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
25525 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
25526 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
25527 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
25528 | #define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
25529 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
25530 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
25531 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
25532 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
25533 | #define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
25534 | #define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
25535 | //BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID |
25536 | #define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
25537 | #define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
25538 | //BIFPLR5_0_PCIE_RP_PIO_STATUS |
25539 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
25540 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
25541 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
25542 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
25543 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
25544 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
25545 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
25546 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
25547 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
25548 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
25549 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
25550 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
25551 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
25552 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
25553 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
25554 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
25555 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
25556 | #define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
25557 | //BIFPLR5_0_PCIE_RP_PIO_MASK |
25558 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
25559 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
25560 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
25561 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
25562 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
25563 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
25564 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
25565 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
25566 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
25567 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
25568 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
25569 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
25570 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
25571 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
25572 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
25573 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
25574 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
25575 | #define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
25576 | //BIFPLR5_0_PCIE_RP_PIO_SEVERITY |
25577 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
25578 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
25579 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
25580 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
25581 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
25582 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
25583 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
25584 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
25585 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
25586 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
25587 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
25588 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
25589 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
25590 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
25591 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
25592 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
25593 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
25594 | #define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
25595 | //BIFPLR5_0_PCIE_RP_PIO_SYSERROR |
25596 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
25597 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
25598 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
25599 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
25600 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
25601 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
25602 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
25603 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
25604 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
25605 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
25606 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
25607 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
25608 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
25609 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
25610 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
25611 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
25612 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
25613 | #define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
25614 | //BIFPLR5_0_PCIE_RP_PIO_EXCEPTION |
25615 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
25616 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
25617 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
25618 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
25619 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
25620 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
25621 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
25622 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
25623 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
25624 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
25625 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
25626 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
25627 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
25628 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
25629 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
25630 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
25631 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
25632 | #define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
25633 | //BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 |
25634 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
25635 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
25636 | //BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 |
25637 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
25638 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
25639 | //BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 |
25640 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
25641 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
25642 | //BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 |
25643 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
25644 | #define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
25645 | //BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG |
25646 | #define BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
25647 | #define BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
25648 | //BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 |
25649 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
25650 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
25651 | //BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 |
25652 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
25653 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
25654 | //BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 |
25655 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
25656 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
25657 | //BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 |
25658 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
25659 | #define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
25660 | //BIFPLR5_0_PCIE_ESM_CAP_LIST |
25661 | #define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
25662 | #define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
25663 | #define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25664 | #define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25665 | #define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25666 | #define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25667 | //BIFPLR5_0_PCIE_ESM_HEADER_1 |
25668 | #define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
25669 | #define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
25670 | #define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
25671 | #define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
25672 | #define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
25673 | #define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
25674 | //BIFPLR5_0_PCIE_ESM_HEADER_2 |
25675 | #define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
25676 | #define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
25677 | //BIFPLR5_0_PCIE_ESM_STATUS |
25678 | #define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
25679 | #define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
25680 | #define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
25681 | #define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
25682 | //BIFPLR5_0_PCIE_ESM_CTRL |
25683 | #define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
25684 | #define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
25685 | #define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
25686 | #define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
25687 | #define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
25688 | #define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
25689 | //BIFPLR5_0_PCIE_ESM_CAP_1 |
25690 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
25691 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
25692 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
25693 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
25694 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
25695 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
25696 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
25697 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
25698 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
25699 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
25700 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
25701 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
25702 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
25703 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
25704 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
25705 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
25706 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
25707 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
25708 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
25709 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
25710 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
25711 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
25712 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
25713 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
25714 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
25715 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
25716 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
25717 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
25718 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
25719 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
25720 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
25721 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
25722 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
25723 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
25724 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
25725 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
25726 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
25727 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
25728 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
25729 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
25730 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
25731 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
25732 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
25733 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
25734 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
25735 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
25736 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
25737 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
25738 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
25739 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
25740 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
25741 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
25742 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
25743 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
25744 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
25745 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
25746 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
25747 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
25748 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
25749 | #define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
25750 | //BIFPLR5_0_PCIE_ESM_CAP_2 |
25751 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
25752 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
25753 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
25754 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
25755 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
25756 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
25757 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
25758 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
25759 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
25760 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
25761 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
25762 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
25763 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
25764 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
25765 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
25766 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
25767 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
25768 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
25769 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
25770 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
25771 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
25772 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
25773 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
25774 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
25775 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
25776 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
25777 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
25778 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
25779 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
25780 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
25781 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
25782 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
25783 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
25784 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
25785 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
25786 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
25787 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
25788 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
25789 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
25790 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
25791 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
25792 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
25793 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
25794 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
25795 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
25796 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
25797 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
25798 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
25799 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
25800 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
25801 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
25802 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
25803 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
25804 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
25805 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
25806 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
25807 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
25808 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
25809 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
25810 | #define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
25811 | //BIFPLR5_0_PCIE_ESM_CAP_3 |
25812 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
25813 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
25814 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
25815 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
25816 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
25817 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
25818 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
25819 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
25820 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
25821 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
25822 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
25823 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
25824 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
25825 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
25826 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
25827 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
25828 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
25829 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
25830 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
25831 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
25832 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
25833 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
25834 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
25835 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
25836 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
25837 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
25838 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
25839 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
25840 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
25841 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
25842 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
25843 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
25844 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
25845 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
25846 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
25847 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
25848 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
25849 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
25850 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
25851 | #define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
25852 | //BIFPLR5_0_PCIE_ESM_CAP_4 |
25853 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
25854 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
25855 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
25856 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
25857 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
25858 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
25859 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
25860 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
25861 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
25862 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
25863 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
25864 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
25865 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
25866 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
25867 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
25868 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
25869 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
25870 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
25871 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
25872 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
25873 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
25874 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
25875 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
25876 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
25877 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
25878 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
25879 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
25880 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
25881 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
25882 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
25883 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
25884 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
25885 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
25886 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
25887 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
25888 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
25889 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
25890 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
25891 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
25892 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
25893 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
25894 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
25895 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
25896 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
25897 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
25898 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
25899 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
25900 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
25901 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
25902 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
25903 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
25904 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
25905 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
25906 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
25907 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
25908 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
25909 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
25910 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
25911 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
25912 | #define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
25913 | //BIFPLR5_0_PCIE_ESM_CAP_5 |
25914 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
25915 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
25916 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
25917 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
25918 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
25919 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
25920 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
25921 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
25922 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
25923 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
25924 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
25925 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
25926 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
25927 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
25928 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
25929 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
25930 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
25931 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
25932 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
25933 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
25934 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
25935 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
25936 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
25937 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
25938 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
25939 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
25940 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
25941 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
25942 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
25943 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
25944 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
25945 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
25946 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
25947 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
25948 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
25949 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
25950 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
25951 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
25952 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
25953 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
25954 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
25955 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
25956 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
25957 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
25958 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
25959 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
25960 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
25961 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
25962 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
25963 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
25964 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
25965 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
25966 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
25967 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
25968 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
25969 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
25970 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
25971 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
25972 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
25973 | #define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
25974 | //BIFPLR5_0_PCIE_ESM_CAP_6 |
25975 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
25976 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
25977 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
25978 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
25979 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
25980 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
25981 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
25982 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
25983 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
25984 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
25985 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
25986 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
25987 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
25988 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
25989 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
25990 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
25991 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
25992 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
25993 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
25994 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
25995 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
25996 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
25997 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
25998 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
25999 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
26000 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
26001 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
26002 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
26003 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
26004 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
26005 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
26006 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
26007 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
26008 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
26009 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
26010 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
26011 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
26012 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
26013 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
26014 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
26015 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
26016 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
26017 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
26018 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
26019 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
26020 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
26021 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
26022 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
26023 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
26024 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
26025 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
26026 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
26027 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
26028 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
26029 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
26030 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
26031 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
26032 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
26033 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
26034 | #define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
26035 | //BIFPLR5_0_PCIE_ESM_CAP_7 |
26036 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
26037 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
26038 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
26039 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
26040 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
26041 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
26042 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
26043 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
26044 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
26045 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
26046 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
26047 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
26048 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
26049 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
26050 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
26051 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
26052 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
26053 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
26054 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
26055 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
26056 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
26057 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
26058 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
26059 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
26060 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
26061 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
26062 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
26063 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
26064 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
26065 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
26066 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
26067 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
26068 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
26069 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
26070 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
26071 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
26072 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
26073 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
26074 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
26075 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
26076 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
26077 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
26078 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
26079 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
26080 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
26081 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
26082 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
26083 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
26084 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
26085 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
26086 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
26087 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
26088 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
26089 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
26090 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
26091 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
26092 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
26093 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
26094 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
26095 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
26096 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
26097 | #define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
26098 | |
26099 | |
26100 | // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
26101 | //BIFPLR6_0_VENDOR_ID |
26102 | #define BIFPLR6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
26103 | #define BIFPLR6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
26104 | //BIFPLR6_0_DEVICE_ID |
26105 | #define BIFPLR6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
26106 | #define BIFPLR6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
26107 | //BIFPLR6_0_COMMAND |
26108 | #define BIFPLR6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
26109 | #define BIFPLR6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
26110 | #define BIFPLR6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
26111 | #define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
26112 | #define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
26113 | #define BIFPLR6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
26114 | #define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
26115 | #define BIFPLR6_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
26116 | #define BIFPLR6_0_COMMAND__SERR_EN__SHIFT 0x8 |
26117 | #define BIFPLR6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
26118 | #define BIFPLR6_0_COMMAND__INT_DIS__SHIFT 0xa |
26119 | #define BIFPLR6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
26120 | #define BIFPLR6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
26121 | #define BIFPLR6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
26122 | #define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
26123 | #define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
26124 | #define BIFPLR6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
26125 | #define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
26126 | #define BIFPLR6_0_COMMAND__AD_STEPPING_MASK 0x0080L |
26127 | #define BIFPLR6_0_COMMAND__SERR_EN_MASK 0x0100L |
26128 | #define BIFPLR6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
26129 | #define BIFPLR6_0_COMMAND__INT_DIS_MASK 0x0400L |
26130 | //BIFPLR6_0_STATUS |
26131 | #define BIFPLR6_0_STATUS__INT_STATUS__SHIFT 0x3 |
26132 | #define BIFPLR6_0_STATUS__CAP_LIST__SHIFT 0x4 |
26133 | #define BIFPLR6_0_STATUS__PCI_66_EN__SHIFT 0x5 |
26134 | #define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
26135 | #define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
26136 | #define BIFPLR6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
26137 | #define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
26138 | #define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
26139 | #define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
26140 | #define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
26141 | #define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
26142 | #define BIFPLR6_0_STATUS__INT_STATUS_MASK 0x0008L |
26143 | #define BIFPLR6_0_STATUS__CAP_LIST_MASK 0x0010L |
26144 | #define BIFPLR6_0_STATUS__PCI_66_EN_MASK 0x0020L |
26145 | #define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
26146 | #define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
26147 | #define BIFPLR6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
26148 | #define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
26149 | #define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
26150 | #define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
26151 | #define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
26152 | #define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
26153 | //BIFPLR6_0_REVISION_ID |
26154 | #define BIFPLR6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
26155 | #define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
26156 | #define BIFPLR6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
26157 | #define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
26158 | //BIFPLR6_0_PROG_INTERFACE |
26159 | #define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
26160 | #define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
26161 | //BIFPLR6_0_SUB_CLASS |
26162 | #define BIFPLR6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
26163 | #define BIFPLR6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
26164 | //BIFPLR6_0_BASE_CLASS |
26165 | #define BIFPLR6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
26166 | #define BIFPLR6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
26167 | //BIFPLR6_0_CACHE_LINE |
26168 | #define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
26169 | #define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
26170 | //BIFPLR6_0_LATENCY |
26171 | #define BIFPLR6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
26172 | #define BIFPLR6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
26173 | //BIFPLR6_0_HEADER |
26174 | #define BIFPLR6_0_HEADER__HEADER_TYPE__SHIFT 0x0 |
26175 | #define BIFPLR6_0_HEADER__DEVICE_TYPE__SHIFT 0x7 |
26176 | #define BIFPLR6_0_HEADER__HEADER_TYPE_MASK 0x7FL |
26177 | #define BIFPLR6_0_HEADER__DEVICE_TYPE_MASK 0x80L |
26178 | //BIFPLR6_0_BIST |
26179 | #define BIFPLR6_0_BIST__BIST_COMP__SHIFT 0x0 |
26180 | #define BIFPLR6_0_BIST__BIST_STRT__SHIFT 0x6 |
26181 | #define BIFPLR6_0_BIST__BIST_CAP__SHIFT 0x7 |
26182 | #define BIFPLR6_0_BIST__BIST_COMP_MASK 0x0FL |
26183 | #define BIFPLR6_0_BIST__BIST_STRT_MASK 0x40L |
26184 | #define BIFPLR6_0_BIST__BIST_CAP_MASK 0x80L |
26185 | //BIFPLR6_0_SUB_BUS_NUMBER_LATENCY |
26186 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
26187 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
26188 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
26189 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
26190 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
26191 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
26192 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
26193 | #define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
26194 | //BIFPLR6_0_IO_BASE_LIMIT |
26195 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
26196 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
26197 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
26198 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
26199 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
26200 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
26201 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
26202 | #define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
26203 | //BIFPLR6_0_SECONDARY_STATUS |
26204 | #define BIFPLR6_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
26205 | #define BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
26206 | #define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
26207 | #define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
26208 | #define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
26209 | #define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
26210 | #define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
26211 | #define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
26212 | #define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
26213 | #define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
26214 | #define BIFPLR6_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
26215 | #define BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
26216 | #define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
26217 | #define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
26218 | #define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
26219 | #define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
26220 | #define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
26221 | #define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
26222 | #define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
26223 | #define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
26224 | //BIFPLR6_0_MEM_BASE_LIMIT |
26225 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
26226 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
26227 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
26228 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
26229 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
26230 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
26231 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
26232 | #define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
26233 | //BIFPLR6_0_PREF_BASE_LIMIT |
26234 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
26235 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
26236 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
26237 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
26238 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
26239 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
26240 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
26241 | #define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
26242 | //BIFPLR6_0_PREF_BASE_UPPER |
26243 | #define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
26244 | #define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
26245 | //BIFPLR6_0_PREF_LIMIT_UPPER |
26246 | #define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
26247 | #define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
26248 | //BIFPLR6_0_IO_BASE_LIMIT_HI |
26249 | #define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
26250 | #define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
26251 | #define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
26252 | #define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
26253 | //BIFPLR6_0_CAP_PTR |
26254 | #define BIFPLR6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
26255 | #define BIFPLR6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
26256 | //BIFPLR6_0_INTERRUPT_LINE |
26257 | #define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
26258 | #define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
26259 | //BIFPLR6_0_INTERRUPT_PIN |
26260 | #define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
26261 | #define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
26262 | //BIFPLR6_0_IRQ_BRIDGE_CNTL |
26263 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
26264 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
26265 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
26266 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
26267 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
26268 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
26269 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
26270 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
26271 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
26272 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
26273 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
26274 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
26275 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
26276 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
26277 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
26278 | #define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
26279 | //BIFPLR6_0_EXT_BRIDGE_CNTL |
26280 | #define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
26281 | #define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
26282 | //BIFPLR6_0_PMI_CAP_LIST |
26283 | #define BIFPLR6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
26284 | #define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26285 | #define BIFPLR6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
26286 | #define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26287 | //BIFPLR6_0_PMI_CAP |
26288 | #define BIFPLR6_0_PMI_CAP__VERSION__SHIFT 0x0 |
26289 | #define BIFPLR6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
26290 | #define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
26291 | #define BIFPLR6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
26292 | #define BIFPLR6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
26293 | #define BIFPLR6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
26294 | #define BIFPLR6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
26295 | #define BIFPLR6_0_PMI_CAP__VERSION_MASK 0x0007L |
26296 | #define BIFPLR6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
26297 | #define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
26298 | #define BIFPLR6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
26299 | #define BIFPLR6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
26300 | #define BIFPLR6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
26301 | #define BIFPLR6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
26302 | //BIFPLR6_0_PMI_STATUS_CNTL |
26303 | #define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
26304 | #define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
26305 | #define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
26306 | #define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
26307 | #define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
26308 | #define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
26309 | #define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
26310 | #define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
26311 | #define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
26312 | #define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
26313 | #define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
26314 | #define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
26315 | #define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
26316 | #define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
26317 | #define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
26318 | #define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
26319 | #define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
26320 | #define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
26321 | //BIFPLR6_0_PCIE_CAP_LIST |
26322 | #define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
26323 | #define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26324 | #define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
26325 | #define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26326 | //BIFPLR6_0_PCIE_CAP |
26327 | #define BIFPLR6_0_PCIE_CAP__VERSION__SHIFT 0x0 |
26328 | #define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
26329 | #define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
26330 | #define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
26331 | #define BIFPLR6_0_PCIE_CAP__VERSION_MASK 0x000FL |
26332 | #define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
26333 | #define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
26334 | #define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
26335 | //BIFPLR6_0_DEVICE_CAP |
26336 | #define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
26337 | #define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
26338 | #define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
26339 | #define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
26340 | #define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
26341 | #define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
26342 | #define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
26343 | #define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
26344 | #define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
26345 | #define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
26346 | #define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
26347 | #define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
26348 | #define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
26349 | #define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
26350 | #define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
26351 | #define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
26352 | #define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
26353 | #define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
26354 | //BIFPLR6_0_DEVICE_CNTL |
26355 | #define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
26356 | #define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
26357 | #define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
26358 | #define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
26359 | #define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
26360 | #define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
26361 | #define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
26362 | #define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
26363 | #define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
26364 | #define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
26365 | #define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
26366 | #define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
26367 | #define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
26368 | #define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
26369 | #define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
26370 | #define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
26371 | #define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
26372 | #define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
26373 | #define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
26374 | #define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
26375 | #define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
26376 | #define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
26377 | #define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
26378 | #define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
26379 | //BIFPLR6_0_DEVICE_STATUS |
26380 | #define BIFPLR6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
26381 | #define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
26382 | #define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
26383 | #define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
26384 | #define BIFPLR6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
26385 | #define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
26386 | #define BIFPLR6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
26387 | #define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
26388 | #define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
26389 | #define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
26390 | #define BIFPLR6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
26391 | #define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
26392 | //BIFPLR6_0_LINK_CAP |
26393 | #define BIFPLR6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
26394 | #define BIFPLR6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
26395 | #define BIFPLR6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
26396 | #define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
26397 | #define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
26398 | #define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
26399 | #define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
26400 | #define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
26401 | #define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
26402 | #define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
26403 | #define BIFPLR6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
26404 | #define BIFPLR6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
26405 | #define BIFPLR6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
26406 | #define BIFPLR6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
26407 | #define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
26408 | #define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
26409 | #define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
26410 | #define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
26411 | #define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
26412 | #define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
26413 | #define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
26414 | #define BIFPLR6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
26415 | //BIFPLR6_0_LINK_CNTL |
26416 | #define BIFPLR6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
26417 | #define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
26418 | #define BIFPLR6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
26419 | #define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
26420 | #define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
26421 | #define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
26422 | #define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
26423 | #define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
26424 | #define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
26425 | #define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
26426 | #define BIFPLR6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
26427 | #define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
26428 | #define BIFPLR6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
26429 | #define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
26430 | #define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
26431 | #define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
26432 | #define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
26433 | #define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
26434 | #define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
26435 | #define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
26436 | //BIFPLR6_0_LINK_STATUS |
26437 | #define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
26438 | #define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
26439 | #define BIFPLR6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
26440 | #define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
26441 | #define BIFPLR6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
26442 | #define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
26443 | #define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
26444 | #define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
26445 | #define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
26446 | #define BIFPLR6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
26447 | #define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
26448 | #define BIFPLR6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
26449 | #define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
26450 | #define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
26451 | //BIFPLR6_0_SLOT_CAP |
26452 | #define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
26453 | #define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
26454 | #define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
26455 | #define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
26456 | #define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
26457 | #define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
26458 | #define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
26459 | #define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
26460 | #define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
26461 | #define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
26462 | #define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
26463 | #define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
26464 | #define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
26465 | #define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
26466 | #define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
26467 | #define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
26468 | #define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
26469 | #define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
26470 | #define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
26471 | #define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
26472 | #define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
26473 | #define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
26474 | #define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
26475 | #define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
26476 | //BIFPLR6_0_SLOT_CNTL |
26477 | #define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
26478 | #define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
26479 | #define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
26480 | #define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
26481 | #define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
26482 | #define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
26483 | #define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
26484 | #define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
26485 | #define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
26486 | #define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
26487 | #define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
26488 | #define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
26489 | #define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
26490 | #define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
26491 | #define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
26492 | #define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
26493 | #define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
26494 | #define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
26495 | #define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
26496 | #define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
26497 | #define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
26498 | #define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
26499 | #define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
26500 | #define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
26501 | //BIFPLR6_0_SLOT_STATUS |
26502 | #define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
26503 | #define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
26504 | #define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
26505 | #define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
26506 | #define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
26507 | #define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
26508 | #define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
26509 | #define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
26510 | #define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
26511 | #define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
26512 | #define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
26513 | #define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
26514 | #define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
26515 | #define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
26516 | #define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
26517 | #define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
26518 | #define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
26519 | #define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
26520 | //BIFPLR6_0_ROOT_CNTL |
26521 | #define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
26522 | #define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
26523 | #define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
26524 | #define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
26525 | #define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
26526 | #define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
26527 | #define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
26528 | #define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
26529 | #define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
26530 | #define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
26531 | //BIFPLR6_0_ROOT_CAP |
26532 | #define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
26533 | #define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
26534 | //BIFPLR6_0_ROOT_STATUS |
26535 | #define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
26536 | #define BIFPLR6_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
26537 | #define BIFPLR6_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
26538 | #define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
26539 | #define BIFPLR6_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
26540 | #define BIFPLR6_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
26541 | //BIFPLR6_0_DEVICE_CAP2 |
26542 | #define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
26543 | #define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
26544 | #define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
26545 | #define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
26546 | #define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
26547 | #define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
26548 | #define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
26549 | #define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
26550 | #define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
26551 | #define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
26552 | #define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
26553 | #define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
26554 | #define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
26555 | #define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
26556 | #define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
26557 | #define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
26558 | #define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
26559 | #define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
26560 | #define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
26561 | #define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
26562 | #define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
26563 | #define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
26564 | #define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
26565 | #define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
26566 | #define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
26567 | #define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
26568 | #define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
26569 | #define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
26570 | //BIFPLR6_0_DEVICE_CNTL2 |
26571 | #define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
26572 | #define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
26573 | #define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
26574 | #define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
26575 | #define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
26576 | #define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
26577 | #define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
26578 | #define BIFPLR6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
26579 | #define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
26580 | #define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
26581 | #define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
26582 | #define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
26583 | #define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
26584 | #define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
26585 | #define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
26586 | #define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
26587 | #define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
26588 | #define BIFPLR6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
26589 | #define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
26590 | #define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
26591 | //BIFPLR6_0_DEVICE_STATUS2 |
26592 | #define BIFPLR6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
26593 | #define BIFPLR6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
26594 | //BIFPLR6_0_LINK_CAP2 |
26595 | #define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
26596 | #define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
26597 | #define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
26598 | #define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
26599 | #define BIFPLR6_0_LINK_CAP2__RESERVED__SHIFT 0x13 |
26600 | #define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
26601 | #define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
26602 | #define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
26603 | #define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
26604 | #define BIFPLR6_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
26605 | //BIFPLR6_0_LINK_CNTL2 |
26606 | #define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
26607 | #define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
26608 | #define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
26609 | #define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
26610 | #define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
26611 | #define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
26612 | #define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
26613 | #define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
26614 | #define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
26615 | #define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
26616 | #define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
26617 | #define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
26618 | #define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
26619 | #define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
26620 | #define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
26621 | #define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
26622 | //BIFPLR6_0_LINK_STATUS2 |
26623 | #define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
26624 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
26625 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
26626 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
26627 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
26628 | #define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
26629 | #define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
26630 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
26631 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
26632 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
26633 | #define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
26634 | #define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
26635 | //BIFPLR6_0_SLOT_CAP2 |
26636 | #define BIFPLR6_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
26637 | #define BIFPLR6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
26638 | //BIFPLR6_0_SLOT_CNTL2 |
26639 | #define BIFPLR6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
26640 | #define BIFPLR6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
26641 | //BIFPLR6_0_SLOT_STATUS2 |
26642 | #define BIFPLR6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
26643 | #define BIFPLR6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
26644 | //BIFPLR6_0_MSI_CAP_LIST |
26645 | #define BIFPLR6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
26646 | #define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26647 | #define BIFPLR6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
26648 | #define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26649 | //BIFPLR6_0_MSI_MSG_CNTL |
26650 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
26651 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
26652 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
26653 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
26654 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
26655 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
26656 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
26657 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
26658 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
26659 | #define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
26660 | //BIFPLR6_0_MSI_MSG_ADDR_LO |
26661 | #define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
26662 | #define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
26663 | //BIFPLR6_0_MSI_MSG_ADDR_HI |
26664 | #define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
26665 | #define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
26666 | //BIFPLR6_0_MSI_MSG_DATA |
26667 | #define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
26668 | #define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
26669 | //BIFPLR6_0_MSI_MSG_DATA_64 |
26670 | #define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
26671 | #define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
26672 | //BIFPLR6_0_SSID_CAP_LIST |
26673 | #define BIFPLR6_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
26674 | #define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26675 | #define BIFPLR6_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
26676 | #define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26677 | //BIFPLR6_0_SSID_CAP |
26678 | #define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
26679 | #define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
26680 | #define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
26681 | #define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
26682 | //BIFPLR6_0_MSI_MAP_CAP_LIST |
26683 | #define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
26684 | #define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26685 | #define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
26686 | #define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26687 | //BIFPLR6_0_MSI_MAP_CAP |
26688 | #define BIFPLR6_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
26689 | #define BIFPLR6_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
26690 | #define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
26691 | #define BIFPLR6_0_MSI_MAP_CAP__EN_MASK 0x0001L |
26692 | #define BIFPLR6_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
26693 | #define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
26694 | //BIFPLR6_0_MSI_MAP_ADDR_LO |
26695 | #define BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
26696 | #define BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
26697 | //BIFPLR6_0_MSI_MAP_ADDR_HI |
26698 | #define BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
26699 | #define BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
26700 | //BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
26701 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26702 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26703 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26704 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26705 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26706 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26707 | //BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR |
26708 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
26709 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
26710 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
26711 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
26712 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
26713 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
26714 | //BIFPLR6_0_PCIE_VENDOR_SPECIFIC1 |
26715 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
26716 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
26717 | //BIFPLR6_0_PCIE_VENDOR_SPECIFIC2 |
26718 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
26719 | #define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
26720 | //BIFPLR6_0_PCIE_VC_ENH_CAP_LIST |
26721 | #define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26722 | #define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26723 | #define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26724 | #define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26725 | #define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26726 | #define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26727 | //BIFPLR6_0_PCIE_PORT_VC_CAP_REG1 |
26728 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
26729 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
26730 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
26731 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
26732 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
26733 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
26734 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
26735 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
26736 | //BIFPLR6_0_PCIE_PORT_VC_CAP_REG2 |
26737 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
26738 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
26739 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
26740 | #define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
26741 | //BIFPLR6_0_PCIE_PORT_VC_CNTL |
26742 | #define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
26743 | #define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
26744 | #define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
26745 | #define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
26746 | //BIFPLR6_0_PCIE_PORT_VC_STATUS |
26747 | #define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
26748 | #define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
26749 | //BIFPLR6_0_PCIE_VC0_RESOURCE_CAP |
26750 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
26751 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
26752 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
26753 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
26754 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
26755 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
26756 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
26757 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
26758 | //BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL |
26759 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
26760 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
26761 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
26762 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
26763 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
26764 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
26765 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
26766 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
26767 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
26768 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
26769 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
26770 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
26771 | //BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS |
26772 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
26773 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
26774 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
26775 | #define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
26776 | //BIFPLR6_0_PCIE_VC1_RESOURCE_CAP |
26777 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
26778 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
26779 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
26780 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
26781 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
26782 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
26783 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
26784 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
26785 | //BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL |
26786 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
26787 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
26788 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
26789 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
26790 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
26791 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
26792 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
26793 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
26794 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
26795 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
26796 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
26797 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
26798 | //BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS |
26799 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
26800 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
26801 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
26802 | #define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
26803 | //BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
26804 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26805 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26806 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26807 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26808 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26809 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26810 | //BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1 |
26811 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
26812 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
26813 | //BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2 |
26814 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
26815 | #define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
26816 | //BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
26817 | #define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26818 | #define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26819 | #define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26820 | #define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26821 | #define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26822 | #define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26823 | //BIFPLR6_0_PCIE_UNCORR_ERR_STATUS |
26824 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
26825 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
26826 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
26827 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
26828 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
26829 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
26830 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
26831 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
26832 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
26833 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
26834 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
26835 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
26836 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
26837 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
26838 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
26839 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
26840 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
26841 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
26842 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
26843 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
26844 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
26845 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
26846 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
26847 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
26848 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
26849 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
26850 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
26851 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
26852 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
26853 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
26854 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
26855 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
26856 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
26857 | #define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
26858 | //BIFPLR6_0_PCIE_UNCORR_ERR_MASK |
26859 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
26860 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
26861 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
26862 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
26863 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
26864 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
26865 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
26866 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
26867 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
26868 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
26869 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
26870 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
26871 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
26872 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
26873 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
26874 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
26875 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
26876 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
26877 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
26878 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
26879 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
26880 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
26881 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
26882 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
26883 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
26884 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
26885 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
26886 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
26887 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
26888 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
26889 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
26890 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
26891 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
26892 | #define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
26893 | //BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY |
26894 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
26895 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
26896 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
26897 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
26898 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
26899 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
26900 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
26901 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
26902 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
26903 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
26904 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
26905 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
26906 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
26907 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
26908 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
26909 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
26910 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
26911 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
26912 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
26913 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
26914 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
26915 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
26916 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
26917 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
26918 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
26919 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
26920 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
26921 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
26922 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
26923 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
26924 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
26925 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
26926 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
26927 | #define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
26928 | //BIFPLR6_0_PCIE_CORR_ERR_STATUS |
26929 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
26930 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
26931 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
26932 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
26933 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
26934 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
26935 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
26936 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
26937 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
26938 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
26939 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
26940 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
26941 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
26942 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
26943 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
26944 | #define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
26945 | //BIFPLR6_0_PCIE_CORR_ERR_MASK |
26946 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
26947 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
26948 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
26949 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
26950 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
26951 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
26952 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
26953 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
26954 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
26955 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
26956 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
26957 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
26958 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
26959 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
26960 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
26961 | #define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
26962 | //BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL |
26963 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
26964 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
26965 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
26966 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
26967 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
26968 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
26969 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
26970 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
26971 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
26972 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
26973 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
26974 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
26975 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
26976 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
26977 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
26978 | #define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
26979 | //BIFPLR6_0_PCIE_HDR_LOG0 |
26980 | #define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
26981 | #define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
26982 | //BIFPLR6_0_PCIE_HDR_LOG1 |
26983 | #define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
26984 | #define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
26985 | //BIFPLR6_0_PCIE_HDR_LOG2 |
26986 | #define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
26987 | #define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
26988 | //BIFPLR6_0_PCIE_HDR_LOG3 |
26989 | #define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
26990 | #define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
26991 | //BIFPLR6_0_PCIE_ROOT_ERR_CMD |
26992 | #define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
26993 | #define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
26994 | #define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
26995 | #define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
26996 | #define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
26997 | #define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
26998 | //BIFPLR6_0_PCIE_ROOT_ERR_STATUS |
26999 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
27000 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
27001 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
27002 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
27003 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
27004 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
27005 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
27006 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
27007 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
27008 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
27009 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
27010 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
27011 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
27012 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
27013 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
27014 | #define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
27015 | //BIFPLR6_0_PCIE_ERR_SRC_ID |
27016 | #define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
27017 | #define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
27018 | #define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
27019 | #define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
27020 | //BIFPLR6_0_PCIE_TLP_PREFIX_LOG0 |
27021 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
27022 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
27023 | //BIFPLR6_0_PCIE_TLP_PREFIX_LOG1 |
27024 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
27025 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
27026 | //BIFPLR6_0_PCIE_TLP_PREFIX_LOG2 |
27027 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
27028 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
27029 | //BIFPLR6_0_PCIE_TLP_PREFIX_LOG3 |
27030 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
27031 | #define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
27032 | //BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST |
27033 | #define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27034 | #define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27035 | #define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27036 | #define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27037 | #define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27038 | #define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27039 | //BIFPLR6_0_PCIE_LINK_CNTL3 |
27040 | #define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
27041 | #define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
27042 | #define BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
27043 | #define BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
27044 | #define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
27045 | #define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
27046 | #define BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
27047 | #define BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
27048 | //BIFPLR6_0_PCIE_LANE_ERROR_STATUS |
27049 | #define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
27050 | #define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
27051 | #define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
27052 | #define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
27053 | //BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL |
27054 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27055 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27056 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27057 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27058 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27059 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27060 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27061 | #define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27062 | //BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL |
27063 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27064 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27065 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27066 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27067 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27068 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27069 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27070 | #define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27071 | //BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL |
27072 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27073 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27074 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27075 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27076 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27077 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27078 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27079 | #define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27080 | //BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL |
27081 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27082 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27083 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27084 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27085 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27086 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27087 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27088 | #define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27089 | //BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL |
27090 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27091 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27092 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27093 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27094 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27095 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27096 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27097 | #define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27098 | //BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL |
27099 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27100 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27101 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27102 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27103 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27104 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27105 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27106 | #define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27107 | //BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL |
27108 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27109 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27110 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27111 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27112 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27113 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27114 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27115 | #define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27116 | //BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL |
27117 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27118 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27119 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27120 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27121 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27122 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27123 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27124 | #define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27125 | //BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL |
27126 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27127 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27128 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27129 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27130 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27131 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27132 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27133 | #define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27134 | //BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL |
27135 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27136 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27137 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27138 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27139 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27140 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27141 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27142 | #define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27143 | //BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL |
27144 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27145 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27146 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27147 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27148 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27149 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27150 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27151 | #define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27152 | //BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL |
27153 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27154 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27155 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27156 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27157 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27158 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27159 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27160 | #define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27161 | //BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL |
27162 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27163 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27164 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27165 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27166 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27167 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27168 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27169 | #define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27170 | //BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL |
27171 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27172 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27173 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27174 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27175 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27176 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27177 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27178 | #define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27179 | //BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL |
27180 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27181 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27182 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27183 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27184 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27185 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27186 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27187 | #define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27188 | //BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL |
27189 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
27190 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
27191 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
27192 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
27193 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
27194 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
27195 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
27196 | #define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
27197 | //BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST |
27198 | #define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27199 | #define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27200 | #define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27201 | #define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27202 | #define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27203 | #define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27204 | //BIFPLR6_0_PCIE_ACS_CAP |
27205 | #define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
27206 | #define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
27207 | #define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
27208 | #define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
27209 | #define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
27210 | #define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
27211 | #define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
27212 | #define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
27213 | #define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
27214 | #define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
27215 | #define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
27216 | #define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
27217 | #define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
27218 | #define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
27219 | #define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
27220 | #define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
27221 | //BIFPLR6_0_PCIE_ACS_CNTL |
27222 | #define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
27223 | #define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
27224 | #define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
27225 | #define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
27226 | #define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
27227 | #define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
27228 | #define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
27229 | #define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
27230 | #define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
27231 | #define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
27232 | #define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
27233 | #define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
27234 | #define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
27235 | #define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
27236 | //BIFPLR6_0_PCIE_MC_ENH_CAP_LIST |
27237 | #define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27238 | #define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27239 | #define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27240 | #define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27241 | #define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27242 | #define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27243 | //BIFPLR6_0_PCIE_MC_CAP |
27244 | #define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
27245 | #define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
27246 | #define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
27247 | #define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
27248 | //BIFPLR6_0_PCIE_MC_CNTL |
27249 | #define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
27250 | #define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
27251 | #define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
27252 | #define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
27253 | //BIFPLR6_0_PCIE_MC_ADDR0 |
27254 | #define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
27255 | #define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
27256 | #define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
27257 | #define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
27258 | //BIFPLR6_0_PCIE_MC_ADDR1 |
27259 | #define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
27260 | #define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
27261 | //BIFPLR6_0_PCIE_MC_RCV0 |
27262 | #define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
27263 | #define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
27264 | //BIFPLR6_0_PCIE_MC_RCV1 |
27265 | #define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
27266 | #define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
27267 | //BIFPLR6_0_PCIE_MC_BLOCK_ALL0 |
27268 | #define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
27269 | #define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
27270 | //BIFPLR6_0_PCIE_MC_BLOCK_ALL1 |
27271 | #define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
27272 | #define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
27273 | //BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
27274 | #define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
27275 | #define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
27276 | //BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
27277 | #define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
27278 | #define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
27279 | //BIFPLR6_0_PCIE_MC_OVERLAY_BAR0 |
27280 | #define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
27281 | #define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
27282 | #define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
27283 | #define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
27284 | //BIFPLR6_0_PCIE_MC_OVERLAY_BAR1 |
27285 | #define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
27286 | #define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
27287 | //BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST |
27288 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
27289 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
27290 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27291 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27292 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27293 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27294 | //BIFPLR6_0_PCIE_L1_PM_SUB_CAP |
27295 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
27296 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
27297 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
27298 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
27299 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
27300 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
27301 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
27302 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
27303 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
27304 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
27305 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
27306 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
27307 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
27308 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
27309 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
27310 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
27311 | //BIFPLR6_0_PCIE_L1_PM_SUB_CNTL |
27312 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
27313 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
27314 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
27315 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
27316 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
27317 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
27318 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
27319 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
27320 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
27321 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
27322 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
27323 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
27324 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
27325 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
27326 | //BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2 |
27327 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
27328 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
27329 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
27330 | #define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
27331 | //BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST |
27332 | #define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27333 | #define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27334 | #define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27335 | #define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27336 | #define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27337 | #define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27338 | //BIFPLR6_0_PCIE_DPC_CAP_LIST |
27339 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
27340 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
27341 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
27342 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
27343 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
27344 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
27345 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
27346 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
27347 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
27348 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
27349 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
27350 | #define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
27351 | //BIFPLR6_0_PCIE_DPC_CNTL |
27352 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
27353 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
27354 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
27355 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
27356 | #define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
27357 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
27358 | #define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
27359 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
27360 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
27361 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
27362 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
27363 | #define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
27364 | #define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
27365 | #define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
27366 | //BIFPLR6_0_PCIE_DPC_STATUS |
27367 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
27368 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
27369 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
27370 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
27371 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
27372 | #define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
27373 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
27374 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
27375 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
27376 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
27377 | #define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
27378 | #define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
27379 | //BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID |
27380 | #define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
27381 | #define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
27382 | //BIFPLR6_0_PCIE_RP_PIO_STATUS |
27383 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
27384 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
27385 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
27386 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
27387 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
27388 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
27389 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
27390 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
27391 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
27392 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
27393 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
27394 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
27395 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
27396 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
27397 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
27398 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
27399 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
27400 | #define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
27401 | //BIFPLR6_0_PCIE_RP_PIO_MASK |
27402 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
27403 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
27404 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
27405 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
27406 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
27407 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
27408 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
27409 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
27410 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
27411 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
27412 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
27413 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
27414 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
27415 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
27416 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
27417 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
27418 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
27419 | #define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
27420 | //BIFPLR6_0_PCIE_RP_PIO_SEVERITY |
27421 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
27422 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
27423 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
27424 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
27425 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
27426 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
27427 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
27428 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
27429 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
27430 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
27431 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
27432 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
27433 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
27434 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
27435 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
27436 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
27437 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
27438 | #define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
27439 | //BIFPLR6_0_PCIE_RP_PIO_SYSERROR |
27440 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
27441 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
27442 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
27443 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
27444 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
27445 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
27446 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
27447 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
27448 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
27449 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
27450 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
27451 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
27452 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
27453 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
27454 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
27455 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
27456 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
27457 | #define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
27458 | //BIFPLR6_0_PCIE_RP_PIO_EXCEPTION |
27459 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
27460 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
27461 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
27462 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
27463 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
27464 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
27465 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
27466 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
27467 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
27468 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
27469 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
27470 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
27471 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
27472 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
27473 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
27474 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
27475 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
27476 | #define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
27477 | //BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0 |
27478 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
27479 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
27480 | //BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1 |
27481 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
27482 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
27483 | //BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2 |
27484 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
27485 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
27486 | //BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3 |
27487 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
27488 | #define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
27489 | //BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG |
27490 | #define BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
27491 | #define BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
27492 | //BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0 |
27493 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
27494 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
27495 | //BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1 |
27496 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
27497 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
27498 | //BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2 |
27499 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
27500 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
27501 | //BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3 |
27502 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
27503 | #define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
27504 | //BIFPLR6_0_PCIE_ESM_CAP_LIST |
27505 | #define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
27506 | #define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
27507 | #define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27508 | #define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27509 | #define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27510 | #define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27511 | //BIFPLR6_0_PCIE_ESM_HEADER_1 |
27512 | #define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
27513 | #define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
27514 | #define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
27515 | #define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
27516 | #define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
27517 | #define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
27518 | //BIFPLR6_0_PCIE_ESM_HEADER_2 |
27519 | #define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
27520 | #define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
27521 | //BIFPLR6_0_PCIE_ESM_STATUS |
27522 | #define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
27523 | #define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
27524 | #define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
27525 | #define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
27526 | //BIFPLR6_0_PCIE_ESM_CTRL |
27527 | #define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
27528 | #define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
27529 | #define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
27530 | #define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
27531 | #define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
27532 | #define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
27533 | //BIFPLR6_0_PCIE_ESM_CAP_1 |
27534 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
27535 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
27536 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
27537 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
27538 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
27539 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
27540 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
27541 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
27542 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
27543 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
27544 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
27545 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
27546 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
27547 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
27548 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
27549 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
27550 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
27551 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
27552 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
27553 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
27554 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
27555 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
27556 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
27557 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
27558 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
27559 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
27560 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
27561 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
27562 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
27563 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
27564 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
27565 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
27566 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
27567 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
27568 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
27569 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
27570 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
27571 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
27572 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
27573 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
27574 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
27575 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
27576 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
27577 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
27578 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
27579 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
27580 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
27581 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
27582 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
27583 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
27584 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
27585 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
27586 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
27587 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
27588 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
27589 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
27590 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
27591 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
27592 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
27593 | #define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
27594 | //BIFPLR6_0_PCIE_ESM_CAP_2 |
27595 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
27596 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
27597 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
27598 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
27599 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
27600 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
27601 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
27602 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
27603 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
27604 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
27605 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
27606 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
27607 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
27608 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
27609 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
27610 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
27611 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
27612 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
27613 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
27614 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
27615 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
27616 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
27617 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
27618 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
27619 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
27620 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
27621 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
27622 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
27623 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
27624 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
27625 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
27626 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
27627 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
27628 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
27629 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
27630 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
27631 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
27632 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
27633 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
27634 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
27635 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
27636 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
27637 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
27638 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
27639 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
27640 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
27641 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
27642 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
27643 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
27644 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
27645 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
27646 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
27647 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
27648 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
27649 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
27650 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
27651 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
27652 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
27653 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
27654 | #define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
27655 | //BIFPLR6_0_PCIE_ESM_CAP_3 |
27656 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
27657 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
27658 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
27659 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
27660 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
27661 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
27662 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
27663 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
27664 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
27665 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
27666 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
27667 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
27668 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
27669 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
27670 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
27671 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
27672 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
27673 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
27674 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
27675 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
27676 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
27677 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
27678 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
27679 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
27680 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
27681 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
27682 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
27683 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
27684 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
27685 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
27686 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
27687 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
27688 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
27689 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
27690 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
27691 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
27692 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
27693 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
27694 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
27695 | #define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
27696 | //BIFPLR6_0_PCIE_ESM_CAP_4 |
27697 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
27698 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
27699 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
27700 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
27701 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
27702 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
27703 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
27704 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
27705 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
27706 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
27707 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
27708 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
27709 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
27710 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
27711 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
27712 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
27713 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
27714 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
27715 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
27716 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
27717 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
27718 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
27719 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
27720 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
27721 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
27722 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
27723 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
27724 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
27725 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
27726 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
27727 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
27728 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
27729 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
27730 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
27731 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
27732 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
27733 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
27734 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
27735 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
27736 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
27737 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
27738 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
27739 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
27740 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
27741 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
27742 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
27743 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
27744 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
27745 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
27746 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
27747 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
27748 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
27749 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
27750 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
27751 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
27752 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
27753 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
27754 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
27755 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
27756 | #define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
27757 | //BIFPLR6_0_PCIE_ESM_CAP_5 |
27758 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
27759 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
27760 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
27761 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
27762 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
27763 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
27764 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
27765 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
27766 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
27767 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
27768 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
27769 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
27770 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
27771 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
27772 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
27773 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
27774 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
27775 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
27776 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
27777 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
27778 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
27779 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
27780 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
27781 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
27782 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
27783 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
27784 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
27785 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
27786 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
27787 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
27788 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
27789 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
27790 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
27791 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
27792 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
27793 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
27794 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
27795 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
27796 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
27797 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
27798 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
27799 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
27800 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
27801 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
27802 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
27803 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
27804 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
27805 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
27806 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
27807 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
27808 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
27809 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
27810 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
27811 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
27812 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
27813 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
27814 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
27815 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
27816 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
27817 | #define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
27818 | //BIFPLR6_0_PCIE_ESM_CAP_6 |
27819 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
27820 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
27821 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
27822 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
27823 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
27824 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
27825 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
27826 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
27827 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
27828 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
27829 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
27830 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
27831 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
27832 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
27833 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
27834 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
27835 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
27836 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
27837 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
27838 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
27839 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
27840 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
27841 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
27842 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
27843 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
27844 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
27845 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
27846 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
27847 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
27848 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
27849 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
27850 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
27851 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
27852 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
27853 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
27854 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
27855 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
27856 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
27857 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
27858 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
27859 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
27860 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
27861 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
27862 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
27863 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
27864 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
27865 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
27866 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
27867 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
27868 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
27869 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
27870 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
27871 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
27872 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
27873 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
27874 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
27875 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
27876 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
27877 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
27878 | #define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
27879 | //BIFPLR6_0_PCIE_ESM_CAP_7 |
27880 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
27881 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
27882 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
27883 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
27884 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
27885 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
27886 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
27887 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
27888 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
27889 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
27890 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
27891 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
27892 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
27893 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
27894 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
27895 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
27896 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
27897 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
27898 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
27899 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
27900 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
27901 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
27902 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
27903 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
27904 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
27905 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
27906 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
27907 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
27908 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
27909 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
27910 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
27911 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
27912 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
27913 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
27914 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
27915 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
27916 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
27917 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
27918 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
27919 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
27920 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
27921 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
27922 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
27923 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
27924 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
27925 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
27926 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
27927 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
27928 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
27929 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
27930 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
27931 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
27932 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
27933 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
27934 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
27935 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
27936 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
27937 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
27938 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
27939 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
27940 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
27941 | #define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
27942 | |
27943 | |
27944 | // addressBlock: nbio_dbgu0_dbgudec |
27945 | //port_a_addr |
27946 | #define port_a_addr__Index__SHIFT 0x0 |
27947 | #define port_a_addr__Reserved__SHIFT 0x8 |
27948 | #define port_a_addr__ReadEnable__SHIFT 0x1f |
27949 | #define port_a_addr__Index_MASK 0x000000FFL |
27950 | #define port_a_addr__Reserved_MASK 0x7FFFFF00L |
27951 | #define port_a_addr__ReadEnable_MASK 0x80000000L |
27952 | //port_a_data_lo |
27953 | #define port_a_data_lo__Data__SHIFT 0x0 |
27954 | #define port_a_data_lo__Data_MASK 0xFFFFFFFFL |
27955 | //port_a_data_hi |
27956 | #define port_a_data_hi__Data__SHIFT 0x0 |
27957 | #define port_a_data_hi__Data_MASK 0xFFFFFFFFL |
27958 | //port_b_addr |
27959 | #define port_b_addr__Index__SHIFT 0x0 |
27960 | #define port_b_addr__Reserved__SHIFT 0x8 |
27961 | #define port_b_addr__ReadEnable__SHIFT 0x1f |
27962 | #define port_b_addr__Index_MASK 0x000000FFL |
27963 | #define port_b_addr__Reserved_MASK 0x7FFFFF00L |
27964 | #define port_b_addr__ReadEnable_MASK 0x80000000L |
27965 | //port_b_data_lo |
27966 | #define port_b_data_lo__Data__SHIFT 0x0 |
27967 | #define port_b_data_lo__Data_MASK 0xFFFFFFFFL |
27968 | //port_b_data_hi |
27969 | #define port_b_data_hi__Data__SHIFT 0x0 |
27970 | #define port_b_data_hi__Data_MASK 0xFFFFFFFFL |
27971 | //port_c_addr |
27972 | #define port_c_addr__Index__SHIFT 0x0 |
27973 | #define port_c_addr__Reserved__SHIFT 0x8 |
27974 | #define port_c_addr__ReadEnable__SHIFT 0x1f |
27975 | #define port_c_addr__Index_MASK 0x000000FFL |
27976 | #define port_c_addr__Reserved_MASK 0x7FFFFF00L |
27977 | #define port_c_addr__ReadEnable_MASK 0x80000000L |
27978 | //port_c_data_lo |
27979 | #define port_c_data_lo__Data__SHIFT 0x0 |
27980 | #define port_c_data_lo__Data_MASK 0xFFFFFFFFL |
27981 | //port_c_data_hi |
27982 | #define port_c_data_hi__Data__SHIFT 0x0 |
27983 | #define port_c_data_hi__Data_MASK 0xFFFFFFFFL |
27984 | //port_d_addr |
27985 | #define port_d_addr__Index__SHIFT 0x0 |
27986 | #define port_d_addr__Reserved__SHIFT 0x8 |
27987 | #define port_d_addr__ReadEnable__SHIFT 0x1f |
27988 | #define port_d_addr__Index_MASK 0x000000FFL |
27989 | #define port_d_addr__Reserved_MASK 0x7FFFFF00L |
27990 | #define port_d_addr__ReadEnable_MASK 0x80000000L |
27991 | //port_d_data_lo |
27992 | #define port_d_data_lo__Data__SHIFT 0x0 |
27993 | #define port_d_data_lo__Data_MASK 0xFFFFFFFFL |
27994 | //port_d_data_hi |
27995 | #define port_d_data_hi__Data__SHIFT 0x0 |
27996 | #define port_d_data_hi__Data_MASK 0xFFFFFFFFL |
27997 | |
27998 | |
27999 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
28000 | //GDC0_NGDC_SDP_PORT_CTRL |
28001 | #define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
28002 | #define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL |
28003 | //GDC0_SHUB_REGS_IF_CTL |
28004 | #define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
28005 | #define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
28006 | //GDC0_NGDC_RESERVED_0 |
28007 | #define GDC0_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 |
28008 | #define GDC0_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL |
28009 | //GDC0_NGDC_RESERVED_1 |
28010 | #define GDC0_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 |
28011 | #define GDC0_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL |
28012 | //GDC0_NGDC_SDP_PORT_CTRL_SOCCLK |
28013 | #define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 |
28014 | #define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL |
28015 | //GDC0_BIF_SDMA0_DOORBELL_RANGE |
28016 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
28017 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
28018 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
28019 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
28020 | //GDC0_BIF_SDMA1_DOORBELL_RANGE |
28021 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
28022 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
28023 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
28024 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
28025 | //GDC0_BIF_IH_DOORBELL_RANGE |
28026 | #define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
28027 | #define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
28028 | #define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
28029 | #define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
28030 | //GDC0_BIF_MMSCH0_DOORBELL_RANGE |
28031 | #define GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
28032 | #define GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
28033 | #define GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
28034 | #define GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
28035 | //GDC0_ATDMA_MISC_CNTL |
28036 | #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 |
28037 | #define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 |
28038 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 |
28039 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 |
28040 | #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L |
28041 | #define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L |
28042 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L |
28043 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L |
28044 | //GDC0_BIF_DOORBELL_FENCE_CNTL |
28045 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 |
28046 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L |
28047 | //GDC0_S2A_MISC_CNTL |
28048 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 |
28049 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 |
28050 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 |
28051 | #define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 |
28052 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L |
28053 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L |
28054 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L |
28055 | #define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L |
28056 | //GDC0_GDC_PG_MISC_CNTL |
28057 | #define GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0 |
28058 | #define GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L |
28059 | |
28060 | |
28061 | // addressBlock: nbio_nbif0_syshub_mmreg_direct_syshubdirect |
28062 | //SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK |
28063 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 |
28064 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 |
28065 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 |
28066 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 |
28067 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 |
28068 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 |
28069 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 |
28070 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 |
28071 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 |
28072 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 |
28073 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 |
28074 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 |
28075 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 |
28076 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 |
28077 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 |
28078 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 |
28079 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c |
28080 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f |
28081 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L |
28082 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L |
28083 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L |
28084 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L |
28085 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L |
28086 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L |
28087 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L |
28088 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L |
28089 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L |
28090 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L |
28091 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L |
28092 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L |
28093 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L |
28094 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L |
28095 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L |
28096 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L |
28097 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L |
28098 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L |
28099 | //SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK |
28100 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 |
28101 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL |
28102 | //SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK |
28103 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 |
28104 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 |
28105 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf |
28106 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 |
28107 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 |
28108 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L |
28109 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L |
28110 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L |
28111 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L |
28112 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L |
28113 | //SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK |
28114 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 |
28115 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 |
28116 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf |
28117 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 |
28118 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 |
28119 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L |
28120 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L |
28121 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L |
28122 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L |
28123 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L |
28124 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL |
28125 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
28126 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
28127 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
28128 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
28129 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
28130 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
28131 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL |
28132 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
28133 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
28134 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
28135 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
28136 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
28137 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
28138 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL |
28139 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
28140 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
28141 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
28142 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
28143 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
28144 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
28145 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL |
28146 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28147 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28148 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28149 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28150 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28151 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28152 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28153 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28154 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28155 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28156 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28157 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28158 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL |
28159 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28160 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28161 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28162 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28163 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28164 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28165 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28166 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28167 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28168 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28169 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28170 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28171 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL |
28172 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28173 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28174 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28175 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28176 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28177 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28178 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28179 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28180 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28181 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28182 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28183 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28184 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL |
28185 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28186 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28187 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28188 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28189 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28190 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28191 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28192 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28193 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28194 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28195 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28196 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28197 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL |
28198 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28199 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28200 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28201 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28202 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28203 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28204 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28205 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28206 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28207 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28208 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28209 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28210 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL |
28211 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28212 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28213 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28214 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28215 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28216 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28217 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28218 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28219 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28220 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28221 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28222 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28223 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL |
28224 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28225 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28226 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28227 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28228 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28229 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28230 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28231 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28232 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28233 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28234 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28235 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28236 | //SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL |
28237 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28238 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28239 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28240 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28241 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28242 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28243 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28244 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28245 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28246 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28247 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28248 | #define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28249 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL |
28250 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28251 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28252 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28253 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28254 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL |
28255 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28256 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28257 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28258 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28259 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL |
28260 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28261 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28262 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28263 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28264 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL |
28265 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28266 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28267 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28268 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28269 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL |
28270 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28271 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28272 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28273 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28274 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL |
28275 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28276 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28277 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28278 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28279 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL |
28280 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28281 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28282 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28283 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28284 | //SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL |
28285 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28286 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28287 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28288 | #define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28289 | //SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL |
28290 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 |
28291 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 |
28292 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 |
28293 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L |
28294 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L |
28295 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L |
28296 | //SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE |
28297 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 |
28298 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 |
28299 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 |
28300 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 |
28301 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 |
28302 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 |
28303 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 |
28304 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 |
28305 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 |
28306 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 |
28307 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa |
28308 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb |
28309 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc |
28310 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd |
28311 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe |
28312 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf |
28313 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 |
28314 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L |
28315 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L |
28316 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L |
28317 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L |
28318 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L |
28319 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L |
28320 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L |
28321 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L |
28322 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L |
28323 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L |
28324 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L |
28325 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L |
28326 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L |
28327 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L |
28328 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L |
28329 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L |
28330 | #define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L |
28331 | //SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER |
28332 | #define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 |
28333 | #define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL |
28334 | //SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK |
28335 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 |
28336 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 |
28337 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 |
28338 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa |
28339 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb |
28340 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc |
28341 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd |
28342 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L |
28343 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L |
28344 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL |
28345 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L |
28346 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L |
28347 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L |
28348 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L |
28349 | //SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET |
28350 | #define SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET__SHIFT 0x0 |
28351 | #define SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET_MASK 0x00000001L |
28352 | //SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH |
28353 | #define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 |
28354 | #define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
28355 | //SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK |
28356 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1 |
28357 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2 |
28358 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L |
28359 | #define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L |
28360 | //SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK |
28361 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 |
28362 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 |
28363 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 |
28364 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 |
28365 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 |
28366 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 |
28367 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 |
28368 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 |
28369 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 |
28370 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 |
28371 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 |
28372 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 |
28373 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 |
28374 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 |
28375 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 |
28376 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 |
28377 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c |
28378 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f |
28379 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L |
28380 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L |
28381 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L |
28382 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L |
28383 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L |
28384 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L |
28385 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L |
28386 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L |
28387 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L |
28388 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L |
28389 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L |
28390 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L |
28391 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L |
28392 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L |
28393 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L |
28394 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L |
28395 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L |
28396 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L |
28397 | //SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK |
28398 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 |
28399 | #define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL |
28400 | //SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK |
28401 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf |
28402 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 |
28403 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L |
28404 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L |
28405 | //SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK |
28406 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf |
28407 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 |
28408 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L |
28409 | #define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L |
28410 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL |
28411 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
28412 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
28413 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
28414 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
28415 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
28416 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
28417 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL |
28418 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
28419 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
28420 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
28421 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
28422 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
28423 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
28424 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL |
28425 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28426 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28427 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28428 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28429 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28430 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28431 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28432 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28433 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28434 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28435 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28436 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28437 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL |
28438 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28439 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28440 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28441 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28442 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28443 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28444 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28445 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28446 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28447 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28448 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28449 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28450 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL |
28451 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28452 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28453 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28454 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28455 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28456 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28457 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28458 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28459 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28460 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28461 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28462 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28463 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL |
28464 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28465 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28466 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28467 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28468 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28469 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28470 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28471 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28472 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28473 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28474 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28475 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28476 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL |
28477 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28478 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28479 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28480 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28481 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28482 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28483 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28484 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28485 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28486 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28487 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28488 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28489 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL |
28490 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28491 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28492 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28493 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28494 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28495 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28496 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28497 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28498 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28499 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28500 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28501 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28502 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL |
28503 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28504 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28505 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28506 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28507 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28508 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28509 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28510 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28511 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28512 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28513 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28514 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28515 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL |
28516 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28517 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28518 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28519 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28520 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28521 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28522 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28523 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28524 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28525 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28526 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28527 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28528 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL |
28529 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28530 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28531 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28532 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28533 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28534 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28535 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28536 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28537 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28538 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28539 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28540 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28541 | //SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL |
28542 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
28543 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
28544 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
28545 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
28546 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
28547 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
28548 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
28549 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
28550 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
28551 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
28552 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
28553 | #define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
28554 | //SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK |
28555 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0 |
28556 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1 |
28557 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2 |
28558 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa |
28559 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb |
28560 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc |
28561 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L |
28562 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L |
28563 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL |
28564 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L |
28565 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L |
28566 | #define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L |
28567 | //SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD |
28568 | #define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28569 | #define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28570 | #define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28571 | #define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28572 | //SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS |
28573 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
28574 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
28575 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
28576 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
28577 | //SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS |
28578 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
28579 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
28580 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
28581 | #define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
28582 | //SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD |
28583 | #define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28584 | #define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28585 | #define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28586 | #define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28587 | //SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD |
28588 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28589 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28590 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28591 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28592 | //SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD |
28593 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
28594 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
28595 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
28596 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
28597 | //SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD |
28598 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0 |
28599 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1 |
28600 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L |
28601 | #define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L |
28602 | //SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD |
28603 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28604 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28605 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28606 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28607 | //SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD |
28608 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
28609 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
28610 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
28611 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
28612 | //SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD |
28613 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 |
28614 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 |
28615 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L |
28616 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L |
28617 | //SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD |
28618 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 |
28619 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 |
28620 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L |
28621 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L |
28622 | //SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD |
28623 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 |
28624 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 |
28625 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L |
28626 | #define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L |
28627 | //SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS |
28628 | #define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
28629 | #define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
28630 | #define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
28631 | #define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
28632 | //SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD |
28633 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28634 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28635 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28636 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28637 | //SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD |
28638 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
28639 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
28640 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
28641 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
28642 | //SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD |
28643 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 |
28644 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 |
28645 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L |
28646 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L |
28647 | //SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD |
28648 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 |
28649 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 |
28650 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L |
28651 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L |
28652 | //SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD |
28653 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 |
28654 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 |
28655 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L |
28656 | #define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L |
28657 | //SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD |
28658 | #define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28659 | #define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28660 | #define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28661 | #define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28662 | //SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD |
28663 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28664 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28665 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28666 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28667 | //SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD |
28668 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
28669 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
28670 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
28671 | #define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
28672 | //SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD |
28673 | #define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
28674 | #define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
28675 | #define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
28676 | #define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
28677 | |
28678 | |
28679 | // addressBlock: nbio_nbif0_nbif_sion_SIONDEC |
28680 | //SION_CL0_RdRsp_BurstTarget_REG0 |
28681 | #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
28682 | #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28683 | //SION_CL0_RdRsp_BurstTarget_REG1 |
28684 | #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
28685 | #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28686 | //SION_CL0_RdRsp_TimeSlot_REG0 |
28687 | #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
28688 | #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28689 | //SION_CL0_RdRsp_TimeSlot_REG1 |
28690 | #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
28691 | #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28692 | //SION_CL0_WrRsp_BurstTarget_REG0 |
28693 | #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
28694 | #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28695 | //SION_CL0_WrRsp_BurstTarget_REG1 |
28696 | #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
28697 | #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28698 | //SION_CL0_WrRsp_TimeSlot_REG0 |
28699 | #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
28700 | #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28701 | //SION_CL0_WrRsp_TimeSlot_REG1 |
28702 | #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
28703 | #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28704 | //SION_CL0_Req_BurstTarget_REG0 |
28705 | #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
28706 | #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28707 | //SION_CL0_Req_BurstTarget_REG1 |
28708 | #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
28709 | #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28710 | //SION_CL0_Req_TimeSlot_REG0 |
28711 | #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
28712 | #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28713 | //SION_CL0_Req_TimeSlot_REG1 |
28714 | #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
28715 | #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28716 | //SION_CL0_ReqPoolCredit_Alloc_REG0 |
28717 | #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
28718 | #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28719 | //SION_CL0_ReqPoolCredit_Alloc_REG1 |
28720 | #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
28721 | #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28722 | //SION_CL0_DataPoolCredit_Alloc_REG0 |
28723 | #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
28724 | #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28725 | //SION_CL0_DataPoolCredit_Alloc_REG1 |
28726 | #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
28727 | #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28728 | //SION_CL0_RdRspPoolCredit_Alloc_REG0 |
28729 | #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28730 | #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28731 | //SION_CL0_RdRspPoolCredit_Alloc_REG1 |
28732 | #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28733 | #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28734 | //SION_CL0_WrRspPoolCredit_Alloc_REG0 |
28735 | #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28736 | #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28737 | //SION_CL0_WrRspPoolCredit_Alloc_REG1 |
28738 | #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28739 | #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28740 | //SION_CL1_RdRsp_BurstTarget_REG0 |
28741 | #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
28742 | #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28743 | //SION_CL1_RdRsp_BurstTarget_REG1 |
28744 | #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
28745 | #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28746 | //SION_CL1_RdRsp_TimeSlot_REG0 |
28747 | #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
28748 | #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28749 | //SION_CL1_RdRsp_TimeSlot_REG1 |
28750 | #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
28751 | #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28752 | //SION_CL1_WrRsp_BurstTarget_REG0 |
28753 | #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
28754 | #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28755 | //SION_CL1_WrRsp_BurstTarget_REG1 |
28756 | #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
28757 | #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28758 | //SION_CL1_WrRsp_TimeSlot_REG0 |
28759 | #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
28760 | #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28761 | //SION_CL1_WrRsp_TimeSlot_REG1 |
28762 | #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
28763 | #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28764 | //SION_CL1_Req_BurstTarget_REG0 |
28765 | #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
28766 | #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28767 | //SION_CL1_Req_BurstTarget_REG1 |
28768 | #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
28769 | #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28770 | //SION_CL1_Req_TimeSlot_REG0 |
28771 | #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
28772 | #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28773 | //SION_CL1_Req_TimeSlot_REG1 |
28774 | #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
28775 | #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28776 | //SION_CL1_ReqPoolCredit_Alloc_REG0 |
28777 | #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
28778 | #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28779 | //SION_CL1_ReqPoolCredit_Alloc_REG1 |
28780 | #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
28781 | #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28782 | //SION_CL1_DataPoolCredit_Alloc_REG0 |
28783 | #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
28784 | #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28785 | //SION_CL1_DataPoolCredit_Alloc_REG1 |
28786 | #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
28787 | #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28788 | //SION_CL1_RdRspPoolCredit_Alloc_REG0 |
28789 | #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28790 | #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28791 | //SION_CL1_RdRspPoolCredit_Alloc_REG1 |
28792 | #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28793 | #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28794 | //SION_CL1_WrRspPoolCredit_Alloc_REG0 |
28795 | #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28796 | #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28797 | //SION_CL1_WrRspPoolCredit_Alloc_REG1 |
28798 | #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28799 | #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28800 | //SION_CL2_RdRsp_BurstTarget_REG0 |
28801 | #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
28802 | #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28803 | //SION_CL2_RdRsp_BurstTarget_REG1 |
28804 | #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
28805 | #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28806 | //SION_CL2_RdRsp_TimeSlot_REG0 |
28807 | #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
28808 | #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28809 | //SION_CL2_RdRsp_TimeSlot_REG1 |
28810 | #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
28811 | #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28812 | //SION_CL2_WrRsp_BurstTarget_REG0 |
28813 | #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
28814 | #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28815 | //SION_CL2_WrRsp_BurstTarget_REG1 |
28816 | #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
28817 | #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28818 | //SION_CL2_WrRsp_TimeSlot_REG0 |
28819 | #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
28820 | #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28821 | //SION_CL2_WrRsp_TimeSlot_REG1 |
28822 | #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
28823 | #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28824 | //SION_CL2_Req_BurstTarget_REG0 |
28825 | #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
28826 | #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28827 | //SION_CL2_Req_BurstTarget_REG1 |
28828 | #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
28829 | #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28830 | //SION_CL2_Req_TimeSlot_REG0 |
28831 | #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
28832 | #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28833 | //SION_CL2_Req_TimeSlot_REG1 |
28834 | #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
28835 | #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28836 | //SION_CL2_ReqPoolCredit_Alloc_REG0 |
28837 | #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
28838 | #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28839 | //SION_CL2_ReqPoolCredit_Alloc_REG1 |
28840 | #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
28841 | #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28842 | //SION_CL2_DataPoolCredit_Alloc_REG0 |
28843 | #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
28844 | #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28845 | //SION_CL2_DataPoolCredit_Alloc_REG1 |
28846 | #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
28847 | #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28848 | //SION_CL2_RdRspPoolCredit_Alloc_REG0 |
28849 | #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28850 | #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28851 | //SION_CL2_RdRspPoolCredit_Alloc_REG1 |
28852 | #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28853 | #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28854 | //SION_CL2_WrRspPoolCredit_Alloc_REG0 |
28855 | #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28856 | #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28857 | //SION_CL2_WrRspPoolCredit_Alloc_REG1 |
28858 | #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28859 | #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28860 | //SION_CL3_RdRsp_BurstTarget_REG0 |
28861 | #define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
28862 | #define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28863 | //SION_CL3_RdRsp_BurstTarget_REG1 |
28864 | #define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
28865 | #define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28866 | //SION_CL3_RdRsp_TimeSlot_REG0 |
28867 | #define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
28868 | #define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28869 | //SION_CL3_RdRsp_TimeSlot_REG1 |
28870 | #define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
28871 | #define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28872 | //SION_CL3_WrRsp_BurstTarget_REG0 |
28873 | #define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
28874 | #define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28875 | //SION_CL3_WrRsp_BurstTarget_REG1 |
28876 | #define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
28877 | #define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28878 | //SION_CL3_WrRsp_TimeSlot_REG0 |
28879 | #define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
28880 | #define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28881 | //SION_CL3_WrRsp_TimeSlot_REG1 |
28882 | #define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
28883 | #define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28884 | //SION_CL3_Req_BurstTarget_REG0 |
28885 | #define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
28886 | #define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
28887 | //SION_CL3_Req_BurstTarget_REG1 |
28888 | #define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
28889 | #define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
28890 | //SION_CL3_Req_TimeSlot_REG0 |
28891 | #define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
28892 | #define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
28893 | //SION_CL3_Req_TimeSlot_REG1 |
28894 | #define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
28895 | #define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
28896 | //SION_CL3_ReqPoolCredit_Alloc_REG0 |
28897 | #define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
28898 | #define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28899 | //SION_CL3_ReqPoolCredit_Alloc_REG1 |
28900 | #define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
28901 | #define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28902 | //SION_CL3_DataPoolCredit_Alloc_REG0 |
28903 | #define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
28904 | #define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28905 | //SION_CL3_DataPoolCredit_Alloc_REG1 |
28906 | #define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
28907 | #define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28908 | //SION_CL3_RdRspPoolCredit_Alloc_REG0 |
28909 | #define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28910 | #define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28911 | //SION_CL3_RdRspPoolCredit_Alloc_REG1 |
28912 | #define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28913 | #define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28914 | //SION_CL3_WrRspPoolCredit_Alloc_REG0 |
28915 | #define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
28916 | #define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
28917 | //SION_CL3_WrRspPoolCredit_Alloc_REG1 |
28918 | #define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
28919 | #define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
28920 | //SION_CNTL_REG0 |
28921 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 |
28922 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 |
28923 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 |
28924 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 |
28925 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 |
28926 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 |
28927 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 |
28928 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 |
28929 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 |
28930 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 |
28931 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa |
28932 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb |
28933 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc |
28934 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd |
28935 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe |
28936 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf |
28937 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 |
28938 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 |
28939 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 |
28940 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 |
28941 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L |
28942 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L |
28943 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L |
28944 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L |
28945 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L |
28946 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L |
28947 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L |
28948 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L |
28949 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L |
28950 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L |
28951 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L |
28952 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L |
28953 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L |
28954 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L |
28955 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L |
28956 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L |
28957 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L |
28958 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L |
28959 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L |
28960 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L |
28961 | //SION_CNTL_REG1 |
28962 | #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 |
28963 | #define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 |
28964 | #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL |
28965 | #define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L |
28966 | |
28967 | |
28968 | // addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC |
28969 | //SHUB_PF_FLR_RST |
28970 | #define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 |
28971 | #define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 |
28972 | #define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 |
28973 | #define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 |
28974 | #define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 |
28975 | #define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 |
28976 | #define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 |
28977 | #define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 |
28978 | #define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8 |
28979 | #define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9 |
28980 | #define SHUB_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa |
28981 | #define SHUB_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb |
28982 | #define SHUB_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc |
28983 | #define SHUB_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd |
28984 | #define SHUB_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe |
28985 | #define SHUB_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf |
28986 | #define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L |
28987 | #define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L |
28988 | #define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L |
28989 | #define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L |
28990 | #define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L |
28991 | #define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L |
28992 | #define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L |
28993 | #define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L |
28994 | #define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L |
28995 | #define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L |
28996 | #define SHUB_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L |
28997 | #define SHUB_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L |
28998 | #define SHUB_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L |
28999 | #define SHUB_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L |
29000 | #define SHUB_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L |
29001 | #define SHUB_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L |
29002 | //SHUB_GFX_DRV_VPU_RST |
29003 | #define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 |
29004 | #define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L |
29005 | //SHUB_LINK_RESET |
29006 | #define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 |
29007 | #define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 |
29008 | #define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L |
29009 | #define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L |
29010 | //SHUB_PF0_VF_FLR_RST |
29011 | #define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 |
29012 | #define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 |
29013 | #define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 |
29014 | #define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 |
29015 | #define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 |
29016 | #define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 |
29017 | #define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 |
29018 | #define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 |
29019 | #define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 |
29020 | #define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 |
29021 | #define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa |
29022 | #define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb |
29023 | #define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc |
29024 | #define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd |
29025 | #define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe |
29026 | #define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf |
29027 | #define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f |
29028 | #define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L |
29029 | #define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L |
29030 | #define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L |
29031 | #define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L |
29032 | #define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L |
29033 | #define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L |
29034 | #define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L |
29035 | #define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L |
29036 | #define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L |
29037 | #define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L |
29038 | #define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L |
29039 | #define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L |
29040 | #define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L |
29041 | #define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L |
29042 | #define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L |
29043 | #define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L |
29044 | #define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L |
29045 | //SHUB_HARD_RST_CTRL |
29046 | #define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 |
29047 | #define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 |
29048 | #define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 |
29049 | #define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 |
29050 | #define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 |
29051 | #define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L |
29052 | #define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L |
29053 | #define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L |
29054 | #define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L |
29055 | #define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L |
29056 | //SHUB_SOFT_RST_CTRL |
29057 | #define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 |
29058 | #define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 |
29059 | #define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 |
29060 | #define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 |
29061 | #define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 |
29062 | #define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L |
29063 | #define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L |
29064 | #define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L |
29065 | #define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L |
29066 | #define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L |
29067 | //SHUB_SDP_PORT_RST |
29068 | #define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0 |
29069 | #define SHUB_SDP_PORT_RST__SDP_PORT_RST_MASK 0x00000001L |
29070 | //SHUB_RST_MISC_TRL |
29071 | #define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC__SHIFT 0x0 |
29072 | #define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE__SHIFT 0x10 |
29073 | #define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC_MASK 0x00000001L |
29074 | #define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L |
29075 | |
29076 | |
29077 | // addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk |
29078 | //GDC_RAS_LEAF0_CTRL |
29079 | #define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 |
29080 | #define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
29081 | #define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 |
29082 | #define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 |
29083 | #define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
29084 | #define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
29085 | #define GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
29086 | #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
29087 | #define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
29088 | #define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 |
29089 | #define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
29090 | #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
29091 | #define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 |
29092 | #define GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L |
29093 | #define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
29094 | #define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L |
29095 | #define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L |
29096 | #define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
29097 | #define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
29098 | #define GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
29099 | #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
29100 | #define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
29101 | #define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L |
29102 | #define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
29103 | #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
29104 | #define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L |
29105 | //GDC_RAS_LEAF1_CTRL |
29106 | #define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 |
29107 | #define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
29108 | #define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 |
29109 | #define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 |
29110 | #define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
29111 | #define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
29112 | #define GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
29113 | #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
29114 | #define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
29115 | #define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 |
29116 | #define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
29117 | #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
29118 | #define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 |
29119 | #define GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L |
29120 | #define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
29121 | #define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L |
29122 | #define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L |
29123 | #define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
29124 | #define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
29125 | #define GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
29126 | #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
29127 | #define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
29128 | #define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L |
29129 | #define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
29130 | #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
29131 | #define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L |
29132 | //GDC_RAS_LEAF2_CTRL |
29133 | #define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 |
29134 | #define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
29135 | #define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 |
29136 | #define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 |
29137 | #define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
29138 | #define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
29139 | #define GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
29140 | #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
29141 | #define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
29142 | #define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 |
29143 | #define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
29144 | #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
29145 | #define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 |
29146 | #define GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L |
29147 | #define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
29148 | #define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L |
29149 | #define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L |
29150 | #define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
29151 | #define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
29152 | #define GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
29153 | #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
29154 | #define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
29155 | #define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L |
29156 | #define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
29157 | #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
29158 | #define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L |
29159 | //GDC_RAS_LEAF3_CTRL |
29160 | #define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0 |
29161 | #define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
29162 | #define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 |
29163 | #define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4 |
29164 | #define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
29165 | #define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
29166 | #define GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
29167 | #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
29168 | #define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
29169 | #define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12 |
29170 | #define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
29171 | #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
29172 | #define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15 |
29173 | #define GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK 0x00000001L |
29174 | #define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
29175 | #define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L |
29176 | #define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK 0x00000010L |
29177 | #define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
29178 | #define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
29179 | #define GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
29180 | #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
29181 | #define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
29182 | #define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK 0x00040000L |
29183 | #define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
29184 | #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
29185 | #define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK 0x00200000L |
29186 | //GDC_RAS_LEAF4_CTRL |
29187 | #define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0 |
29188 | #define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
29189 | #define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 |
29190 | #define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4 |
29191 | #define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
29192 | #define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
29193 | #define GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
29194 | #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
29195 | #define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
29196 | #define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12 |
29197 | #define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
29198 | #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
29199 | #define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15 |
29200 | #define GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK 0x00000001L |
29201 | #define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
29202 | #define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L |
29203 | #define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK 0x00000010L |
29204 | #define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
29205 | #define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
29206 | #define GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
29207 | #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
29208 | #define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
29209 | #define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK 0x00040000L |
29210 | #define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
29211 | #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
29212 | #define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK 0x00200000L |
29213 | //GDC_RAS_LEAF5_CTRL |
29214 | #define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0 |
29215 | #define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
29216 | #define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 |
29217 | #define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4 |
29218 | #define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
29219 | #define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
29220 | #define GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
29221 | #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
29222 | #define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
29223 | #define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12 |
29224 | #define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
29225 | #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
29226 | #define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15 |
29227 | #define GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK 0x00000001L |
29228 | #define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
29229 | #define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L |
29230 | #define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK 0x00000010L |
29231 | #define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
29232 | #define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
29233 | #define GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
29234 | #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
29235 | #define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
29236 | #define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK 0x00040000L |
29237 | #define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
29238 | #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
29239 | #define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK 0x00200000L |
29240 | |
29241 | |
29242 | // addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg |
29243 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0 |
29244 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 |
29245 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT 0x9 |
29246 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT 0xc |
29247 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL |
29248 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK 0x00000E00L |
29249 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK 0xFFFFF000L |
29250 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1 |
29251 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT 0x0 |
29252 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT 0x14 |
29253 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK 0x000FFFFFL |
29254 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK 0xFFF00000L |
29255 | //IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0 |
29256 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT 0x0 |
29257 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT 0xc |
29258 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK 0x00000FFFL |
29259 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK 0xFFFFF000L |
29260 | //IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1 |
29261 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT 0x0 |
29262 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT 0x14 |
29263 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT 0x18 |
29264 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT 0x1c |
29265 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK 0x000FFFFFL |
29266 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK 0x00F00000L |
29267 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK 0x0F000000L |
29268 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK 0xF0000000L |
29269 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0 |
29270 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT 0x0 |
29271 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT 0xc |
29272 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK 0x00000FFFL |
29273 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK 0xFFFFF000L |
29274 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1 |
29275 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT 0x0 |
29276 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT 0x14 |
29277 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT 0x18 |
29278 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT 0x1c |
29279 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK 0x000FFFFFL |
29280 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK 0x00F00000L |
29281 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK 0x0F000000L |
29282 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK 0xF0000000L |
29283 | //IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0 |
29284 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 |
29285 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 |
29286 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 |
29287 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 |
29288 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 |
29289 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 |
29290 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 |
29291 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 |
29292 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa |
29293 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb |
29294 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc |
29295 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd |
29296 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT 0xe |
29297 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf |
29298 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 |
29299 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 |
29300 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 |
29301 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16 |
29302 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18 |
29303 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19 |
29304 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT 0x1c |
29305 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT 0x1d |
29306 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT 0x1e |
29307 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L |
29308 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L |
29309 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L |
29310 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L |
29311 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L |
29312 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L |
29313 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L |
29314 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L |
29315 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L |
29316 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L |
29317 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L |
29318 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L |
29319 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK 0x00004000L |
29320 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L |
29321 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L |
29322 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L |
29323 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L |
29324 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L |
29325 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L |
29326 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L |
29327 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK 0x10000000L |
29328 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK 0x20000000L |
29329 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ_MASK 0xC0000000L |
29330 | //IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1 |
29331 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT 0x0 |
29332 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 |
29333 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT 0x4 |
29334 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5 |
29335 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT 0x7 |
29336 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT 0x8 |
29337 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT 0x9 |
29338 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT 0xa |
29339 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT 0xb |
29340 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT 0xc |
29341 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd |
29342 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT 0xe |
29343 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT 0x10 |
29344 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT 0x11 |
29345 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ_MASK 0x00000003L |
29346 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL |
29347 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1_MASK 0x00000010L |
29348 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L |
29349 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK 0x00000080L |
29350 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en_MASK 0x00000100L |
29351 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK 0x00000200L |
29352 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK 0x00000400L |
29353 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK 0x00000800L |
29354 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK 0x00001000L |
29355 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L |
29356 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK 0x0000C000L |
29357 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK 0x00010000L |
29358 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0_MASK 0xFFFE0000L |
29359 | //IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0 |
29360 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 |
29361 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 |
29362 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 |
29363 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc |
29364 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L |
29365 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L |
29366 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL |
29367 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L |
29368 | //IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1 |
29369 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 |
29370 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 |
29371 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL |
29372 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L |
29373 | //IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0 |
29374 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 |
29375 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc |
29376 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL |
29377 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L |
29378 | //IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1 |
29379 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 |
29380 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 |
29381 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL |
29382 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L |
29383 | //IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0 |
29384 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT 0x0 |
29385 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT 0x1 |
29386 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP__SHIFT 0x2 |
29387 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP__SHIFT 0x3 |
29388 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP__SHIFT 0x4 |
29389 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved__SHIFT 0x5 |
29390 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP__SHIFT 0x6 |
29391 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP__SHIFT 0x7 |
29392 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP__SHIFT 0x8 |
29393 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP__SHIFT 0x9 |
29394 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS__SHIFT 0xa |
29395 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS__SHIFT 0xc |
29396 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT 0xe |
29397 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT 0x10 |
29398 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT 0x12 |
29399 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT 0x15 |
29400 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF__SHIFT 0x18 |
29401 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF__SHIFT 0x1a |
29402 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF__SHIFT 0x1c |
29403 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT 0x1e |
29404 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1__SHIFT 0x1f |
29405 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP_MASK 0x00000001L |
29406 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP_MASK 0x00000002L |
29407 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP_MASK 0x00000004L |
29408 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP_MASK 0x00000008L |
29409 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP_MASK 0x00000010L |
29410 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved_MASK 0x00000020L |
29411 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP_MASK 0x00000040L |
29412 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP_MASK 0x00000080L |
29413 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP_MASK 0x00000100L |
29414 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP_MASK 0x00000200L |
29415 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS_MASK 0x00000C00L |
29416 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS_MASK 0x00003000L |
29417 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP_MASK 0x0000C000L |
29418 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP_MASK 0x00030000L |
29419 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC_MASK 0x001C0000L |
29420 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP_MASK 0x00E00000L |
29421 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF_MASK 0x03000000L |
29422 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF_MASK 0x0C000000L |
29423 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF_MASK 0x30000000L |
29424 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK 0x40000000L |
29425 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1_MASK 0x80000000L |
29426 | //IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1 |
29427 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT 0x0 |
29428 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1__SHIFT 0x4 |
29429 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP__SHIFT 0x5 |
29430 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg__SHIFT 0x6 |
29431 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT 0x8 |
29432 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT 0x9 |
29433 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum__SHIFT 0xa |
29434 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT 0xc |
29435 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT 0xd |
29436 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT 0xe |
29437 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT 0xf |
29438 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT 0x10 |
29439 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP__SHIFT 0x11 |
29440 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT 0x12 |
29441 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT 0x13 |
29442 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP__SHIFT 0x14 |
29443 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT 0x15 |
29444 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT 0x16 |
29445 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0__SHIFT 0x17 |
29446 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX_MASK 0x0000000FL |
29447 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1_MASK 0x00000010L |
29448 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP_MASK 0x00000020L |
29449 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg_MASK 0x000000C0L |
29450 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK 0x00000100L |
29451 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK 0x00000200L |
29452 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum_MASK 0x00000C00L |
29453 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK 0x00001000L |
29454 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK 0x00002000L |
29455 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK 0x00004000L |
29456 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK 0x00008000L |
29457 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP_MASK 0x00010000L |
29458 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP_MASK 0x00020000L |
29459 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP_MASK 0x00040000L |
29460 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK 0x00080000L |
29461 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP_MASK 0x00100000L |
29462 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK 0x00200000L |
29463 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK 0x00400000L |
29464 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0_MASK 0xFF800000L |
29465 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0 |
29466 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT 0x0 |
29467 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT 0xc |
29468 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK 0x00000FFFL |
29469 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK 0xFFFFF000L |
29470 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1 |
29471 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT 0x0 |
29472 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT 0x14 |
29473 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT 0x18 |
29474 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT 0x1c |
29475 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK 0x000FFFFFL |
29476 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK 0x00F00000L |
29477 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK 0x0F000000L |
29478 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK 0xF0000000L |
29479 | //IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0 |
29480 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0 |
29481 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL |
29482 | //IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1 |
29483 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0 |
29484 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c |
29485 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL |
29486 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L |
29487 | //IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0 |
29488 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0 |
29489 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL |
29490 | //IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1 |
29491 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0 |
29492 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL |
29493 | //IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0 |
29494 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT 0x0 |
29495 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT 0x1 |
29496 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT 0x2 |
29497 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK 0x00000001L |
29498 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK 0x00000002L |
29499 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFFCL |
29500 | //IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1 |
29501 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT 0x0 |
29502 | #define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL |
29503 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0 |
29504 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0 |
29505 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10 |
29506 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11 |
29507 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12 |
29508 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL |
29509 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L |
29510 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L |
29511 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L |
29512 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1 |
29513 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved__SHIFT 0x0 |
29514 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved_MASK 0xFFFFFFFFL |
29515 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0 |
29516 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0 |
29517 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10 |
29518 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11 |
29519 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12 |
29520 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL |
29521 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L |
29522 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L |
29523 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L |
29524 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1 |
29525 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved__SHIFT 0x0 |
29526 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved_MASK 0xFFFFFFFFL |
29527 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0 |
29528 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0 |
29529 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10 |
29530 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11 |
29531 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12 |
29532 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL |
29533 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L |
29534 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L |
29535 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L |
29536 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1 |
29537 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved__SHIFT 0x0 |
29538 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved_MASK 0xFFFFFFFFL |
29539 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0 |
29540 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0 |
29541 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10 |
29542 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11 |
29543 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12 |
29544 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL |
29545 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L |
29546 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L |
29547 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L |
29548 | //IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1 |
29549 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved__SHIFT 0x0 |
29550 | #define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved_MASK 0xFFFFFFFFL |
29551 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0 |
29552 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT 0xc |
29553 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK 0xFFFFF000L |
29554 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1 |
29555 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT 0x0 |
29556 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT 0x18 |
29557 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK 0x000FFFFFL |
29558 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK 0x0F000000L |
29559 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 |
29560 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT 0x3 |
29561 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK 0xFFFFFFF8L |
29562 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 |
29563 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT 0x0 |
29564 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK 0x000FFFFFL |
29565 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0 |
29566 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT 0x0 |
29567 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT 0xc |
29568 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK 0x00000FFFL |
29569 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK 0xFFFFF000L |
29570 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1 |
29571 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT 0x0 |
29572 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT 0x14 |
29573 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT 0x18 |
29574 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT 0x1c |
29575 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK 0x000FFFFFL |
29576 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK 0x00F00000L |
29577 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK 0x0F000000L |
29578 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK 0xF0000000L |
29579 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0 |
29580 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT 0x0 |
29581 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT 0xc |
29582 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK 0x00000FFFL |
29583 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK 0xFFFFF000L |
29584 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1 |
29585 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT 0x0 |
29586 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT 0x14 |
29587 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT 0x18 |
29588 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT 0x1c |
29589 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK 0x000FFFFFL |
29590 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK 0x00F00000L |
29591 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK 0x0F000000L |
29592 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK 0xF0000000L |
29593 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0 |
29594 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 |
29595 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT 0x9 |
29596 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT 0xc |
29597 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL |
29598 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK 0x00000E00L |
29599 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK 0xFFFFF000L |
29600 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1 |
29601 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT 0x0 |
29602 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT 0x14 |
29603 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK 0x000FFFFFL |
29604 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK 0xFFF00000L |
29605 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0 |
29606 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 |
29607 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT 0x9 |
29608 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT 0xc |
29609 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL |
29610 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK 0x00000E00L |
29611 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK 0xFFFFF000L |
29612 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1 |
29613 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT 0x0 |
29614 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT 0x14 |
29615 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK 0x000FFFFFL |
29616 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK 0xFFF00000L |
29617 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0 |
29618 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 |
29619 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT 0x9 |
29620 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT 0xc |
29621 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL |
29622 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK 0x00000E00L |
29623 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK 0xFFFFF000L |
29624 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1 |
29625 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT 0x0 |
29626 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT 0x14 |
29627 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK 0x000FFFFFL |
29628 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK 0xFFF00000L |
29629 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0 |
29630 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 |
29631 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT 0x9 |
29632 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT 0xc |
29633 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL |
29634 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK 0x00000E00L |
29635 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK 0xFFFFF000L |
29636 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1 |
29637 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT 0x0 |
29638 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT 0x14 |
29639 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK 0x000FFFFFL |
29640 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK 0xFFF00000L |
29641 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0 |
29642 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 |
29643 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT 0x9 |
29644 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT 0xc |
29645 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL |
29646 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK 0x00000E00L |
29647 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK 0xFFFFF000L |
29648 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1 |
29649 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT 0x0 |
29650 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT 0x14 |
29651 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK 0x000FFFFFL |
29652 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK 0xFFF00000L |
29653 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0 |
29654 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 |
29655 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT 0x9 |
29656 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT 0xc |
29657 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL |
29658 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK 0x00000E00L |
29659 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK 0xFFFFF000L |
29660 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1 |
29661 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT 0x0 |
29662 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT 0x14 |
29663 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK 0x000FFFFFL |
29664 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK 0xFFF00000L |
29665 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0 |
29666 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 |
29667 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT 0x9 |
29668 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT 0xc |
29669 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL |
29670 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK 0x00000E00L |
29671 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK 0xFFFFF000L |
29672 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1 |
29673 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT 0x0 |
29674 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT 0x14 |
29675 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK 0x000FFFFFL |
29676 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK 0xFFF00000L |
29677 | //IOMMU_L2MMIO0_IOMMU_MMIO_DSFX |
29678 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup__SHIFT 0x0 |
29679 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT 0x18 |
29680 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT 0x1c |
29681 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup_MASK 0x00FFFFFFL |
29682 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR_MASK 0x0F000000L |
29683 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK 0xF0000000L |
29684 | //IOMMU_L2MMIO0_IOMMU_MMIO_DSCX |
29685 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT 0x0 |
29686 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT 0x18 |
29687 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT 0x1c |
29688 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK 0x00FFFFFFL |
29689 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR_MASK 0x0F000000L |
29690 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK 0xF0000000L |
29691 | //IOMMU_L2MMIO0_IOMMU_MMIO_DSSX |
29692 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status__SHIFT 0x0 |
29693 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT 0x18 |
29694 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT 0x1c |
29695 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status_MASK 0x00FFFFFFL |
29696 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR_MASK 0x0F000000L |
29697 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK 0xF0000000L |
29698 | //IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC |
29699 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 |
29700 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT 0x5 |
29701 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b |
29702 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL |
29703 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1_MASK 0x07FFFFE0L |
29704 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L |
29705 | //IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1 |
29706 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 |
29707 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT 0x5 |
29708 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL |
29709 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved_MASK 0xFFFFFFE0L |
29710 | //IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP |
29711 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 |
29712 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 |
29713 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT 0x10 |
29714 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 |
29715 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 |
29716 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT 0x17 |
29717 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved__SHIFT 0x18 |
29718 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL |
29719 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L |
29720 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN_MASK 0x00010000L |
29721 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L |
29722 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L |
29723 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK 0x00800000L |
29724 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved_MASK 0xFF000000L |
29725 | //IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO |
29726 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT 0x0 |
29727 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 |
29728 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK 0x00000003L |
29729 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL |
29730 | //IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI |
29731 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 |
29732 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL |
29733 | //IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA |
29734 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT 0x0 |
29735 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved__SHIFT 0x10 |
29736 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL |
29737 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved_MASK 0xFFFF0000L |
29738 | //IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP |
29739 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 |
29740 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 |
29741 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 |
29742 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 |
29743 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 |
29744 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b |
29745 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL |
29746 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L |
29747 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L |
29748 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L |
29749 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L |
29750 | #define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L |
29751 | //IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W |
29752 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT 0x0 |
29753 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT 0xd |
29754 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT 0xe |
29755 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0_MASK 0x00001FFFL |
29756 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK 0x00002000L |
29757 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1_MASK 0xFFFFC000L |
29758 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0 |
29759 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved__SHIFT 0x0 |
29760 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT 0xc |
29761 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved_MASK 0x00000FFFL |
29762 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK 0xFFFFF000L |
29763 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0 |
29764 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT 0x0 |
29765 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved__SHIFT 0x14 |
29766 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK 0x000FFFFFL |
29767 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved_MASK 0xFFF00000L |
29768 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0 |
29769 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT 0x0 |
29770 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT 0x1 |
29771 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT 0x2 |
29772 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT 0xc |
29773 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK 0x00000001L |
29774 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK 0x00000002L |
29775 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved_MASK 0x00000FFCL |
29776 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK 0xFFFFF000L |
29777 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0 |
29778 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT 0x0 |
29779 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT 0x14 |
29780 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK 0x000FFFFFL |
29781 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved_MASK 0xFFF00000L |
29782 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0 |
29783 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved__SHIFT 0x0 |
29784 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT 0xc |
29785 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved_MASK 0x00000FFFL |
29786 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK 0xFFFFF000L |
29787 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0 |
29788 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT 0x0 |
29789 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved__SHIFT 0x14 |
29790 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK 0x000FFFFFL |
29791 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved_MASK 0xFFF00000L |
29792 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1 |
29793 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved__SHIFT 0x0 |
29794 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT 0xc |
29795 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved_MASK 0x00000FFFL |
29796 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK 0xFFFFF000L |
29797 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1 |
29798 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT 0x0 |
29799 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved__SHIFT 0x14 |
29800 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK 0x000FFFFFL |
29801 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved_MASK 0xFFF00000L |
29802 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1 |
29803 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT 0x0 |
29804 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT 0x1 |
29805 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT 0x2 |
29806 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT 0xc |
29807 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK 0x00000001L |
29808 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK 0x00000002L |
29809 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved_MASK 0x00000FFCL |
29810 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK 0xFFFFF000L |
29811 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1 |
29812 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT 0x0 |
29813 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT 0x14 |
29814 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK 0x000FFFFFL |
29815 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved_MASK 0xFFF00000L |
29816 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1 |
29817 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved__SHIFT 0x0 |
29818 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT 0xc |
29819 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved_MASK 0x00000FFFL |
29820 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK 0xFFFFF000L |
29821 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1 |
29822 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT 0x0 |
29823 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved__SHIFT 0x14 |
29824 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK 0x000FFFFFL |
29825 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved_MASK 0xFFF00000L |
29826 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2 |
29827 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved__SHIFT 0x0 |
29828 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT 0xc |
29829 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved_MASK 0x00000FFFL |
29830 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK 0xFFFFF000L |
29831 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2 |
29832 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT 0x0 |
29833 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved__SHIFT 0x14 |
29834 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK 0x000FFFFFL |
29835 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved_MASK 0xFFF00000L |
29836 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2 |
29837 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT 0x0 |
29838 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT 0x1 |
29839 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT 0x2 |
29840 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT 0xc |
29841 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK 0x00000001L |
29842 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK 0x00000002L |
29843 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved_MASK 0x00000FFCL |
29844 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK 0xFFFFF000L |
29845 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2 |
29846 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT 0x0 |
29847 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT 0x14 |
29848 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK 0x000FFFFFL |
29849 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved_MASK 0xFFF00000L |
29850 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2 |
29851 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved__SHIFT 0x0 |
29852 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT 0xc |
29853 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved_MASK 0x00000FFFL |
29854 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK 0xFFFFF000L |
29855 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2 |
29856 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT 0x0 |
29857 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved__SHIFT 0x14 |
29858 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK 0x000FFFFFL |
29859 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved_MASK 0xFFF00000L |
29860 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3 |
29861 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved__SHIFT 0x0 |
29862 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT 0xc |
29863 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved_MASK 0x00000FFFL |
29864 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK 0xFFFFF000L |
29865 | //IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3 |
29866 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT 0x0 |
29867 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved__SHIFT 0x14 |
29868 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK 0x000FFFFFL |
29869 | #define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved_MASK 0xFFF00000L |
29870 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3 |
29871 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT 0x0 |
29872 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT 0x1 |
29873 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT 0x2 |
29874 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT 0xc |
29875 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK 0x00000001L |
29876 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK 0x00000002L |
29877 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved_MASK 0x00000FFCL |
29878 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK 0xFFFFF000L |
29879 | //IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3 |
29880 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT 0x0 |
29881 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT 0x14 |
29882 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK 0x000FFFFFL |
29883 | #define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved_MASK 0xFFF00000L |
29884 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3 |
29885 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved__SHIFT 0x0 |
29886 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT 0xc |
29887 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved_MASK 0x00000FFFL |
29888 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK 0xFFFFF000L |
29889 | //IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3 |
29890 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT 0x0 |
29891 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved__SHIFT 0x14 |
29892 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK 0x000FFFFFL |
29893 | #define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved_MASK 0xFFF00000L |
29894 | //IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0 |
29895 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
29896 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT 0x4 |
29897 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
29898 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
29899 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK 0x0007FFF0L |
29900 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
29901 | //IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1 |
29902 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
29903 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
29904 | //IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0 |
29905 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
29906 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT 0x4 |
29907 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
29908 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
29909 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK 0x0007FFF0L |
29910 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
29911 | //IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1 |
29912 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
29913 | #define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
29914 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0 |
29915 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
29916 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT 0x4 |
29917 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
29918 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
29919 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK 0x0007FFF0L |
29920 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
29921 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1 |
29922 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
29923 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
29924 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0 |
29925 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
29926 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT 0x4 |
29927 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
29928 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
29929 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK 0x0007FFF0L |
29930 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
29931 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1 |
29932 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
29933 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
29934 | //IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0 |
29935 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT 0x0 |
29936 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT 0x1 |
29937 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT 0x2 |
29938 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT 0x3 |
29939 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT 0x4 |
29940 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT 0x5 |
29941 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT 0x6 |
29942 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT 0x7 |
29943 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT 0x8 |
29944 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT 0x9 |
29945 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT__SHIFT 0xa |
29946 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT 0xb |
29947 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT 0xc |
29948 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0__SHIFT 0xd |
29949 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT 0xf |
29950 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT 0x10 |
29951 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT 0x11 |
29952 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT 0x12 |
29953 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1__SHIFT 0x13 |
29954 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK 0x00000001L |
29955 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK 0x00000002L |
29956 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK 0x00000004L |
29957 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK 0x00000008L |
29958 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK 0x00000010L |
29959 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK 0x00000020L |
29960 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT_MASK 0x00000040L |
29961 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN_MASK 0x00000080L |
29962 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN_MASK 0x00000100L |
29963 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK 0x00000200L |
29964 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT_MASK 0x00000400L |
29965 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK 0x00000800L |
29966 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK 0x00001000L |
29967 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0_MASK 0x00006000L |
29968 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK 0x00008000L |
29969 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK 0x00010000L |
29970 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK 0x00020000L |
29971 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK 0x00040000L |
29972 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1_MASK 0xFFF80000L |
29973 | //IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1 |
29974 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0__SHIFT 0x0 |
29975 | #define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0_MASK 0xFFFFFFFFL |
29976 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0 |
29977 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
29978 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT 0x4 |
29979 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
29980 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
29981 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK 0x0007FFF0L |
29982 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
29983 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1 |
29984 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
29985 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
29986 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0 |
29987 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
29988 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT 0x4 |
29989 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
29990 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
29991 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK 0x0007FFF0L |
29992 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
29993 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1 |
29994 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
29995 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
29996 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0 |
29997 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
29998 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT 0x3 |
29999 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT 0x10 |
30000 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK 0x00000007L |
30001 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK 0x0000FFF8L |
30002 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK 0xFFFF0000L |
30003 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1 |
30004 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
30005 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
30006 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0 |
30007 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
30008 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT 0x3 |
30009 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT 0x10 |
30010 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK 0x00000007L |
30011 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK 0x0000FFF8L |
30012 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK 0xFFFF0000L |
30013 | //IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1 |
30014 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
30015 | #define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
30016 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0 |
30017 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
30018 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT 0x4 |
30019 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
30020 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
30021 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK 0x0007FFF0L |
30022 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
30023 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1 |
30024 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
30025 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
30026 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0 |
30027 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
30028 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT 0x4 |
30029 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
30030 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
30031 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK 0x0007FFF0L |
30032 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
30033 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1 |
30034 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
30035 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
30036 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0 |
30037 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
30038 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT 0x4 |
30039 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
30040 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
30041 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK 0x0007FFF0L |
30042 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
30043 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1 |
30044 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
30045 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
30046 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 |
30047 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
30048 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT 0x4 |
30049 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
30050 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
30051 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK 0x0007FFF0L |
30052 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
30053 | //IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 |
30054 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
30055 | #define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
30056 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0 |
30057 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT 0x0 |
30058 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT 0x4 |
30059 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT 0x5 |
30060 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK 0x0000000FL |
30061 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK 0x00000010L |
30062 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK 0xFFFFFFE0L |
30063 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0 |
30064 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT 0x0 |
30065 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf |
30066 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT 0x1e |
30067 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT 0x1f |
30068 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK 0x00007FFFL |
30069 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L |
30070 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK 0x40000000L |
30071 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK 0x80000000L |
30072 | //IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 |
30073 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT 0x0 |
30074 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf |
30075 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT 0x1e |
30076 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT 0x1f |
30077 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK 0x00007FFFL |
30078 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L |
30079 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK 0x40000000L |
30080 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK 0x80000000L |
30081 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0 |
30082 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT 0x0 |
30083 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT 0x7 |
30084 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT 0xb |
30085 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT 0xc |
30086 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT 0x12 |
30087 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK 0x0000007FL |
30088 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK 0x00000780L |
30089 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK 0x00000800L |
30090 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK 0x0003F000L |
30091 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK 0xFFFC0000L |
30092 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1 |
30093 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT 0x0 |
30094 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK 0xFFFFFFFFL |
30095 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 |
30096 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 |
30097 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL |
30098 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 |
30099 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 |
30100 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL |
30101 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 |
30102 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 |
30103 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL |
30104 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 |
30105 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 |
30106 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL |
30107 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 |
30108 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 |
30109 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL |
30110 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 |
30111 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 |
30112 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL |
30113 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 |
30114 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT 0x0 |
30115 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK 0xFFFFFFFFL |
30116 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 |
30117 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT 0x0 |
30118 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT 0x10 |
30119 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK 0x0000FFFFL |
30120 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK 0xFFFF0000L |
30121 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 |
30122 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 |
30123 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 |
30124 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e |
30125 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f |
30126 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL |
30127 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
30128 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L |
30129 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L |
30130 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 |
30131 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT 0x0 |
30132 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL |
30133 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 |
30134 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 |
30135 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
30136 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f |
30137 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL |
30138 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
30139 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L |
30140 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 |
30141 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 |
30142 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
30143 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL |
30144 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
30145 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 |
30146 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 |
30147 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
30148 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f |
30149 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL |
30150 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
30151 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L |
30152 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 |
30153 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 |
30154 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
30155 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL |
30156 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
30157 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 |
30158 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 |
30159 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
30160 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f |
30161 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL |
30162 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
30163 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L |
30164 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 |
30165 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 |
30166 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
30167 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL |
30168 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
30169 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 |
30170 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT 0x0 |
30171 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK 0xFFFFFFFFL |
30172 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 |
30173 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT 0x0 |
30174 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT 0x14 |
30175 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT 0x1f |
30176 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK 0x000FFFFFL |
30177 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK 0x7FF00000L |
30178 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK 0x80000000L |
30179 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 |
30180 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT 0x0 |
30181 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK 0xFFFFFFFFL |
30182 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 |
30183 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT 0x0 |
30184 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT 0x10 |
30185 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK 0x0000FFFFL |
30186 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK 0xFFFF0000L |
30187 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 |
30188 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 |
30189 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 |
30190 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e |
30191 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f |
30192 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL |
30193 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
30194 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L |
30195 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L |
30196 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 |
30197 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT 0x0 |
30198 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL |
30199 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 |
30200 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 |
30201 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
30202 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f |
30203 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL |
30204 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
30205 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L |
30206 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 |
30207 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 |
30208 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
30209 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL |
30210 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
30211 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 |
30212 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 |
30213 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
30214 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f |
30215 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL |
30216 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
30217 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L |
30218 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 |
30219 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 |
30220 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
30221 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL |
30222 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
30223 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 |
30224 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 |
30225 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
30226 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f |
30227 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL |
30228 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
30229 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L |
30230 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 |
30231 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 |
30232 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
30233 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL |
30234 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
30235 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 |
30236 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT 0x0 |
30237 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK 0xFFFFFFFFL |
30238 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 |
30239 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT 0x0 |
30240 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT 0x14 |
30241 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT 0x1f |
30242 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK 0x000FFFFFL |
30243 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK 0x7FF00000L |
30244 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK 0x80000000L |
30245 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 |
30246 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT 0x0 |
30247 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK 0xFFFFFFFFL |
30248 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 |
30249 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT 0x0 |
30250 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT 0x10 |
30251 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK 0x0000FFFFL |
30252 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK 0xFFFF0000L |
30253 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 |
30254 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 |
30255 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 |
30256 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e |
30257 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f |
30258 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL |
30259 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
30260 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L |
30261 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L |
30262 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 |
30263 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT 0x0 |
30264 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL |
30265 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 |
30266 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 |
30267 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
30268 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f |
30269 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL |
30270 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
30271 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L |
30272 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 |
30273 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 |
30274 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
30275 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL |
30276 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
30277 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 |
30278 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 |
30279 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
30280 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f |
30281 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL |
30282 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
30283 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L |
30284 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 |
30285 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 |
30286 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
30287 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL |
30288 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
30289 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 |
30290 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 |
30291 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
30292 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f |
30293 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL |
30294 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
30295 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L |
30296 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 |
30297 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 |
30298 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
30299 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL |
30300 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
30301 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 |
30302 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT 0x0 |
30303 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK 0xFFFFFFFFL |
30304 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 |
30305 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT 0x0 |
30306 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT 0x14 |
30307 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT 0x1f |
30308 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK 0x000FFFFFL |
30309 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK 0x7FF00000L |
30310 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK 0x80000000L |
30311 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 |
30312 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT 0x0 |
30313 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK 0xFFFFFFFFL |
30314 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 |
30315 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT 0x0 |
30316 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT 0x10 |
30317 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK 0x0000FFFFL |
30318 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK 0xFFFF0000L |
30319 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 |
30320 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 |
30321 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 |
30322 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e |
30323 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f |
30324 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL |
30325 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
30326 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L |
30327 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L |
30328 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 |
30329 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT 0x0 |
30330 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL |
30331 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 |
30332 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 |
30333 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
30334 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f |
30335 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL |
30336 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
30337 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L |
30338 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 |
30339 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 |
30340 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
30341 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL |
30342 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
30343 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 |
30344 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 |
30345 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
30346 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f |
30347 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL |
30348 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
30349 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L |
30350 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 |
30351 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 |
30352 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
30353 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL |
30354 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
30355 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 |
30356 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 |
30357 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
30358 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f |
30359 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL |
30360 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
30361 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L |
30362 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 |
30363 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 |
30364 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
30365 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL |
30366 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
30367 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 |
30368 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT 0x0 |
30369 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK 0xFFFFFFFFL |
30370 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 |
30371 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT 0x0 |
30372 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT 0x14 |
30373 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT 0x1f |
30374 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK 0x000FFFFFL |
30375 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK 0x7FF00000L |
30376 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK 0x80000000L |
30377 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 |
30378 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT 0x0 |
30379 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK 0xFFFFFFFFL |
30380 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 |
30381 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT 0x0 |
30382 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT 0x10 |
30383 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK 0x0000FFFFL |
30384 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK 0xFFFF0000L |
30385 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 |
30386 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 |
30387 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 |
30388 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e |
30389 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f |
30390 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL |
30391 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
30392 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L |
30393 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L |
30394 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 |
30395 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT 0x0 |
30396 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL |
30397 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 |
30398 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 |
30399 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
30400 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f |
30401 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL |
30402 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
30403 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L |
30404 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 |
30405 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 |
30406 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
30407 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL |
30408 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
30409 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 |
30410 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 |
30411 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
30412 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f |
30413 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL |
30414 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
30415 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L |
30416 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 |
30417 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 |
30418 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
30419 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL |
30420 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
30421 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 |
30422 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 |
30423 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
30424 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f |
30425 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL |
30426 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
30427 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L |
30428 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 |
30429 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 |
30430 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
30431 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL |
30432 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
30433 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 |
30434 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT 0x0 |
30435 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK 0xFFFFFFFFL |
30436 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 |
30437 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT 0x0 |
30438 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT 0x14 |
30439 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT 0x1f |
30440 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK 0x000FFFFFL |
30441 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK 0x7FF00000L |
30442 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK 0x80000000L |
30443 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 |
30444 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT 0x0 |
30445 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK 0xFFFFFFFFL |
30446 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 |
30447 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT 0x0 |
30448 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT 0x10 |
30449 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK 0x0000FFFFL |
30450 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK 0xFFFF0000L |
30451 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 |
30452 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 |
30453 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 |
30454 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e |
30455 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f |
30456 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL |
30457 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
30458 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L |
30459 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L |
30460 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 |
30461 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT 0x0 |
30462 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL |
30463 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 |
30464 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 |
30465 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
30466 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f |
30467 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL |
30468 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
30469 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L |
30470 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 |
30471 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 |
30472 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
30473 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL |
30474 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
30475 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 |
30476 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 |
30477 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
30478 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f |
30479 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL |
30480 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
30481 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L |
30482 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 |
30483 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 |
30484 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
30485 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL |
30486 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
30487 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 |
30488 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 |
30489 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
30490 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f |
30491 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL |
30492 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
30493 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L |
30494 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 |
30495 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 |
30496 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
30497 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL |
30498 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
30499 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 |
30500 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT 0x0 |
30501 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK 0xFFFFFFFFL |
30502 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 |
30503 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT 0x0 |
30504 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT 0x14 |
30505 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT 0x1f |
30506 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK 0x000FFFFFL |
30507 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK 0x7FF00000L |
30508 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK 0x80000000L |
30509 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 |
30510 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT 0x0 |
30511 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK 0xFFFFFFFFL |
30512 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 |
30513 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT 0x0 |
30514 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT 0x10 |
30515 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK 0x0000FFFFL |
30516 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK 0xFFFF0000L |
30517 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 |
30518 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 |
30519 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 |
30520 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e |
30521 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f |
30522 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL |
30523 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
30524 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L |
30525 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L |
30526 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 |
30527 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT 0x0 |
30528 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL |
30529 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 |
30530 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 |
30531 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
30532 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f |
30533 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL |
30534 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
30535 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L |
30536 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 |
30537 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 |
30538 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
30539 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL |
30540 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
30541 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 |
30542 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 |
30543 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
30544 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f |
30545 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL |
30546 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
30547 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L |
30548 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 |
30549 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 |
30550 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
30551 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL |
30552 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
30553 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 |
30554 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 |
30555 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
30556 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f |
30557 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL |
30558 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
30559 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L |
30560 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 |
30561 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 |
30562 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
30563 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL |
30564 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
30565 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 |
30566 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT 0x0 |
30567 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK 0xFFFFFFFFL |
30568 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 |
30569 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT 0x0 |
30570 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT 0x14 |
30571 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT 0x1f |
30572 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK 0x000FFFFFL |
30573 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK 0x7FF00000L |
30574 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK 0x80000000L |
30575 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 |
30576 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT 0x0 |
30577 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK 0xFFFFFFFFL |
30578 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 |
30579 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT 0x0 |
30580 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT 0x10 |
30581 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK 0x0000FFFFL |
30582 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK 0xFFFF0000L |
30583 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 |
30584 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 |
30585 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 |
30586 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e |
30587 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f |
30588 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL |
30589 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
30590 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L |
30591 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L |
30592 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 |
30593 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT 0x0 |
30594 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL |
30595 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 |
30596 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 |
30597 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
30598 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f |
30599 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL |
30600 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
30601 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L |
30602 | //IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 |
30603 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 |
30604 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
30605 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL |
30606 | #define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
30607 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 |
30608 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 |
30609 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
30610 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f |
30611 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL |
30612 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
30613 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L |
30614 | //IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 |
30615 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 |
30616 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
30617 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL |
30618 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
30619 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 |
30620 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 |
30621 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
30622 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f |
30623 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL |
30624 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
30625 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L |
30626 | //IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 |
30627 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 |
30628 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
30629 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL |
30630 | #define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
30631 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 |
30632 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT 0x0 |
30633 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK 0xFFFFFFFFL |
30634 | //IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 |
30635 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT 0x0 |
30636 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT 0x14 |
30637 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT 0x1f |
30638 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK 0x000FFFFFL |
30639 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK 0x7FF00000L |
30640 | #define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK 0x80000000L |
30641 | |
30642 | |
30643 | // addressBlock: nbio_iohub_nb_ioapicmio_ioapic_miodec |
30644 | //IOAPICMIO_INDEX |
30645 | #define IOAPICMIO_INDEX__IOAPICMIO_INDEX_data__SHIFT 0x0 |
30646 | #define IOAPICMIO_INDEX__IOAPICMIO_INDEX_data_MASK 0xFFFFFFFFL |
30647 | //IOAPICMIO_DATA |
30648 | #define IOAPICMIO_DATA__IOAPICMIO_DATA__SHIFT 0x0 |
30649 | #define IOAPICMIO_DATA__IOAPICMIO_DATA_MASK 0xFFFFFFFFL |
30650 | //IRQ_PIN_ASSERTION_REGISTER |
30651 | #define IRQ_PIN_ASSERTION_REGISTER__Input_IRQ__SHIFT 0x0 |
30652 | #define IRQ_PIN_ASSERTION_REGISTER__Input_IRQ_MASK 0x000000FFL |
30653 | //EOI_REGISTER |
30654 | #define EOI_REGISTER__Vector__SHIFT 0x0 |
30655 | #define EOI_REGISTER__Vector_MASK 0x000000FFL |
30656 | |
30657 | |
30658 | // addressBlock: nbio_iohub_nb_ioapicmioindex_ioapic_mioindexdec |
30659 | //IOAPIC_ID_REGISTER |
30660 | #define IOAPIC_ID_REGISTER__DEV_ID__SHIFT 0x18 |
30661 | #define IOAPIC_ID_REGISTER__EXTEND_ID__SHIFT 0x1c |
30662 | #define IOAPIC_ID_REGISTER__DEV_ID_MASK 0x0F000000L |
30663 | #define IOAPIC_ID_REGISTER__EXTEND_ID_MASK 0xF0000000L |
30664 | //IOAPIC_VERSION_REGISTER |
30665 | #define IOAPIC_VERSION_REGISTER__Version__SHIFT 0x0 |
30666 | #define IOAPIC_VERSION_REGISTER__PRQ__SHIFT 0xf |
30667 | #define IOAPIC_VERSION_REGISTER__Max_Redirection_Entries__SHIFT 0x10 |
30668 | #define IOAPIC_VERSION_REGISTER__Version_MASK 0x000000FFL |
30669 | #define IOAPIC_VERSION_REGISTER__PRQ_MASK 0x00008000L |
30670 | #define IOAPIC_VERSION_REGISTER__Max_Redirection_Entries_MASK 0x00FF0000L |
30671 | //IOAPIC_ARBITRATION_REGISTER |
30672 | #define IOAPIC_ARBITRATION_REGISTER__Arbitration_ID__SHIFT 0x18 |
30673 | #define IOAPIC_ARBITRATION_REGISTER__Arbitration_ID_MASK 0x0F000000L |
30674 | //REDIRECTION_TABLE_ENTRY_LOW_0 |
30675 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0__SHIFT 0x0 |
30676 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0__SHIFT 0x8 |
30677 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0__SHIFT 0xb |
30678 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0__SHIFT 0xc |
30679 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0__SHIFT 0xd |
30680 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0__SHIFT 0xe |
30681 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0__SHIFT 0xf |
30682 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0__SHIFT 0x10 |
30683 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0_MASK 0x000000FFL |
30684 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0_MASK 0x00000700L |
30685 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0_MASK 0x00000800L |
30686 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0_MASK 0x00001000L |
30687 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0_MASK 0x00002000L |
30688 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0_MASK 0x00004000L |
30689 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0_MASK 0x00008000L |
30690 | #define REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0_MASK 0x00010000L |
30691 | //REDIRECTION_TABLE_ENTRY_HIGH_0 |
30692 | #define REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0__SHIFT 0x18 |
30693 | #define REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0_MASK 0xFF000000L |
30694 | //REDIRECTION_TABLE_ENTRY_LOW_1 |
30695 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1__SHIFT 0x0 |
30696 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1__SHIFT 0x8 |
30697 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1__SHIFT 0xb |
30698 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1__SHIFT 0xc |
30699 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1__SHIFT 0xd |
30700 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1__SHIFT 0xe |
30701 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1__SHIFT 0xf |
30702 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1__SHIFT 0x10 |
30703 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1_MASK 0x000000FFL |
30704 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1_MASK 0x00000700L |
30705 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1_MASK 0x00000800L |
30706 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1_MASK 0x00001000L |
30707 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1_MASK 0x00002000L |
30708 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1_MASK 0x00004000L |
30709 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1_MASK 0x00008000L |
30710 | #define REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1_MASK 0x00010000L |
30711 | //REDIRECTION_TABLE_ENTRY_HIGH_1 |
30712 | #define REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1__SHIFT 0x18 |
30713 | #define REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1_MASK 0xFF000000L |
30714 | //REDIRECTION_TABLE_ENTRY_LOW_2 |
30715 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2__SHIFT 0x0 |
30716 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2__SHIFT 0x8 |
30717 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2__SHIFT 0xb |
30718 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2__SHIFT 0xc |
30719 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2__SHIFT 0xd |
30720 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2__SHIFT 0xe |
30721 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2__SHIFT 0xf |
30722 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2__SHIFT 0x10 |
30723 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2_MASK 0x000000FFL |
30724 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2_MASK 0x00000700L |
30725 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2_MASK 0x00000800L |
30726 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2_MASK 0x00001000L |
30727 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2_MASK 0x00002000L |
30728 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2_MASK 0x00004000L |
30729 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2_MASK 0x00008000L |
30730 | #define REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2_MASK 0x00010000L |
30731 | //REDIRECTION_TABLE_ENTRY_HIGH_2 |
30732 | #define REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2__SHIFT 0x18 |
30733 | #define REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2_MASK 0xFF000000L |
30734 | //REDIRECTION_TABLE_ENTRY_LOW_3 |
30735 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3__SHIFT 0x0 |
30736 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3__SHIFT 0x8 |
30737 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3__SHIFT 0xb |
30738 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3__SHIFT 0xc |
30739 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3__SHIFT 0xd |
30740 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3__SHIFT 0xe |
30741 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3__SHIFT 0xf |
30742 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3__SHIFT 0x10 |
30743 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3_MASK 0x000000FFL |
30744 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3_MASK 0x00000700L |
30745 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3_MASK 0x00000800L |
30746 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3_MASK 0x00001000L |
30747 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3_MASK 0x00002000L |
30748 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3_MASK 0x00004000L |
30749 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3_MASK 0x00008000L |
30750 | #define REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3_MASK 0x00010000L |
30751 | //REDIRECTION_TABLE_ENTRY_HIGH_3 |
30752 | #define REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3__SHIFT 0x18 |
30753 | #define REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3_MASK 0xFF000000L |
30754 | //REDIRECTION_TABLE_ENTRY_LOW_4 |
30755 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4__SHIFT 0x0 |
30756 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4__SHIFT 0x8 |
30757 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4__SHIFT 0xb |
30758 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4__SHIFT 0xc |
30759 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4__SHIFT 0xd |
30760 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4__SHIFT 0xe |
30761 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4__SHIFT 0xf |
30762 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4__SHIFT 0x10 |
30763 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4_MASK 0x000000FFL |
30764 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4_MASK 0x00000700L |
30765 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4_MASK 0x00000800L |
30766 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4_MASK 0x00001000L |
30767 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4_MASK 0x00002000L |
30768 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4_MASK 0x00004000L |
30769 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4_MASK 0x00008000L |
30770 | #define REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4_MASK 0x00010000L |
30771 | //REDIRECTION_TABLE_ENTRY_HIGH_4 |
30772 | #define REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4__SHIFT 0x18 |
30773 | #define REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4_MASK 0xFF000000L |
30774 | //REDIRECTION_TABLE_ENTRY_LOW_5 |
30775 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5__SHIFT 0x0 |
30776 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5__SHIFT 0x8 |
30777 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5__SHIFT 0xb |
30778 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5__SHIFT 0xc |
30779 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5__SHIFT 0xd |
30780 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5__SHIFT 0xe |
30781 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5__SHIFT 0xf |
30782 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5__SHIFT 0x10 |
30783 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5_MASK 0x000000FFL |
30784 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5_MASK 0x00000700L |
30785 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5_MASK 0x00000800L |
30786 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5_MASK 0x00001000L |
30787 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5_MASK 0x00002000L |
30788 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5_MASK 0x00004000L |
30789 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5_MASK 0x00008000L |
30790 | #define REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5_MASK 0x00010000L |
30791 | //REDIRECTION_TABLE_ENTRY_HIGH_5 |
30792 | #define REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5__SHIFT 0x18 |
30793 | #define REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5_MASK 0xFF000000L |
30794 | //REDIRECTION_TABLE_ENTRY_LOW_6 |
30795 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6__SHIFT 0x0 |
30796 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6__SHIFT 0x8 |
30797 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6__SHIFT 0xb |
30798 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6__SHIFT 0xc |
30799 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6__SHIFT 0xd |
30800 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6__SHIFT 0xe |
30801 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6__SHIFT 0xf |
30802 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6__SHIFT 0x10 |
30803 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6_MASK 0x000000FFL |
30804 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6_MASK 0x00000700L |
30805 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6_MASK 0x00000800L |
30806 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6_MASK 0x00001000L |
30807 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6_MASK 0x00002000L |
30808 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6_MASK 0x00004000L |
30809 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6_MASK 0x00008000L |
30810 | #define REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6_MASK 0x00010000L |
30811 | //REDIRECTION_TABLE_ENTRY_HIGH_6 |
30812 | #define REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6__SHIFT 0x18 |
30813 | #define REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6_MASK 0xFF000000L |
30814 | //REDIRECTION_TABLE_ENTRY_LOW_7 |
30815 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7__SHIFT 0x0 |
30816 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7__SHIFT 0x8 |
30817 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7__SHIFT 0xb |
30818 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7__SHIFT 0xc |
30819 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7__SHIFT 0xd |
30820 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7__SHIFT 0xe |
30821 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7__SHIFT 0xf |
30822 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7__SHIFT 0x10 |
30823 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7_MASK 0x000000FFL |
30824 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7_MASK 0x00000700L |
30825 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7_MASK 0x00000800L |
30826 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7_MASK 0x00001000L |
30827 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7_MASK 0x00002000L |
30828 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7_MASK 0x00004000L |
30829 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7_MASK 0x00008000L |
30830 | #define REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7_MASK 0x00010000L |
30831 | //REDIRECTION_TABLE_ENTRY_HIGH_7 |
30832 | #define REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7__SHIFT 0x18 |
30833 | #define REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7_MASK 0xFF000000L |
30834 | //REDIRECTION_TABLE_ENTRY_LOW_8 |
30835 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8__SHIFT 0x0 |
30836 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8__SHIFT 0x8 |
30837 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8__SHIFT 0xb |
30838 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8__SHIFT 0xc |
30839 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8__SHIFT 0xd |
30840 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8__SHIFT 0xe |
30841 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8__SHIFT 0xf |
30842 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8__SHIFT 0x10 |
30843 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8_MASK 0x000000FFL |
30844 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8_MASK 0x00000700L |
30845 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8_MASK 0x00000800L |
30846 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8_MASK 0x00001000L |
30847 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8_MASK 0x00002000L |
30848 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8_MASK 0x00004000L |
30849 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8_MASK 0x00008000L |
30850 | #define REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8_MASK 0x00010000L |
30851 | //REDIRECTION_TABLE_ENTRY_HIGH_8 |
30852 | #define REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8__SHIFT 0x18 |
30853 | #define REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8_MASK 0xFF000000L |
30854 | //REDIRECTION_TABLE_ENTRY_LOW_9 |
30855 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9__SHIFT 0x0 |
30856 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9__SHIFT 0x8 |
30857 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9__SHIFT 0xb |
30858 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9__SHIFT 0xc |
30859 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9__SHIFT 0xd |
30860 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9__SHIFT 0xe |
30861 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9__SHIFT 0xf |
30862 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9__SHIFT 0x10 |
30863 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9_MASK 0x000000FFL |
30864 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9_MASK 0x00000700L |
30865 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9_MASK 0x00000800L |
30866 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9_MASK 0x00001000L |
30867 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9_MASK 0x00002000L |
30868 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9_MASK 0x00004000L |
30869 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9_MASK 0x00008000L |
30870 | #define REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9_MASK 0x00010000L |
30871 | //REDIRECTION_TABLE_ENTRY_HIGH_9 |
30872 | #define REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9__SHIFT 0x18 |
30873 | #define REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9_MASK 0xFF000000L |
30874 | //REDIRECTION_TABLE_ENTRY_LOW_10 |
30875 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10__SHIFT 0x0 |
30876 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10__SHIFT 0x8 |
30877 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10__SHIFT 0xb |
30878 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10__SHIFT 0xc |
30879 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10__SHIFT 0xd |
30880 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10__SHIFT 0xe |
30881 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10__SHIFT 0xf |
30882 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10__SHIFT 0x10 |
30883 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10_MASK 0x000000FFL |
30884 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10_MASK 0x00000700L |
30885 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10_MASK 0x00000800L |
30886 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10_MASK 0x00001000L |
30887 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10_MASK 0x00002000L |
30888 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10_MASK 0x00004000L |
30889 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10_MASK 0x00008000L |
30890 | #define REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10_MASK 0x00010000L |
30891 | //REDIRECTION_TABLE_ENTRY_HIGH_10 |
30892 | #define REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10__SHIFT 0x18 |
30893 | #define REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10_MASK 0xFF000000L |
30894 | //REDIRECTION_TABLE_ENTRY_LOW_11 |
30895 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11__SHIFT 0x0 |
30896 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11__SHIFT 0x8 |
30897 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11__SHIFT 0xb |
30898 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11__SHIFT 0xc |
30899 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11__SHIFT 0xd |
30900 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11__SHIFT 0xe |
30901 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11__SHIFT 0xf |
30902 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11__SHIFT 0x10 |
30903 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11_MASK 0x000000FFL |
30904 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11_MASK 0x00000700L |
30905 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11_MASK 0x00000800L |
30906 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11_MASK 0x00001000L |
30907 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11_MASK 0x00002000L |
30908 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11_MASK 0x00004000L |
30909 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11_MASK 0x00008000L |
30910 | #define REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11_MASK 0x00010000L |
30911 | //REDIRECTION_TABLE_ENTRY_HIGH_11 |
30912 | #define REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11__SHIFT 0x18 |
30913 | #define REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11_MASK 0xFF000000L |
30914 | //REDIRECTION_TABLE_ENTRY_LOW_12 |
30915 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12__SHIFT 0x0 |
30916 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12__SHIFT 0x8 |
30917 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12__SHIFT 0xb |
30918 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12__SHIFT 0xc |
30919 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12__SHIFT 0xd |
30920 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12__SHIFT 0xe |
30921 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12__SHIFT 0xf |
30922 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12__SHIFT 0x10 |
30923 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12_MASK 0x000000FFL |
30924 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12_MASK 0x00000700L |
30925 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12_MASK 0x00000800L |
30926 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12_MASK 0x00001000L |
30927 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12_MASK 0x00002000L |
30928 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12_MASK 0x00004000L |
30929 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12_MASK 0x00008000L |
30930 | #define REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12_MASK 0x00010000L |
30931 | //REDIRECTION_TABLE_ENTRY_HIGH_12 |
30932 | #define REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12__SHIFT 0x18 |
30933 | #define REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12_MASK 0xFF000000L |
30934 | //REDIRECTION_TABLE_ENTRY_LOW_13 |
30935 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13__SHIFT 0x0 |
30936 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13__SHIFT 0x8 |
30937 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13__SHIFT 0xb |
30938 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13__SHIFT 0xc |
30939 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13__SHIFT 0xd |
30940 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13__SHIFT 0xe |
30941 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13__SHIFT 0xf |
30942 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13__SHIFT 0x10 |
30943 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13_MASK 0x000000FFL |
30944 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13_MASK 0x00000700L |
30945 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13_MASK 0x00000800L |
30946 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13_MASK 0x00001000L |
30947 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13_MASK 0x00002000L |
30948 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13_MASK 0x00004000L |
30949 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13_MASK 0x00008000L |
30950 | #define REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13_MASK 0x00010000L |
30951 | //REDIRECTION_TABLE_ENTRY_HIGH_13 |
30952 | #define REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13__SHIFT 0x18 |
30953 | #define REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13_MASK 0xFF000000L |
30954 | //REDIRECTION_TABLE_ENTRY_LOW_14 |
30955 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14__SHIFT 0x0 |
30956 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14__SHIFT 0x8 |
30957 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14__SHIFT 0xb |
30958 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14__SHIFT 0xc |
30959 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14__SHIFT 0xd |
30960 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14__SHIFT 0xe |
30961 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14__SHIFT 0xf |
30962 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14__SHIFT 0x10 |
30963 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14_MASK 0x000000FFL |
30964 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14_MASK 0x00000700L |
30965 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14_MASK 0x00000800L |
30966 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14_MASK 0x00001000L |
30967 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14_MASK 0x00002000L |
30968 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14_MASK 0x00004000L |
30969 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14_MASK 0x00008000L |
30970 | #define REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14_MASK 0x00010000L |
30971 | //REDIRECTION_TABLE_ENTRY_HIGH_14 |
30972 | #define REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14__SHIFT 0x18 |
30973 | #define REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14_MASK 0xFF000000L |
30974 | //REDIRECTION_TABLE_ENTRY_LOW_15 |
30975 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15__SHIFT 0x0 |
30976 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15__SHIFT 0x8 |
30977 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15__SHIFT 0xb |
30978 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15__SHIFT 0xc |
30979 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15__SHIFT 0xd |
30980 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15__SHIFT 0xe |
30981 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15__SHIFT 0xf |
30982 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15__SHIFT 0x10 |
30983 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15_MASK 0x000000FFL |
30984 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15_MASK 0x00000700L |
30985 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15_MASK 0x00000800L |
30986 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15_MASK 0x00001000L |
30987 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15_MASK 0x00002000L |
30988 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15_MASK 0x00004000L |
30989 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15_MASK 0x00008000L |
30990 | #define REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15_MASK 0x00010000L |
30991 | //REDIRECTION_TABLE_ENTRY_HIGH_15 |
30992 | #define REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15__SHIFT 0x18 |
30993 | #define REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15_MASK 0xFF000000L |
30994 | //REDIRECTION_TABLE_ENTRY_LOW_16 |
30995 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16__SHIFT 0x0 |
30996 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16__SHIFT 0x8 |
30997 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16__SHIFT 0xb |
30998 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16__SHIFT 0xc |
30999 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16__SHIFT 0xd |
31000 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16__SHIFT 0xe |
31001 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16__SHIFT 0xf |
31002 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16__SHIFT 0x10 |
31003 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16_MASK 0x000000FFL |
31004 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16_MASK 0x00000700L |
31005 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16_MASK 0x00000800L |
31006 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16_MASK 0x00001000L |
31007 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16_MASK 0x00002000L |
31008 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16_MASK 0x00004000L |
31009 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16_MASK 0x00008000L |
31010 | #define REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16_MASK 0x00010000L |
31011 | //REDIRECTION_TABLE_ENTRY_HIGH_16 |
31012 | #define REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16__SHIFT 0x18 |
31013 | #define REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16_MASK 0xFF000000L |
31014 | //REDIRECTION_TABLE_ENTRY_LOW_17 |
31015 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17__SHIFT 0x0 |
31016 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17__SHIFT 0x8 |
31017 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17__SHIFT 0xb |
31018 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17__SHIFT 0xc |
31019 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17__SHIFT 0xd |
31020 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17__SHIFT 0xe |
31021 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17__SHIFT 0xf |
31022 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17__SHIFT 0x10 |
31023 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17_MASK 0x000000FFL |
31024 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17_MASK 0x00000700L |
31025 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17_MASK 0x00000800L |
31026 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17_MASK 0x00001000L |
31027 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17_MASK 0x00002000L |
31028 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17_MASK 0x00004000L |
31029 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17_MASK 0x00008000L |
31030 | #define REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17_MASK 0x00010000L |
31031 | //REDIRECTION_TABLE_ENTRY_HIGH_17 |
31032 | #define REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17__SHIFT 0x18 |
31033 | #define REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17_MASK 0xFF000000L |
31034 | //REDIRECTION_TABLE_ENTRY_LOW_18 |
31035 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18__SHIFT 0x0 |
31036 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18__SHIFT 0x8 |
31037 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18__SHIFT 0xb |
31038 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18__SHIFT 0xc |
31039 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18__SHIFT 0xd |
31040 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18__SHIFT 0xe |
31041 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18__SHIFT 0xf |
31042 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18__SHIFT 0x10 |
31043 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18_MASK 0x000000FFL |
31044 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18_MASK 0x00000700L |
31045 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18_MASK 0x00000800L |
31046 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18_MASK 0x00001000L |
31047 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18_MASK 0x00002000L |
31048 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18_MASK 0x00004000L |
31049 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18_MASK 0x00008000L |
31050 | #define REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18_MASK 0x00010000L |
31051 | //REDIRECTION_TABLE_ENTRY_HIGH_18 |
31052 | #define REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18__SHIFT 0x18 |
31053 | #define REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18_MASK 0xFF000000L |
31054 | //REDIRECTION_TABLE_ENTRY_LOW_19 |
31055 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19__SHIFT 0x0 |
31056 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19__SHIFT 0x8 |
31057 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19__SHIFT 0xb |
31058 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19__SHIFT 0xc |
31059 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19__SHIFT 0xd |
31060 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19__SHIFT 0xe |
31061 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19__SHIFT 0xf |
31062 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19__SHIFT 0x10 |
31063 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19_MASK 0x000000FFL |
31064 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19_MASK 0x00000700L |
31065 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19_MASK 0x00000800L |
31066 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19_MASK 0x00001000L |
31067 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19_MASK 0x00002000L |
31068 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19_MASK 0x00004000L |
31069 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19_MASK 0x00008000L |
31070 | #define REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19_MASK 0x00010000L |
31071 | //REDIRECTION_TABLE_ENTRY_HIGH_19 |
31072 | #define REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19__SHIFT 0x18 |
31073 | #define REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19_MASK 0xFF000000L |
31074 | //REDIRECTION_TABLE_ENTRY_LOW_20 |
31075 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20__SHIFT 0x0 |
31076 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20__SHIFT 0x8 |
31077 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20__SHIFT 0xb |
31078 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20__SHIFT 0xc |
31079 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20__SHIFT 0xd |
31080 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20__SHIFT 0xe |
31081 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20__SHIFT 0xf |
31082 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20__SHIFT 0x10 |
31083 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20_MASK 0x000000FFL |
31084 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20_MASK 0x00000700L |
31085 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20_MASK 0x00000800L |
31086 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20_MASK 0x00001000L |
31087 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20_MASK 0x00002000L |
31088 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20_MASK 0x00004000L |
31089 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20_MASK 0x00008000L |
31090 | #define REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20_MASK 0x00010000L |
31091 | //REDIRECTION_TABLE_ENTRY_HIGH_20 |
31092 | #define REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20__SHIFT 0x18 |
31093 | #define REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20_MASK 0xFF000000L |
31094 | //REDIRECTION_TABLE_ENTRY_LOW_21 |
31095 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21__SHIFT 0x0 |
31096 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21__SHIFT 0x8 |
31097 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21__SHIFT 0xb |
31098 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21__SHIFT 0xc |
31099 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21__SHIFT 0xd |
31100 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21__SHIFT 0xe |
31101 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21__SHIFT 0xf |
31102 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21__SHIFT 0x10 |
31103 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21_MASK 0x000000FFL |
31104 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21_MASK 0x00000700L |
31105 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21_MASK 0x00000800L |
31106 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21_MASK 0x00001000L |
31107 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21_MASK 0x00002000L |
31108 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21_MASK 0x00004000L |
31109 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21_MASK 0x00008000L |
31110 | #define REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21_MASK 0x00010000L |
31111 | //REDIRECTION_TABLE_ENTRY_HIGH_21 |
31112 | #define REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21__SHIFT 0x18 |
31113 | #define REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21_MASK 0xFF000000L |
31114 | //REDIRECTION_TABLE_ENTRY_LOW_22 |
31115 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22__SHIFT 0x0 |
31116 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22__SHIFT 0x8 |
31117 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22__SHIFT 0xb |
31118 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22__SHIFT 0xc |
31119 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22__SHIFT 0xd |
31120 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22__SHIFT 0xe |
31121 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22__SHIFT 0xf |
31122 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22__SHIFT 0x10 |
31123 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22_MASK 0x000000FFL |
31124 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22_MASK 0x00000700L |
31125 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22_MASK 0x00000800L |
31126 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22_MASK 0x00001000L |
31127 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22_MASK 0x00002000L |
31128 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22_MASK 0x00004000L |
31129 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22_MASK 0x00008000L |
31130 | #define REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22_MASK 0x00010000L |
31131 | //REDIRECTION_TABLE_ENTRY_HIGH_22 |
31132 | #define REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22__SHIFT 0x18 |
31133 | #define REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22_MASK 0xFF000000L |
31134 | //REDIRECTION_TABLE_ENTRY_LOW_23 |
31135 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23__SHIFT 0x0 |
31136 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23__SHIFT 0x8 |
31137 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23__SHIFT 0xb |
31138 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23__SHIFT 0xc |
31139 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23__SHIFT 0xd |
31140 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23__SHIFT 0xe |
31141 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23__SHIFT 0xf |
31142 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23__SHIFT 0x10 |
31143 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23_MASK 0x000000FFL |
31144 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23_MASK 0x00000700L |
31145 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23_MASK 0x00000800L |
31146 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23_MASK 0x00001000L |
31147 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23_MASK 0x00002000L |
31148 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23_MASK 0x00004000L |
31149 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23_MASK 0x00008000L |
31150 | #define REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23_MASK 0x00010000L |
31151 | //REDIRECTION_TABLE_ENTRY_HIGH_23 |
31152 | #define REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23__SHIFT 0x18 |
31153 | #define REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23_MASK 0xFF000000L |
31154 | //REDIRECTION_TABLE_ENTRY_LOW_24 |
31155 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24__SHIFT 0x0 |
31156 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24__SHIFT 0x8 |
31157 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24__SHIFT 0xb |
31158 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24__SHIFT 0xc |
31159 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24__SHIFT 0xd |
31160 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24__SHIFT 0xe |
31161 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24__SHIFT 0xf |
31162 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24__SHIFT 0x10 |
31163 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24_MASK 0x000000FFL |
31164 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24_MASK 0x00000700L |
31165 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24_MASK 0x00000800L |
31166 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24_MASK 0x00001000L |
31167 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24_MASK 0x00002000L |
31168 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24_MASK 0x00004000L |
31169 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24_MASK 0x00008000L |
31170 | #define REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24_MASK 0x00010000L |
31171 | //REDIRECTION_TABLE_ENTRY_HIGH_24 |
31172 | #define REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24__SHIFT 0x18 |
31173 | #define REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24_MASK 0xFF000000L |
31174 | //REDIRECTION_TABLE_ENTRY_LOW_25 |
31175 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25__SHIFT 0x0 |
31176 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25__SHIFT 0x8 |
31177 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25__SHIFT 0xb |
31178 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25__SHIFT 0xc |
31179 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25__SHIFT 0xd |
31180 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25__SHIFT 0xe |
31181 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25__SHIFT 0xf |
31182 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25__SHIFT 0x10 |
31183 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25_MASK 0x000000FFL |
31184 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25_MASK 0x00000700L |
31185 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25_MASK 0x00000800L |
31186 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25_MASK 0x00001000L |
31187 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25_MASK 0x00002000L |
31188 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25_MASK 0x00004000L |
31189 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25_MASK 0x00008000L |
31190 | #define REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25_MASK 0x00010000L |
31191 | //REDIRECTION_TABLE_ENTRY_HIGH_25 |
31192 | #define REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25__SHIFT 0x18 |
31193 | #define REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25_MASK 0xFF000000L |
31194 | //REDIRECTION_TABLE_ENTRY_LOW_26 |
31195 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26__SHIFT 0x0 |
31196 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26__SHIFT 0x8 |
31197 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26__SHIFT 0xb |
31198 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26__SHIFT 0xc |
31199 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26__SHIFT 0xd |
31200 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26__SHIFT 0xe |
31201 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26__SHIFT 0xf |
31202 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26__SHIFT 0x10 |
31203 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26_MASK 0x000000FFL |
31204 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26_MASK 0x00000700L |
31205 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26_MASK 0x00000800L |
31206 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26_MASK 0x00001000L |
31207 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26_MASK 0x00002000L |
31208 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26_MASK 0x00004000L |
31209 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26_MASK 0x00008000L |
31210 | #define REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26_MASK 0x00010000L |
31211 | //REDIRECTION_TABLE_ENTRY_HIGH_26 |
31212 | #define REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26__SHIFT 0x18 |
31213 | #define REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26_MASK 0xFF000000L |
31214 | //REDIRECTION_TABLE_ENTRY_LOW_27 |
31215 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27__SHIFT 0x0 |
31216 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27__SHIFT 0x8 |
31217 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27__SHIFT 0xb |
31218 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27__SHIFT 0xc |
31219 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27__SHIFT 0xd |
31220 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27__SHIFT 0xe |
31221 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27__SHIFT 0xf |
31222 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27__SHIFT 0x10 |
31223 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27_MASK 0x000000FFL |
31224 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27_MASK 0x00000700L |
31225 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27_MASK 0x00000800L |
31226 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27_MASK 0x00001000L |
31227 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27_MASK 0x00002000L |
31228 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27_MASK 0x00004000L |
31229 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27_MASK 0x00008000L |
31230 | #define REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27_MASK 0x00010000L |
31231 | //REDIRECTION_TABLE_ENTRY_HIGH_27 |
31232 | #define REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27__SHIFT 0x18 |
31233 | #define REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27_MASK 0xFF000000L |
31234 | //REDIRECTION_TABLE_ENTRY_LOW_28 |
31235 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28__SHIFT 0x0 |
31236 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28__SHIFT 0x8 |
31237 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28__SHIFT 0xb |
31238 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28__SHIFT 0xc |
31239 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28__SHIFT 0xd |
31240 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28__SHIFT 0xe |
31241 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28__SHIFT 0xf |
31242 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28__SHIFT 0x10 |
31243 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28_MASK 0x000000FFL |
31244 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28_MASK 0x00000700L |
31245 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28_MASK 0x00000800L |
31246 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28_MASK 0x00001000L |
31247 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28_MASK 0x00002000L |
31248 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28_MASK 0x00004000L |
31249 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28_MASK 0x00008000L |
31250 | #define REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28_MASK 0x00010000L |
31251 | //REDIRECTION_TABLE_ENTRY_HIGH_28 |
31252 | #define REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28__SHIFT 0x18 |
31253 | #define REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28_MASK 0xFF000000L |
31254 | //REDIRECTION_TABLE_ENTRY_LOW_29 |
31255 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29__SHIFT 0x0 |
31256 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29__SHIFT 0x8 |
31257 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29__SHIFT 0xb |
31258 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29__SHIFT 0xc |
31259 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29__SHIFT 0xd |
31260 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29__SHIFT 0xe |
31261 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29__SHIFT 0xf |
31262 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29__SHIFT 0x10 |
31263 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29_MASK 0x000000FFL |
31264 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29_MASK 0x00000700L |
31265 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29_MASK 0x00000800L |
31266 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29_MASK 0x00001000L |
31267 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29_MASK 0x00002000L |
31268 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29_MASK 0x00004000L |
31269 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29_MASK 0x00008000L |
31270 | #define REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29_MASK 0x00010000L |
31271 | //REDIRECTION_TABLE_ENTRY_HIGH_29 |
31272 | #define REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29__SHIFT 0x18 |
31273 | #define REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29_MASK 0xFF000000L |
31274 | //REDIRECTION_TABLE_ENTRY_LOW_30 |
31275 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30__SHIFT 0x0 |
31276 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30__SHIFT 0x8 |
31277 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30__SHIFT 0xb |
31278 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30__SHIFT 0xc |
31279 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30__SHIFT 0xd |
31280 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30__SHIFT 0xe |
31281 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30__SHIFT 0xf |
31282 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30__SHIFT 0x10 |
31283 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30_MASK 0x000000FFL |
31284 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30_MASK 0x00000700L |
31285 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30_MASK 0x00000800L |
31286 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30_MASK 0x00001000L |
31287 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30_MASK 0x00002000L |
31288 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30_MASK 0x00004000L |
31289 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30_MASK 0x00008000L |
31290 | #define REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30_MASK 0x00010000L |
31291 | //REDIRECTION_TABLE_ENTRY_HIGH_30 |
31292 | #define REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30__SHIFT 0x18 |
31293 | #define REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30_MASK 0xFF000000L |
31294 | //REDIRECTION_TABLE_ENTRY_LOW_31 |
31295 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31__SHIFT 0x0 |
31296 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31__SHIFT 0x8 |
31297 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31__SHIFT 0xb |
31298 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31__SHIFT 0xc |
31299 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31__SHIFT 0xd |
31300 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31__SHIFT 0xe |
31301 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31__SHIFT 0xf |
31302 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31__SHIFT 0x10 |
31303 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31_MASK 0x000000FFL |
31304 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31_MASK 0x00000700L |
31305 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31_MASK 0x00000800L |
31306 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31_MASK 0x00001000L |
31307 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31_MASK 0x00002000L |
31308 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31_MASK 0x00004000L |
31309 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31_MASK 0x00008000L |
31310 | #define REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31_MASK 0x00010000L |
31311 | //REDIRECTION_TABLE_ENTRY_HIGH_31 |
31312 | #define REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31__SHIFT 0x18 |
31313 | #define REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31_MASK 0xFF000000L |
31314 | |
31315 | |
31316 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
31317 | //BIF_CFG_DEV0_RC1_VENDOR_ID |
31318 | #define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
31319 | #define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
31320 | //BIF_CFG_DEV0_RC1_DEVICE_ID |
31321 | #define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
31322 | #define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
31323 | //BIF_CFG_DEV0_RC1_COMMAND |
31324 | #define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT 0x0 |
31325 | #define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT 0x1 |
31326 | #define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
31327 | #define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
31328 | #define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
31329 | #define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
31330 | #define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
31331 | #define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT 0x7 |
31332 | #define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT 0x8 |
31333 | #define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
31334 | #define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT 0xa |
31335 | #define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK 0x0001L |
31336 | #define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK 0x0002L |
31337 | #define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
31338 | #define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
31339 | #define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
31340 | #define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
31341 | #define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
31342 | #define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK 0x0080L |
31343 | #define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK 0x0100L |
31344 | #define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
31345 | #define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK 0x0400L |
31346 | //BIF_CFG_DEV0_RC1_STATUS |
31347 | #define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT 0x3 |
31348 | #define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT 0x4 |
31349 | #define BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN__SHIFT 0x5 |
31350 | #define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
31351 | #define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
31352 | #define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
31353 | #define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
31354 | #define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
31355 | #define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
31356 | #define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
31357 | #define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
31358 | #define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK 0x0008L |
31359 | #define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK 0x0010L |
31360 | #define BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN_MASK 0x0020L |
31361 | #define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
31362 | #define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
31363 | #define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
31364 | #define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
31365 | #define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
31366 | #define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
31367 | #define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
31368 | #define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
31369 | //BIF_CFG_DEV0_RC1_REVISION_ID |
31370 | #define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
31371 | #define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
31372 | #define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
31373 | #define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
31374 | //BIF_CFG_DEV0_RC1_PROG_INTERFACE |
31375 | #define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
31376 | #define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
31377 | //BIF_CFG_DEV0_RC1_SUB_CLASS |
31378 | #define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
31379 | #define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
31380 | //BIF_CFG_DEV0_RC1_BASE_CLASS |
31381 | #define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
31382 | #define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
31383 | //BIF_CFG_DEV0_RC1_CACHE_LINE |
31384 | #define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
31385 | #define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
31386 | //BIF_CFG_DEV0_RC1_LATENCY |
31387 | #define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
31388 | #define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
31389 | //BIF_CFG_DEV0_RC1_HEADER |
31390 | #define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT 0x0 |
31391 | #define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
31392 | #define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK 0x7FL |
31393 | #define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK 0x80L |
31394 | //BIF_CFG_DEV0_RC1_BIST |
31395 | #define BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT 0x0 |
31396 | #define BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT 0x6 |
31397 | #define BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT 0x7 |
31398 | #define BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK 0x0FL |
31399 | #define BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK 0x40L |
31400 | #define BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK 0x80L |
31401 | //BIF_CFG_DEV0_RC1_BASE_ADDR_1 |
31402 | #define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
31403 | #define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
31404 | //BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY |
31405 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
31406 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
31407 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
31408 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
31409 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
31410 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
31411 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
31412 | #define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
31413 | //BIF_CFG_DEV0_RC1_IO_BASE_LIMIT |
31414 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
31415 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
31416 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
31417 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
31418 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
31419 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
31420 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
31421 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
31422 | //BIF_CFG_DEV0_RC1_SECONDARY_STATUS |
31423 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
31424 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
31425 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
31426 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
31427 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
31428 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
31429 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
31430 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
31431 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
31432 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
31433 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
31434 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
31435 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
31436 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
31437 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
31438 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
31439 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
31440 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
31441 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
31442 | #define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
31443 | //BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT |
31444 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
31445 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
31446 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
31447 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
31448 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
31449 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
31450 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
31451 | #define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
31452 | //BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT |
31453 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
31454 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
31455 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
31456 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
31457 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
31458 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
31459 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
31460 | #define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
31461 | //BIF_CFG_DEV0_RC1_PREF_BASE_UPPER |
31462 | #define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
31463 | #define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
31464 | //BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER |
31465 | #define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
31466 | #define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
31467 | //BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI |
31468 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
31469 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
31470 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
31471 | #define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
31472 | //BIF_CFG_DEV0_RC1_CAP_PTR |
31473 | #define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
31474 | #define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
31475 | //BIF_CFG_DEV0_RC1_INTERRUPT_LINE |
31476 | #define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
31477 | #define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
31478 | //BIF_CFG_DEV0_RC1_INTERRUPT_PIN |
31479 | #define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
31480 | #define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
31481 | //BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL |
31482 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
31483 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
31484 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
31485 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
31486 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
31487 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
31488 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
31489 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
31490 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
31491 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
31492 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
31493 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
31494 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
31495 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
31496 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
31497 | #define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
31498 | //BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL |
31499 | #define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
31500 | #define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
31501 | //BIF_CFG_DEV0_RC1_PMI_CAP_LIST |
31502 | #define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
31503 | #define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31504 | #define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
31505 | #define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31506 | //BIF_CFG_DEV0_RC1_PMI_CAP |
31507 | #define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT 0x0 |
31508 | #define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
31509 | #define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
31510 | #define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
31511 | #define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
31512 | #define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
31513 | #define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
31514 | #define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK 0x0007L |
31515 | #define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
31516 | #define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
31517 | #define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
31518 | #define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
31519 | #define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
31520 | #define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
31521 | //BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL |
31522 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
31523 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
31524 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
31525 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
31526 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
31527 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
31528 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
31529 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
31530 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
31531 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
31532 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
31533 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
31534 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
31535 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
31536 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
31537 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
31538 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
31539 | #define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
31540 | //BIF_CFG_DEV0_RC1_PCIE_CAP_LIST |
31541 | #define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
31542 | #define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31543 | #define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
31544 | #define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31545 | //BIF_CFG_DEV0_RC1_PCIE_CAP |
31546 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT 0x0 |
31547 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
31548 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
31549 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
31550 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK 0x000FL |
31551 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
31552 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
31553 | #define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
31554 | //BIF_CFG_DEV0_RC1_DEVICE_CAP |
31555 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
31556 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
31557 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
31558 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
31559 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
31560 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
31561 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
31562 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
31563 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
31564 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
31565 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
31566 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
31567 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
31568 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
31569 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
31570 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
31571 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
31572 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
31573 | //BIF_CFG_DEV0_RC1_DEVICE_CNTL |
31574 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
31575 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
31576 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
31577 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
31578 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
31579 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
31580 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
31581 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
31582 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
31583 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
31584 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
31585 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
31586 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
31587 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
31588 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
31589 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
31590 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
31591 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
31592 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
31593 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
31594 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
31595 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
31596 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
31597 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
31598 | //BIF_CFG_DEV0_RC1_DEVICE_STATUS |
31599 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
31600 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
31601 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
31602 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
31603 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
31604 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
31605 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
31606 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
31607 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
31608 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
31609 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
31610 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
31611 | //BIF_CFG_DEV0_RC1_LINK_CAP |
31612 | #define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
31613 | #define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
31614 | #define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
31615 | #define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
31616 | #define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
31617 | #define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
31618 | #define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
31619 | #define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
31620 | #define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
31621 | #define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
31622 | #define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
31623 | #define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
31624 | #define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
31625 | #define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
31626 | #define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
31627 | #define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
31628 | #define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
31629 | #define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
31630 | #define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
31631 | #define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
31632 | #define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
31633 | #define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
31634 | //BIF_CFG_DEV0_RC1_LINK_CNTL |
31635 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
31636 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
31637 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
31638 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
31639 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
31640 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
31641 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
31642 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
31643 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
31644 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
31645 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
31646 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
31647 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
31648 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
31649 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
31650 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
31651 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
31652 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
31653 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
31654 | #define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
31655 | //BIF_CFG_DEV0_RC1_LINK_STATUS |
31656 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
31657 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
31658 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
31659 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
31660 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
31661 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
31662 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
31663 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
31664 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
31665 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
31666 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
31667 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
31668 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
31669 | #define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
31670 | //BIF_CFG_DEV0_RC1_SLOT_CAP |
31671 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
31672 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
31673 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
31674 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
31675 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
31676 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
31677 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
31678 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
31679 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
31680 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
31681 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
31682 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
31683 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
31684 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
31685 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
31686 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
31687 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
31688 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
31689 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
31690 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
31691 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
31692 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
31693 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
31694 | #define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
31695 | //BIF_CFG_DEV0_RC1_SLOT_CNTL |
31696 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
31697 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
31698 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
31699 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
31700 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
31701 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
31702 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
31703 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
31704 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
31705 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
31706 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
31707 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
31708 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
31709 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
31710 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
31711 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
31712 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
31713 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
31714 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
31715 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
31716 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
31717 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
31718 | //BIF_CFG_DEV0_RC1_SLOT_STATUS |
31719 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
31720 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
31721 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
31722 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
31723 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
31724 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
31725 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
31726 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
31727 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
31728 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
31729 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
31730 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
31731 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
31732 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
31733 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
31734 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
31735 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
31736 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
31737 | //BIF_CFG_DEV0_RC1_ROOT_CNTL |
31738 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
31739 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
31740 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
31741 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
31742 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
31743 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
31744 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
31745 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
31746 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
31747 | #define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
31748 | //BIF_CFG_DEV0_RC1_ROOT_CAP |
31749 | #define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
31750 | #define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
31751 | //BIF_CFG_DEV0_RC1_ROOT_STATUS |
31752 | #define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
31753 | #define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
31754 | #define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
31755 | #define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
31756 | #define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
31757 | #define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
31758 | //BIF_CFG_DEV0_RC1_DEVICE_CAP2 |
31759 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
31760 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
31761 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
31762 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
31763 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
31764 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
31765 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
31766 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
31767 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
31768 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
31769 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
31770 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
31771 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
31772 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
31773 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
31774 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
31775 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
31776 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
31777 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
31778 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
31779 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
31780 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
31781 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
31782 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
31783 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
31784 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
31785 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
31786 | #define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
31787 | //BIF_CFG_DEV0_RC1_DEVICE_CNTL2 |
31788 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
31789 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
31790 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
31791 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
31792 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
31793 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
31794 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
31795 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
31796 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
31797 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
31798 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
31799 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
31800 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
31801 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
31802 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
31803 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
31804 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
31805 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
31806 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
31807 | #define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
31808 | //BIF_CFG_DEV0_RC1_DEVICE_STATUS2 |
31809 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
31810 | #define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
31811 | //BIF_CFG_DEV0_RC1_LINK_CAP2 |
31812 | #define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
31813 | #define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
31814 | #define BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED__SHIFT 0x9 |
31815 | #define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
31816 | #define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
31817 | #define BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
31818 | //BIF_CFG_DEV0_RC1_LINK_CNTL2 |
31819 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
31820 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
31821 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
31822 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
31823 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
31824 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
31825 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
31826 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
31827 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
31828 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
31829 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
31830 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
31831 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
31832 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
31833 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
31834 | #define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
31835 | //BIF_CFG_DEV0_RC1_LINK_STATUS2 |
31836 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
31837 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
31838 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
31839 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
31840 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
31841 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
31842 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
31843 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
31844 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
31845 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
31846 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
31847 | #define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
31848 | //BIF_CFG_DEV0_RC1_SLOT_CAP2 |
31849 | #define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
31850 | #define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
31851 | //BIF_CFG_DEV0_RC1_SLOT_CNTL2 |
31852 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
31853 | #define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
31854 | //BIF_CFG_DEV0_RC1_SLOT_STATUS2 |
31855 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
31856 | #define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
31857 | //BIF_CFG_DEV0_RC1_MSI_CAP_LIST |
31858 | #define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
31859 | #define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31860 | #define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
31861 | #define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31862 | //BIF_CFG_DEV0_RC1_MSI_MSG_CNTL |
31863 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
31864 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
31865 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
31866 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
31867 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
31868 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
31869 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
31870 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
31871 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
31872 | #define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
31873 | //BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO |
31874 | #define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
31875 | #define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
31876 | //BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI |
31877 | #define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
31878 | #define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
31879 | //BIF_CFG_DEV0_RC1_MSI_MSG_DATA |
31880 | #define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
31881 | #define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
31882 | //BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 |
31883 | #define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
31884 | #define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
31885 | //BIF_CFG_DEV0_RC1_SSID_CAP_LIST |
31886 | #define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
31887 | #define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31888 | #define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
31889 | #define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31890 | //BIF_CFG_DEV0_RC1_SSID_CAP |
31891 | #define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
31892 | #define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
31893 | #define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
31894 | #define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
31895 | //BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST |
31896 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
31897 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31898 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
31899 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31900 | //BIF_CFG_DEV0_RC1_MSI_MAP_CAP |
31901 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN__SHIFT 0x0 |
31902 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
31903 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
31904 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN_MASK 0x0001L |
31905 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
31906 | #define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
31907 | //BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO |
31908 | #define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
31909 | #define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
31910 | //BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI |
31911 | #define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
31912 | #define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
31913 | //BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
31914 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31915 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31916 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31917 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31918 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31919 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31920 | //BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR |
31921 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
31922 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
31923 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
31924 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
31925 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
31926 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
31927 | //BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 |
31928 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
31929 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
31930 | //BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 |
31931 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
31932 | #define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
31933 | //BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST |
31934 | #define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31935 | #define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31936 | #define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31937 | #define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31938 | #define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31939 | #define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31940 | //BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 |
31941 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
31942 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
31943 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
31944 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
31945 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
31946 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
31947 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
31948 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
31949 | //BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 |
31950 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
31951 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
31952 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
31953 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
31954 | //BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL |
31955 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
31956 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
31957 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
31958 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
31959 | //BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS |
31960 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
31961 | #define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
31962 | //BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP |
31963 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
31964 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
31965 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
31966 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
31967 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
31968 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
31969 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
31970 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
31971 | //BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL |
31972 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
31973 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
31974 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
31975 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
31976 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
31977 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
31978 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
31979 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
31980 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
31981 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
31982 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
31983 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
31984 | //BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS |
31985 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
31986 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
31987 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
31988 | #define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
31989 | //BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP |
31990 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
31991 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
31992 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
31993 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
31994 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
31995 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
31996 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
31997 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
31998 | //BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL |
31999 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
32000 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
32001 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
32002 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
32003 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
32004 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
32005 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
32006 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
32007 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
32008 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
32009 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
32010 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
32011 | //BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS |
32012 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
32013 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
32014 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
32015 | #define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
32016 | //BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
32017 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32018 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32019 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32020 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32021 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32022 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32023 | //BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 |
32024 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
32025 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
32026 | //BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 |
32027 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
32028 | #define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
32029 | //BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
32030 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32031 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32032 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32033 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32034 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32035 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32036 | //BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS |
32037 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
32038 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
32039 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
32040 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
32041 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
32042 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
32043 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
32044 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
32045 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
32046 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
32047 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
32048 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
32049 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
32050 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
32051 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
32052 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
32053 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
32054 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
32055 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
32056 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
32057 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
32058 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
32059 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
32060 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
32061 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
32062 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
32063 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
32064 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
32065 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
32066 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
32067 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
32068 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
32069 | //BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK |
32070 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
32071 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
32072 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
32073 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
32074 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
32075 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
32076 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
32077 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
32078 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
32079 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
32080 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
32081 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
32082 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
32083 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
32084 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
32085 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
32086 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
32087 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
32088 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
32089 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
32090 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
32091 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
32092 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
32093 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
32094 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
32095 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
32096 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
32097 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
32098 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
32099 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
32100 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
32101 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
32102 | //BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY |
32103 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
32104 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
32105 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
32106 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
32107 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
32108 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
32109 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
32110 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
32111 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
32112 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
32113 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
32114 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
32115 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
32116 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
32117 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
32118 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
32119 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
32120 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
32121 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
32122 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
32123 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
32124 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
32125 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
32126 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
32127 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
32128 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
32129 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
32130 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
32131 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
32132 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
32133 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
32134 | #define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
32135 | //BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS |
32136 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
32137 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
32138 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
32139 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
32140 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
32141 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
32142 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
32143 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
32144 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
32145 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
32146 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
32147 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
32148 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
32149 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
32150 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
32151 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
32152 | //BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK |
32153 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
32154 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
32155 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
32156 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
32157 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
32158 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
32159 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
32160 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
32161 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
32162 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
32163 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
32164 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
32165 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
32166 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
32167 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
32168 | #define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
32169 | //BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL |
32170 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
32171 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
32172 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
32173 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
32174 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
32175 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
32176 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
32177 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
32178 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
32179 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
32180 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
32181 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
32182 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
32183 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
32184 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
32185 | #define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
32186 | //BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 |
32187 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
32188 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
32189 | //BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 |
32190 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
32191 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
32192 | //BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 |
32193 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
32194 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
32195 | //BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 |
32196 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
32197 | #define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
32198 | //BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD |
32199 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
32200 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
32201 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
32202 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
32203 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
32204 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
32205 | //BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS |
32206 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
32207 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
32208 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
32209 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
32210 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
32211 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
32212 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
32213 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
32214 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
32215 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
32216 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
32217 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
32218 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
32219 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
32220 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
32221 | #define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
32222 | //BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID |
32223 | #define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
32224 | #define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
32225 | #define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
32226 | #define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
32227 | //BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 |
32228 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
32229 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
32230 | //BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 |
32231 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
32232 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
32233 | //BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 |
32234 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
32235 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
32236 | //BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 |
32237 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
32238 | #define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
32239 | //BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST |
32240 | #define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32241 | #define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32242 | #define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32243 | #define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32244 | #define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32245 | #define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32246 | //BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 |
32247 | #define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
32248 | #define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
32249 | #define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
32250 | #define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
32251 | #define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
32252 | #define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
32253 | //BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS |
32254 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
32255 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
32256 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
32257 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
32258 | //BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL |
32259 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32260 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32261 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32262 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32263 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32264 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32265 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32266 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32267 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32268 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32269 | //BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL |
32270 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32271 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32272 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32273 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32274 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32275 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32276 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32277 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32278 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32279 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32280 | //BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL |
32281 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32282 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32283 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32284 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32285 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32286 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32287 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32288 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32289 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32290 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32291 | //BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL |
32292 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32293 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32294 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32295 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32296 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32297 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32298 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32299 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32300 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32301 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32302 | //BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL |
32303 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32304 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32305 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32306 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32307 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32308 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32309 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32310 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32311 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32312 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32313 | //BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL |
32314 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32315 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32316 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32317 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32318 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32319 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32320 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32321 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32322 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32323 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32324 | //BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL |
32325 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32326 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32327 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32328 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32329 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32330 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32331 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32332 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32333 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32334 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32335 | //BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL |
32336 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32337 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32338 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32339 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32340 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32341 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32342 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32343 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32344 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32345 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32346 | //BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL |
32347 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32348 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32349 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32350 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32351 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32352 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32353 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32354 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32355 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32356 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32357 | //BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL |
32358 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32359 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32360 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32361 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32362 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32363 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32364 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32365 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32366 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32367 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32368 | //BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL |
32369 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32370 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32371 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32372 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32373 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32374 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32375 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32376 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32377 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32378 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32379 | //BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL |
32380 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32381 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32382 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32383 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32384 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32385 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32386 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32387 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32388 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32389 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32390 | //BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL |
32391 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32392 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32393 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32394 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32395 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32396 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32397 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32398 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32399 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32400 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32401 | //BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL |
32402 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32403 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32404 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32405 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32406 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32407 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32408 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32409 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32410 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32411 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32412 | //BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL |
32413 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32414 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32415 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32416 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32417 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32418 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32419 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32420 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32421 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32422 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32423 | //BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL |
32424 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
32425 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
32426 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
32427 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
32428 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
32429 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
32430 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
32431 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
32432 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
32433 | #define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
32434 | //BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST |
32435 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32436 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32437 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32438 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32439 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32440 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32441 | //BIF_CFG_DEV0_RC1_PCIE_ACS_CAP |
32442 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
32443 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
32444 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
32445 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
32446 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
32447 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
32448 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
32449 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
32450 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
32451 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
32452 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
32453 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
32454 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
32455 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
32456 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
32457 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
32458 | //BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL |
32459 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
32460 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
32461 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
32462 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
32463 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
32464 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
32465 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
32466 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
32467 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
32468 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
32469 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
32470 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
32471 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
32472 | #define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
32473 | |
32474 | |
32475 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
32476 | //BIF_CFG_DEV1_RC1_VENDOR_ID |
32477 | #define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
32478 | #define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
32479 | //BIF_CFG_DEV1_RC1_DEVICE_ID |
32480 | #define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
32481 | #define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
32482 | //BIF_CFG_DEV1_RC1_COMMAND |
32483 | #define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN__SHIFT 0x0 |
32484 | #define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN__SHIFT 0x1 |
32485 | #define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
32486 | #define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
32487 | #define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
32488 | #define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
32489 | #define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
32490 | #define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING__SHIFT 0x7 |
32491 | #define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN__SHIFT 0x8 |
32492 | #define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
32493 | #define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS__SHIFT 0xa |
32494 | #define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN_MASK 0x0001L |
32495 | #define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN_MASK 0x0002L |
32496 | #define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
32497 | #define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
32498 | #define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
32499 | #define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
32500 | #define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
32501 | #define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING_MASK 0x0080L |
32502 | #define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN_MASK 0x0100L |
32503 | #define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
32504 | #define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS_MASK 0x0400L |
32505 | //BIF_CFG_DEV1_RC1_STATUS |
32506 | #define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS__SHIFT 0x3 |
32507 | #define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST__SHIFT 0x4 |
32508 | #define BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN__SHIFT 0x5 |
32509 | #define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
32510 | #define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
32511 | #define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
32512 | #define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
32513 | #define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
32514 | #define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
32515 | #define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
32516 | #define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
32517 | #define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS_MASK 0x0008L |
32518 | #define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST_MASK 0x0010L |
32519 | #define BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN_MASK 0x0020L |
32520 | #define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
32521 | #define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
32522 | #define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
32523 | #define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
32524 | #define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
32525 | #define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
32526 | #define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
32527 | #define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
32528 | //BIF_CFG_DEV1_RC1_REVISION_ID |
32529 | #define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
32530 | #define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
32531 | #define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
32532 | #define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
32533 | //BIF_CFG_DEV1_RC1_PROG_INTERFACE |
32534 | #define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
32535 | #define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
32536 | //BIF_CFG_DEV1_RC1_SUB_CLASS |
32537 | #define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
32538 | #define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
32539 | //BIF_CFG_DEV1_RC1_BASE_CLASS |
32540 | #define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
32541 | #define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
32542 | //BIF_CFG_DEV1_RC1_CACHE_LINE |
32543 | #define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
32544 | #define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
32545 | //BIF_CFG_DEV1_RC1_LATENCY |
32546 | #define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
32547 | #define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
32548 | //BIF_CFG_DEV1_RC1_HEADER |
32549 | #define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE__SHIFT 0x0 |
32550 | #define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
32551 | #define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE_MASK 0x7FL |
32552 | #define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE_MASK 0x80L |
32553 | //BIF_CFG_DEV1_RC1_BIST |
32554 | #define BIF_CFG_DEV1_RC1_BIST__BIST_COMP__SHIFT 0x0 |
32555 | #define BIF_CFG_DEV1_RC1_BIST__BIST_STRT__SHIFT 0x6 |
32556 | #define BIF_CFG_DEV1_RC1_BIST__BIST_CAP__SHIFT 0x7 |
32557 | #define BIF_CFG_DEV1_RC1_BIST__BIST_COMP_MASK 0x0FL |
32558 | #define BIF_CFG_DEV1_RC1_BIST__BIST_STRT_MASK 0x40L |
32559 | #define BIF_CFG_DEV1_RC1_BIST__BIST_CAP_MASK 0x80L |
32560 | //BIF_CFG_DEV1_RC1_BASE_ADDR_1 |
32561 | #define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
32562 | #define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
32563 | //BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY |
32564 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
32565 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
32566 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
32567 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
32568 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
32569 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
32570 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
32571 | #define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
32572 | //BIF_CFG_DEV1_RC1_IO_BASE_LIMIT |
32573 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
32574 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
32575 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
32576 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
32577 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
32578 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
32579 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
32580 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
32581 | //BIF_CFG_DEV1_RC1_SECONDARY_STATUS |
32582 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
32583 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
32584 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
32585 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
32586 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
32587 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
32588 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
32589 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
32590 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
32591 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
32592 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
32593 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
32594 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
32595 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
32596 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
32597 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
32598 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
32599 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
32600 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
32601 | #define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
32602 | //BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT |
32603 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
32604 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
32605 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
32606 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
32607 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
32608 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
32609 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
32610 | #define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
32611 | //BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT |
32612 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
32613 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
32614 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
32615 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
32616 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
32617 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
32618 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
32619 | #define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
32620 | //BIF_CFG_DEV1_RC1_PREF_BASE_UPPER |
32621 | #define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
32622 | #define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
32623 | //BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER |
32624 | #define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
32625 | #define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
32626 | //BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI |
32627 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
32628 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
32629 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
32630 | #define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
32631 | //BIF_CFG_DEV1_RC1_CAP_PTR |
32632 | #define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
32633 | #define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
32634 | //BIF_CFG_DEV1_RC1_INTERRUPT_LINE |
32635 | #define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
32636 | #define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
32637 | //BIF_CFG_DEV1_RC1_INTERRUPT_PIN |
32638 | #define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
32639 | #define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
32640 | //BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL |
32641 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
32642 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
32643 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
32644 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
32645 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
32646 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
32647 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
32648 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
32649 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
32650 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
32651 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
32652 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
32653 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
32654 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
32655 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
32656 | #define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
32657 | //BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL |
32658 | #define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
32659 | #define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
32660 | //BIF_CFG_DEV1_RC1_PMI_CAP_LIST |
32661 | #define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
32662 | #define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32663 | #define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
32664 | #define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
32665 | //BIF_CFG_DEV1_RC1_PMI_CAP |
32666 | #define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION__SHIFT 0x0 |
32667 | #define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
32668 | #define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
32669 | #define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
32670 | #define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
32671 | #define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
32672 | #define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
32673 | #define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION_MASK 0x0007L |
32674 | #define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
32675 | #define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
32676 | #define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
32677 | #define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
32678 | #define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
32679 | #define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
32680 | //BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL |
32681 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
32682 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
32683 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
32684 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
32685 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
32686 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
32687 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
32688 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
32689 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
32690 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
32691 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
32692 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
32693 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
32694 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
32695 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
32696 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
32697 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
32698 | #define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
32699 | //BIF_CFG_DEV1_RC1_PCIE_CAP_LIST |
32700 | #define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
32701 | #define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32702 | #define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
32703 | #define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
32704 | //BIF_CFG_DEV1_RC1_PCIE_CAP |
32705 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION__SHIFT 0x0 |
32706 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
32707 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
32708 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
32709 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION_MASK 0x000FL |
32710 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
32711 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
32712 | #define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
32713 | //BIF_CFG_DEV1_RC1_DEVICE_CAP |
32714 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
32715 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
32716 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
32717 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
32718 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
32719 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
32720 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
32721 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
32722 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
32723 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
32724 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
32725 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
32726 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
32727 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
32728 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
32729 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
32730 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
32731 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
32732 | //BIF_CFG_DEV1_RC1_DEVICE_CNTL |
32733 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
32734 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
32735 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
32736 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
32737 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
32738 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
32739 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
32740 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
32741 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
32742 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
32743 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
32744 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
32745 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
32746 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
32747 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
32748 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
32749 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
32750 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
32751 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
32752 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
32753 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
32754 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
32755 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
32756 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
32757 | //BIF_CFG_DEV1_RC1_DEVICE_STATUS |
32758 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
32759 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
32760 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
32761 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
32762 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
32763 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
32764 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
32765 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
32766 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
32767 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
32768 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
32769 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
32770 | //BIF_CFG_DEV1_RC1_LINK_CAP |
32771 | #define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
32772 | #define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
32773 | #define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
32774 | #define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
32775 | #define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
32776 | #define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
32777 | #define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
32778 | #define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
32779 | #define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
32780 | #define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
32781 | #define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
32782 | #define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
32783 | #define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
32784 | #define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
32785 | #define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
32786 | #define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
32787 | #define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
32788 | #define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
32789 | #define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
32790 | #define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
32791 | #define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
32792 | #define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
32793 | //BIF_CFG_DEV1_RC1_LINK_CNTL |
32794 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
32795 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
32796 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
32797 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
32798 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
32799 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
32800 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
32801 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
32802 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
32803 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
32804 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
32805 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
32806 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
32807 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
32808 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
32809 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
32810 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
32811 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
32812 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
32813 | #define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
32814 | //BIF_CFG_DEV1_RC1_LINK_STATUS |
32815 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
32816 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
32817 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
32818 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
32819 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
32820 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
32821 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
32822 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
32823 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
32824 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
32825 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
32826 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
32827 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
32828 | #define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
32829 | //BIF_CFG_DEV1_RC1_SLOT_CAP |
32830 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
32831 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
32832 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
32833 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
32834 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
32835 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
32836 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
32837 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
32838 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
32839 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
32840 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
32841 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
32842 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
32843 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
32844 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
32845 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
32846 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
32847 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
32848 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
32849 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
32850 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
32851 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
32852 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
32853 | #define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
32854 | //BIF_CFG_DEV1_RC1_SLOT_CNTL |
32855 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
32856 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
32857 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
32858 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
32859 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
32860 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
32861 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
32862 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
32863 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
32864 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
32865 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
32866 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
32867 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
32868 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
32869 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
32870 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
32871 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
32872 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
32873 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
32874 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
32875 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
32876 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
32877 | //BIF_CFG_DEV1_RC1_SLOT_STATUS |
32878 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
32879 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
32880 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
32881 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
32882 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
32883 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
32884 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
32885 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
32886 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
32887 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
32888 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
32889 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
32890 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
32891 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
32892 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
32893 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
32894 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
32895 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
32896 | //BIF_CFG_DEV1_RC1_ROOT_CNTL |
32897 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
32898 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
32899 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
32900 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
32901 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
32902 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
32903 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
32904 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
32905 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
32906 | #define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
32907 | //BIF_CFG_DEV1_RC1_ROOT_CAP |
32908 | #define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
32909 | #define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
32910 | //BIF_CFG_DEV1_RC1_ROOT_STATUS |
32911 | #define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
32912 | #define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
32913 | #define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
32914 | #define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
32915 | #define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
32916 | #define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
32917 | //BIF_CFG_DEV1_RC1_DEVICE_CAP2 |
32918 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
32919 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
32920 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
32921 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
32922 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
32923 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
32924 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
32925 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
32926 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
32927 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
32928 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
32929 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
32930 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
32931 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
32932 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
32933 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
32934 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
32935 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
32936 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
32937 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
32938 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
32939 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
32940 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
32941 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
32942 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
32943 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
32944 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
32945 | #define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
32946 | //BIF_CFG_DEV1_RC1_DEVICE_CNTL2 |
32947 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
32948 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
32949 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
32950 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
32951 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
32952 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
32953 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
32954 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
32955 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
32956 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
32957 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
32958 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
32959 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
32960 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
32961 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
32962 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
32963 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
32964 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
32965 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
32966 | #define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
32967 | //BIF_CFG_DEV1_RC1_DEVICE_STATUS2 |
32968 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
32969 | #define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
32970 | //BIF_CFG_DEV1_RC1_LINK_CAP2 |
32971 | #define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
32972 | #define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
32973 | #define BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED__SHIFT 0x9 |
32974 | #define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
32975 | #define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
32976 | #define BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
32977 | //BIF_CFG_DEV1_RC1_LINK_CNTL2 |
32978 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
32979 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
32980 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
32981 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
32982 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
32983 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
32984 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
32985 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
32986 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
32987 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
32988 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
32989 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
32990 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
32991 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
32992 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
32993 | #define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
32994 | //BIF_CFG_DEV1_RC1_LINK_STATUS2 |
32995 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
32996 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
32997 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
32998 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
32999 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
33000 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
33001 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
33002 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
33003 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
33004 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
33005 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
33006 | #define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
33007 | //BIF_CFG_DEV1_RC1_SLOT_CAP2 |
33008 | #define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
33009 | #define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
33010 | //BIF_CFG_DEV1_RC1_SLOT_CNTL2 |
33011 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
33012 | #define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
33013 | //BIF_CFG_DEV1_RC1_SLOT_STATUS2 |
33014 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
33015 | #define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
33016 | //BIF_CFG_DEV1_RC1_MSI_CAP_LIST |
33017 | #define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
33018 | #define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33019 | #define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
33020 | #define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33021 | //BIF_CFG_DEV1_RC1_MSI_MSG_CNTL |
33022 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
33023 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
33024 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
33025 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
33026 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
33027 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
33028 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
33029 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
33030 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
33031 | #define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
33032 | //BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO |
33033 | #define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
33034 | #define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
33035 | //BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI |
33036 | #define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
33037 | #define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
33038 | //BIF_CFG_DEV1_RC1_MSI_MSG_DATA |
33039 | #define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
33040 | #define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
33041 | //BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64 |
33042 | #define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
33043 | #define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
33044 | //BIF_CFG_DEV1_RC1_SSID_CAP_LIST |
33045 | #define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
33046 | #define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33047 | #define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
33048 | #define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33049 | //BIF_CFG_DEV1_RC1_SSID_CAP |
33050 | #define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
33051 | #define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
33052 | #define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
33053 | #define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
33054 | //BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST |
33055 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
33056 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33057 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
33058 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33059 | //BIF_CFG_DEV1_RC1_MSI_MAP_CAP |
33060 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN__SHIFT 0x0 |
33061 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
33062 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
33063 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN_MASK 0x0001L |
33064 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
33065 | #define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
33066 | //BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO |
33067 | #define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
33068 | #define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
33069 | //BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI |
33070 | #define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
33071 | #define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
33072 | //BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
33073 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33074 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33075 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33076 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33077 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33078 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33079 | //BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR |
33080 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
33081 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
33082 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
33083 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
33084 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
33085 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
33086 | //BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1 |
33087 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
33088 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
33089 | //BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2 |
33090 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
33091 | #define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
33092 | //BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST |
33093 | #define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33094 | #define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33095 | #define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33096 | #define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33097 | #define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33098 | #define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33099 | //BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1 |
33100 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
33101 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
33102 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
33103 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
33104 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
33105 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
33106 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
33107 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
33108 | //BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2 |
33109 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
33110 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
33111 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
33112 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
33113 | //BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL |
33114 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
33115 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
33116 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
33117 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
33118 | //BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS |
33119 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
33120 | #define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
33121 | //BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP |
33122 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
33123 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
33124 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
33125 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
33126 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
33127 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
33128 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
33129 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
33130 | //BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL |
33131 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
33132 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
33133 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
33134 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
33135 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
33136 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
33137 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
33138 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
33139 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
33140 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
33141 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
33142 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
33143 | //BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS |
33144 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
33145 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
33146 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
33147 | #define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
33148 | //BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP |
33149 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
33150 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
33151 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
33152 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
33153 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
33154 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
33155 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
33156 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
33157 | //BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL |
33158 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
33159 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
33160 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
33161 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
33162 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
33163 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
33164 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
33165 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
33166 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
33167 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
33168 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
33169 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
33170 | //BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS |
33171 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
33172 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
33173 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
33174 | #define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
33175 | //BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
33176 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33177 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33178 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33179 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33180 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33181 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33182 | //BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1 |
33183 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
33184 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
33185 | //BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2 |
33186 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
33187 | #define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
33188 | //BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
33189 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33190 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33191 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33192 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33193 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33194 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33195 | //BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS |
33196 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
33197 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
33198 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
33199 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
33200 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
33201 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
33202 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
33203 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
33204 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
33205 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
33206 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
33207 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
33208 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
33209 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
33210 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
33211 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
33212 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
33213 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
33214 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
33215 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
33216 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
33217 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
33218 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
33219 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
33220 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
33221 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
33222 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
33223 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
33224 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
33225 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
33226 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
33227 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
33228 | //BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK |
33229 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
33230 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
33231 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
33232 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
33233 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
33234 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
33235 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
33236 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
33237 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
33238 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
33239 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
33240 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
33241 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
33242 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
33243 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
33244 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
33245 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
33246 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
33247 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
33248 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
33249 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
33250 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
33251 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
33252 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
33253 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
33254 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
33255 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
33256 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
33257 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
33258 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
33259 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
33260 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
33261 | //BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY |
33262 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
33263 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
33264 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
33265 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
33266 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
33267 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
33268 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
33269 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
33270 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
33271 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
33272 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
33273 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
33274 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
33275 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
33276 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
33277 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
33278 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
33279 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
33280 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
33281 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
33282 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
33283 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
33284 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
33285 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
33286 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
33287 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
33288 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
33289 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
33290 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
33291 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
33292 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
33293 | #define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
33294 | //BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS |
33295 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
33296 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
33297 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
33298 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
33299 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
33300 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
33301 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
33302 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
33303 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
33304 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
33305 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
33306 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
33307 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
33308 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
33309 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
33310 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
33311 | //BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK |
33312 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
33313 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
33314 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
33315 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
33316 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
33317 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
33318 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
33319 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
33320 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
33321 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
33322 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
33323 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
33324 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
33325 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
33326 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
33327 | #define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
33328 | //BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL |
33329 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
33330 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
33331 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
33332 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
33333 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
33334 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
33335 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
33336 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
33337 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
33338 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
33339 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
33340 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
33341 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
33342 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
33343 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
33344 | #define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
33345 | //BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0 |
33346 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
33347 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
33348 | //BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1 |
33349 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
33350 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
33351 | //BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2 |
33352 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
33353 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
33354 | //BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3 |
33355 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
33356 | #define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
33357 | //BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD |
33358 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
33359 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
33360 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
33361 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
33362 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
33363 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
33364 | //BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS |
33365 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
33366 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
33367 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
33368 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
33369 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
33370 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
33371 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
33372 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
33373 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
33374 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
33375 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
33376 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
33377 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
33378 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
33379 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
33380 | #define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
33381 | //BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID |
33382 | #define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
33383 | #define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
33384 | #define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
33385 | #define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
33386 | //BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0 |
33387 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
33388 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
33389 | //BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1 |
33390 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
33391 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
33392 | //BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2 |
33393 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
33394 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
33395 | //BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3 |
33396 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
33397 | #define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
33398 | //BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST |
33399 | #define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33400 | #define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33401 | #define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33402 | #define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33403 | #define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33404 | #define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33405 | //BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3 |
33406 | #define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
33407 | #define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
33408 | #define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
33409 | #define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
33410 | #define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
33411 | #define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
33412 | //BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS |
33413 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
33414 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
33415 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
33416 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
33417 | //BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL |
33418 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33419 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33420 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33421 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33422 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33423 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33424 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33425 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33426 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33427 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33428 | //BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL |
33429 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33430 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33431 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33432 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33433 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33434 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33435 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33436 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33437 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33438 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33439 | //BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL |
33440 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33441 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33442 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33443 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33444 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33445 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33446 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33447 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33448 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33449 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33450 | //BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL |
33451 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33452 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33453 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33454 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33455 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33456 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33457 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33458 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33459 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33460 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33461 | //BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL |
33462 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33463 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33464 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33465 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33466 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33467 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33468 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33469 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33470 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33471 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33472 | //BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL |
33473 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33474 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33475 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33476 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33477 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33478 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33479 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33480 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33481 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33482 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33483 | //BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL |
33484 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33485 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33486 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33487 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33488 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33489 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33490 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33491 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33492 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33493 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33494 | //BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL |
33495 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33496 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33497 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33498 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33499 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33500 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33501 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33502 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33503 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33504 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33505 | //BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL |
33506 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33507 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33508 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33509 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33510 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33511 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33512 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33513 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33514 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33515 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33516 | //BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL |
33517 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33518 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33519 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33520 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33521 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33522 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33523 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33524 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33525 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33526 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33527 | //BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL |
33528 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33529 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33530 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33531 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33532 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33533 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33534 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33535 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33536 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33537 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33538 | //BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL |
33539 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33540 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33541 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33542 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33543 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33544 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33545 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33546 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33547 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33548 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33549 | //BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL |
33550 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33551 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33552 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33553 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33554 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33555 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33556 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33557 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33558 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33559 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33560 | //BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL |
33561 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33562 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33563 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33564 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33565 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33566 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33567 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33568 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33569 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33570 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33571 | //BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL |
33572 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33573 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33574 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33575 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33576 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33577 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33578 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33579 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33580 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33581 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33582 | //BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL |
33583 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
33584 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
33585 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
33586 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
33587 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
33588 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
33589 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
33590 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
33591 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
33592 | #define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
33593 | //BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST |
33594 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33595 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33596 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33597 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33598 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33599 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33600 | //BIF_CFG_DEV1_RC1_PCIE_ACS_CAP |
33601 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
33602 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
33603 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
33604 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
33605 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
33606 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
33607 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
33608 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
33609 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
33610 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
33611 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
33612 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
33613 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
33614 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
33615 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
33616 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
33617 | //BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL |
33618 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
33619 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
33620 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
33621 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
33622 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
33623 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
33624 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
33625 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
33626 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
33627 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
33628 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
33629 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
33630 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
33631 | #define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
33632 | |
33633 | |
33634 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
33635 | //BIF_BX_PF0_MM_INDEX |
33636 | #define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
33637 | #define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f |
33638 | #define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
33639 | #define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L |
33640 | //BIF_BX_PF0_MM_DATA |
33641 | #define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 |
33642 | #define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
33643 | //BIF_BX_PF0_MM_INDEX_HI |
33644 | #define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
33645 | #define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
33646 | |
33647 | |
33648 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
33649 | //BIF_BX_PF0_SYSHUB_INDEX_OVLP |
33650 | #define BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 |
33651 | #define BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL |
33652 | //BIF_BX_PF0_SYSHUB_DATA_OVLP |
33653 | #define BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 |
33654 | #define BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL |
33655 | //BIF_BX_PF0_PCIE_INDEX |
33656 | #define BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
33657 | #define BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
33658 | //BIF_BX_PF0_PCIE_DATA |
33659 | #define BIF_BX_PF0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
33660 | #define BIF_BX_PF0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
33661 | //BIF_BX_PF0_PCIE_INDEX2 |
33662 | #define BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
33663 | #define BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
33664 | //BIF_BX_PF0_PCIE_DATA2 |
33665 | #define BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
33666 | #define BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
33667 | //BIF_BX_PF0_SBIOS_SCRATCH_0 |
33668 | #define BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
33669 | #define BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
33670 | //BIF_BX_PF0_SBIOS_SCRATCH_1 |
33671 | #define BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
33672 | #define BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
33673 | //BIF_BX_PF0_SBIOS_SCRATCH_2 |
33674 | #define BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
33675 | #define BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
33676 | //BIF_BX_PF0_SBIOS_SCRATCH_3 |
33677 | #define BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
33678 | #define BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
33679 | //BIF_BX_PF0_BIOS_SCRATCH_0 |
33680 | #define BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
33681 | #define BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
33682 | //BIF_BX_PF0_BIOS_SCRATCH_1 |
33683 | #define BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
33684 | #define BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
33685 | //BIF_BX_PF0_BIOS_SCRATCH_2 |
33686 | #define BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
33687 | #define BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
33688 | //BIF_BX_PF0_BIOS_SCRATCH_3 |
33689 | #define BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
33690 | #define BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
33691 | //BIF_BX_PF0_BIOS_SCRATCH_4 |
33692 | #define BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
33693 | #define BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
33694 | //BIF_BX_PF0_BIOS_SCRATCH_5 |
33695 | #define BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
33696 | #define BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
33697 | //BIF_BX_PF0_BIOS_SCRATCH_6 |
33698 | #define BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
33699 | #define BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
33700 | //BIF_BX_PF0_BIOS_SCRATCH_7 |
33701 | #define BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
33702 | #define BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
33703 | //BIF_BX_PF0_BIOS_SCRATCH_8 |
33704 | #define BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
33705 | #define BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
33706 | //BIF_BX_PF0_BIOS_SCRATCH_9 |
33707 | #define BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
33708 | #define BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
33709 | //BIF_BX_PF0_BIOS_SCRATCH_10 |
33710 | #define BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
33711 | #define BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
33712 | //BIF_BX_PF0_BIOS_SCRATCH_11 |
33713 | #define BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
33714 | #define BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
33715 | //BIF_BX_PF0_BIOS_SCRATCH_12 |
33716 | #define BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
33717 | #define BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
33718 | //BIF_BX_PF0_BIOS_SCRATCH_13 |
33719 | #define BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
33720 | #define BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
33721 | //BIF_BX_PF0_BIOS_SCRATCH_14 |
33722 | #define BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
33723 | #define BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
33724 | //BIF_BX_PF0_BIOS_SCRATCH_15 |
33725 | #define BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
33726 | #define BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
33727 | //BIF_BX_PF0_BIF_RLC_INTR_CNTL |
33728 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
33729 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
33730 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
33731 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
33732 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
33733 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
33734 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
33735 | #define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
33736 | //BIF_BX_PF0_BIF_VCE_INTR_CNTL |
33737 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
33738 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
33739 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
33740 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
33741 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
33742 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
33743 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
33744 | #define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
33745 | //BIF_BX_PF0_BIF_UVD_INTR_CNTL |
33746 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
33747 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
33748 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
33749 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
33750 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
33751 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
33752 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
33753 | #define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
33754 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0 |
33755 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
33756 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
33757 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0 |
33758 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
33759 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
33760 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1 |
33761 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
33762 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
33763 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1 |
33764 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
33765 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
33766 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2 |
33767 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
33768 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
33769 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2 |
33770 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
33771 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
33772 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3 |
33773 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
33774 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
33775 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3 |
33776 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
33777 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
33778 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4 |
33779 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
33780 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
33781 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4 |
33782 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
33783 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
33784 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5 |
33785 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
33786 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
33787 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5 |
33788 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
33789 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
33790 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6 |
33791 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
33792 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
33793 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6 |
33794 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
33795 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
33796 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7 |
33797 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
33798 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
33799 | //BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7 |
33800 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
33801 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
33802 | //BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL |
33803 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
33804 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
33805 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL |
33806 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
33807 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
33808 | //BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL |
33809 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
33810 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
33811 | //BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
33812 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
33813 | #define BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
33814 | |
33815 | |
33816 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
33817 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 |
33818 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
33819 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
33820 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
33821 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
33822 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
33823 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
33824 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
33825 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
33826 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
33827 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
33828 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
33829 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
33830 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
33831 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
33832 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
33833 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
33834 | |
33835 | |
33836 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
33837 | //RCC_EP_DEV0_0_EP_PCIE_SCRATCH |
33838 | #define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
33839 | #define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
33840 | //RCC_EP_DEV0_0_EP_PCIE_CNTL |
33841 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
33842 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
33843 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
33844 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
33845 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
33846 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
33847 | //RCC_EP_DEV0_0_EP_PCIE_INT_CNTL |
33848 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
33849 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
33850 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
33851 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
33852 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
33853 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
33854 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
33855 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
33856 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
33857 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
33858 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
33859 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
33860 | //RCC_EP_DEV0_0_EP_PCIE_INT_STATUS |
33861 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
33862 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
33863 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
33864 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
33865 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
33866 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
33867 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
33868 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
33869 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
33870 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
33871 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
33872 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
33873 | //RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 |
33874 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
33875 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
33876 | //RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL |
33877 | #define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
33878 | #define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
33879 | //RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL |
33880 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
33881 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
33882 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
33883 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
33884 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
33885 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
33886 | //RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL |
33887 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
33888 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
33889 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
33890 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
33891 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
33892 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
33893 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
33894 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
33895 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
33896 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
33897 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
33898 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
33899 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
33900 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
33901 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
33902 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
33903 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
33904 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
33905 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
33906 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
33907 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
33908 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33909 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33910 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
33911 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33912 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33913 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
33914 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33915 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33916 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
33917 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33918 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33919 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
33920 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33921 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33922 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
33923 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33924 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33925 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
33926 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33927 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33928 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
33929 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33930 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33931 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP |
33932 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
33933 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
33934 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
33935 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
33936 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
33937 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
33938 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
33939 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
33940 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
33941 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
33942 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
33943 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL |
33944 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
33945 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
33946 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
33947 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
33948 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
33949 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33950 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33951 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
33952 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33953 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33954 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
33955 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33956 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33957 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
33958 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33959 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33960 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
33961 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33962 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33963 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
33964 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33965 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33966 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
33967 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33968 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33969 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
33970 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33971 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33972 | //RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL |
33973 | #define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
33974 | #define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
33975 | //RCC_EP_DEV0_0_EP_PCIEP_RESERVED |
33976 | #define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
33977 | #define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
33978 | //RCC_EP_DEV0_0_EP_PCIE_TX_CNTL |
33979 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
33980 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
33981 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
33982 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
33983 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
33984 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
33985 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
33986 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
33987 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
33988 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
33989 | //RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID |
33990 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
33991 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
33992 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
33993 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
33994 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
33995 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
33996 | //RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL |
33997 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
33998 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
33999 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
34000 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
34001 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
34002 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
34003 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
34004 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
34005 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
34006 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
34007 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
34008 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
34009 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
34010 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
34011 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
34012 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
34013 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
34014 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
34015 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
34016 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
34017 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
34018 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
34019 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
34020 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
34021 | //RCC_EP_DEV0_0_EP_PCIE_RX_CNTL |
34022 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
34023 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
34024 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
34025 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
34026 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
34027 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
34028 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
34029 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
34030 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
34031 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
34032 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
34033 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
34034 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
34035 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
34036 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
34037 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
34038 | //RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL |
34039 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
34040 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
34041 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
34042 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
34043 | |
34044 | |
34045 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
34046 | //RCC_DWN_DEV0_0_DN_PCIE_RESERVED |
34047 | #define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
34048 | #define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
34049 | //RCC_DWN_DEV0_0_DN_PCIE_SCRATCH |
34050 | #define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
34051 | #define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
34052 | //RCC_DWN_DEV0_0_DN_PCIE_CNTL |
34053 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
34054 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
34055 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
34056 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
34057 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
34058 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
34059 | //RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL |
34060 | #define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
34061 | #define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
34062 | //RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 |
34063 | #define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
34064 | #define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
34065 | //RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL |
34066 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
34067 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
34068 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
34069 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
34070 | //RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL |
34071 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
34072 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
34073 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
34074 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
34075 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
34076 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
34077 | |
34078 | |
34079 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
34080 | //RCC_DWNP_DEV0_0_PCIE_ERR_CNTL |
34081 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
34082 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
34083 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
34084 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
34085 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
34086 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
34087 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
34088 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
34089 | //RCC_DWNP_DEV0_0_PCIE_RX_CNTL |
34090 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
34091 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
34092 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
34093 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
34094 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
34095 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
34096 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
34097 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
34098 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
34099 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
34100 | //RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL |
34101 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
34102 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
34103 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
34104 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
34105 | //RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 |
34106 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
34107 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
34108 | //RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC |
34109 | #define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
34110 | #define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
34111 | //RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP |
34112 | #define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
34113 | #define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
34114 | |
34115 | |
34116 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
34117 | //BIF_BX_PF0_BIF_MM_INDACCESS_CNTL |
34118 | #define BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
34119 | #define BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
34120 | //BIF_BX_PF0_BUS_CNTL |
34121 | #define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 |
34122 | #define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 |
34123 | #define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 |
34124 | #define BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
34125 | #define BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
34126 | #define BIF_BX_PF0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
34127 | #define BIF_BX_PF0_BUS_CNTL__SET_MC_TC__SHIFT 0xd |
34128 | #define BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
34129 | #define BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
34130 | #define BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
34131 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 |
34132 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 |
34133 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 |
34134 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 |
34135 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 |
34136 | #define BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 |
34137 | #define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
34138 | #define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
34139 | #define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b |
34140 | #define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c |
34141 | #define BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
34142 | #define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
34143 | #define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
34144 | #define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L |
34145 | #define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L |
34146 | #define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L |
34147 | #define BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
34148 | #define BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
34149 | #define BIF_BX_PF0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
34150 | #define BIF_BX_PF0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
34151 | #define BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
34152 | #define BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
34153 | #define BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
34154 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L |
34155 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L |
34156 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L |
34157 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L |
34158 | #define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L |
34159 | #define BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L |
34160 | #define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
34161 | #define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
34162 | #define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L |
34163 | #define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L |
34164 | #define BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
34165 | #define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
34166 | #define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
34167 | //BIF_BX_PF0_BIF_SCRATCH0 |
34168 | #define BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
34169 | #define BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
34170 | //BIF_BX_PF0_BIF_SCRATCH1 |
34171 | #define BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
34172 | #define BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
34173 | //BIF_BX_PF0_BX_RESET_EN |
34174 | #define BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 |
34175 | #define BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 |
34176 | #define BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 |
34177 | #define BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 |
34178 | #define BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
34179 | #define BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L |
34180 | #define BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L |
34181 | #define BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L |
34182 | #define BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L |
34183 | #define BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
34184 | //BIF_BX_PF0_MM_CFGREGS_CNTL |
34185 | #define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
34186 | #define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
34187 | #define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
34188 | #define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
34189 | #define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
34190 | #define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
34191 | //BIF_BX_PF0_BX_RESET_CNTL |
34192 | #define BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
34193 | #define BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
34194 | //BIF_BX_PF0_INTERRUPT_CNTL |
34195 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
34196 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
34197 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
34198 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
34199 | #define BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
34200 | #define BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
34201 | #define BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
34202 | #define BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
34203 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
34204 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
34205 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
34206 | #define BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
34207 | #define BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
34208 | #define BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
34209 | #define BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
34210 | #define BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
34211 | //BIF_BX_PF0_INTERRUPT_CNTL2 |
34212 | #define BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
34213 | #define BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
34214 | //BIF_BX_PF0_CLKREQB_PAD_CNTL |
34215 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
34216 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
34217 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
34218 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
34219 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
34220 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
34221 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
34222 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
34223 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
34224 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
34225 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
34226 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
34227 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
34228 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
34229 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
34230 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
34231 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
34232 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
34233 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
34234 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
34235 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
34236 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
34237 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
34238 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
34239 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
34240 | #define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
34241 | //BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC |
34242 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
34243 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
34244 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
34245 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
34246 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
34247 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
34248 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
34249 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 |
34250 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 |
34251 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
34252 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
34253 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
34254 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
34255 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
34256 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
34257 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
34258 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
34259 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L |
34260 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L |
34261 | #define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
34262 | //BIF_BX_PF0_BIF_DOORBELL_CNTL |
34263 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
34264 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
34265 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
34266 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
34267 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
34268 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
34269 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
34270 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
34271 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
34272 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
34273 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
34274 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
34275 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
34276 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
34277 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
34278 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
34279 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
34280 | #define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
34281 | //BIF_BX_PF0_BIF_DOORBELL_INT_CNTL |
34282 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
34283 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 |
34284 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
34285 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 |
34286 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
34287 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L |
34288 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
34289 | #define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L |
34290 | //BIF_BX_PF0_BIF_FB_EN |
34291 | #define BIF_BX_PF0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
34292 | #define BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
34293 | #define BIF_BX_PF0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
34294 | #define BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
34295 | //BIF_BX_PF0_BIF_BUSY_DELAY_CNTR |
34296 | #define BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 |
34297 | #define BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL |
34298 | //BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF |
34299 | #define BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
34300 | #define BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL |
34301 | //BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF |
34302 | #define BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
34303 | #define BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL |
34304 | //BIF_BX_PF0_BACO_CNTL |
34305 | #define BIF_BX_PF0_BACO_CNTL__BACO_EN__SHIFT 0x0 |
34306 | #define BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 |
34307 | #define BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
34308 | #define BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
34309 | #define BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
34310 | #define BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
34311 | #define BIF_BX_PF0_BACO_CNTL__BACO_MODE__SHIFT 0x8 |
34312 | #define BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
34313 | #define BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
34314 | #define BIF_BX_PF0_BACO_CNTL__BACO_EN_MASK 0x00000001L |
34315 | #define BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L |
34316 | #define BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
34317 | #define BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
34318 | #define BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
34319 | #define BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
34320 | #define BIF_BX_PF0_BACO_CNTL__BACO_MODE_MASK 0x00000100L |
34321 | #define BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
34322 | #define BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
34323 | //BIF_BX_PF0_BIF_BACO_EXIT_TIME0 |
34324 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
34325 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
34326 | //BIF_BX_PF0_BIF_BACO_EXIT_TIMER1 |
34327 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
34328 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
34329 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19 |
34330 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
34331 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
34332 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
34333 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
34334 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
34335 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
34336 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
34337 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L |
34338 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
34339 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
34340 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
34341 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
34342 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
34343 | //BIF_BX_PF0_BIF_BACO_EXIT_TIMER2 |
34344 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
34345 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
34346 | //BIF_BX_PF0_BIF_BACO_EXIT_TIMER3 |
34347 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
34348 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
34349 | //BIF_BX_PF0_BIF_BACO_EXIT_TIMER4 |
34350 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
34351 | #define BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
34352 | //BIF_BX_PF0_MEM_TYPE_CNTL |
34353 | #define BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
34354 | #define BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
34355 | //BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS |
34356 | #define BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 |
34357 | #define BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L |
34358 | //BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER |
34359 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 |
34360 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e |
34361 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f |
34362 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL |
34363 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L |
34364 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L |
34365 | //BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER |
34366 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 |
34367 | #define BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL |
34368 | //BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER |
34369 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 |
34370 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e |
34371 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f |
34372 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL |
34373 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L |
34374 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L |
34375 | //BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER |
34376 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 |
34377 | #define BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL |
34378 | //BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER |
34379 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 |
34380 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e |
34381 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f |
34382 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL |
34383 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L |
34384 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L |
34385 | //BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER |
34386 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 |
34387 | #define BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL |
34388 | //BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER |
34389 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 |
34390 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e |
34391 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f |
34392 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL |
34393 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L |
34394 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L |
34395 | //BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER |
34396 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 |
34397 | #define BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL |
34398 | //BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER |
34399 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 |
34400 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e |
34401 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f |
34402 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL |
34403 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L |
34404 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L |
34405 | //BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER |
34406 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 |
34407 | #define BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL |
34408 | //BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER |
34409 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 |
34410 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e |
34411 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f |
34412 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL |
34413 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L |
34414 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L |
34415 | //BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER |
34416 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 |
34417 | #define BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL |
34418 | //BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER |
34419 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 |
34420 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e |
34421 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f |
34422 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL |
34423 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L |
34424 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L |
34425 | //BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER |
34426 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 |
34427 | #define BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL |
34428 | //BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER |
34429 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 |
34430 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e |
34431 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f |
34432 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL |
34433 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L |
34434 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L |
34435 | //BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER |
34436 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 |
34437 | #define BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL |
34438 | //BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER |
34439 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 |
34440 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e |
34441 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f |
34442 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL |
34443 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L |
34444 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L |
34445 | //BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER |
34446 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 |
34447 | #define BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL |
34448 | //BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER |
34449 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 |
34450 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e |
34451 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f |
34452 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL |
34453 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L |
34454 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L |
34455 | //BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER |
34456 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 |
34457 | #define BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL |
34458 | //BIF_BX_PF0_BIF_VDDGFX_FB_CMP |
34459 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 |
34460 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 |
34461 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 |
34462 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 |
34463 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 |
34464 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 |
34465 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L |
34466 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L |
34467 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L |
34468 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L |
34469 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L |
34470 | #define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L |
34471 | //BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER |
34472 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 |
34473 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f |
34474 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL |
34475 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L |
34476 | //BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER |
34477 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 |
34478 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL |
34479 | //BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER |
34480 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 |
34481 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f |
34482 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL |
34483 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L |
34484 | //BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER |
34485 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 |
34486 | #define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL |
34487 | //BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL |
34488 | #define BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
34489 | #define BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
34490 | //BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL |
34491 | #define BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
34492 | #define BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
34493 | //BIF_BX_PF0_BIF_RB_CNTL |
34494 | #define BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
34495 | #define BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
34496 | #define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
34497 | #define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
34498 | #define BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
34499 | #define BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
34500 | #define BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
34501 | #define BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
34502 | #define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
34503 | #define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
34504 | #define BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
34505 | #define BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
34506 | //BIF_BX_PF0_BIF_RB_BASE |
34507 | #define BIF_BX_PF0_BIF_RB_BASE__ADDR__SHIFT 0x0 |
34508 | #define BIF_BX_PF0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
34509 | //BIF_BX_PF0_BIF_RB_RPTR |
34510 | #define BIF_BX_PF0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
34511 | #define BIF_BX_PF0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
34512 | //BIF_BX_PF0_BIF_RB_WPTR |
34513 | #define BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
34514 | #define BIF_BX_PF0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
34515 | #define BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
34516 | #define BIF_BX_PF0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
34517 | //BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI |
34518 | #define BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
34519 | #define BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
34520 | //BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO |
34521 | #define BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
34522 | #define BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
34523 | //BIF_BX_PF0_MAILBOX_INDEX |
34524 | #define BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
34525 | #define BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
34526 | //BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE |
34527 | #define BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 |
34528 | #define BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
34529 | //BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE |
34530 | #define BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 |
34531 | #define BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
34532 | //BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
34533 | #define BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
34534 | #define BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
34535 | //BIF_BX_PF0_BIF_PERSTB_PAD_CNTL |
34536 | #define BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
34537 | #define BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
34538 | //BIF_BX_PF0_BIF_PX_EN_PAD_CNTL |
34539 | #define BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
34540 | #define BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
34541 | //BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL |
34542 | #define BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
34543 | #define BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
34544 | //BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL |
34545 | #define BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
34546 | #define BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
34547 | |
34548 | |
34549 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
34550 | //BIF_BX_PF0_BIF_BME_STATUS |
34551 | #define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
34552 | #define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
34553 | #define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
34554 | #define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
34555 | //BIF_BX_PF0_BIF_ATOMIC_ERR_LOG |
34556 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
34557 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
34558 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
34559 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
34560 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
34561 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
34562 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
34563 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
34564 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
34565 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
34566 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
34567 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
34568 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
34569 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
34570 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
34571 | #define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
34572 | //BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
34573 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
34574 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
34575 | //BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
34576 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
34577 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
34578 | //BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL |
34579 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
34580 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
34581 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
34582 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
34583 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
34584 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
34585 | //BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL |
34586 | #define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
34587 | #define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
34588 | //BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL |
34589 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
34590 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
34591 | //BIF_BX_PF0_GPU_HDP_FLUSH_REQ |
34592 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
34593 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
34594 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
34595 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
34596 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
34597 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
34598 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
34599 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
34600 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
34601 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
34602 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
34603 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
34604 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
34605 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
34606 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
34607 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
34608 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
34609 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
34610 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
34611 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
34612 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
34613 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
34614 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
34615 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
34616 | //BIF_BX_PF0_GPU_HDP_FLUSH_DONE |
34617 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
34618 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
34619 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
34620 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
34621 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
34622 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
34623 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
34624 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
34625 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
34626 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
34627 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
34628 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
34629 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
34630 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
34631 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
34632 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
34633 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
34634 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
34635 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
34636 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
34637 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
34638 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
34639 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
34640 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
34641 | //BIF_BX_PF0_BIF_TRANS_PENDING |
34642 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
34643 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
34644 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
34645 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
34646 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 |
34647 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
34648 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34649 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 |
34650 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
34651 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34652 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 |
34653 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
34654 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34655 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 |
34656 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
34657 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34658 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 |
34659 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
34660 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34661 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 |
34662 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
34663 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34664 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 |
34665 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
34666 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34667 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 |
34668 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
34669 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
34670 | //BIF_BX_PF0_MAILBOX_CONTROL |
34671 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
34672 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
34673 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
34674 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
34675 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
34676 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
34677 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
34678 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
34679 | //BIF_BX_PF0_MAILBOX_INT_CNTL |
34680 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
34681 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
34682 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
34683 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
34684 | //BIF_BX_PF0_BIF_VMHV_MAILBOX |
34685 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
34686 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
34687 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
34688 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
34689 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
34690 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
34691 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
34692 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
34693 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
34694 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
34695 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
34696 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
34697 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
34698 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
34699 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
34700 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
34701 | |
34702 | |
34703 | // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec |
34704 | //SHADOW_COMMAND |
34705 | #define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 |
34706 | #define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 |
34707 | #define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L |
34708 | #define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L |
34709 | //SHADOW_BASE_ADDR_1 |
34710 | #define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 |
34711 | #define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL |
34712 | //SHADOW_BASE_ADDR_2 |
34713 | #define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 |
34714 | #define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL |
34715 | //SHADOW_SUB_BUS_NUMBER_LATENCY |
34716 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 |
34717 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 |
34718 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L |
34719 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L |
34720 | //SHADOW_IO_BASE_LIMIT |
34721 | #define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 |
34722 | #define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc |
34723 | #define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L |
34724 | #define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L |
34725 | //SHADOW_MEM_BASE_LIMIT |
34726 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
34727 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 |
34728 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
34729 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 |
34730 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
34731 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L |
34732 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
34733 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L |
34734 | //SHADOW_PREF_BASE_LIMIT |
34735 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
34736 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 |
34737 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
34738 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 |
34739 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
34740 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L |
34741 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
34742 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L |
34743 | //SHADOW_PREF_BASE_UPPER |
34744 | #define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 |
34745 | #define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL |
34746 | //SHADOW_PREF_LIMIT_UPPER |
34747 | #define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 |
34748 | #define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL |
34749 | //SHADOW_IO_BASE_LIMIT_HI |
34750 | #define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 |
34751 | #define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 |
34752 | #define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL |
34753 | #define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L |
34754 | //SHADOW_IRQ_BRIDGE_CNTL |
34755 | #define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 |
34756 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 |
34757 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 |
34758 | #define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 |
34759 | #define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L |
34760 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L |
34761 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L |
34762 | #define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L |
34763 | //SUC_INDEX |
34764 | #define SUC_INDEX__SUC_INDEX__SHIFT 0x0 |
34765 | #define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL |
34766 | //SUC_DATA |
34767 | #define SUC_DATA__SUC_DATA__SHIFT 0x0 |
34768 | #define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL |
34769 | |
34770 | |
34771 | // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC |
34772 | //RCC_EP_DEV0_1_EP_PCIE_SCRATCH |
34773 | #define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
34774 | #define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
34775 | //RCC_EP_DEV0_1_EP_PCIE_CNTL |
34776 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
34777 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
34778 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
34779 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
34780 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
34781 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
34782 | //RCC_EP_DEV0_1_EP_PCIE_INT_CNTL |
34783 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
34784 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
34785 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
34786 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
34787 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
34788 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
34789 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
34790 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
34791 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
34792 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
34793 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
34794 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
34795 | //RCC_EP_DEV0_1_EP_PCIE_INT_STATUS |
34796 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
34797 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
34798 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
34799 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
34800 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
34801 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
34802 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
34803 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
34804 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
34805 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
34806 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
34807 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
34808 | //RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 |
34809 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
34810 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
34811 | //RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL |
34812 | #define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
34813 | #define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
34814 | //RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL |
34815 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
34816 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
34817 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
34818 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
34819 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
34820 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
34821 | //RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL |
34822 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
34823 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
34824 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
34825 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
34826 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
34827 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
34828 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
34829 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
34830 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
34831 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
34832 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
34833 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
34834 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
34835 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
34836 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
34837 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
34838 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
34839 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
34840 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
34841 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
34842 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP |
34843 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
34844 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
34845 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
34846 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
34847 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
34848 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
34849 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
34850 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
34851 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
34852 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
34853 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
34854 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL |
34855 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
34856 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
34857 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
34858 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
34859 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
34860 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34861 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34862 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
34863 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34864 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34865 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
34866 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34867 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34868 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
34869 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34870 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34871 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
34872 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34873 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34874 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
34875 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34876 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34877 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
34878 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34879 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34880 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
34881 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34882 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34883 | //RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL |
34884 | #define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
34885 | #define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
34886 | //RCC_EP_DEV0_1_EP_PCIEP_RESERVED |
34887 | #define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
34888 | #define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
34889 | //RCC_EP_DEV0_1_EP_PCIE_TX_CNTL |
34890 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
34891 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
34892 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
34893 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
34894 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
34895 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
34896 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
34897 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
34898 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
34899 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
34900 | //RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID |
34901 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
34902 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
34903 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
34904 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
34905 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
34906 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
34907 | //RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL |
34908 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
34909 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
34910 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
34911 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
34912 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
34913 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
34914 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
34915 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
34916 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
34917 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
34918 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
34919 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
34920 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
34921 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
34922 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
34923 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
34924 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
34925 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
34926 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
34927 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
34928 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
34929 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
34930 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
34931 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
34932 | //RCC_EP_DEV0_1_EP_PCIE_RX_CNTL |
34933 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
34934 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
34935 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
34936 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
34937 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
34938 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
34939 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
34940 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
34941 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
34942 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
34943 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
34944 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
34945 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
34946 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
34947 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
34948 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
34949 | //RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL |
34950 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
34951 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
34952 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
34953 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
34954 | |
34955 | |
34956 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC |
34957 | //RCC_DWN_DEV0_1_DN_PCIE_RESERVED |
34958 | #define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
34959 | #define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
34960 | //RCC_DWN_DEV0_1_DN_PCIE_SCRATCH |
34961 | #define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
34962 | #define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
34963 | //RCC_DWN_DEV0_1_DN_PCIE_CNTL |
34964 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
34965 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
34966 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
34967 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
34968 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
34969 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
34970 | //RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL |
34971 | #define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
34972 | #define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
34973 | //RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 |
34974 | #define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
34975 | #define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
34976 | //RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL |
34977 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
34978 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
34979 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
34980 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
34981 | //RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL |
34982 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
34983 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
34984 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
34985 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
34986 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
34987 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
34988 | |
34989 | |
34990 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC |
34991 | //RCC_DWNP_DEV0_1_PCIE_ERR_CNTL |
34992 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
34993 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
34994 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
34995 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
34996 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
34997 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
34998 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
34999 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
35000 | //RCC_DWNP_DEV0_1_PCIE_RX_CNTL |
35001 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
35002 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
35003 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
35004 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
35005 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
35006 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
35007 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
35008 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
35009 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
35010 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
35011 | //RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL |
35012 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
35013 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
35014 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
35015 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
35016 | //RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 |
35017 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
35018 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
35019 | //RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC |
35020 | #define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
35021 | #define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
35022 | //RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP |
35023 | #define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
35024 | #define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
35025 | |
35026 | |
35027 | // addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC |
35028 | //RCC_EP_DEV1_EP_PCIE_SCRATCH |
35029 | #define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
35030 | #define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
35031 | //RCC_EP_DEV1_EP_PCIE_CNTL |
35032 | #define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
35033 | #define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
35034 | #define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
35035 | #define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
35036 | #define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
35037 | #define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
35038 | //RCC_EP_DEV1_EP_PCIE_INT_CNTL |
35039 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
35040 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
35041 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
35042 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
35043 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
35044 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
35045 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
35046 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
35047 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
35048 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
35049 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
35050 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
35051 | //RCC_EP_DEV1_EP_PCIE_INT_STATUS |
35052 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
35053 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
35054 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
35055 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
35056 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
35057 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
35058 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
35059 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
35060 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
35061 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
35062 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
35063 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
35064 | //RCC_EP_DEV1_EP_PCIE_RX_CNTL2 |
35065 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
35066 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
35067 | //RCC_EP_DEV1_EP_PCIE_BUS_CNTL |
35068 | #define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
35069 | #define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
35070 | //RCC_EP_DEV1_EP_PCIE_CFG_CNTL |
35071 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
35072 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
35073 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
35074 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
35075 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
35076 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
35077 | //RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL |
35078 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
35079 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
35080 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
35081 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
35082 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
35083 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
35084 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
35085 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
35086 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
35087 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
35088 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
35089 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
35090 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
35091 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
35092 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
35093 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
35094 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
35095 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
35096 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
35097 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
35098 | //RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP |
35099 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
35100 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
35101 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
35102 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
35103 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
35104 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
35105 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
35106 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
35107 | //RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
35108 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
35109 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
35110 | //RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL |
35111 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
35112 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
35113 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
35114 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
35115 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
35116 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35117 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35118 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
35119 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35120 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35121 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
35122 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35123 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35124 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
35125 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35126 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35127 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
35128 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35129 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35130 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
35131 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35132 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35133 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
35134 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35135 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35136 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
35137 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35138 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35139 | //RCC_EP_DEV1_EP_PCIE_PME_CONTROL |
35140 | #define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
35141 | #define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
35142 | //RCC_EP_DEV1_EP_PCIEP_RESERVED |
35143 | #define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
35144 | #define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
35145 | //RCC_EP_DEV1_EP_PCIE_TX_CNTL |
35146 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
35147 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
35148 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
35149 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
35150 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
35151 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
35152 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
35153 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
35154 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
35155 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
35156 | //RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID |
35157 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
35158 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
35159 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
35160 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
35161 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
35162 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
35163 | //RCC_EP_DEV1_EP_PCIE_ERR_CNTL |
35164 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
35165 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
35166 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
35167 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
35168 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
35169 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
35170 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
35171 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
35172 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
35173 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
35174 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
35175 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
35176 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
35177 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
35178 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
35179 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
35180 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
35181 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
35182 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
35183 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
35184 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
35185 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
35186 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
35187 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
35188 | //RCC_EP_DEV1_EP_PCIE_RX_CNTL |
35189 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
35190 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
35191 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
35192 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
35193 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
35194 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
35195 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
35196 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
35197 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
35198 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
35199 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
35200 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
35201 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
35202 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
35203 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
35204 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
35205 | //RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL |
35206 | #define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
35207 | #define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
35208 | #define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
35209 | #define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
35210 | |
35211 | |
35212 | // addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC |
35213 | //RCC_DWN_DEV1_DN_PCIE_RESERVED |
35214 | #define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
35215 | #define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
35216 | //RCC_DWN_DEV1_DN_PCIE_SCRATCH |
35217 | #define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
35218 | #define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
35219 | //RCC_DWN_DEV1_DN_PCIE_CNTL |
35220 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
35221 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
35222 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
35223 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
35224 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
35225 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
35226 | //RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL |
35227 | #define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
35228 | #define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
35229 | //RCC_DWN_DEV1_DN_PCIE_RX_CNTL2 |
35230 | #define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
35231 | #define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
35232 | //RCC_DWN_DEV1_DN_PCIE_BUS_CNTL |
35233 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
35234 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
35235 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
35236 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
35237 | //RCC_DWN_DEV1_DN_PCIE_CFG_CNTL |
35238 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
35239 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
35240 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
35241 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
35242 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
35243 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
35244 | |
35245 | |
35246 | // addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC |
35247 | //RCC_DWNP_DEV1_PCIE_ERR_CNTL |
35248 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
35249 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
35250 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
35251 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
35252 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
35253 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
35254 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
35255 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
35256 | //RCC_DWNP_DEV1_PCIE_RX_CNTL |
35257 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
35258 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
35259 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
35260 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
35261 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
35262 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
35263 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
35264 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
35265 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
35266 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
35267 | //RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL |
35268 | #define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
35269 | #define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
35270 | #define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
35271 | #define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
35272 | //RCC_DWNP_DEV1_PCIE_LC_CNTL2 |
35273 | #define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
35274 | #define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
35275 | //RCC_DWNP_DEV1_PCIEP_STRAP_MISC |
35276 | #define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
35277 | #define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
35278 | //RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP |
35279 | #define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
35280 | #define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
35281 | |
35282 | |
35283 | // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal |
35284 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 |
35285 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
35286 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
35287 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
35288 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
35289 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
35290 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
35291 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
35292 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
35293 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
35294 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
35295 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
35296 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
35297 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
35298 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
35299 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
35300 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
35301 | |
35302 | |
35303 | // addressBlock: nbio_nbif0_bif_bx_pf_SUMDEC |
35304 | //SUM_INDEX |
35305 | #define SUM_INDEX__SUM_INDEX__SHIFT 0x0 |
35306 | #define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL |
35307 | //SUM_DATA |
35308 | #define SUM_DATA__SUM_DATA__SHIFT 0x0 |
35309 | #define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL |
35310 | |
35311 | |
35312 | // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk |
35313 | //MISC_SCRATCH |
35314 | #define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 |
35315 | #define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL |
35316 | //INTR_LINE_POLARITY |
35317 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 |
35318 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT 0x8 |
35319 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL |
35320 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK 0x0000FF00L |
35321 | //INTR_LINE_ENABLE |
35322 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 |
35323 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT 0x8 |
35324 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL |
35325 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK 0x0000FF00L |
35326 | //OUTSTANDING_VC_ALLOC |
35327 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 |
35328 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 |
35329 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 |
35330 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 |
35331 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 |
35332 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa |
35333 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc |
35334 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe |
35335 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 |
35336 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 |
35337 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a |
35338 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c |
35339 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L |
35340 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL |
35341 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L |
35342 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L |
35343 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L |
35344 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L |
35345 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L |
35346 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L |
35347 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L |
35348 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L |
35349 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L |
35350 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L |
35351 | //BIFC_MISC_CTRL0 |
35352 | #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 |
35353 | #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 |
35354 | #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 |
35355 | #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 |
35356 | #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa |
35357 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 |
35358 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 |
35359 | #define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 |
35360 | #define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 |
35361 | #define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 |
35362 | #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 |
35363 | #define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 |
35364 | #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a |
35365 | #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b |
35366 | #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c |
35367 | #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f |
35368 | #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L |
35369 | #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L |
35370 | #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L |
35371 | #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L |
35372 | #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L |
35373 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L |
35374 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L |
35375 | #define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L |
35376 | #define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L |
35377 | #define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L |
35378 | #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L |
35379 | #define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L |
35380 | #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L |
35381 | #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L |
35382 | #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L |
35383 | #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L |
35384 | //BIFC_MISC_CTRL1 |
35385 | #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 |
35386 | #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 |
35387 | #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 |
35388 | #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 |
35389 | #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 |
35390 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 |
35391 | #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 |
35392 | #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7 |
35393 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 |
35394 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa |
35395 | #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc |
35396 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd |
35397 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe |
35398 | #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf |
35399 | #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 |
35400 | #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 |
35401 | #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 |
35402 | #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 |
35403 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 |
35404 | #define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 |
35405 | #define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 |
35406 | #define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a |
35407 | #define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b |
35408 | #define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c |
35409 | #define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d |
35410 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x1f |
35411 | #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L |
35412 | #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L |
35413 | #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L |
35414 | #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L |
35415 | #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L |
35416 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L |
35417 | #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L |
35418 | #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0x00000080L |
35419 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L |
35420 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L |
35421 | #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L |
35422 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L |
35423 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L |
35424 | #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L |
35425 | #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L |
35426 | #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L |
35427 | #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L |
35428 | #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L |
35429 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L |
35430 | #define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L |
35431 | #define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L |
35432 | #define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L |
35433 | #define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L |
35434 | #define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L |
35435 | #define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L |
35436 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x80000000L |
35437 | //BIFC_BME_ERR_LOG |
35438 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 |
35439 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 |
35440 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 |
35441 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 |
35442 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 |
35443 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 |
35444 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 |
35445 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 |
35446 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x8 |
35447 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x9 |
35448 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2__SHIFT 0xa |
35449 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3__SHIFT 0xb |
35450 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4__SHIFT 0xc |
35451 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5__SHIFT 0xd |
35452 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6__SHIFT 0xe |
35453 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7__SHIFT 0xf |
35454 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 |
35455 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 |
35456 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 |
35457 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 |
35458 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 |
35459 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 |
35460 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 |
35461 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 |
35462 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x18 |
35463 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x19 |
35464 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2__SHIFT 0x1a |
35465 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3__SHIFT 0x1b |
35466 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4__SHIFT 0x1c |
35467 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5__SHIFT 0x1d |
35468 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6__SHIFT 0x1e |
35469 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7__SHIFT 0x1f |
35470 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L |
35471 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L |
35472 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L |
35473 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L |
35474 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L |
35475 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L |
35476 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L |
35477 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L |
35478 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0_MASK 0x00000100L |
35479 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1_MASK 0x00000200L |
35480 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2_MASK 0x00000400L |
35481 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3_MASK 0x00000800L |
35482 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4_MASK 0x00001000L |
35483 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5_MASK 0x00002000L |
35484 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6_MASK 0x00004000L |
35485 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7_MASK 0x00008000L |
35486 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L |
35487 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L |
35488 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L |
35489 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L |
35490 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L |
35491 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L |
35492 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L |
35493 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L |
35494 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0_MASK 0x01000000L |
35495 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1_MASK 0x02000000L |
35496 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2_MASK 0x04000000L |
35497 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3_MASK 0x08000000L |
35498 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4_MASK 0x10000000L |
35499 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5_MASK 0x20000000L |
35500 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6_MASK 0x40000000L |
35501 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7_MASK 0x80000000L |
35502 | //BIFC_RCCBIH_BME_ERR_LOG |
35503 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 |
35504 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 |
35505 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 |
35506 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 |
35507 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 |
35508 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 |
35509 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 |
35510 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 |
35511 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x8 |
35512 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x9 |
35513 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT 0xa |
35514 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT 0xb |
35515 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT 0xc |
35516 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT 0xd |
35517 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT 0xe |
35518 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT 0xf |
35519 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 |
35520 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 |
35521 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 |
35522 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 |
35523 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 |
35524 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 |
35525 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 |
35526 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 |
35527 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x18 |
35528 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x19 |
35529 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT 0x1a |
35530 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT 0x1b |
35531 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT 0x1c |
35532 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT 0x1d |
35533 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT 0x1e |
35534 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT 0x1f |
35535 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L |
35536 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L |
35537 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L |
35538 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L |
35539 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L |
35540 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L |
35541 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L |
35542 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L |
35543 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x00000100L |
35544 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x00000200L |
35545 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2_MASK 0x00000400L |
35546 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3_MASK 0x00000800L |
35547 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4_MASK 0x00001000L |
35548 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5_MASK 0x00002000L |
35549 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6_MASK 0x00004000L |
35550 | #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7_MASK 0x00008000L |
35551 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L |
35552 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L |
35553 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L |
35554 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L |
35555 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L |
35556 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L |
35557 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L |
35558 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L |
35559 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x01000000L |
35560 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x02000000L |
35561 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2_MASK 0x04000000L |
35562 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3_MASK 0x08000000L |
35563 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4_MASK 0x10000000L |
35564 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5_MASK 0x20000000L |
35565 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6_MASK 0x40000000L |
35566 | #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7_MASK 0x80000000L |
35567 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 |
35568 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 |
35569 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 |
35570 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 |
35571 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 |
35572 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa |
35573 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc |
35574 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 |
35575 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 |
35576 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 |
35577 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 |
35578 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a |
35579 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c |
35580 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L |
35581 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL |
35582 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L |
35583 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L |
35584 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L |
35585 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L |
35586 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L |
35587 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L |
35588 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L |
35589 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L |
35590 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L |
35591 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L |
35592 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 |
35593 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 |
35594 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 |
35595 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 |
35596 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 |
35597 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa |
35598 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc |
35599 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 |
35600 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 |
35601 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 |
35602 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 |
35603 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a |
35604 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c |
35605 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L |
35606 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL |
35607 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L |
35608 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L |
35609 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L |
35610 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L |
35611 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L |
35612 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L |
35613 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L |
35614 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L |
35615 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L |
35616 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L |
35617 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 |
35618 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 |
35619 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 |
35620 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 |
35621 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 |
35622 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa |
35623 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc |
35624 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 |
35625 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 |
35626 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 |
35627 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 |
35628 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a |
35629 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c |
35630 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L |
35631 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL |
35632 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L |
35633 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L |
35634 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L |
35635 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L |
35636 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L |
35637 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L |
35638 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L |
35639 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L |
35640 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L |
35641 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L |
35642 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 |
35643 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 |
35644 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 |
35645 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 |
35646 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 |
35647 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa |
35648 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc |
35649 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 |
35650 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 |
35651 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 |
35652 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 |
35653 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a |
35654 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c |
35655 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L |
35656 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL |
35657 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L |
35658 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L |
35659 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L |
35660 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L |
35661 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L |
35662 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L |
35663 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L |
35664 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L |
35665 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L |
35666 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L |
35667 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1 |
35668 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT 0x0 |
35669 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT 0x2 |
35670 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT 0x6 |
35671 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT 0x8 |
35672 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT 0xa |
35673 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT 0xc |
35674 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT 0x10 |
35675 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT 0x12 |
35676 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT 0x16 |
35677 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT 0x18 |
35678 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT 0x1a |
35679 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT 0x1c |
35680 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK 0x00000003L |
35681 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK 0x0000000CL |
35682 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK 0x000000C0L |
35683 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK 0x00000300L |
35684 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK 0x00000C00L |
35685 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK 0x00003000L |
35686 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK 0x00030000L |
35687 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK 0x000C0000L |
35688 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK 0x00C00000L |
35689 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK 0x03000000L |
35690 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK 0x0C000000L |
35691 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK 0x30000000L |
35692 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3 |
35693 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT 0x0 |
35694 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT 0x2 |
35695 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT 0x6 |
35696 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT 0x8 |
35697 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT 0xa |
35698 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT 0xc |
35699 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT 0x10 |
35700 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT 0x12 |
35701 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT 0x16 |
35702 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT 0x18 |
35703 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT 0x1a |
35704 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT 0x1c |
35705 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK 0x00000003L |
35706 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK 0x0000000CL |
35707 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK 0x000000C0L |
35708 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK 0x00000300L |
35709 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK 0x00000C00L |
35710 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK 0x00003000L |
35711 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK 0x00030000L |
35712 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK 0x000C0000L |
35713 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK 0x00C00000L |
35714 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK 0x03000000L |
35715 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK 0x0C000000L |
35716 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK 0x30000000L |
35717 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5 |
35718 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT 0x0 |
35719 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT 0x2 |
35720 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT 0x6 |
35721 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT 0x8 |
35722 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT 0xa |
35723 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT 0xc |
35724 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT 0x10 |
35725 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT 0x12 |
35726 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT 0x16 |
35727 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT 0x18 |
35728 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT 0x1a |
35729 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT 0x1c |
35730 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK 0x00000003L |
35731 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK 0x0000000CL |
35732 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK 0x000000C0L |
35733 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK 0x00000300L |
35734 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK 0x00000C00L |
35735 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK 0x00003000L |
35736 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK 0x00030000L |
35737 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK 0x000C0000L |
35738 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK 0x00C00000L |
35739 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK 0x03000000L |
35740 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK 0x0C000000L |
35741 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK 0x30000000L |
35742 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7 |
35743 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT 0x0 |
35744 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT 0x2 |
35745 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT 0x6 |
35746 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT 0x8 |
35747 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT 0xa |
35748 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT 0xc |
35749 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT 0x10 |
35750 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT 0x12 |
35751 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT 0x16 |
35752 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT 0x18 |
35753 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT 0x1a |
35754 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT 0x1c |
35755 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK 0x00000003L |
35756 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK 0x0000000CL |
35757 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK 0x000000C0L |
35758 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK 0x00000300L |
35759 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK 0x00000C00L |
35760 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK 0x00003000L |
35761 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK 0x00030000L |
35762 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK 0x000C0000L |
35763 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK 0x00C00000L |
35764 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK 0x03000000L |
35765 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK 0x0C000000L |
35766 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK 0x30000000L |
35767 | //NBIF_VWIRE_CTRL |
35768 | #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 |
35769 | #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 |
35770 | #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 |
35771 | #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a |
35772 | #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L |
35773 | #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L |
35774 | #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L |
35775 | #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L |
35776 | //NBIF_SMN_VWR_VCHG_DIS_CTRL |
35777 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 |
35778 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 |
35779 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 |
35780 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 |
35781 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 |
35782 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 |
35783 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 |
35784 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7 |
35785 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8 |
35786 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9 |
35787 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS__SHIFT 0xa |
35788 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS__SHIFT 0xb |
35789 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS__SHIFT 0xc |
35790 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS__SHIFT 0xd |
35791 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS__SHIFT 0xe |
35792 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS__SHIFT 0xf |
35793 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS__SHIFT 0x10 |
35794 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS__SHIFT 0x11 |
35795 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L |
35796 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L |
35797 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L |
35798 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L |
35799 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L |
35800 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L |
35801 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L |
35802 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L |
35803 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L |
35804 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L |
35805 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS_MASK 0x00000400L |
35806 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS_MASK 0x00000800L |
35807 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS_MASK 0x00001000L |
35808 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS_MASK 0x00002000L |
35809 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS_MASK 0x00004000L |
35810 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS_MASK 0x00008000L |
35811 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS_MASK 0x00010000L |
35812 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS_MASK 0x00020000L |
35813 | //NBIF_SMN_VWR_VCHG_RST_CTRL0 |
35814 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 |
35815 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 |
35816 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 |
35817 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 |
35818 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 |
35819 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 |
35820 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 |
35821 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7 |
35822 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8 |
35823 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9 |
35824 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV__SHIFT 0xa |
35825 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV__SHIFT 0xb |
35826 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV__SHIFT 0xc |
35827 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV__SHIFT 0xd |
35828 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV__SHIFT 0xe |
35829 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV__SHIFT 0xf |
35830 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV__SHIFT 0x10 |
35831 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV__SHIFT 0x11 |
35832 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L |
35833 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L |
35834 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L |
35835 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L |
35836 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L |
35837 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L |
35838 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L |
35839 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L |
35840 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L |
35841 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L |
35842 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV_MASK 0x00000400L |
35843 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV_MASK 0x00000800L |
35844 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV_MASK 0x00001000L |
35845 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV_MASK 0x00002000L |
35846 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV_MASK 0x00004000L |
35847 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV_MASK 0x00008000L |
35848 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV_MASK 0x00010000L |
35849 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV_MASK 0x00020000L |
35850 | //NBIF_SMN_VWR_VCHG_TRIG |
35851 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 |
35852 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 |
35853 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 |
35854 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 |
35855 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 |
35856 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 |
35857 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 |
35858 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7 |
35859 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8 |
35860 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9 |
35861 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG__SHIFT 0xa |
35862 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG__SHIFT 0xb |
35863 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG__SHIFT 0xc |
35864 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG__SHIFT 0xd |
35865 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG__SHIFT 0xe |
35866 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG__SHIFT 0xf |
35867 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG__SHIFT 0x10 |
35868 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG__SHIFT 0x11 |
35869 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L |
35870 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L |
35871 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L |
35872 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L |
35873 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L |
35874 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L |
35875 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L |
35876 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L |
35877 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L |
35878 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L |
35879 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG_MASK 0x00000400L |
35880 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG_MASK 0x00000800L |
35881 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG_MASK 0x00001000L |
35882 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG_MASK 0x00002000L |
35883 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG_MASK 0x00004000L |
35884 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG_MASK 0x00008000L |
35885 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG_MASK 0x00010000L |
35886 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG_MASK 0x00020000L |
35887 | //NBIF_SMN_VWR_WTRIG_CNTL |
35888 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 |
35889 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 |
35890 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 |
35891 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 |
35892 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 |
35893 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 |
35894 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 |
35895 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7 |
35896 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8 |
35897 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9 |
35898 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS__SHIFT 0xa |
35899 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS__SHIFT 0xb |
35900 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS__SHIFT 0xc |
35901 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS__SHIFT 0xd |
35902 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS__SHIFT 0xe |
35903 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS__SHIFT 0xf |
35904 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS__SHIFT 0x10 |
35905 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS__SHIFT 0x11 |
35906 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L |
35907 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L |
35908 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L |
35909 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L |
35910 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L |
35911 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L |
35912 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L |
35913 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L |
35914 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L |
35915 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L |
35916 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS_MASK 0x00000400L |
35917 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS_MASK 0x00000800L |
35918 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS_MASK 0x00001000L |
35919 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS_MASK 0x00002000L |
35920 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS_MASK 0x00004000L |
35921 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS_MASK 0x00008000L |
35922 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS_MASK 0x00010000L |
35923 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS_MASK 0x00020000L |
35924 | //NBIF_SMN_VWR_VCHG_DIS_CTRL_1 |
35925 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 |
35926 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 |
35927 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 |
35928 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 |
35929 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 |
35930 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 |
35931 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 |
35932 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7 |
35933 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8 |
35934 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9 |
35935 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV__SHIFT 0xa |
35936 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV__SHIFT 0xb |
35937 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV__SHIFT 0xc |
35938 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV__SHIFT 0xd |
35939 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV__SHIFT 0xe |
35940 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV__SHIFT 0xf |
35941 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV__SHIFT 0x10 |
35942 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV__SHIFT 0x11 |
35943 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L |
35944 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L |
35945 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L |
35946 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L |
35947 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L |
35948 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L |
35949 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L |
35950 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L |
35951 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L |
35952 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L |
35953 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV_MASK 0x00000400L |
35954 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV_MASK 0x00000800L |
35955 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV_MASK 0x00001000L |
35956 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV_MASK 0x00002000L |
35957 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV_MASK 0x00004000L |
35958 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV_MASK 0x00008000L |
35959 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV_MASK 0x00010000L |
35960 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV_MASK 0x00020000L |
35961 | //NBIF_MGCG_CTRL_LCLK |
35962 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 |
35963 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 |
35964 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 |
35965 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa |
35966 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb |
35967 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK__SHIFT 0xc |
35968 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd |
35969 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L |
35970 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L |
35971 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL |
35972 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L |
35973 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L |
35974 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK_MASK 0x00001000L |
35975 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L |
35976 | //NBIF_DS_CTRL_LCLK |
35977 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 |
35978 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 |
35979 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L |
35980 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L |
35981 | //SMN_MST_CNTL0 |
35982 | #define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 |
35983 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 |
35984 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 |
35985 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa |
35986 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb |
35987 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 |
35988 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT 0x11 |
35989 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 |
35990 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT 0x15 |
35991 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 |
35992 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT 0x19 |
35993 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c |
35994 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT 0x1d |
35995 | #define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L |
35996 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L |
35997 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L |
35998 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L |
35999 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L |
36000 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L |
36001 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK 0x00020000L |
36002 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L |
36003 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK 0x00200000L |
36004 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L |
36005 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK 0x02000000L |
36006 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L |
36007 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK 0x20000000L |
36008 | //SMN_MST_EP_CNTL1 |
36009 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 |
36010 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 |
36011 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 |
36012 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 |
36013 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 |
36014 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 |
36015 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 |
36016 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 |
36017 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT 0x8 |
36018 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT 0x9 |
36019 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT 0xa |
36020 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT 0xb |
36021 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT 0xc |
36022 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT 0xd |
36023 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT 0xe |
36024 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT 0xf |
36025 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L |
36026 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L |
36027 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L |
36028 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L |
36029 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L |
36030 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L |
36031 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L |
36032 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L |
36033 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK 0x00000100L |
36034 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK 0x00000200L |
36035 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK 0x00000400L |
36036 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK 0x00000800L |
36037 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK 0x00001000L |
36038 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK 0x00002000L |
36039 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK 0x00004000L |
36040 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK 0x00008000L |
36041 | //SMN_MST_EP_CNTL2 |
36042 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 |
36043 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 |
36044 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 |
36045 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 |
36046 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 |
36047 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 |
36048 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 |
36049 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 |
36050 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT 0x8 |
36051 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT 0x9 |
36052 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT 0xa |
36053 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT 0xb |
36054 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT 0xc |
36055 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT 0xd |
36056 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT 0xe |
36057 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT 0xf |
36058 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L |
36059 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L |
36060 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L |
36061 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L |
36062 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L |
36063 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L |
36064 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L |
36065 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L |
36066 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK 0x00000100L |
36067 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK 0x00000200L |
36068 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK 0x00000400L |
36069 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK 0x00000800L |
36070 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK 0x00001000L |
36071 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK 0x00002000L |
36072 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK 0x00004000L |
36073 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK 0x00008000L |
36074 | //NBIF_SDP_VWR_VCHG_DIS_CTRL |
36075 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 |
36076 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 |
36077 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 |
36078 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 |
36079 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 |
36080 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 |
36081 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 |
36082 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 |
36083 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 |
36084 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L |
36085 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L |
36086 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L |
36087 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L |
36088 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L |
36089 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L |
36090 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L |
36091 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L |
36092 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L |
36093 | //NBIF_SDP_VWR_VCHG_RST_CTRL0 |
36094 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 |
36095 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 |
36096 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 |
36097 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 |
36098 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 |
36099 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 |
36100 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 |
36101 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 |
36102 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 |
36103 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L |
36104 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L |
36105 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L |
36106 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L |
36107 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L |
36108 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L |
36109 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L |
36110 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L |
36111 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L |
36112 | //NBIF_SDP_VWR_VCHG_RST_CTRL1 |
36113 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 |
36114 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 |
36115 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 |
36116 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 |
36117 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 |
36118 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 |
36119 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 |
36120 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 |
36121 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 |
36122 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L |
36123 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L |
36124 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L |
36125 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L |
36126 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L |
36127 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L |
36128 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L |
36129 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L |
36130 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L |
36131 | //NBIF_SDP_VWR_VCHG_TRIG |
36132 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 |
36133 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 |
36134 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 |
36135 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 |
36136 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 |
36137 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 |
36138 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 |
36139 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 |
36140 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 |
36141 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L |
36142 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L |
36143 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L |
36144 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L |
36145 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L |
36146 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L |
36147 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L |
36148 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L |
36149 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L |
36150 | //BME_DUMMY_CNTL_0 |
36151 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 |
36152 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 |
36153 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 |
36154 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 |
36155 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 |
36156 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa |
36157 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc |
36158 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe |
36159 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT 0x10 |
36160 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT 0x12 |
36161 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT 0x14 |
36162 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT 0x16 |
36163 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT 0x18 |
36164 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT 0x1a |
36165 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT 0x1c |
36166 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT 0x1e |
36167 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L |
36168 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL |
36169 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L |
36170 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L |
36171 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L |
36172 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L |
36173 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L |
36174 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L |
36175 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK 0x00030000L |
36176 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK 0x000C0000L |
36177 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK 0x00300000L |
36178 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK 0x00C00000L |
36179 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK 0x03000000L |
36180 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK 0x0C000000L |
36181 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK 0x30000000L |
36182 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK 0xC0000000L |
36183 | //BIFC_THT_CNTL |
36184 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 |
36185 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 |
36186 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 |
36187 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL |
36188 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L |
36189 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L |
36190 | //BIFC_HSTARB_CNTL |
36191 | #define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 |
36192 | #define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L |
36193 | //BIFC_GSI_CNTL |
36194 | #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 |
36195 | #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 |
36196 | #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 |
36197 | #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 |
36198 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 |
36199 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 |
36200 | #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 |
36201 | #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa |
36202 | #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc |
36203 | #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L |
36204 | #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL |
36205 | #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L |
36206 | #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L |
36207 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L |
36208 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L |
36209 | #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L |
36210 | #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L |
36211 | #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L |
36212 | //BIFC_PCIEFUNC_CNTL |
36213 | #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 |
36214 | #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 |
36215 | #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL |
36216 | #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L |
36217 | //BIFC_SDP_CNTL_0 |
36218 | #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
36219 | #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 |
36220 | #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 |
36221 | #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 |
36222 | #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL |
36223 | #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L |
36224 | #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L |
36225 | #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L |
36226 | //BIFC_SDP_CNTL_1 |
36227 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 |
36228 | #define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 |
36229 | #define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 |
36230 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 |
36231 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 |
36232 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 |
36233 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L |
36234 | #define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L |
36235 | #define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L |
36236 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L |
36237 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L |
36238 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L |
36239 | //BIFC_PERF_CNTL_0 |
36240 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 |
36241 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 |
36242 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 |
36243 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 |
36244 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 |
36245 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 |
36246 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L |
36247 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L |
36248 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L |
36249 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L |
36250 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x001F0000L |
36251 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x1F000000L |
36252 | //BIFC_PERF_CNTL_1 |
36253 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 |
36254 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 |
36255 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 |
36256 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 |
36257 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 |
36258 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 |
36259 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L |
36260 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L |
36261 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L |
36262 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L |
36263 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003F0000L |
36264 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7F000000L |
36265 | //BIFC_PERF_CNT_MMIO_RD |
36266 | #define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 |
36267 | #define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL |
36268 | //BIFC_PERF_CNT_MMIO_WR |
36269 | #define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 |
36270 | #define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL |
36271 | //BIFC_PERF_CNT_DMA_RD |
36272 | #define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 |
36273 | #define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL |
36274 | //BIFC_PERF_CNT_DMA_WR |
36275 | #define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 |
36276 | #define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL |
36277 | //NBIF_REGIF_ERRSET_CTRL |
36278 | #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
36279 | #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
36280 | //NBIF_PGMST_CTRL |
36281 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 |
36282 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 |
36283 | #define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
36284 | #define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe |
36285 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL |
36286 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L |
36287 | #define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
36288 | #define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L |
36289 | //NBIF_PGSLV_CTRL |
36290 | #define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
36291 | #define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
36292 | //NBIF_PG_MISC_CTRL |
36293 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 |
36294 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 |
36295 | #define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa |
36296 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb |
36297 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc |
36298 | #define NBIF_PG_MISC_CTRL__NBIF_PG_SHUB_CLK_PERM__SHIFT 0xd |
36299 | #define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe |
36300 | #define NBIF_PG_MISC_CTRL__NBIF_PG_RESET_SELECT_COLD_RESET__SHIFT 0x10 |
36301 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 |
36302 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f |
36303 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL |
36304 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L |
36305 | #define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L |
36306 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L |
36307 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L |
36308 | #define NBIF_PG_MISC_CTRL__NBIF_PG_SHUB_CLK_PERM_MASK 0x00002000L |
36309 | #define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L |
36310 | #define NBIF_PG_MISC_CTRL__NBIF_PG_RESET_SELECT_COLD_RESET_MASK 0x00010000L |
36311 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L |
36312 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L |
36313 | //SMN_MST_EP_CNTL3 |
36314 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 |
36315 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 |
36316 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 |
36317 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 |
36318 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 |
36319 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 |
36320 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 |
36321 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 |
36322 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT 0x8 |
36323 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT 0x9 |
36324 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT 0xa |
36325 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT 0xb |
36326 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT 0xc |
36327 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT 0xd |
36328 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT 0xe |
36329 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT 0xf |
36330 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L |
36331 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L |
36332 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L |
36333 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L |
36334 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L |
36335 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L |
36336 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L |
36337 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L |
36338 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK 0x00000100L |
36339 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK 0x00000200L |
36340 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK 0x00000400L |
36341 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK 0x00000800L |
36342 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK 0x00001000L |
36343 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK 0x00002000L |
36344 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK 0x00004000L |
36345 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK 0x00008000L |
36346 | //SMN_MST_EP_CNTL4 |
36347 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 |
36348 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 |
36349 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 |
36350 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 |
36351 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 |
36352 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 |
36353 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 |
36354 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 |
36355 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT 0x8 |
36356 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT 0x9 |
36357 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT 0xa |
36358 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT 0xb |
36359 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT 0xc |
36360 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT 0xd |
36361 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT 0xe |
36362 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT 0xf |
36363 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L |
36364 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L |
36365 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L |
36366 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L |
36367 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L |
36368 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L |
36369 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L |
36370 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L |
36371 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK 0x00000100L |
36372 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK 0x00000200L |
36373 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK 0x00000400L |
36374 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK 0x00000800L |
36375 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK 0x00001000L |
36376 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK 0x00002000L |
36377 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK 0x00004000L |
36378 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK 0x00008000L |
36379 | //SMN_MST_CNTL1 |
36380 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 |
36381 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 |
36382 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT 0x11 |
36383 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L |
36384 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L |
36385 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK 0x00020000L |
36386 | //SMN_MST_EP_CNTL5 |
36387 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 |
36388 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 |
36389 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 |
36390 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 |
36391 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 |
36392 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 |
36393 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 |
36394 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 |
36395 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT 0x8 |
36396 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT 0x9 |
36397 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT 0xa |
36398 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT 0xb |
36399 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT 0xc |
36400 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT 0xd |
36401 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT 0xe |
36402 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT 0xf |
36403 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L |
36404 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L |
36405 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L |
36406 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L |
36407 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L |
36408 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L |
36409 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L |
36410 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L |
36411 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK 0x00000100L |
36412 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK 0x00000200L |
36413 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK 0x00000400L |
36414 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK 0x00000800L |
36415 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK 0x00001000L |
36416 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK 0x00002000L |
36417 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK 0x00004000L |
36418 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK 0x00008000L |
36419 | //BIF_SELFRING_BUFFER_VID |
36420 | #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 |
36421 | #define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8 |
36422 | #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL |
36423 | #define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID_MASK 0x0000FF00L |
36424 | //BIF_SELFRING_VECTOR_CNTL |
36425 | #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 |
36426 | #define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 |
36427 | #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L |
36428 | #define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L |
36429 | //BIF_GMI_WRR_WEIGHT |
36430 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0 |
36431 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8 |
36432 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10 |
36433 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT 0x1f |
36434 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK 0x000000FFL |
36435 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK 0x0000FF00L |
36436 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK 0x00FF0000L |
36437 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK 0x80000000L |
36438 | //BIF_GMI_CPLBUF_WR_CTRL |
36439 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV__SHIFT 0x0 |
36440 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV__SHIFT 0x4 |
36441 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV__SHIFT 0x8 |
36442 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV__SHIFT 0xc |
36443 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV_MASK 0x0000000FL |
36444 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV_MASK 0x000000F0L |
36445 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV_MASK 0x00000F00L |
36446 | #define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV_MASK 0x0000F000L |
36447 | //BIF_GMI_CPLBUF_RD_CTRL |
36448 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV__SHIFT 0x0 |
36449 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV__SHIFT 0x4 |
36450 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV__SHIFT 0x8 |
36451 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV__SHIFT 0xc |
36452 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV_MASK 0x0000000FL |
36453 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV_MASK 0x000000F0L |
36454 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV_MASK 0x00000F00L |
36455 | #define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV_MASK 0x0000F000L |
36456 | |
36457 | |
36458 | // addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC |
36459 | //RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL |
36460 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36461 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36462 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36463 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36464 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36465 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36466 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36467 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36468 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36469 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36470 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36471 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36472 | //RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE |
36473 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36474 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36475 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36476 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36477 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 |
36478 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36479 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36480 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36481 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36482 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36483 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36484 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36485 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36486 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36487 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36488 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36489 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36490 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36491 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36492 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36493 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36494 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 |
36495 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36496 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36497 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 |
36498 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36499 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36500 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 |
36501 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36502 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36503 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 |
36504 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36505 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36506 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 |
36507 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36508 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36509 | //RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL |
36510 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36511 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36512 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36513 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36514 | |
36515 | |
36516 | // addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC |
36517 | //RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL |
36518 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36519 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36520 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36521 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36522 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36523 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36524 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36525 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36526 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36527 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36528 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36529 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36530 | //RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE |
36531 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36532 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36533 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36534 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36535 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 |
36536 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36537 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36538 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36539 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36540 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36541 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36542 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36543 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36544 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36545 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36546 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36547 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36548 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36549 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36550 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36551 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36552 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 |
36553 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36554 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36555 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 |
36556 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36557 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36558 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 |
36559 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36560 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36561 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 |
36562 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36563 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36564 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 |
36565 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36566 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36567 | //RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL |
36568 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36569 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36570 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36571 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36572 | |
36573 | |
36574 | // addressBlock: nbio_nbif0_rcc_pfc_psp_RCCPFCDEC |
36575 | //RCC_PFC_PSP_RCC_PFC_LTR_CNTL |
36576 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36577 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36578 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36579 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36580 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36581 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36582 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36583 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36584 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36585 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36586 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36587 | #define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36588 | //RCC_PFC_PSP_RCC_PFC_PME_RESTORE |
36589 | #define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36590 | #define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36591 | #define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36592 | #define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36593 | //RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0 |
36594 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36595 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36596 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36597 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36598 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36599 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36600 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36601 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36602 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36603 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36604 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36605 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36606 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36607 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36608 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36609 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36610 | //RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1 |
36611 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36612 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36613 | //RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2 |
36614 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36615 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36616 | //RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3 |
36617 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36618 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36619 | //RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4 |
36620 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36621 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36622 | //RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5 |
36623 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36624 | #define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36625 | //RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL |
36626 | #define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36627 | #define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36628 | #define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36629 | #define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36630 | |
36631 | |
36632 | // addressBlock: nbio_nbif0_rcc_pfc_usb3_0_RCCPFCDEC |
36633 | //RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL |
36634 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36635 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36636 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36637 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36638 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36639 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36640 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36641 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36642 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36643 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36644 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36645 | #define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36646 | //RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE |
36647 | #define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36648 | #define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36649 | #define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36650 | #define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36651 | //RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0 |
36652 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36653 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36654 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36655 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36656 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36657 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36658 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36659 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36660 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36661 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36662 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36663 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36664 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36665 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36666 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36667 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36668 | //RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1 |
36669 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36670 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36671 | //RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2 |
36672 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36673 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36674 | //RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3 |
36675 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36676 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36677 | //RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4 |
36678 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36679 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36680 | //RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5 |
36681 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36682 | #define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36683 | //RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL |
36684 | #define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36685 | #define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36686 | #define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36687 | #define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36688 | |
36689 | |
36690 | // addressBlock: nbio_nbif0_rcc_pfc_usb3_1_RCCPFCDEC |
36691 | //RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL |
36692 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36693 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36694 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36695 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36696 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36697 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36698 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36699 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36700 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36701 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36702 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36703 | #define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36704 | //RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE |
36705 | #define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36706 | #define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36707 | #define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36708 | #define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36709 | //RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0 |
36710 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36711 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36712 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36713 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36714 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36715 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36716 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36717 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36718 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36719 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36720 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36721 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36722 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36723 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36724 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36725 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36726 | //RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1 |
36727 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36728 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36729 | //RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2 |
36730 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36731 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36732 | //RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3 |
36733 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36734 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36735 | //RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4 |
36736 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36737 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36738 | //RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5 |
36739 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36740 | #define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36741 | //RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL |
36742 | #define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36743 | #define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36744 | #define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36745 | #define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36746 | |
36747 | |
36748 | // addressBlock: nbio_nbif0_rcc_pfc_acp_RCCPFCDEC |
36749 | //RCC_PFC_ACP_RCC_PFC_LTR_CNTL |
36750 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36751 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36752 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36753 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36754 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36755 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36756 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36757 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36758 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36759 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36760 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36761 | #define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36762 | //RCC_PFC_ACP_RCC_PFC_PME_RESTORE |
36763 | #define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36764 | #define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36765 | #define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36766 | #define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36767 | //RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0 |
36768 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36769 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36770 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36771 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36772 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36773 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36774 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36775 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36776 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36777 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36778 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36779 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36780 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36781 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36782 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36783 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36784 | //RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1 |
36785 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36786 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36787 | //RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2 |
36788 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36789 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36790 | //RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3 |
36791 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36792 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36793 | //RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4 |
36794 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36795 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36796 | //RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5 |
36797 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36798 | #define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36799 | //RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL |
36800 | #define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36801 | #define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36802 | #define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36803 | #define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36804 | |
36805 | |
36806 | // addressBlock: nbio_nbif0_rcc_pfc_az_RCCPFCDEC |
36807 | //RCC_PFC_AZ_RCC_PFC_LTR_CNTL |
36808 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36809 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36810 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36811 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36812 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36813 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36814 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36815 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36816 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36817 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36818 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36819 | #define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36820 | //RCC_PFC_AZ_RCC_PFC_PME_RESTORE |
36821 | #define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36822 | #define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36823 | #define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36824 | #define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36825 | //RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0 |
36826 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36827 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36828 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36829 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36830 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36831 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36832 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36833 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36834 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36835 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36836 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36837 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36838 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36839 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36840 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36841 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36842 | //RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1 |
36843 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36844 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36845 | //RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2 |
36846 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36847 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36848 | //RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3 |
36849 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36850 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36851 | //RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4 |
36852 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36853 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36854 | //RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5 |
36855 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36856 | #define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36857 | //RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL |
36858 | #define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36859 | #define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36860 | #define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36861 | #define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36862 | |
36863 | |
36864 | // addressBlock: nbio_nbif0_rcc_pfc_mp2_RCCPFCDEC |
36865 | //RCC_PFC_MP2_RCC_PFC_LTR_CNTL |
36866 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36867 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36868 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36869 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36870 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36871 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36872 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36873 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36874 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36875 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36876 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36877 | #define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36878 | //RCC_PFC_MP2_RCC_PFC_PME_RESTORE |
36879 | #define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36880 | #define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36881 | #define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36882 | #define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36883 | //RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0 |
36884 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36885 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36886 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36887 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36888 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36889 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36890 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36891 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36892 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36893 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36894 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36895 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36896 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36897 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36898 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36899 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36900 | //RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1 |
36901 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36902 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36903 | //RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2 |
36904 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36905 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36906 | //RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3 |
36907 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36908 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36909 | //RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4 |
36910 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36911 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36912 | //RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5 |
36913 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36914 | #define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36915 | //RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL |
36916 | #define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36917 | #define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36918 | #define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36919 | #define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36920 | |
36921 | |
36922 | // addressBlock: nbio_nbif0_rcc_pfc_sata_RCCPFCDEC |
36923 | //RCC_PFC_SATA_RCC_PFC_LTR_CNTL |
36924 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36925 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36926 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36927 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36928 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36929 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36930 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36931 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36932 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36933 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36934 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36935 | #define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36936 | //RCC_PFC_SATA_RCC_PFC_PME_RESTORE |
36937 | #define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36938 | #define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36939 | #define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36940 | #define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36941 | //RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0 |
36942 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
36943 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
36944 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
36945 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
36946 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
36947 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
36948 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
36949 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
36950 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
36951 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
36952 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
36953 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
36954 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
36955 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
36956 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
36957 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
36958 | //RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1 |
36959 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
36960 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
36961 | //RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2 |
36962 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
36963 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
36964 | //RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3 |
36965 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
36966 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
36967 | //RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4 |
36968 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
36969 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
36970 | //RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5 |
36971 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
36972 | #define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
36973 | //RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL |
36974 | #define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
36975 | #define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
36976 | #define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
36977 | #define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
36978 | |
36979 | |
36980 | // addressBlock: nbio_nbif0_rcc_pfc_gbe0_RCCPFCDEC |
36981 | //RCC_PFC_GBE0_RCC_PFC_LTR_CNTL |
36982 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
36983 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
36984 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
36985 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
36986 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
36987 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
36988 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
36989 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
36990 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
36991 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
36992 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
36993 | #define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
36994 | //RCC_PFC_GBE0_RCC_PFC_PME_RESTORE |
36995 | #define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
36996 | #define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
36997 | #define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
36998 | #define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
36999 | //RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0 |
37000 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
37001 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
37002 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
37003 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
37004 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
37005 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
37006 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
37007 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
37008 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
37009 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
37010 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
37011 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
37012 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
37013 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
37014 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
37015 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
37016 | //RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1 |
37017 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
37018 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
37019 | //RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2 |
37020 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
37021 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
37022 | //RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3 |
37023 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
37024 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
37025 | //RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4 |
37026 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
37027 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
37028 | //RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5 |
37029 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
37030 | #define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
37031 | //RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL |
37032 | #define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
37033 | #define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
37034 | #define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
37035 | #define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
37036 | |
37037 | |
37038 | // addressBlock: nbio_nbif0_rcc_pfc_gbe1_RCCPFCDEC |
37039 | //RCC_PFC_GBE1_RCC_PFC_LTR_CNTL |
37040 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
37041 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
37042 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
37043 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
37044 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
37045 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
37046 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
37047 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
37048 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
37049 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
37050 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
37051 | #define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
37052 | //RCC_PFC_GBE1_RCC_PFC_PME_RESTORE |
37053 | #define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
37054 | #define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
37055 | #define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
37056 | #define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
37057 | //RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0 |
37058 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
37059 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
37060 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
37061 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
37062 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
37063 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
37064 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
37065 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
37066 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
37067 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
37068 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
37069 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
37070 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
37071 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
37072 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
37073 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
37074 | //RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1 |
37075 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
37076 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
37077 | //RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2 |
37078 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
37079 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
37080 | //RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3 |
37081 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
37082 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
37083 | //RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4 |
37084 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
37085 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
37086 | //RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5 |
37087 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
37088 | #define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
37089 | //RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL |
37090 | #define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
37091 | #define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
37092 | #define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
37093 | #define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
37094 | |
37095 | |
37096 | // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk |
37097 | //HARD_RST_CTRL |
37098 | #define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 |
37099 | #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 |
37100 | #define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 |
37101 | #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 |
37102 | #define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 |
37103 | #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 |
37104 | #define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 |
37105 | #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 |
37106 | #define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c |
37107 | #define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d |
37108 | #define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e |
37109 | #define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f |
37110 | #define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L |
37111 | #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L |
37112 | #define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L |
37113 | #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L |
37114 | #define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L |
37115 | #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L |
37116 | #define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L |
37117 | #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L |
37118 | #define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L |
37119 | #define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L |
37120 | #define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L |
37121 | #define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L |
37122 | //RSMU_SOFT_RST_CTRL |
37123 | #define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 |
37124 | #define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 |
37125 | #define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 |
37126 | #define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 |
37127 | #define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 |
37128 | #define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 |
37129 | #define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 |
37130 | #define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 |
37131 | #define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c |
37132 | #define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d |
37133 | #define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e |
37134 | #define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f |
37135 | #define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L |
37136 | #define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L |
37137 | #define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L |
37138 | #define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L |
37139 | #define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L |
37140 | #define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L |
37141 | #define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L |
37142 | #define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L |
37143 | #define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L |
37144 | #define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L |
37145 | #define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L |
37146 | #define RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK 0x80000000L |
37147 | //SELF_SOFT_RST |
37148 | #define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 |
37149 | #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 |
37150 | #define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 |
37151 | #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 |
37152 | #define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 |
37153 | #define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 |
37154 | #define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 |
37155 | #define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 |
37156 | #define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT 0x8 |
37157 | #define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT 0x9 |
37158 | #define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT 0xa |
37159 | #define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT 0xb |
37160 | #define SELF_SOFT_RST__EP1_CFG_RST__SHIFT 0xc |
37161 | #define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT 0xd |
37162 | #define SELF_SOFT_RST__EP1_PRV_RST__SHIFT 0xe |
37163 | #define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT 0xf |
37164 | #define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 |
37165 | #define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 |
37166 | #define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a |
37167 | #define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b |
37168 | #define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c |
37169 | #define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d |
37170 | #define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e |
37171 | #define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f |
37172 | #define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L |
37173 | #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L |
37174 | #define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L |
37175 | #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L |
37176 | #define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L |
37177 | #define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L |
37178 | #define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L |
37179 | #define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L |
37180 | #define SELF_SOFT_RST__DSPT1_CFG_RST_MASK 0x00000100L |
37181 | #define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK 0x00000200L |
37182 | #define SELF_SOFT_RST__DSPT1_PRV_RST_MASK 0x00000400L |
37183 | #define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK 0x00000800L |
37184 | #define SELF_SOFT_RST__EP1_CFG_RST_MASK 0x00001000L |
37185 | #define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK 0x00002000L |
37186 | #define SELF_SOFT_RST__EP1_PRV_RST_MASK 0x00004000L |
37187 | #define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK 0x00008000L |
37188 | #define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L |
37189 | #define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L |
37190 | #define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L |
37191 | #define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L |
37192 | #define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L |
37193 | #define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L |
37194 | #define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L |
37195 | #define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L |
37196 | //BIF_GFX_DRV_VPU_RST |
37197 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 |
37198 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 |
37199 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 |
37200 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 |
37201 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 |
37202 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 |
37203 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 |
37204 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 |
37205 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L |
37206 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L |
37207 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L |
37208 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L |
37209 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L |
37210 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L |
37211 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L |
37212 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L |
37213 | //BIF_RST_MISC_CTRL |
37214 | #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 |
37215 | #define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 |
37216 | #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 |
37217 | #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 |
37218 | #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 |
37219 | #define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 |
37220 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 |
37221 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa |
37222 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd |
37223 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf |
37224 | #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 |
37225 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 |
37226 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 |
37227 | #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L |
37228 | #define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL |
37229 | #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L |
37230 | #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L |
37231 | #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L |
37232 | #define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L |
37233 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L |
37234 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L |
37235 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L |
37236 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L |
37237 | #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L |
37238 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L |
37239 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L |
37240 | //BIF_RST_MISC_CTRL2 |
37241 | #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 |
37242 | #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 |
37243 | #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 |
37244 | #define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT 0x13 |
37245 | #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f |
37246 | #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L |
37247 | #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L |
37248 | #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L |
37249 | #define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK 0x00080000L |
37250 | #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L |
37251 | //BIF_RST_MISC_CTRL3 |
37252 | #define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 |
37253 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 |
37254 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 |
37255 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 |
37256 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa |
37257 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd |
37258 | #define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT 0x10 |
37259 | #define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL |
37260 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L |
37261 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L |
37262 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L |
37263 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L |
37264 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L |
37265 | #define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L |
37266 | //DEV0_PF0_FLR_RST_CTRL |
37267 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37268 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37269 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37270 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37271 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37272 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 |
37273 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 |
37274 | #define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 |
37275 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 |
37276 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 |
37277 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa |
37278 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb |
37279 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc |
37280 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd |
37281 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe |
37282 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf |
37283 | #define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 |
37284 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37285 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37286 | #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37287 | #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37288 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f |
37289 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37290 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37291 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37292 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37293 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37294 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L |
37295 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L |
37296 | #define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L |
37297 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L |
37298 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L |
37299 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L |
37300 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L |
37301 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L |
37302 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L |
37303 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L |
37304 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L |
37305 | #define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L |
37306 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37307 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37308 | #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37309 | #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37310 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L |
37311 | //DEV0_PF1_FLR_RST_CTRL |
37312 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37313 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37314 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37315 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37316 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37317 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37318 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37319 | #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37320 | #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37321 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37322 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37323 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37324 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37325 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37326 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37327 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37328 | #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37329 | #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37330 | //DEV0_PF2_FLR_RST_CTRL |
37331 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37332 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37333 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37334 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37335 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37336 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37337 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37338 | #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37339 | #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37340 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37341 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37342 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37343 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37344 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37345 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37346 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37347 | #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37348 | #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37349 | //DEV0_PF3_FLR_RST_CTRL |
37350 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37351 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37352 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37353 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37354 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37355 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37356 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37357 | #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37358 | #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37359 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37360 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37361 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37362 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37363 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37364 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37365 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37366 | #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37367 | #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37368 | //DEV0_PF4_FLR_RST_CTRL |
37369 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37370 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37371 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37372 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37373 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37374 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37375 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37376 | #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37377 | #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37378 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37379 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37380 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37381 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37382 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37383 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37384 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37385 | #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37386 | #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37387 | //DEV0_PF5_FLR_RST_CTRL |
37388 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37389 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37390 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37391 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37392 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37393 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37394 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37395 | #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37396 | #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37397 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37398 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37399 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37400 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37401 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37402 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37403 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37404 | #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37405 | #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37406 | //DEV0_PF6_FLR_RST_CTRL |
37407 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37408 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37409 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37410 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37411 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37412 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37413 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37414 | #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37415 | #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37416 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37417 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37418 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37419 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37420 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37421 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37422 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37423 | #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37424 | #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37425 | //DEV0_PF7_FLR_RST_CTRL |
37426 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37427 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37428 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37429 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37430 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37431 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37432 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37433 | #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37434 | #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37435 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37436 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37437 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37438 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37439 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37440 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37441 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37442 | #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37443 | #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37444 | //BIF_INST_RESET_INTR_STS |
37445 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 |
37446 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 |
37447 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 |
37448 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 |
37449 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 |
37450 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT 0x8 |
37451 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x9 |
37452 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L |
37453 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L |
37454 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L |
37455 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L |
37456 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L |
37457 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK 0x00000100L |
37458 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000200L |
37459 | //BIF_PF_FLR_INTR_STS |
37460 | #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 |
37461 | #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 |
37462 | #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 |
37463 | #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 |
37464 | #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 |
37465 | #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 |
37466 | #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 |
37467 | #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 |
37468 | #define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT 0x8 |
37469 | #define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT 0x9 |
37470 | #define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS__SHIFT 0xa |
37471 | #define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS__SHIFT 0xb |
37472 | #define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS__SHIFT 0xc |
37473 | #define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS__SHIFT 0xd |
37474 | #define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS__SHIFT 0xe |
37475 | #define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS__SHIFT 0xf |
37476 | #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L |
37477 | #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L |
37478 | #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L |
37479 | #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L |
37480 | #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L |
37481 | #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L |
37482 | #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L |
37483 | #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L |
37484 | #define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK 0x00000100L |
37485 | #define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK 0x00000200L |
37486 | #define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS_MASK 0x00000400L |
37487 | #define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS_MASK 0x00000800L |
37488 | #define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS_MASK 0x00001000L |
37489 | #define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS_MASK 0x00002000L |
37490 | #define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS_MASK 0x00004000L |
37491 | #define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS_MASK 0x00008000L |
37492 | //BIF_D3HOTD0_INTR_STS |
37493 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 |
37494 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 |
37495 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 |
37496 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 |
37497 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 |
37498 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 |
37499 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 |
37500 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 |
37501 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT 0x8 |
37502 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT 0x9 |
37503 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS__SHIFT 0xa |
37504 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS__SHIFT 0xb |
37505 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS__SHIFT 0xc |
37506 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS__SHIFT 0xd |
37507 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS__SHIFT 0xe |
37508 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS__SHIFT 0xf |
37509 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L |
37510 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L |
37511 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L |
37512 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L |
37513 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L |
37514 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L |
37515 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L |
37516 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L |
37517 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK 0x00000100L |
37518 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK 0x00000200L |
37519 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS_MASK 0x00000400L |
37520 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS_MASK 0x00000800L |
37521 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS_MASK 0x00001000L |
37522 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS_MASK 0x00002000L |
37523 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS_MASK 0x00004000L |
37524 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS_MASK 0x00008000L |
37525 | //BIF_POWER_INTR_STS |
37526 | #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 |
37527 | #define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT 0x1 |
37528 | #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 |
37529 | #define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT 0x11 |
37530 | #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L |
37531 | #define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK 0x00000002L |
37532 | #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L |
37533 | #define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK 0x00020000L |
37534 | //BIF_PF_DSTATE_INTR_STS |
37535 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 |
37536 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 |
37537 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 |
37538 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 |
37539 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 |
37540 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 |
37541 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 |
37542 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 |
37543 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT 0x8 |
37544 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT 0x9 |
37545 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT 0xa |
37546 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT 0xb |
37547 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT 0xc |
37548 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT 0xd |
37549 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT 0xe |
37550 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT 0xf |
37551 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L |
37552 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L |
37553 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L |
37554 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L |
37555 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L |
37556 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L |
37557 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L |
37558 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L |
37559 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK 0x00000100L |
37560 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK 0x00000200L |
37561 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK 0x00000400L |
37562 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK 0x00000800L |
37563 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK 0x00001000L |
37564 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK 0x00002000L |
37565 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK 0x00004000L |
37566 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK 0x00008000L |
37567 | //BIF_INST_RESET_INTR_MASK |
37568 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 |
37569 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 |
37570 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 |
37571 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 |
37572 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 |
37573 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT 0x8 |
37574 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x9 |
37575 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L |
37576 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L |
37577 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L |
37578 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L |
37579 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L |
37580 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK 0x00000100L |
37581 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000200L |
37582 | //BIF_PF_FLR_INTR_MASK |
37583 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 |
37584 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 |
37585 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 |
37586 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 |
37587 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 |
37588 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 |
37589 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 |
37590 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 |
37591 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT 0x8 |
37592 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT 0x9 |
37593 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK__SHIFT 0xa |
37594 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK__SHIFT 0xb |
37595 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK__SHIFT 0xc |
37596 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK__SHIFT 0xd |
37597 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK__SHIFT 0xe |
37598 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK__SHIFT 0xf |
37599 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L |
37600 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L |
37601 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L |
37602 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L |
37603 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L |
37604 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L |
37605 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L |
37606 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L |
37607 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK 0x00000100L |
37608 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK 0x00000200L |
37609 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK_MASK 0x00000400L |
37610 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK_MASK 0x00000800L |
37611 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK_MASK 0x00001000L |
37612 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK_MASK 0x00002000L |
37613 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK_MASK 0x00004000L |
37614 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK_MASK 0x00008000L |
37615 | //BIF_D3HOTD0_INTR_MASK |
37616 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 |
37617 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 |
37618 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 |
37619 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 |
37620 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 |
37621 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 |
37622 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 |
37623 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 |
37624 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT 0x8 |
37625 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT 0x9 |
37626 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK__SHIFT 0xa |
37627 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK__SHIFT 0xb |
37628 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK__SHIFT 0xc |
37629 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK__SHIFT 0xd |
37630 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK__SHIFT 0xe |
37631 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK__SHIFT 0xf |
37632 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L |
37633 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L |
37634 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L |
37635 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L |
37636 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L |
37637 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L |
37638 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L |
37639 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L |
37640 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK 0x00000100L |
37641 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK 0x00000200L |
37642 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK_MASK 0x00000400L |
37643 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK_MASK 0x00000800L |
37644 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK_MASK 0x00001000L |
37645 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK_MASK 0x00002000L |
37646 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK_MASK 0x00004000L |
37647 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK_MASK 0x00008000L |
37648 | //BIF_POWER_INTR_MASK |
37649 | #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 |
37650 | #define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT 0x1 |
37651 | #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 |
37652 | #define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT 0x11 |
37653 | #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L |
37654 | #define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK 0x00000002L |
37655 | #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L |
37656 | #define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK 0x00020000L |
37657 | //BIF_PF_DSTATE_INTR_MASK |
37658 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 |
37659 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 |
37660 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 |
37661 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 |
37662 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 |
37663 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 |
37664 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 |
37665 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 |
37666 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT 0x8 |
37667 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT 0x9 |
37668 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT 0xa |
37669 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT 0xb |
37670 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT 0xc |
37671 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT 0xd |
37672 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT 0xe |
37673 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT 0xf |
37674 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L |
37675 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L |
37676 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L |
37677 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L |
37678 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L |
37679 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L |
37680 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L |
37681 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L |
37682 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK 0x00000100L |
37683 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK 0x00000200L |
37684 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK 0x00000400L |
37685 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK 0x00000800L |
37686 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK 0x00001000L |
37687 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK 0x00002000L |
37688 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK 0x00004000L |
37689 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK 0x00008000L |
37690 | //BIF_PF_FLR_RST |
37691 | #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 |
37692 | #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 |
37693 | #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 |
37694 | #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 |
37695 | #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 |
37696 | #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 |
37697 | #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 |
37698 | #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 |
37699 | #define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8 |
37700 | #define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9 |
37701 | #define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa |
37702 | #define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb |
37703 | #define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc |
37704 | #define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd |
37705 | #define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe |
37706 | #define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf |
37707 | #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L |
37708 | #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L |
37709 | #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L |
37710 | #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L |
37711 | #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L |
37712 | #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L |
37713 | #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L |
37714 | #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L |
37715 | #define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L |
37716 | #define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L |
37717 | #define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L |
37718 | #define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L |
37719 | #define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L |
37720 | #define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L |
37721 | #define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L |
37722 | #define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L |
37723 | //BIF_DEV0_PF0_DSTATE_VALUE |
37724 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 |
37725 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37726 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 |
37727 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L |
37728 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37729 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L |
37730 | //BIF_DEV0_PF1_DSTATE_VALUE |
37731 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 |
37732 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37733 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 |
37734 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L |
37735 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37736 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L |
37737 | //BIF_DEV0_PF2_DSTATE_VALUE |
37738 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 |
37739 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37740 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 |
37741 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L |
37742 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37743 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L |
37744 | //BIF_DEV0_PF3_DSTATE_VALUE |
37745 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 |
37746 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37747 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 |
37748 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L |
37749 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37750 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L |
37751 | //BIF_DEV0_PF4_DSTATE_VALUE |
37752 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 |
37753 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37754 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 |
37755 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L |
37756 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37757 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L |
37758 | //BIF_DEV0_PF5_DSTATE_VALUE |
37759 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 |
37760 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37761 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 |
37762 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L |
37763 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37764 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L |
37765 | //BIF_DEV0_PF6_DSTATE_VALUE |
37766 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 |
37767 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37768 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 |
37769 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L |
37770 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37771 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L |
37772 | //BIF_DEV0_PF7_DSTATE_VALUE |
37773 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 |
37774 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
37775 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 |
37776 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L |
37777 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
37778 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L |
37779 | //DEV0_PF0_D3HOTD0_RST_CTRL |
37780 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37781 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37782 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37783 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37784 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37785 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37786 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37787 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37788 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37789 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37790 | //DEV0_PF1_D3HOTD0_RST_CTRL |
37791 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37792 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37793 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37794 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37795 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37796 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37797 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37798 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37799 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37800 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37801 | //DEV0_PF2_D3HOTD0_RST_CTRL |
37802 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37803 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37804 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37805 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37806 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37807 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37808 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37809 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37810 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37811 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37812 | //DEV0_PF3_D3HOTD0_RST_CTRL |
37813 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37814 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37815 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37816 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37817 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37818 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37819 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37820 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37821 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37822 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37823 | //DEV0_PF4_D3HOTD0_RST_CTRL |
37824 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37825 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37826 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37827 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37828 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37829 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37830 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37831 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37832 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37833 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37834 | //DEV0_PF5_D3HOTD0_RST_CTRL |
37835 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37836 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37837 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37838 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37839 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37840 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37841 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37842 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37843 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37844 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37845 | //DEV0_PF6_D3HOTD0_RST_CTRL |
37846 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37847 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37848 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37849 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37850 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37851 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37852 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37853 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37854 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37855 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37856 | //DEV0_PF7_D3HOTD0_RST_CTRL |
37857 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37858 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37859 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37860 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37861 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37862 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37863 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37864 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37865 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37866 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37867 | //DEV1_PF0_FLR_RST_CTRL |
37868 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37869 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37870 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37871 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37872 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37873 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37874 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37875 | #define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37876 | #define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37877 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37878 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37879 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37880 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37881 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37882 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37883 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37884 | #define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37885 | #define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37886 | //DEV1_PF1_FLR_RST_CTRL |
37887 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37888 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37889 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37890 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37891 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37892 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37893 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37894 | #define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37895 | #define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37896 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37897 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37898 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37899 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37900 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37901 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37902 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37903 | #define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37904 | #define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37905 | //DEV1_PF2_FLR_RST_CTRL |
37906 | #define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37907 | #define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37908 | #define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37909 | #define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37910 | #define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37911 | #define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37912 | #define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37913 | #define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37914 | #define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37915 | #define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37916 | #define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37917 | #define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37918 | #define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37919 | #define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37920 | #define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37921 | #define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37922 | #define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37923 | #define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37924 | //DEV1_PF3_FLR_RST_CTRL |
37925 | #define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37926 | #define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37927 | #define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37928 | #define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37929 | #define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37930 | #define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37931 | #define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37932 | #define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37933 | #define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37934 | #define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37935 | #define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37936 | #define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37937 | #define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37938 | #define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37939 | #define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37940 | #define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37941 | #define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37942 | #define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37943 | //DEV1_PF4_FLR_RST_CTRL |
37944 | #define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37945 | #define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37946 | #define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37947 | #define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37948 | #define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37949 | #define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37950 | #define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37951 | #define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37952 | #define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37953 | #define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37954 | #define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37955 | #define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37956 | #define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37957 | #define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37958 | #define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37959 | #define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37960 | #define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37961 | #define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37962 | //DEV1_PF5_FLR_RST_CTRL |
37963 | #define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37964 | #define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37965 | #define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37966 | #define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37967 | #define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37968 | #define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37969 | #define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37970 | #define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37971 | #define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37972 | #define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37973 | #define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37974 | #define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37975 | #define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37976 | #define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37977 | #define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37978 | #define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37979 | #define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37980 | #define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
37981 | //DEV1_PF6_FLR_RST_CTRL |
37982 | #define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
37983 | #define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
37984 | #define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
37985 | #define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
37986 | #define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
37987 | #define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
37988 | #define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
37989 | #define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
37990 | #define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
37991 | #define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
37992 | #define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
37993 | #define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
37994 | #define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
37995 | #define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
37996 | #define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
37997 | #define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
37998 | #define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
37999 | #define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
38000 | //DEV1_PF7_FLR_RST_CTRL |
38001 | #define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38002 | #define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38003 | #define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38004 | #define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38005 | #define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38006 | #define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
38007 | #define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
38008 | #define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
38009 | #define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
38010 | #define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38011 | #define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38012 | #define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38013 | #define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38014 | #define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38015 | #define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
38016 | #define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
38017 | #define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
38018 | #define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
38019 | //BIF_DEV1_PF0_DSTATE_VALUE |
38020 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 |
38021 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38022 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 |
38023 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L |
38024 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38025 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L |
38026 | //BIF_DEV1_PF1_DSTATE_VALUE |
38027 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 |
38028 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38029 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 |
38030 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L |
38031 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38032 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L |
38033 | //BIF_DEV1_PF2_DSTATE_VALUE |
38034 | #define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 |
38035 | #define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38036 | #define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 |
38037 | #define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L |
38038 | #define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38039 | #define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L |
38040 | //BIF_DEV1_PF3_DSTATE_VALUE |
38041 | #define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 |
38042 | #define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38043 | #define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 |
38044 | #define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L |
38045 | #define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38046 | #define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L |
38047 | //BIF_DEV1_PF4_DSTATE_VALUE |
38048 | #define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 |
38049 | #define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38050 | #define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 |
38051 | #define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L |
38052 | #define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38053 | #define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L |
38054 | //BIF_DEV1_PF5_DSTATE_VALUE |
38055 | #define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 |
38056 | #define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38057 | #define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 |
38058 | #define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L |
38059 | #define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38060 | #define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L |
38061 | //BIF_DEV1_PF6_DSTATE_VALUE |
38062 | #define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 |
38063 | #define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38064 | #define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 |
38065 | #define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L |
38066 | #define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38067 | #define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L |
38068 | //BIF_DEV1_PF7_DSTATE_VALUE |
38069 | #define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 |
38070 | #define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
38071 | #define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 |
38072 | #define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L |
38073 | #define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
38074 | #define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L |
38075 | //DEV1_PF0_D3HOTD0_RST_CTRL |
38076 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38077 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38078 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38079 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38080 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38081 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38082 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38083 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38084 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38085 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38086 | //DEV1_PF1_D3HOTD0_RST_CTRL |
38087 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38088 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38089 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38090 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38091 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38092 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38093 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38094 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38095 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38096 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38097 | //DEV1_PF2_D3HOTD0_RST_CTRL |
38098 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38099 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38100 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38101 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38102 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38103 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38104 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38105 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38106 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38107 | #define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38108 | //DEV1_PF3_D3HOTD0_RST_CTRL |
38109 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38110 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38111 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38112 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38113 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38114 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38115 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38116 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38117 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38118 | #define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38119 | //DEV1_PF4_D3HOTD0_RST_CTRL |
38120 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38121 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38122 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38123 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38124 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38125 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38126 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38127 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38128 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38129 | #define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38130 | //DEV1_PF5_D3HOTD0_RST_CTRL |
38131 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38132 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38133 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38134 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38135 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38136 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38137 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38138 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38139 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38140 | #define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38141 | //DEV1_PF6_D3HOTD0_RST_CTRL |
38142 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38143 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38144 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38145 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38146 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38147 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38148 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38149 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38150 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38151 | #define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38152 | //DEV1_PF7_D3HOTD0_RST_CTRL |
38153 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
38154 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
38155 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
38156 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
38157 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
38158 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
38159 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
38160 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
38161 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
38162 | #define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
38163 | //BIF_PORT0_DSTATE_VALUE |
38164 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 |
38165 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 |
38166 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L |
38167 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L |
38168 | //BIF_PORT1_DSTATE_VALUE |
38169 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT 0x0 |
38170 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT 0x10 |
38171 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK 0x00000003L |
38172 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK 0x00030000L |
38173 | |
38174 | |
38175 | // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk |
38176 | //BIF_RAS_LEAF0_CTRL |
38177 | #define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 |
38178 | #define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
38179 | #define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 |
38180 | #define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 |
38181 | #define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
38182 | #define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
38183 | #define BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
38184 | #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
38185 | #define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
38186 | #define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 |
38187 | #define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
38188 | #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
38189 | #define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 |
38190 | #define BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L |
38191 | #define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
38192 | #define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L |
38193 | #define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L |
38194 | #define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
38195 | #define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
38196 | #define BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
38197 | #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
38198 | #define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
38199 | #define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L |
38200 | #define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
38201 | #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
38202 | #define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L |
38203 | //BIF_RAS_LEAF1_CTRL |
38204 | #define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 |
38205 | #define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
38206 | #define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 |
38207 | #define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 |
38208 | #define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
38209 | #define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
38210 | #define BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
38211 | #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
38212 | #define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
38213 | #define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 |
38214 | #define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
38215 | #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
38216 | #define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 |
38217 | #define BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L |
38218 | #define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
38219 | #define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L |
38220 | #define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L |
38221 | #define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
38222 | #define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
38223 | #define BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
38224 | #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
38225 | #define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
38226 | #define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L |
38227 | #define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
38228 | #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
38229 | #define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L |
38230 | //BIF_RAS_LEAF2_CTRL |
38231 | #define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 |
38232 | #define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
38233 | #define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 |
38234 | #define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 |
38235 | #define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 |
38236 | #define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 |
38237 | #define BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 |
38238 | #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 |
38239 | #define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 |
38240 | #define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 |
38241 | #define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 |
38242 | #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 |
38243 | #define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 |
38244 | #define BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L |
38245 | #define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
38246 | #define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L |
38247 | #define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L |
38248 | #define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L |
38249 | #define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L |
38250 | #define BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L |
38251 | #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L |
38252 | #define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L |
38253 | #define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L |
38254 | #define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L |
38255 | #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L |
38256 | #define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L |
38257 | //BIF_RAS_MISC_CTRL |
38258 | #define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0 |
38259 | #define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK 0x00000001L |
38260 | //BIF_IOHUB_RAS_IH_CNTL |
38261 | #define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0 |
38262 | #define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN_MASK 0x00000001L |
38263 | //BIF_RAS_VWR_FROM_IOHUB |
38264 | #define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0 |
38265 | #define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG_MASK 0x00000001L |
38266 | |
38267 | |
38268 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
38269 | //BIF_CFG_DEV0_EPF0_2_VENDOR_ID |
38270 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
38271 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
38272 | //BIF_CFG_DEV0_EPF0_2_DEVICE_ID |
38273 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
38274 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
38275 | //BIF_CFG_DEV0_EPF0_2_COMMAND |
38276 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
38277 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
38278 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
38279 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
38280 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
38281 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
38282 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
38283 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
38284 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN__SHIFT 0x8 |
38285 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
38286 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS__SHIFT 0xa |
38287 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
38288 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
38289 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
38290 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
38291 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
38292 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
38293 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
38294 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING_MASK 0x0080L |
38295 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN_MASK 0x0100L |
38296 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
38297 | #define BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS_MASK 0x0400L |
38298 | //BIF_CFG_DEV0_EPF0_2_STATUS |
38299 | #define BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS__SHIFT 0x3 |
38300 | #define BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST__SHIFT 0x4 |
38301 | #define BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN__SHIFT 0x5 |
38302 | #define BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
38303 | #define BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
38304 | #define BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
38305 | #define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
38306 | #define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
38307 | #define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
38308 | #define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
38309 | #define BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
38310 | #define BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS_MASK 0x0008L |
38311 | #define BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST_MASK 0x0010L |
38312 | #define BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN_MASK 0x0020L |
38313 | #define BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
38314 | #define BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
38315 | #define BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
38316 | #define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
38317 | #define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
38318 | #define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
38319 | #define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
38320 | #define BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
38321 | //BIF_CFG_DEV0_EPF0_2_REVISION_ID |
38322 | #define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
38323 | #define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
38324 | #define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
38325 | #define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
38326 | //BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE |
38327 | #define BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
38328 | #define BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
38329 | //BIF_CFG_DEV0_EPF0_2_SUB_CLASS |
38330 | #define BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
38331 | #define BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
38332 | //BIF_CFG_DEV0_EPF0_2_BASE_CLASS |
38333 | #define BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
38334 | #define BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
38335 | //BIF_CFG_DEV0_EPF0_2_CACHE_LINE |
38336 | #define BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
38337 | #define BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
38338 | //BIF_CFG_DEV0_EPF0_2_LATENCY |
38339 | #define BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
38340 | #define BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
38341 | //BIF_CFG_DEV0_EPF0_2_HEADER |
38342 | #define BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
38343 | #define BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
38344 | #define BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE_MASK 0x7FL |
38345 | #define BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE_MASK 0x80L |
38346 | //BIF_CFG_DEV0_EPF0_2_BIST |
38347 | #define BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP__SHIFT 0x0 |
38348 | #define BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT__SHIFT 0x6 |
38349 | #define BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP__SHIFT 0x7 |
38350 | #define BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP_MASK 0x0FL |
38351 | #define BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT_MASK 0x40L |
38352 | #define BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP_MASK 0x80L |
38353 | //BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1 |
38354 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
38355 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
38356 | //BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2 |
38357 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
38358 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
38359 | //BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3 |
38360 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
38361 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
38362 | //BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4 |
38363 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
38364 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
38365 | //BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5 |
38366 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
38367 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
38368 | //BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6 |
38369 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
38370 | #define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
38371 | //BIF_CFG_DEV0_EPF0_2_ADAPTER_ID |
38372 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
38373 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
38374 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
38375 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
38376 | //BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR |
38377 | #define BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
38378 | #define BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
38379 | //BIF_CFG_DEV0_EPF0_2_CAP_PTR |
38380 | #define BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
38381 | #define BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
38382 | //BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE |
38383 | #define BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
38384 | #define BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
38385 | //BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN |
38386 | #define BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
38387 | #define BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
38388 | //BIF_CFG_DEV0_EPF0_2_MIN_GRANT |
38389 | #define BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
38390 | #define BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
38391 | //BIF_CFG_DEV0_EPF0_2_MAX_LATENCY |
38392 | #define BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
38393 | #define BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
38394 | //BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST |
38395 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
38396 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38397 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
38398 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
38399 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
38400 | #define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
38401 | //BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W |
38402 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
38403 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
38404 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
38405 | #define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
38406 | //BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST |
38407 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
38408 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38409 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
38410 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
38411 | //BIF_CFG_DEV0_EPF0_2_PMI_CAP |
38412 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION__SHIFT 0x0 |
38413 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
38414 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
38415 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
38416 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
38417 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
38418 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
38419 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION_MASK 0x0007L |
38420 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
38421 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
38422 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
38423 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
38424 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
38425 | #define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
38426 | //BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL |
38427 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
38428 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
38429 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
38430 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
38431 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
38432 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
38433 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
38434 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
38435 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
38436 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
38437 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
38438 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
38439 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
38440 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
38441 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
38442 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
38443 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
38444 | #define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
38445 | //BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST |
38446 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
38447 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38448 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
38449 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
38450 | //BIF_CFG_DEV0_EPF0_2_PCIE_CAP |
38451 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION__SHIFT 0x0 |
38452 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
38453 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
38454 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
38455 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION_MASK 0x000FL |
38456 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
38457 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
38458 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
38459 | //BIF_CFG_DEV0_EPF0_2_DEVICE_CAP |
38460 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
38461 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
38462 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
38463 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
38464 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
38465 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
38466 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
38467 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
38468 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
38469 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
38470 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
38471 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
38472 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
38473 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
38474 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
38475 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
38476 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
38477 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
38478 | //BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL |
38479 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
38480 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
38481 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
38482 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
38483 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
38484 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
38485 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
38486 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
38487 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
38488 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
38489 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
38490 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
38491 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
38492 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
38493 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
38494 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
38495 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
38496 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
38497 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
38498 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
38499 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
38500 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
38501 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
38502 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
38503 | //BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS |
38504 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
38505 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
38506 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
38507 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
38508 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
38509 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
38510 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
38511 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
38512 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
38513 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
38514 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
38515 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
38516 | //BIF_CFG_DEV0_EPF0_2_LINK_CAP |
38517 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
38518 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
38519 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
38520 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
38521 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
38522 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
38523 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
38524 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
38525 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
38526 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
38527 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
38528 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
38529 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
38530 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
38531 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
38532 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
38533 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
38534 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
38535 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
38536 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
38537 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
38538 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
38539 | //BIF_CFG_DEV0_EPF0_2_LINK_CNTL |
38540 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
38541 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
38542 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
38543 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
38544 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
38545 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
38546 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
38547 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
38548 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
38549 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
38550 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
38551 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
38552 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
38553 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
38554 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
38555 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
38556 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
38557 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
38558 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
38559 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
38560 | //BIF_CFG_DEV0_EPF0_2_LINK_STATUS |
38561 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
38562 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
38563 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
38564 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
38565 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
38566 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
38567 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
38568 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
38569 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
38570 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
38571 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
38572 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
38573 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
38574 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
38575 | //BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2 |
38576 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
38577 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
38578 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
38579 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
38580 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
38581 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
38582 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
38583 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
38584 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
38585 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
38586 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
38587 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
38588 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
38589 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
38590 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
38591 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
38592 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
38593 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
38594 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
38595 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
38596 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
38597 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
38598 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
38599 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
38600 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
38601 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
38602 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
38603 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
38604 | //BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2 |
38605 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
38606 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
38607 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
38608 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
38609 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
38610 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
38611 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
38612 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
38613 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
38614 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
38615 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
38616 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
38617 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
38618 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
38619 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
38620 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
38621 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
38622 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
38623 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
38624 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
38625 | //BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2 |
38626 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
38627 | #define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
38628 | //BIF_CFG_DEV0_EPF0_2_LINK_CAP2 |
38629 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
38630 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
38631 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
38632 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
38633 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
38634 | #define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
38635 | //BIF_CFG_DEV0_EPF0_2_LINK_CNTL2 |
38636 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
38637 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
38638 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
38639 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
38640 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
38641 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
38642 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
38643 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
38644 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
38645 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
38646 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
38647 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
38648 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
38649 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
38650 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
38651 | #define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
38652 | //BIF_CFG_DEV0_EPF0_2_LINK_STATUS2 |
38653 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
38654 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
38655 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
38656 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
38657 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
38658 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
38659 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
38660 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
38661 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
38662 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
38663 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
38664 | #define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
38665 | //BIF_CFG_DEV0_EPF0_2_SLOT_CAP2 |
38666 | #define BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
38667 | #define BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
38668 | //BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2 |
38669 | #define BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
38670 | #define BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
38671 | //BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2 |
38672 | #define BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
38673 | #define BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
38674 | //BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST |
38675 | #define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
38676 | #define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38677 | #define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
38678 | #define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
38679 | //BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL |
38680 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
38681 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
38682 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
38683 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
38684 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
38685 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
38686 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
38687 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
38688 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
38689 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
38690 | //BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO |
38691 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
38692 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
38693 | //BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI |
38694 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
38695 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
38696 | //BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA |
38697 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
38698 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
38699 | //BIF_CFG_DEV0_EPF0_2_MSI_MASK |
38700 | #define BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
38701 | #define BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
38702 | //BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64 |
38703 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
38704 | #define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
38705 | //BIF_CFG_DEV0_EPF0_2_MSI_MASK_64 |
38706 | #define BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
38707 | #define BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
38708 | //BIF_CFG_DEV0_EPF0_2_MSI_PENDING |
38709 | #define BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
38710 | #define BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
38711 | //BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64 |
38712 | #define BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
38713 | #define BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
38714 | //BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST |
38715 | #define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
38716 | #define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38717 | #define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
38718 | #define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
38719 | //BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL |
38720 | #define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
38721 | #define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
38722 | #define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
38723 | #define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
38724 | #define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
38725 | #define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
38726 | //BIF_CFG_DEV0_EPF0_2_MSIX_TABLE |
38727 | #define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
38728 | #define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
38729 | #define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
38730 | #define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
38731 | //BIF_CFG_DEV0_EPF0_2_MSIX_PBA |
38732 | #define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
38733 | #define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
38734 | #define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
38735 | #define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
38736 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
38737 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38738 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38739 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38740 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38741 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38742 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38743 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR |
38744 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
38745 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
38746 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
38747 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
38748 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
38749 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
38750 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1 |
38751 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
38752 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
38753 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2 |
38754 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
38755 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
38756 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST |
38757 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38758 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38759 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38760 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38761 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38762 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38763 | //BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1 |
38764 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
38765 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
38766 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
38767 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
38768 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
38769 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
38770 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
38771 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
38772 | //BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2 |
38773 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
38774 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
38775 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
38776 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
38777 | //BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL |
38778 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
38779 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
38780 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
38781 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
38782 | //BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS |
38783 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
38784 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
38785 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP |
38786 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
38787 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
38788 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
38789 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
38790 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
38791 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
38792 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
38793 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
38794 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL |
38795 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
38796 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
38797 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
38798 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
38799 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
38800 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
38801 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
38802 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
38803 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
38804 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
38805 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
38806 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
38807 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS |
38808 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
38809 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
38810 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
38811 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
38812 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP |
38813 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
38814 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
38815 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
38816 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
38817 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
38818 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
38819 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
38820 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
38821 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL |
38822 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
38823 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
38824 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
38825 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
38826 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
38827 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
38828 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
38829 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
38830 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
38831 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
38832 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
38833 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
38834 | //BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS |
38835 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
38836 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
38837 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
38838 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
38839 | //BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
38840 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38841 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38842 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38843 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38844 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38845 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38846 | //BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1 |
38847 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
38848 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
38849 | //BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2 |
38850 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
38851 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
38852 | //BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
38853 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38854 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38855 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38856 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38857 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38858 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38859 | //BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS |
38860 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
38861 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
38862 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
38863 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
38864 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
38865 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
38866 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
38867 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
38868 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
38869 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
38870 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
38871 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
38872 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
38873 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
38874 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
38875 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
38876 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
38877 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
38878 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
38879 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
38880 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
38881 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
38882 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
38883 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
38884 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
38885 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
38886 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
38887 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
38888 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
38889 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
38890 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
38891 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
38892 | //BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK |
38893 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
38894 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
38895 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
38896 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
38897 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
38898 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
38899 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
38900 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
38901 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
38902 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
38903 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
38904 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
38905 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
38906 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
38907 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
38908 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
38909 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
38910 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
38911 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
38912 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
38913 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
38914 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
38915 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
38916 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
38917 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
38918 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
38919 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
38920 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
38921 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
38922 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
38923 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
38924 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
38925 | //BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY |
38926 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
38927 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
38928 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
38929 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
38930 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
38931 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
38932 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
38933 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
38934 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
38935 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
38936 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
38937 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
38938 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
38939 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
38940 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
38941 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
38942 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
38943 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
38944 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
38945 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
38946 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
38947 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
38948 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
38949 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
38950 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
38951 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
38952 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
38953 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
38954 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
38955 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
38956 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
38957 | #define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
38958 | //BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS |
38959 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
38960 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
38961 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
38962 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
38963 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
38964 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
38965 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
38966 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
38967 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
38968 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
38969 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
38970 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
38971 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
38972 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
38973 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
38974 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
38975 | //BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK |
38976 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
38977 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
38978 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
38979 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
38980 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
38981 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
38982 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
38983 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
38984 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
38985 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
38986 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
38987 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
38988 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
38989 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
38990 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
38991 | #define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
38992 | //BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL |
38993 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
38994 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
38995 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
38996 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
38997 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
38998 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
38999 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
39000 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
39001 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
39002 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
39003 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
39004 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
39005 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
39006 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
39007 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
39008 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
39009 | //BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0 |
39010 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
39011 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
39012 | //BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1 |
39013 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
39014 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
39015 | //BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2 |
39016 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
39017 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
39018 | //BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3 |
39019 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
39020 | #define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
39021 | //BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0 |
39022 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
39023 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
39024 | //BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1 |
39025 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
39026 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
39027 | //BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2 |
39028 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
39029 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
39030 | //BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3 |
39031 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
39032 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
39033 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST |
39034 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39035 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39036 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39037 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39038 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39039 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39040 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP |
39041 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
39042 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
39043 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL |
39044 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
39045 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
39046 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
39047 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
39048 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
39049 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
39050 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP |
39051 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
39052 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
39053 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL |
39054 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
39055 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
39056 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
39057 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
39058 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
39059 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
39060 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP |
39061 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
39062 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
39063 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL |
39064 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
39065 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
39066 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
39067 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
39068 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
39069 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
39070 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP |
39071 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
39072 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
39073 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL |
39074 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
39075 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
39076 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
39077 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
39078 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
39079 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
39080 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP |
39081 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
39082 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
39083 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL |
39084 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
39085 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
39086 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
39087 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
39088 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
39089 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
39090 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP |
39091 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
39092 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
39093 | //BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL |
39094 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
39095 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
39096 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
39097 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
39098 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
39099 | #define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
39100 | //BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
39101 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39102 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39103 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39104 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39105 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39106 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39107 | //BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT |
39108 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
39109 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
39110 | //BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA |
39111 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
39112 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
39113 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
39114 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
39115 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
39116 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
39117 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
39118 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
39119 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
39120 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
39121 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
39122 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
39123 | //BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP |
39124 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
39125 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
39126 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST |
39127 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39128 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39129 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39130 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39131 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39132 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39133 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP |
39134 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
39135 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
39136 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
39137 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
39138 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
39139 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
39140 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
39141 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
39142 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
39143 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
39144 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR |
39145 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
39146 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
39147 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS |
39148 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
39149 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
39150 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
39151 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
39152 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL |
39153 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
39154 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
39155 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
39156 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39157 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39158 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
39159 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39160 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39161 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
39162 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39163 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39164 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
39165 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39166 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39167 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
39168 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39169 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39170 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
39171 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39172 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39173 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
39174 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39175 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39176 | //BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
39177 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
39178 | #define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
39179 | //BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST |
39180 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39181 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39182 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39183 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39184 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39185 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39186 | //BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3 |
39187 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
39188 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
39189 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
39190 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
39191 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
39192 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
39193 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS |
39194 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
39195 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
39196 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
39197 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
39198 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL |
39199 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39200 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39201 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39202 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39203 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39204 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39205 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39206 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39207 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39208 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39209 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL |
39210 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39211 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39212 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39213 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39214 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39215 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39216 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39217 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39218 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39219 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39220 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL |
39221 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39222 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39223 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39224 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39225 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39226 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39227 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39228 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39229 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39230 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39231 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL |
39232 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39233 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39234 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39235 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39236 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39237 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39238 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39239 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39240 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39241 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39242 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL |
39243 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39244 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39245 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39246 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39247 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39248 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39249 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39250 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39251 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39252 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39253 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL |
39254 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39255 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39256 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39257 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39258 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39259 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39260 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39261 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39262 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39263 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39264 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL |
39265 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39266 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39267 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39268 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39269 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39270 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39271 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39272 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39273 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39274 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39275 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL |
39276 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39277 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39278 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39279 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39280 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39281 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39282 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39283 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39284 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39285 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39286 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL |
39287 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39288 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39289 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39290 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39291 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39292 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39293 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39294 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39295 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39296 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39297 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL |
39298 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39299 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39300 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39301 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39302 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39303 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39304 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39305 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39306 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39307 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39308 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL |
39309 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39310 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39311 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39312 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39313 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39314 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39315 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39316 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39317 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39318 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39319 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL |
39320 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39321 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39322 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39323 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39324 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39325 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39326 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39327 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39328 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39329 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39330 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL |
39331 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39332 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39333 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39334 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39335 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39336 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39337 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39338 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39339 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39340 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39341 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL |
39342 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39343 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39344 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39345 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39346 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39347 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39348 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39349 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39350 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39351 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39352 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL |
39353 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39354 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39355 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39356 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39357 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39358 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39359 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39360 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39361 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39362 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39363 | //BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL |
39364 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
39365 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
39366 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
39367 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
39368 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
39369 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
39370 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
39371 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
39372 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
39373 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
39374 | //BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST |
39375 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39376 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39377 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39378 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39379 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39380 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39381 | //BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP |
39382 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
39383 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
39384 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
39385 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
39386 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
39387 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
39388 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
39389 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
39390 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
39391 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
39392 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
39393 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
39394 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
39395 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
39396 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
39397 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
39398 | //BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL |
39399 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
39400 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
39401 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
39402 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
39403 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
39404 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
39405 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
39406 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
39407 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
39408 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
39409 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
39410 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
39411 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
39412 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
39413 | //BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST |
39414 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39415 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39416 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39417 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39418 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39419 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39420 | //BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP |
39421 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
39422 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
39423 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
39424 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
39425 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
39426 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
39427 | //BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL |
39428 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
39429 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
39430 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU_MASK 0x001FL |
39431 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
39432 | //BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST |
39433 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39434 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39435 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39436 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39437 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39438 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39439 | //BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL |
39440 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
39441 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
39442 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
39443 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
39444 | //BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS |
39445 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
39446 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
39447 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
39448 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
39449 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
39450 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
39451 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
39452 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
39453 | //BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
39454 | #define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
39455 | #define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
39456 | //BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
39457 | #define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
39458 | #define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
39459 | //BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST |
39460 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39461 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39462 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39463 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39464 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39465 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39466 | //BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP |
39467 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
39468 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
39469 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
39470 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
39471 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
39472 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
39473 | //BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL |
39474 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
39475 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
39476 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
39477 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
39478 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
39479 | #define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
39480 | //BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST |
39481 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39482 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39483 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39484 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39485 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39486 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39487 | //BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP |
39488 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
39489 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
39490 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
39491 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
39492 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
39493 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
39494 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
39495 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
39496 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
39497 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
39498 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
39499 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
39500 | //BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL |
39501 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
39502 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
39503 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
39504 | #define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
39505 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST |
39506 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39507 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39508 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39509 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39510 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39511 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39512 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP |
39513 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
39514 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
39515 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
39516 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
39517 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
39518 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
39519 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL |
39520 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
39521 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
39522 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
39523 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
39524 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0 |
39525 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
39526 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
39527 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
39528 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
39529 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1 |
39530 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
39531 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
39532 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0 |
39533 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
39534 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
39535 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1 |
39536 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
39537 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
39538 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0 |
39539 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
39540 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
39541 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1 |
39542 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
39543 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
39544 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
39545 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
39546 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
39547 | //BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
39548 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
39549 | #define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
39550 | //BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST |
39551 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39552 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39553 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39554 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39555 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39556 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39557 | //BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP |
39558 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
39559 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
39560 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
39561 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
39562 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
39563 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
39564 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
39565 | #define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
39566 | //BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST |
39567 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39568 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39569 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39570 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39571 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39572 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39573 | //BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP |
39574 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
39575 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
39576 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
39577 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
39578 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
39579 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
39580 | //BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL |
39581 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
39582 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
39583 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
39584 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
39585 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
39586 | #define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
39587 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST |
39588 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39589 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39590 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39591 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39592 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39593 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39594 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP |
39595 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
39596 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
39597 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
39598 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
39599 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
39600 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
39601 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL |
39602 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
39603 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
39604 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
39605 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
39606 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
39607 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
39608 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
39609 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
39610 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
39611 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
39612 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS |
39613 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
39614 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
39615 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS |
39616 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
39617 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
39618 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS |
39619 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
39620 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
39621 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS |
39622 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
39623 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
39624 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK |
39625 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
39626 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
39627 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET |
39628 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
39629 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
39630 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE |
39631 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
39632 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
39633 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID |
39634 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
39635 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
39636 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
39637 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
39638 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
39639 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
39640 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
39641 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
39642 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0 |
39643 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
39644 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
39645 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1 |
39646 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
39647 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
39648 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2 |
39649 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
39650 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
39651 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3 |
39652 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
39653 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
39654 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4 |
39655 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
39656 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
39657 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5 |
39658 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
39659 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
39660 | //BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
39661 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
39662 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
39663 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
39664 | #define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
39665 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
39666 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
39667 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
39668 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
39669 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
39670 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
39671 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
39672 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
39673 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
39674 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
39675 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
39676 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
39677 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
39678 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
39679 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
39680 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
39681 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
39682 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
39683 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
39684 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
39685 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
39686 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
39687 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
39688 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
39689 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
39690 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
39691 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
39692 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
39693 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
39694 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
39695 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
39696 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
39697 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
39698 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
39699 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
39700 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
39701 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
39702 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
39703 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
39704 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
39705 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
39706 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
39707 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
39708 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
39709 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
39710 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
39711 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
39712 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
39713 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
39714 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
39715 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
39716 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
39717 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
39718 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
39719 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
39720 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
39721 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
39722 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
39723 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
39724 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
39725 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
39726 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
39727 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
39728 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
39729 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
39730 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
39731 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
39732 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
39733 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
39734 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
39735 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
39736 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
39737 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
39738 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
39739 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
39740 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
39741 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
39742 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
39743 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
39744 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
39745 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
39746 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
39747 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
39748 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
39749 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
39750 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
39751 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
39752 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
39753 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
39754 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
39755 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
39756 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
39757 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
39758 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
39759 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
39760 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
39761 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
39762 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
39763 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
39764 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
39765 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
39766 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
39767 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
39768 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
39769 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
39770 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
39771 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
39772 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
39773 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
39774 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
39775 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
39776 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
39777 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
39778 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
39779 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
39780 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
39781 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
39782 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
39783 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
39784 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
39785 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
39786 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
39787 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
39788 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
39789 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
39790 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
39791 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
39792 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
39793 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
39794 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
39795 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
39796 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
39797 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
39798 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
39799 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
39800 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
39801 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
39802 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
39803 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
39804 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
39805 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
39806 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
39807 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
39808 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
39809 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
39810 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
39811 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
39812 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
39813 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
39814 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
39815 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
39816 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
39817 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
39818 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
39819 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
39820 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
39821 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
39822 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
39823 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
39824 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
39825 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
39826 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
39827 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
39828 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
39829 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
39830 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
39831 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
39832 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
39833 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
39834 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
39835 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
39836 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
39837 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
39838 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
39839 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
39840 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
39841 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
39842 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
39843 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
39844 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
39845 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
39846 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
39847 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
39848 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
39849 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
39850 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
39851 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
39852 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
39853 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
39854 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
39855 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
39856 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
39857 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
39858 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
39859 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
39860 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
39861 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
39862 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
39863 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
39864 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
39865 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
39866 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
39867 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
39868 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
39869 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
39870 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
39871 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
39872 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
39873 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
39874 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
39875 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
39876 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
39877 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
39878 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
39879 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
39880 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
39881 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
39882 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
39883 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
39884 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
39885 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
39886 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
39887 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
39888 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
39889 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
39890 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
39891 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
39892 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
39893 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
39894 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
39895 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
39896 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
39897 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
39898 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
39899 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
39900 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
39901 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
39902 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
39903 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
39904 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
39905 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
39906 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
39907 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
39908 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
39909 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
39910 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
39911 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
39912 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
39913 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
39914 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
39915 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
39916 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
39917 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
39918 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
39919 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
39920 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
39921 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
39922 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
39923 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
39924 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
39925 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
39926 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
39927 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
39928 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
39929 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
39930 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
39931 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
39932 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
39933 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
39934 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
39935 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
39936 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
39937 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
39938 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
39939 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
39940 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
39941 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
39942 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
39943 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
39944 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
39945 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
39946 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
39947 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
39948 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
39949 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
39950 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
39951 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
39952 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
39953 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
39954 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
39955 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
39956 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
39957 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
39958 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
39959 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
39960 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
39961 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
39962 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
39963 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
39964 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
39965 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
39966 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
39967 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
39968 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
39969 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
39970 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
39971 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
39972 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
39973 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
39974 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
39975 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
39976 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
39977 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
39978 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
39979 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
39980 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
39981 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
39982 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
39983 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
39984 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
39985 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
39986 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
39987 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
39988 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
39989 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
39990 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
39991 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
39992 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
39993 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
39994 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
39995 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
39996 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
39997 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
39998 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
39999 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
40000 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
40001 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
40002 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
40003 | //BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
40004 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
40005 | #define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
40006 | |
40007 | |
40008 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
40009 | //BIF_CFG_DEV0_EPF1_1_VENDOR_ID |
40010 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
40011 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
40012 | //BIF_CFG_DEV0_EPF1_1_DEVICE_ID |
40013 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
40014 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
40015 | //BIF_CFG_DEV0_EPF1_1_COMMAND |
40016 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
40017 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
40018 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
40019 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
40020 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
40021 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
40022 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
40023 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
40024 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8 |
40025 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
40026 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa |
40027 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
40028 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
40029 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
40030 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
40031 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
40032 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
40033 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
40034 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L |
40035 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L |
40036 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
40037 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L |
40038 | //BIF_CFG_DEV0_EPF1_1_STATUS |
40039 | #define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3 |
40040 | #define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4 |
40041 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5 |
40042 | #define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
40043 | #define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
40044 | #define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
40045 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
40046 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
40047 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
40048 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
40049 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
40050 | #define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L |
40051 | #define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L |
40052 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L |
40053 | #define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
40054 | #define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
40055 | #define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
40056 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
40057 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
40058 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
40059 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
40060 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
40061 | //BIF_CFG_DEV0_EPF1_1_REVISION_ID |
40062 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
40063 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
40064 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
40065 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
40066 | //BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE |
40067 | #define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
40068 | #define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
40069 | //BIF_CFG_DEV0_EPF1_1_SUB_CLASS |
40070 | #define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
40071 | #define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
40072 | //BIF_CFG_DEV0_EPF1_1_BASE_CLASS |
40073 | #define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
40074 | #define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
40075 | //BIF_CFG_DEV0_EPF1_1_CACHE_LINE |
40076 | #define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
40077 | #define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
40078 | //BIF_CFG_DEV0_EPF1_1_LATENCY |
40079 | #define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
40080 | #define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
40081 | //BIF_CFG_DEV0_EPF1_1_HEADER |
40082 | #define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
40083 | #define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
40084 | #define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL |
40085 | #define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L |
40086 | //BIF_CFG_DEV0_EPF1_1_BIST |
40087 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0 |
40088 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6 |
40089 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7 |
40090 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL |
40091 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L |
40092 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L |
40093 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 |
40094 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
40095 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
40096 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 |
40097 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
40098 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
40099 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 |
40100 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
40101 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
40102 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 |
40103 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
40104 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
40105 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 |
40106 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
40107 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
40108 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 |
40109 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
40110 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
40111 | //BIF_CFG_DEV0_EPF1_1_ADAPTER_ID |
40112 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
40113 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
40114 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
40115 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
40116 | //BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR |
40117 | #define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
40118 | #define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
40119 | //BIF_CFG_DEV0_EPF1_1_CAP_PTR |
40120 | #define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
40121 | #define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
40122 | //BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE |
40123 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
40124 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
40125 | //BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN |
40126 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
40127 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
40128 | //BIF_CFG_DEV0_EPF1_1_MIN_GRANT |
40129 | #define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
40130 | #define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
40131 | //BIF_CFG_DEV0_EPF1_1_MAX_LATENCY |
40132 | #define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
40133 | #define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
40134 | //BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST |
40135 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
40136 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40137 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
40138 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
40139 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
40140 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
40141 | //BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W |
40142 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
40143 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
40144 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
40145 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
40146 | //BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST |
40147 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
40148 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40149 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
40150 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
40151 | //BIF_CFG_DEV0_EPF1_1_PMI_CAP |
40152 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0 |
40153 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
40154 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
40155 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
40156 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
40157 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
40158 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
40159 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L |
40160 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
40161 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
40162 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
40163 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
40164 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
40165 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
40166 | //BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL |
40167 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
40168 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
40169 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
40170 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
40171 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
40172 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
40173 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
40174 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
40175 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
40176 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
40177 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
40178 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
40179 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
40180 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
40181 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
40182 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
40183 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
40184 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
40185 | //BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST |
40186 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
40187 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40188 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
40189 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
40190 | //BIF_CFG_DEV0_EPF1_1_PCIE_CAP |
40191 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0 |
40192 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
40193 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
40194 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
40195 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL |
40196 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
40197 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
40198 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
40199 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CAP |
40200 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
40201 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
40202 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
40203 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
40204 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
40205 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
40206 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
40207 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
40208 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
40209 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
40210 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
40211 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
40212 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
40213 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
40214 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
40215 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
40216 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
40217 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
40218 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL |
40219 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
40220 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
40221 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
40222 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
40223 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
40224 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
40225 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
40226 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
40227 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
40228 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
40229 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
40230 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
40231 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
40232 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
40233 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
40234 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
40235 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
40236 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
40237 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
40238 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
40239 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
40240 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
40241 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
40242 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
40243 | //BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS |
40244 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
40245 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
40246 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
40247 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
40248 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
40249 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
40250 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
40251 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
40252 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
40253 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
40254 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
40255 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
40256 | //BIF_CFG_DEV0_EPF1_1_LINK_CAP |
40257 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
40258 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
40259 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
40260 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
40261 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
40262 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
40263 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
40264 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
40265 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
40266 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
40267 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
40268 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
40269 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
40270 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
40271 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
40272 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
40273 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
40274 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
40275 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
40276 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
40277 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
40278 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
40279 | //BIF_CFG_DEV0_EPF1_1_LINK_CNTL |
40280 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
40281 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
40282 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
40283 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
40284 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
40285 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
40286 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
40287 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
40288 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
40289 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
40290 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
40291 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
40292 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
40293 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
40294 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
40295 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
40296 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
40297 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
40298 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
40299 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
40300 | //BIF_CFG_DEV0_EPF1_1_LINK_STATUS |
40301 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
40302 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
40303 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
40304 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
40305 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
40306 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
40307 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
40308 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
40309 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
40310 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
40311 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
40312 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
40313 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
40314 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
40315 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 |
40316 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
40317 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
40318 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
40319 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
40320 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
40321 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
40322 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
40323 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
40324 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
40325 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
40326 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
40327 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
40328 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
40329 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
40330 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
40331 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
40332 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
40333 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
40334 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
40335 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
40336 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
40337 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
40338 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
40339 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
40340 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
40341 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
40342 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
40343 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
40344 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 |
40345 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
40346 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
40347 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
40348 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
40349 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
40350 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
40351 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
40352 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
40353 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
40354 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
40355 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
40356 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
40357 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
40358 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
40359 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
40360 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
40361 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
40362 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
40363 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
40364 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
40365 | //BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 |
40366 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
40367 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
40368 | //BIF_CFG_DEV0_EPF1_1_LINK_CAP2 |
40369 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
40370 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
40371 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
40372 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
40373 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
40374 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
40375 | //BIF_CFG_DEV0_EPF1_1_LINK_CNTL2 |
40376 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
40377 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
40378 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
40379 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
40380 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
40381 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
40382 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
40383 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
40384 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
40385 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
40386 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
40387 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
40388 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
40389 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
40390 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
40391 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
40392 | //BIF_CFG_DEV0_EPF1_1_LINK_STATUS2 |
40393 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
40394 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
40395 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
40396 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
40397 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
40398 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
40399 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
40400 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
40401 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
40402 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
40403 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
40404 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
40405 | //BIF_CFG_DEV0_EPF1_1_SLOT_CAP2 |
40406 | #define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
40407 | #define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
40408 | //BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2 |
40409 | #define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
40410 | #define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
40411 | //BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2 |
40412 | #define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
40413 | #define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
40414 | //BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST |
40415 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
40416 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40417 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
40418 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
40419 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL |
40420 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
40421 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
40422 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
40423 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
40424 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
40425 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
40426 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
40427 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
40428 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
40429 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
40430 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO |
40431 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
40432 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
40433 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI |
40434 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
40435 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
40436 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA |
40437 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
40438 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
40439 | //BIF_CFG_DEV0_EPF1_1_MSI_MASK |
40440 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
40441 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
40442 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 |
40443 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
40444 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
40445 | //BIF_CFG_DEV0_EPF1_1_MSI_MASK_64 |
40446 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
40447 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
40448 | //BIF_CFG_DEV0_EPF1_1_MSI_PENDING |
40449 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
40450 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
40451 | //BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 |
40452 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
40453 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
40454 | //BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST |
40455 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
40456 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40457 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
40458 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
40459 | //BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL |
40460 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
40461 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
40462 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
40463 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
40464 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
40465 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
40466 | //BIF_CFG_DEV0_EPF1_1_MSIX_TABLE |
40467 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
40468 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
40469 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
40470 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
40471 | //BIF_CFG_DEV0_EPF1_1_MSIX_PBA |
40472 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
40473 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
40474 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
40475 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
40476 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
40477 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40478 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40479 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40480 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40481 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40482 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40483 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR |
40484 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
40485 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
40486 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
40487 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
40488 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
40489 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
40490 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 |
40491 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
40492 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
40493 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 |
40494 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
40495 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
40496 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST |
40497 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40498 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40499 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40500 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40501 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40502 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40503 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 |
40504 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
40505 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
40506 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
40507 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
40508 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
40509 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
40510 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
40511 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
40512 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 |
40513 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
40514 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
40515 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
40516 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
40517 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL |
40518 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
40519 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
40520 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
40521 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
40522 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS |
40523 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
40524 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
40525 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP |
40526 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
40527 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
40528 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
40529 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
40530 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
40531 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
40532 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
40533 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
40534 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL |
40535 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
40536 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
40537 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
40538 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
40539 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
40540 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
40541 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
40542 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
40543 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
40544 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
40545 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
40546 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
40547 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS |
40548 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
40549 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
40550 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
40551 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
40552 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP |
40553 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
40554 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
40555 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
40556 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
40557 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
40558 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
40559 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
40560 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
40561 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL |
40562 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
40563 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
40564 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
40565 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
40566 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
40567 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
40568 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
40569 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
40570 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
40571 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
40572 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
40573 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
40574 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS |
40575 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
40576 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
40577 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
40578 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
40579 | //BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
40580 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40581 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40582 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40583 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40584 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40585 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40586 | //BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 |
40587 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
40588 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
40589 | //BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 |
40590 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
40591 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
40592 | //BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
40593 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40594 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40595 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40596 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40597 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40598 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40599 | //BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS |
40600 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
40601 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
40602 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
40603 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
40604 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
40605 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
40606 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
40607 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
40608 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
40609 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
40610 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
40611 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
40612 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
40613 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
40614 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
40615 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
40616 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
40617 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
40618 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
40619 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
40620 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
40621 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
40622 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
40623 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
40624 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
40625 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
40626 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
40627 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
40628 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
40629 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
40630 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
40631 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
40632 | //BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK |
40633 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
40634 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
40635 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
40636 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
40637 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
40638 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
40639 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
40640 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
40641 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
40642 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
40643 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
40644 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
40645 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
40646 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
40647 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
40648 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
40649 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
40650 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
40651 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
40652 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
40653 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
40654 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
40655 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
40656 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
40657 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
40658 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
40659 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
40660 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
40661 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
40662 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
40663 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
40664 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
40665 | //BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY |
40666 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
40667 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
40668 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
40669 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
40670 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
40671 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
40672 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
40673 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
40674 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
40675 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
40676 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
40677 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
40678 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
40679 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
40680 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
40681 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
40682 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
40683 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
40684 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
40685 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
40686 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
40687 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
40688 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
40689 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
40690 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
40691 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
40692 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
40693 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
40694 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
40695 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
40696 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
40697 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
40698 | //BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS |
40699 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
40700 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
40701 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
40702 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
40703 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
40704 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
40705 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
40706 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
40707 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
40708 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
40709 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
40710 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
40711 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
40712 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
40713 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
40714 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
40715 | //BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK |
40716 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
40717 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
40718 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
40719 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
40720 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
40721 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
40722 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
40723 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
40724 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
40725 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
40726 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
40727 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
40728 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
40729 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
40730 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
40731 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
40732 | //BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL |
40733 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
40734 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
40735 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
40736 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
40737 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
40738 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
40739 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
40740 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
40741 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
40742 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
40743 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
40744 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
40745 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
40746 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
40747 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
40748 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
40749 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 |
40750 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
40751 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
40752 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 |
40753 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
40754 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
40755 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 |
40756 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
40757 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
40758 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 |
40759 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
40760 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
40761 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 |
40762 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
40763 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
40764 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 |
40765 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
40766 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
40767 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 |
40768 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
40769 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
40770 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 |
40771 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
40772 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
40773 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST |
40774 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40775 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40776 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40777 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40778 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40779 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40780 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP |
40781 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40782 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
40783 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL |
40784 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
40785 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40786 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
40787 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
40788 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
40789 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
40790 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP |
40791 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40792 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
40793 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL |
40794 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
40795 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40796 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
40797 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
40798 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
40799 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
40800 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP |
40801 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40802 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
40803 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL |
40804 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
40805 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40806 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
40807 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
40808 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
40809 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
40810 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP |
40811 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40812 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
40813 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL |
40814 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
40815 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40816 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
40817 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
40818 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
40819 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
40820 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP |
40821 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40822 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
40823 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL |
40824 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
40825 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40826 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
40827 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
40828 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
40829 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
40830 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP |
40831 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40832 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
40833 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL |
40834 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
40835 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40836 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
40837 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
40838 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
40839 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
40840 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
40841 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40842 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40843 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40844 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40845 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40846 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40847 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT |
40848 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
40849 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
40850 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA |
40851 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
40852 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
40853 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
40854 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
40855 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
40856 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
40857 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
40858 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
40859 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
40860 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
40861 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
40862 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
40863 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP |
40864 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
40865 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
40866 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST |
40867 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40868 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40869 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40870 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40871 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40872 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40873 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP |
40874 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
40875 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
40876 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
40877 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
40878 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
40879 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
40880 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
40881 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
40882 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
40883 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
40884 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR |
40885 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
40886 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
40887 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS |
40888 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
40889 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
40890 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
40891 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
40892 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL |
40893 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
40894 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
40895 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
40896 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40897 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40898 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
40899 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40900 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40901 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
40902 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40903 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40904 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
40905 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40906 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40907 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
40908 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40909 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40910 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
40911 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40912 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40913 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
40914 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40915 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40916 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
40917 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40918 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40919 | //BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST |
40920 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40921 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40922 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40923 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40924 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40925 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40926 | //BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 |
40927 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
40928 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
40929 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
40930 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
40931 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
40932 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
40933 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS |
40934 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
40935 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
40936 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
40937 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
40938 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL |
40939 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
40940 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
40941 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
40942 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
40943 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
40944 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
40945 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
40946 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
40947 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
40948 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
40949 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL |
40950 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
40951 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
40952 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
40953 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
40954 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
40955 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
40956 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
40957 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
40958 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
40959 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
40960 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL |
40961 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
40962 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
40963 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
40964 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
40965 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
40966 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
40967 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
40968 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
40969 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
40970 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
40971 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL |
40972 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
40973 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
40974 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
40975 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
40976 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
40977 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
40978 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
40979 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
40980 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
40981 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
40982 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL |
40983 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
40984 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
40985 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
40986 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
40987 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
40988 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
40989 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
40990 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
40991 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
40992 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
40993 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL |
40994 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
40995 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
40996 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
40997 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
40998 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
40999 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41000 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41001 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41002 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41003 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41004 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL |
41005 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41006 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41007 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41008 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41009 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41010 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41011 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41012 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41013 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41014 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41015 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL |
41016 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41017 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41018 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41019 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41020 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41021 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41022 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41023 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41024 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41025 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41026 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL |
41027 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41028 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41029 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41030 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41031 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41032 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41033 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41034 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41035 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41036 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41037 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL |
41038 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41039 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41040 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41041 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41042 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41043 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41044 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41045 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41046 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41047 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41048 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL |
41049 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41050 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41051 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41052 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41053 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41054 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41055 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41056 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41057 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41058 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41059 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL |
41060 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41061 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41062 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41063 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41064 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41065 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41066 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41067 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41068 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41069 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41070 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL |
41071 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41072 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41073 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41074 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41075 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41076 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41077 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41078 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41079 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41080 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41081 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL |
41082 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41083 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41084 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41085 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41086 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41087 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41088 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41089 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41090 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41091 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41092 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL |
41093 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41094 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41095 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41096 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41097 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41098 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41099 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41100 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41101 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41102 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41103 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL |
41104 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
41105 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
41106 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
41107 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
41108 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
41109 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
41110 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
41111 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
41112 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
41113 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
41114 | //BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST |
41115 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41116 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41117 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41118 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41119 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41120 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41121 | //BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP |
41122 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
41123 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
41124 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
41125 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
41126 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
41127 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
41128 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
41129 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
41130 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
41131 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
41132 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
41133 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
41134 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
41135 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
41136 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
41137 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
41138 | //BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL |
41139 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
41140 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
41141 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
41142 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
41143 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
41144 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
41145 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
41146 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
41147 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
41148 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
41149 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
41150 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
41151 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
41152 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
41153 | //BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST |
41154 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41155 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41156 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41157 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41158 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41159 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41160 | //BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP |
41161 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
41162 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
41163 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
41164 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
41165 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
41166 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
41167 | //BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL |
41168 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
41169 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
41170 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
41171 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
41172 | //BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST |
41173 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41174 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41175 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41176 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41177 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41178 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41179 | //BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL |
41180 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
41181 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
41182 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
41183 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
41184 | //BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS |
41185 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
41186 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
41187 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
41188 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
41189 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
41190 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
41191 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
41192 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
41193 | //BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
41194 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
41195 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
41196 | //BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
41197 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
41198 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
41199 | //BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST |
41200 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41201 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41202 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41203 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41204 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41205 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41206 | //BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP |
41207 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
41208 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
41209 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
41210 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
41211 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
41212 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
41213 | //BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL |
41214 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
41215 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
41216 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
41217 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
41218 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
41219 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
41220 | //BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST |
41221 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41222 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41223 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41224 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41225 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41226 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41227 | //BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP |
41228 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
41229 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
41230 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
41231 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
41232 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
41233 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
41234 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
41235 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
41236 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
41237 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
41238 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
41239 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
41240 | //BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL |
41241 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
41242 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
41243 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
41244 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
41245 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST |
41246 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41247 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41248 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41249 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41250 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41251 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41252 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP |
41253 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
41254 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
41255 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
41256 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
41257 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
41258 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
41259 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL |
41260 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
41261 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
41262 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
41263 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
41264 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 |
41265 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
41266 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
41267 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
41268 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
41269 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 |
41270 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
41271 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
41272 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 |
41273 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
41274 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
41275 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 |
41276 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
41277 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
41278 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 |
41279 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
41280 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
41281 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 |
41282 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
41283 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
41284 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
41285 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
41286 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
41287 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
41288 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
41289 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
41290 | //BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST |
41291 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41292 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41293 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41294 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41295 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41296 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41297 | //BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP |
41298 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
41299 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
41300 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
41301 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
41302 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
41303 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
41304 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
41305 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
41306 | //BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST |
41307 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41308 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41309 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41310 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41311 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41312 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41313 | //BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP |
41314 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
41315 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
41316 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
41317 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
41318 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
41319 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
41320 | //BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL |
41321 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
41322 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
41323 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
41324 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
41325 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
41326 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
41327 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST |
41328 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41329 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41330 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41331 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41332 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41333 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41334 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP |
41335 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
41336 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
41337 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
41338 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
41339 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
41340 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
41341 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL |
41342 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
41343 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
41344 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
41345 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
41346 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
41347 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
41348 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
41349 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
41350 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
41351 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
41352 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS |
41353 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
41354 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
41355 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS |
41356 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
41357 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
41358 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS |
41359 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
41360 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
41361 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS |
41362 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
41363 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
41364 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK |
41365 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
41366 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
41367 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET |
41368 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
41369 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
41370 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE |
41371 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
41372 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
41373 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID |
41374 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
41375 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
41376 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
41377 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
41378 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
41379 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
41380 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
41381 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
41382 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 |
41383 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
41384 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
41385 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 |
41386 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
41387 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
41388 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 |
41389 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
41390 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
41391 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 |
41392 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
41393 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
41394 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 |
41395 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
41396 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
41397 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 |
41398 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
41399 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
41400 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
41401 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
41402 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
41403 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
41404 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
41405 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
41406 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
41407 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
41408 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
41409 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
41410 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
41411 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
41412 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
41413 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
41414 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
41415 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
41416 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
41417 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
41418 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
41419 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
41420 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
41421 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
41422 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
41423 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
41424 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
41425 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
41426 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
41427 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
41428 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
41429 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
41430 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
41431 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
41432 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
41433 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
41434 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
41435 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
41436 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
41437 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
41438 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
41439 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
41440 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
41441 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
41442 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
41443 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
41444 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
41445 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
41446 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
41447 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
41448 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
41449 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
41450 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
41451 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
41452 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
41453 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
41454 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
41455 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
41456 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
41457 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
41458 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
41459 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
41460 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
41461 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
41462 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
41463 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
41464 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
41465 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
41466 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
41467 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
41468 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
41469 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
41470 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
41471 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
41472 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
41473 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
41474 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
41475 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
41476 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
41477 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
41478 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
41479 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
41480 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
41481 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
41482 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
41483 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
41484 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
41485 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
41486 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
41487 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
41488 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
41489 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
41490 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
41491 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
41492 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
41493 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
41494 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
41495 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
41496 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
41497 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
41498 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
41499 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
41500 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
41501 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
41502 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
41503 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
41504 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
41505 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
41506 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
41507 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
41508 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
41509 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
41510 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
41511 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
41512 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
41513 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
41514 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
41515 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
41516 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
41517 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
41518 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
41519 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
41520 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
41521 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
41522 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
41523 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
41524 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
41525 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
41526 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
41527 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
41528 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
41529 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
41530 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
41531 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
41532 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
41533 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
41534 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
41535 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
41536 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
41537 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
41538 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
41539 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
41540 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
41541 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
41542 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
41543 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
41544 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
41545 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
41546 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
41547 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
41548 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
41549 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
41550 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
41551 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
41552 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
41553 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
41554 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
41555 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
41556 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
41557 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
41558 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
41559 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
41560 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
41561 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
41562 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
41563 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
41564 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
41565 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
41566 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
41567 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
41568 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
41569 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
41570 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
41571 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
41572 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
41573 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
41574 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
41575 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
41576 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
41577 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
41578 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
41579 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
41580 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
41581 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
41582 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
41583 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
41584 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
41585 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
41586 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
41587 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
41588 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
41589 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
41590 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
41591 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
41592 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
41593 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
41594 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
41595 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
41596 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
41597 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
41598 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
41599 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
41600 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
41601 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
41602 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
41603 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
41604 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
41605 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
41606 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
41607 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
41608 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
41609 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
41610 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
41611 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
41612 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
41613 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
41614 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
41615 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
41616 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
41617 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
41618 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
41619 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
41620 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
41621 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
41622 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
41623 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
41624 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
41625 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
41626 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
41627 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
41628 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
41629 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
41630 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
41631 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
41632 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
41633 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
41634 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
41635 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
41636 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
41637 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
41638 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
41639 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
41640 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
41641 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
41642 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
41643 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
41644 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
41645 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
41646 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
41647 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
41648 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
41649 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
41650 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
41651 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
41652 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
41653 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
41654 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
41655 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
41656 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
41657 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
41658 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
41659 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
41660 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
41661 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
41662 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
41663 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
41664 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
41665 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
41666 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
41667 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
41668 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
41669 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
41670 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
41671 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
41672 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
41673 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
41674 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
41675 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
41676 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
41677 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
41678 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
41679 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
41680 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
41681 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
41682 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
41683 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
41684 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
41685 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
41686 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
41687 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
41688 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
41689 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
41690 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
41691 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
41692 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
41693 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
41694 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
41695 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
41696 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
41697 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
41698 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
41699 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
41700 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
41701 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
41702 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
41703 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
41704 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
41705 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
41706 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
41707 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
41708 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
41709 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
41710 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
41711 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
41712 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
41713 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
41714 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
41715 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
41716 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
41717 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
41718 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
41719 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
41720 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
41721 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
41722 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
41723 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
41724 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
41725 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
41726 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
41727 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
41728 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
41729 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
41730 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
41731 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
41732 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
41733 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
41734 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
41735 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
41736 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
41737 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
41738 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
41739 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
41740 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
41741 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
41742 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
41743 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
41744 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
41745 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
41746 | |
41747 | |
41748 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
41749 | //BIF_CFG_DEV0_EPF2_1_VENDOR_ID |
41750 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
41751 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
41752 | //BIF_CFG_DEV0_EPF2_1_DEVICE_ID |
41753 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
41754 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
41755 | //BIF_CFG_DEV0_EPF2_1_COMMAND |
41756 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
41757 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
41758 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
41759 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
41760 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
41761 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
41762 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
41763 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
41764 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8 |
41765 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
41766 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa |
41767 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
41768 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
41769 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
41770 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
41771 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
41772 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
41773 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
41774 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L |
41775 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L |
41776 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
41777 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L |
41778 | //BIF_CFG_DEV0_EPF2_1_STATUS |
41779 | #define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3 |
41780 | #define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4 |
41781 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN__SHIFT 0x5 |
41782 | #define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
41783 | #define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
41784 | #define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
41785 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
41786 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
41787 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
41788 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
41789 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
41790 | #define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L |
41791 | #define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L |
41792 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN_MASK 0x0020L |
41793 | #define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
41794 | #define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
41795 | #define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
41796 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
41797 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
41798 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
41799 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
41800 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
41801 | //BIF_CFG_DEV0_EPF2_1_REVISION_ID |
41802 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
41803 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
41804 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
41805 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
41806 | //BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE |
41807 | #define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
41808 | #define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
41809 | //BIF_CFG_DEV0_EPF2_1_SUB_CLASS |
41810 | #define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
41811 | #define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
41812 | //BIF_CFG_DEV0_EPF2_1_BASE_CLASS |
41813 | #define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
41814 | #define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
41815 | //BIF_CFG_DEV0_EPF2_1_CACHE_LINE |
41816 | #define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
41817 | #define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
41818 | //BIF_CFG_DEV0_EPF2_1_LATENCY |
41819 | #define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
41820 | #define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
41821 | //BIF_CFG_DEV0_EPF2_1_HEADER |
41822 | #define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
41823 | #define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
41824 | #define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL |
41825 | #define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L |
41826 | //BIF_CFG_DEV0_EPF2_1_BIST |
41827 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0 |
41828 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6 |
41829 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7 |
41830 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL |
41831 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L |
41832 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L |
41833 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 |
41834 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
41835 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
41836 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 |
41837 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
41838 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
41839 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 |
41840 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
41841 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
41842 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 |
41843 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
41844 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
41845 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 |
41846 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
41847 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
41848 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 |
41849 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
41850 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
41851 | //BIF_CFG_DEV0_EPF2_1_ADAPTER_ID |
41852 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
41853 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
41854 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
41855 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
41856 | //BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR |
41857 | #define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
41858 | #define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
41859 | //BIF_CFG_DEV0_EPF2_1_CAP_PTR |
41860 | #define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
41861 | #define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
41862 | //BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE |
41863 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
41864 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
41865 | //BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN |
41866 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
41867 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
41868 | //BIF_CFG_DEV0_EPF2_1_MIN_GRANT |
41869 | #define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
41870 | #define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
41871 | //BIF_CFG_DEV0_EPF2_1_MAX_LATENCY |
41872 | #define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
41873 | #define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
41874 | //BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST |
41875 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
41876 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
41877 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
41878 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
41879 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
41880 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
41881 | //BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W |
41882 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
41883 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
41884 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
41885 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
41886 | //BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST |
41887 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
41888 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
41889 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
41890 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
41891 | //BIF_CFG_DEV0_EPF2_1_PMI_CAP |
41892 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0 |
41893 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
41894 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
41895 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
41896 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
41897 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
41898 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
41899 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L |
41900 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
41901 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
41902 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
41903 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
41904 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
41905 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
41906 | //BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL |
41907 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
41908 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
41909 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
41910 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
41911 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
41912 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
41913 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
41914 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
41915 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
41916 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
41917 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
41918 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
41919 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
41920 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
41921 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
41922 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
41923 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
41924 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
41925 | //BIF_CFG_DEV0_EPF2_1_SBRN |
41926 | #define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0 |
41927 | #define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL |
41928 | //BIF_CFG_DEV0_EPF2_1_FLADJ |
41929 | #define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0 |
41930 | #define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL |
41931 | //BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD |
41932 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
41933 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
41934 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
41935 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
41936 | //BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST |
41937 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
41938 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
41939 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
41940 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
41941 | //BIF_CFG_DEV0_EPF2_1_PCIE_CAP |
41942 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0 |
41943 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
41944 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
41945 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
41946 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL |
41947 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
41948 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
41949 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
41950 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CAP |
41951 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
41952 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
41953 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
41954 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
41955 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
41956 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
41957 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
41958 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
41959 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
41960 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
41961 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
41962 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
41963 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
41964 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
41965 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
41966 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
41967 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
41968 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
41969 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL |
41970 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
41971 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
41972 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
41973 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
41974 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
41975 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
41976 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
41977 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
41978 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
41979 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
41980 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
41981 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
41982 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
41983 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
41984 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
41985 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
41986 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
41987 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
41988 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
41989 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
41990 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
41991 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
41992 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
41993 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
41994 | //BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS |
41995 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
41996 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
41997 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
41998 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
41999 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
42000 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
42001 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
42002 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
42003 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
42004 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
42005 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
42006 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
42007 | //BIF_CFG_DEV0_EPF2_1_LINK_CAP |
42008 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
42009 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
42010 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
42011 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
42012 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
42013 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
42014 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
42015 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
42016 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
42017 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
42018 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
42019 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
42020 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
42021 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
42022 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
42023 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
42024 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
42025 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
42026 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
42027 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
42028 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
42029 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
42030 | //BIF_CFG_DEV0_EPF2_1_LINK_CNTL |
42031 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
42032 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
42033 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
42034 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
42035 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
42036 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
42037 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
42038 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
42039 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
42040 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
42041 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
42042 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
42043 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
42044 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
42045 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
42046 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
42047 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
42048 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
42049 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
42050 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
42051 | //BIF_CFG_DEV0_EPF2_1_LINK_STATUS |
42052 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
42053 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
42054 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
42055 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
42056 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
42057 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
42058 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
42059 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
42060 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
42061 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
42062 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
42063 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
42064 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
42065 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
42066 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 |
42067 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
42068 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
42069 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
42070 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
42071 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
42072 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
42073 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
42074 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
42075 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
42076 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
42077 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
42078 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
42079 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
42080 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
42081 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
42082 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
42083 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
42084 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
42085 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
42086 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
42087 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
42088 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
42089 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
42090 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
42091 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
42092 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
42093 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
42094 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
42095 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 |
42096 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
42097 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
42098 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
42099 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
42100 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
42101 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
42102 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
42103 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
42104 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
42105 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
42106 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
42107 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
42108 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
42109 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
42110 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
42111 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
42112 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
42113 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
42114 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
42115 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
42116 | //BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 |
42117 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
42118 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
42119 | //BIF_CFG_DEV0_EPF2_1_LINK_CAP2 |
42120 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
42121 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
42122 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
42123 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
42124 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
42125 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
42126 | //BIF_CFG_DEV0_EPF2_1_LINK_CNTL2 |
42127 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
42128 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
42129 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
42130 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
42131 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
42132 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
42133 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
42134 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
42135 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
42136 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
42137 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
42138 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
42139 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
42140 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
42141 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
42142 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
42143 | //BIF_CFG_DEV0_EPF2_1_LINK_STATUS2 |
42144 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
42145 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
42146 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
42147 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
42148 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
42149 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
42150 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
42151 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
42152 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
42153 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
42154 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
42155 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
42156 | //BIF_CFG_DEV0_EPF2_1_SLOT_CAP2 |
42157 | #define BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
42158 | #define BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
42159 | //BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2 |
42160 | #define BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
42161 | #define BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
42162 | //BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2 |
42163 | #define BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
42164 | #define BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
42165 | //BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST |
42166 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
42167 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42168 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
42169 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42170 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL |
42171 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
42172 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
42173 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
42174 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
42175 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
42176 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
42177 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
42178 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
42179 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
42180 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
42181 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO |
42182 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
42183 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
42184 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI |
42185 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
42186 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
42187 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA |
42188 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
42189 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
42190 | //BIF_CFG_DEV0_EPF2_1_MSI_MASK |
42191 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
42192 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
42193 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 |
42194 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
42195 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
42196 | //BIF_CFG_DEV0_EPF2_1_MSI_MASK_64 |
42197 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
42198 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
42199 | //BIF_CFG_DEV0_EPF2_1_MSI_PENDING |
42200 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
42201 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
42202 | //BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 |
42203 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
42204 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
42205 | //BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST |
42206 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
42207 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42208 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
42209 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42210 | //BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL |
42211 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
42212 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
42213 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
42214 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
42215 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
42216 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
42217 | //BIF_CFG_DEV0_EPF2_1_MSIX_TABLE |
42218 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
42219 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
42220 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
42221 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
42222 | //BIF_CFG_DEV0_EPF2_1_MSIX_PBA |
42223 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
42224 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
42225 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
42226 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
42227 | //BIF_CFG_DEV0_EPF2_1_SATA_CAP_0 |
42228 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
42229 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
42230 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
42231 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
42232 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
42233 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
42234 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
42235 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
42236 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
42237 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
42238 | //BIF_CFG_DEV0_EPF2_1_SATA_CAP_1 |
42239 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
42240 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
42241 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
42242 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
42243 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
42244 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
42245 | //BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX |
42246 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
42247 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
42248 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
42249 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
42250 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
42251 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
42252 | //BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA |
42253 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
42254 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
42255 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
42256 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42257 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42258 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42259 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42260 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42261 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42262 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR |
42263 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
42264 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
42265 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
42266 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
42267 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
42268 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
42269 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 |
42270 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
42271 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
42272 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 |
42273 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
42274 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
42275 | //BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
42276 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42277 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42278 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42279 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42280 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42281 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42282 | //BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS |
42283 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
42284 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
42285 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
42286 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
42287 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
42288 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
42289 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
42290 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
42291 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
42292 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
42293 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
42294 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
42295 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
42296 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
42297 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
42298 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
42299 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
42300 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
42301 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
42302 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
42303 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
42304 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
42305 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
42306 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
42307 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
42308 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
42309 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
42310 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
42311 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
42312 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
42313 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
42314 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
42315 | //BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK |
42316 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
42317 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
42318 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
42319 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
42320 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
42321 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
42322 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
42323 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
42324 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
42325 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
42326 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
42327 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
42328 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
42329 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
42330 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
42331 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
42332 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
42333 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
42334 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
42335 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
42336 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
42337 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
42338 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
42339 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
42340 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
42341 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
42342 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
42343 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
42344 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
42345 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
42346 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
42347 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
42348 | //BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY |
42349 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
42350 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
42351 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
42352 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
42353 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
42354 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
42355 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
42356 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
42357 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
42358 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
42359 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
42360 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
42361 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
42362 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
42363 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
42364 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
42365 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
42366 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
42367 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
42368 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
42369 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
42370 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
42371 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
42372 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
42373 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
42374 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
42375 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
42376 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
42377 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
42378 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
42379 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
42380 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
42381 | //BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS |
42382 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
42383 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
42384 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
42385 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
42386 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
42387 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
42388 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
42389 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
42390 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
42391 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
42392 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
42393 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
42394 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
42395 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
42396 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
42397 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
42398 | //BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK |
42399 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
42400 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
42401 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
42402 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
42403 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
42404 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
42405 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
42406 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
42407 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
42408 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
42409 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
42410 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
42411 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
42412 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
42413 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
42414 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
42415 | //BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL |
42416 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
42417 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
42418 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
42419 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
42420 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
42421 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
42422 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
42423 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
42424 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
42425 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
42426 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
42427 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
42428 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
42429 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
42430 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
42431 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
42432 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 |
42433 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
42434 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
42435 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 |
42436 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
42437 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
42438 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 |
42439 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
42440 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
42441 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 |
42442 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
42443 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
42444 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 |
42445 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
42446 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
42447 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 |
42448 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
42449 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
42450 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 |
42451 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
42452 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
42453 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 |
42454 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
42455 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
42456 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST |
42457 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42458 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42459 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42460 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42461 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42462 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42463 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP |
42464 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
42465 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
42466 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL |
42467 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
42468 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
42469 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
42470 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
42471 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
42472 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
42473 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP |
42474 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
42475 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
42476 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL |
42477 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
42478 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
42479 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
42480 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
42481 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
42482 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
42483 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP |
42484 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
42485 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
42486 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL |
42487 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
42488 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
42489 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
42490 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
42491 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
42492 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
42493 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP |
42494 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
42495 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
42496 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL |
42497 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
42498 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
42499 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
42500 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
42501 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
42502 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
42503 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP |
42504 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
42505 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
42506 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL |
42507 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
42508 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
42509 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
42510 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
42511 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
42512 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
42513 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP |
42514 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
42515 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
42516 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL |
42517 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
42518 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
42519 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
42520 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
42521 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
42522 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
42523 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
42524 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42525 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42526 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42527 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42528 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42529 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42530 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT |
42531 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
42532 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
42533 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA |
42534 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
42535 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
42536 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
42537 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
42538 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
42539 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
42540 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
42541 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
42542 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
42543 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
42544 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
42545 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
42546 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP |
42547 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
42548 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
42549 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST |
42550 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42551 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42552 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42553 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42554 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42555 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42556 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP |
42557 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
42558 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
42559 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
42560 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
42561 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
42562 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
42563 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
42564 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
42565 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
42566 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
42567 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR |
42568 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
42569 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
42570 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS |
42571 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
42572 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
42573 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
42574 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
42575 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL |
42576 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
42577 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
42578 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
42579 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42580 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42581 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
42582 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42583 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42584 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
42585 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42586 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42587 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
42588 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42589 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42590 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
42591 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42592 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42593 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
42594 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42595 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42596 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
42597 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42598 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42599 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
42600 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
42601 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
42602 | //BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST |
42603 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42604 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42605 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42606 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42607 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42608 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42609 | //BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP |
42610 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
42611 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
42612 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
42613 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
42614 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
42615 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
42616 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
42617 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
42618 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
42619 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
42620 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
42621 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
42622 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
42623 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
42624 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
42625 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
42626 | //BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL |
42627 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
42628 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
42629 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
42630 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
42631 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
42632 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
42633 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
42634 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
42635 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
42636 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
42637 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
42638 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
42639 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
42640 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
42641 | //BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST |
42642 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42643 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42644 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42645 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42646 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42647 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42648 | //BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP |
42649 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
42650 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
42651 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
42652 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
42653 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
42654 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
42655 | //BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL |
42656 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
42657 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
42658 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
42659 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
42660 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
42661 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
42662 | |
42663 | |
42664 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
42665 | //BIF_CFG_DEV0_EPF3_1_VENDOR_ID |
42666 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
42667 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
42668 | //BIF_CFG_DEV0_EPF3_1_DEVICE_ID |
42669 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
42670 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
42671 | //BIF_CFG_DEV0_EPF3_1_COMMAND |
42672 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
42673 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
42674 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
42675 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
42676 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
42677 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
42678 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
42679 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
42680 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8 |
42681 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
42682 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa |
42683 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
42684 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
42685 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
42686 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
42687 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
42688 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
42689 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
42690 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L |
42691 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L |
42692 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
42693 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L |
42694 | //BIF_CFG_DEV0_EPF3_1_STATUS |
42695 | #define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3 |
42696 | #define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4 |
42697 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN__SHIFT 0x5 |
42698 | #define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
42699 | #define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
42700 | #define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
42701 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
42702 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
42703 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
42704 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
42705 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
42706 | #define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L |
42707 | #define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L |
42708 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN_MASK 0x0020L |
42709 | #define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
42710 | #define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
42711 | #define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
42712 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
42713 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
42714 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
42715 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
42716 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
42717 | //BIF_CFG_DEV0_EPF3_1_REVISION_ID |
42718 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
42719 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
42720 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
42721 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
42722 | //BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE |
42723 | #define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
42724 | #define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
42725 | //BIF_CFG_DEV0_EPF3_1_SUB_CLASS |
42726 | #define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
42727 | #define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
42728 | //BIF_CFG_DEV0_EPF3_1_BASE_CLASS |
42729 | #define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
42730 | #define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
42731 | //BIF_CFG_DEV0_EPF3_1_CACHE_LINE |
42732 | #define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
42733 | #define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
42734 | //BIF_CFG_DEV0_EPF3_1_LATENCY |
42735 | #define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
42736 | #define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
42737 | //BIF_CFG_DEV0_EPF3_1_HEADER |
42738 | #define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
42739 | #define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
42740 | #define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK 0x7FL |
42741 | #define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK 0x80L |
42742 | //BIF_CFG_DEV0_EPF3_1_BIST |
42743 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0 |
42744 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6 |
42745 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7 |
42746 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL |
42747 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L |
42748 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L |
42749 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 |
42750 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
42751 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
42752 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 |
42753 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
42754 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
42755 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 |
42756 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
42757 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
42758 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 |
42759 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
42760 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
42761 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 |
42762 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
42763 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
42764 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 |
42765 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
42766 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
42767 | //BIF_CFG_DEV0_EPF3_1_ADAPTER_ID |
42768 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
42769 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
42770 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
42771 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
42772 | //BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR |
42773 | #define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
42774 | #define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
42775 | //BIF_CFG_DEV0_EPF3_1_CAP_PTR |
42776 | #define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
42777 | #define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
42778 | //BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE |
42779 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
42780 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
42781 | //BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN |
42782 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
42783 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
42784 | //BIF_CFG_DEV0_EPF3_1_MIN_GRANT |
42785 | #define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
42786 | #define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
42787 | //BIF_CFG_DEV0_EPF3_1_MAX_LATENCY |
42788 | #define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
42789 | #define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
42790 | //BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST |
42791 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
42792 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42793 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
42794 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
42795 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
42796 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
42797 | //BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W |
42798 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
42799 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
42800 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
42801 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
42802 | //BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST |
42803 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
42804 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42805 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
42806 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42807 | //BIF_CFG_DEV0_EPF3_1_PMI_CAP |
42808 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0 |
42809 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
42810 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
42811 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
42812 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
42813 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
42814 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
42815 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L |
42816 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
42817 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
42818 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
42819 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
42820 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
42821 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
42822 | //BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL |
42823 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
42824 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
42825 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
42826 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
42827 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
42828 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
42829 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
42830 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
42831 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
42832 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
42833 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
42834 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
42835 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
42836 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
42837 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
42838 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
42839 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
42840 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
42841 | //BIF_CFG_DEV0_EPF3_1_SBRN |
42842 | #define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0 |
42843 | #define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL |
42844 | //BIF_CFG_DEV0_EPF3_1_FLADJ |
42845 | #define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0 |
42846 | #define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL |
42847 | //BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD |
42848 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
42849 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
42850 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
42851 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
42852 | //BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST |
42853 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
42854 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42855 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
42856 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42857 | //BIF_CFG_DEV0_EPF3_1_PCIE_CAP |
42858 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0 |
42859 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
42860 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
42861 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
42862 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL |
42863 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
42864 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
42865 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
42866 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CAP |
42867 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
42868 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
42869 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
42870 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
42871 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
42872 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
42873 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
42874 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
42875 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
42876 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
42877 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
42878 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
42879 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
42880 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
42881 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
42882 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
42883 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
42884 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
42885 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL |
42886 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
42887 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
42888 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
42889 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
42890 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
42891 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
42892 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
42893 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
42894 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
42895 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
42896 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
42897 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
42898 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
42899 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
42900 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
42901 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
42902 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
42903 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
42904 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
42905 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
42906 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
42907 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
42908 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
42909 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
42910 | //BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS |
42911 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
42912 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
42913 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
42914 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
42915 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
42916 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
42917 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
42918 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
42919 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
42920 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
42921 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
42922 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
42923 | //BIF_CFG_DEV0_EPF3_1_LINK_CAP |
42924 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
42925 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
42926 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
42927 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
42928 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
42929 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
42930 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
42931 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
42932 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
42933 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
42934 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
42935 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
42936 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
42937 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
42938 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
42939 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
42940 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
42941 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
42942 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
42943 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
42944 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
42945 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
42946 | //BIF_CFG_DEV0_EPF3_1_LINK_CNTL |
42947 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
42948 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
42949 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
42950 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
42951 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
42952 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
42953 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
42954 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
42955 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
42956 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
42957 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
42958 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
42959 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
42960 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
42961 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
42962 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
42963 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
42964 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
42965 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
42966 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
42967 | //BIF_CFG_DEV0_EPF3_1_LINK_STATUS |
42968 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
42969 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
42970 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
42971 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
42972 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
42973 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
42974 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
42975 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
42976 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
42977 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
42978 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
42979 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
42980 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
42981 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
42982 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 |
42983 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
42984 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
42985 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
42986 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
42987 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
42988 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
42989 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
42990 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
42991 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
42992 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
42993 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
42994 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
42995 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
42996 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
42997 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
42998 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
42999 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
43000 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
43001 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
43002 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
43003 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
43004 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
43005 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
43006 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
43007 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
43008 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
43009 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
43010 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
43011 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 |
43012 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
43013 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
43014 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
43015 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
43016 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
43017 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
43018 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
43019 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
43020 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
43021 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
43022 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
43023 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
43024 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
43025 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
43026 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
43027 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
43028 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
43029 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
43030 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
43031 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
43032 | //BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 |
43033 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
43034 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
43035 | //BIF_CFG_DEV0_EPF3_1_LINK_CAP2 |
43036 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
43037 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
43038 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
43039 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
43040 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
43041 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
43042 | //BIF_CFG_DEV0_EPF3_1_LINK_CNTL2 |
43043 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
43044 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
43045 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
43046 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
43047 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
43048 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
43049 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
43050 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
43051 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
43052 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
43053 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
43054 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
43055 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
43056 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
43057 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
43058 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
43059 | //BIF_CFG_DEV0_EPF3_1_LINK_STATUS2 |
43060 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
43061 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
43062 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
43063 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
43064 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
43065 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
43066 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
43067 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
43068 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
43069 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
43070 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
43071 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
43072 | //BIF_CFG_DEV0_EPF3_1_SLOT_CAP2 |
43073 | #define BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
43074 | #define BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
43075 | //BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2 |
43076 | #define BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
43077 | #define BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
43078 | //BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2 |
43079 | #define BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
43080 | #define BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
43081 | //BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST |
43082 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
43083 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
43084 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
43085 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
43086 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL |
43087 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
43088 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
43089 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
43090 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
43091 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
43092 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
43093 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
43094 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
43095 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
43096 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
43097 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO |
43098 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
43099 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
43100 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI |
43101 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
43102 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
43103 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA |
43104 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
43105 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
43106 | //BIF_CFG_DEV0_EPF3_1_MSI_MASK |
43107 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
43108 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
43109 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 |
43110 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
43111 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
43112 | //BIF_CFG_DEV0_EPF3_1_MSI_MASK_64 |
43113 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
43114 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
43115 | //BIF_CFG_DEV0_EPF3_1_MSI_PENDING |
43116 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
43117 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
43118 | //BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 |
43119 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
43120 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
43121 | //BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST |
43122 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
43123 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
43124 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
43125 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
43126 | //BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL |
43127 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
43128 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
43129 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
43130 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
43131 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
43132 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
43133 | //BIF_CFG_DEV0_EPF3_1_MSIX_TABLE |
43134 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
43135 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
43136 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
43137 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
43138 | //BIF_CFG_DEV0_EPF3_1_MSIX_PBA |
43139 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
43140 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
43141 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
43142 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
43143 | //BIF_CFG_DEV0_EPF3_1_SATA_CAP_0 |
43144 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
43145 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
43146 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
43147 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
43148 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
43149 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
43150 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
43151 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
43152 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
43153 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
43154 | //BIF_CFG_DEV0_EPF3_1_SATA_CAP_1 |
43155 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
43156 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
43157 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
43158 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
43159 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
43160 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
43161 | //BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX |
43162 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
43163 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
43164 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
43165 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
43166 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
43167 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
43168 | //BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA |
43169 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
43170 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
43171 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
43172 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43173 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43174 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43175 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43176 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43177 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43178 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR |
43179 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
43180 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
43181 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
43182 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
43183 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
43184 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
43185 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 |
43186 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
43187 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
43188 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 |
43189 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
43190 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
43191 | //BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
43192 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43193 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43194 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43195 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43196 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43197 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43198 | //BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS |
43199 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
43200 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
43201 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
43202 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
43203 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
43204 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
43205 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
43206 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
43207 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
43208 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
43209 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
43210 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
43211 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
43212 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
43213 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
43214 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
43215 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
43216 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
43217 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
43218 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
43219 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
43220 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
43221 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
43222 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
43223 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
43224 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
43225 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
43226 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
43227 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
43228 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
43229 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
43230 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
43231 | //BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK |
43232 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
43233 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
43234 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
43235 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
43236 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
43237 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
43238 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
43239 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
43240 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
43241 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
43242 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
43243 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
43244 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
43245 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
43246 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
43247 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
43248 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
43249 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
43250 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
43251 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
43252 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
43253 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
43254 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
43255 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
43256 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
43257 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
43258 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
43259 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
43260 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
43261 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
43262 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
43263 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
43264 | //BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY |
43265 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
43266 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
43267 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
43268 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
43269 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
43270 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
43271 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
43272 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
43273 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
43274 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
43275 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
43276 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
43277 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
43278 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
43279 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
43280 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
43281 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
43282 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
43283 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
43284 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
43285 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
43286 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
43287 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
43288 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
43289 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
43290 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
43291 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
43292 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
43293 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
43294 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
43295 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
43296 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
43297 | //BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS |
43298 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
43299 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
43300 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
43301 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
43302 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
43303 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
43304 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
43305 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
43306 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
43307 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
43308 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
43309 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
43310 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
43311 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
43312 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
43313 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
43314 | //BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK |
43315 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
43316 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
43317 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
43318 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
43319 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
43320 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
43321 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
43322 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
43323 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
43324 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
43325 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
43326 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
43327 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
43328 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
43329 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
43330 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
43331 | //BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL |
43332 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
43333 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
43334 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
43335 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
43336 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
43337 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
43338 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
43339 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
43340 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
43341 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
43342 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
43343 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
43344 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
43345 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
43346 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
43347 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
43348 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 |
43349 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
43350 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
43351 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 |
43352 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
43353 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
43354 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 |
43355 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
43356 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
43357 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 |
43358 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
43359 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
43360 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 |
43361 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
43362 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
43363 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 |
43364 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
43365 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
43366 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 |
43367 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
43368 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
43369 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 |
43370 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
43371 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
43372 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST |
43373 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43374 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43375 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43376 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43377 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43378 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43379 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP |
43380 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43381 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
43382 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL |
43383 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
43384 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43385 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
43386 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
43387 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
43388 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
43389 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP |
43390 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43391 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
43392 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL |
43393 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
43394 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43395 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
43396 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
43397 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
43398 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
43399 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP |
43400 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43401 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
43402 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL |
43403 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
43404 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43405 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
43406 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
43407 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
43408 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
43409 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP |
43410 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43411 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
43412 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL |
43413 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
43414 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43415 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
43416 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
43417 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
43418 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
43419 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP |
43420 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43421 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
43422 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL |
43423 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
43424 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43425 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
43426 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
43427 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
43428 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
43429 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP |
43430 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43431 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
43432 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL |
43433 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
43434 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43435 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
43436 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
43437 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
43438 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
43439 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
43440 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43441 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43442 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43443 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43444 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43445 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43446 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT |
43447 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
43448 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
43449 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA |
43450 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
43451 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
43452 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
43453 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
43454 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
43455 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
43456 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
43457 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
43458 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
43459 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
43460 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
43461 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
43462 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP |
43463 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
43464 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
43465 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST |
43466 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43467 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43468 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43469 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43470 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43471 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43472 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP |
43473 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
43474 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
43475 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
43476 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
43477 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
43478 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
43479 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
43480 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
43481 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
43482 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
43483 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR |
43484 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
43485 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
43486 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS |
43487 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
43488 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
43489 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
43490 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
43491 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL |
43492 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
43493 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
43494 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
43495 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43496 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43497 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
43498 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43499 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43500 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
43501 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43502 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43503 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
43504 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43505 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43506 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
43507 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43508 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43509 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
43510 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43511 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43512 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
43513 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43514 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43515 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
43516 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43517 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43518 | //BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST |
43519 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43520 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43521 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43522 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43523 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43524 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43525 | //BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP |
43526 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
43527 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
43528 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
43529 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
43530 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
43531 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
43532 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
43533 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
43534 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
43535 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
43536 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
43537 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
43538 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
43539 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
43540 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
43541 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
43542 | //BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL |
43543 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
43544 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
43545 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
43546 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
43547 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
43548 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
43549 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
43550 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
43551 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
43552 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
43553 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
43554 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
43555 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
43556 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
43557 | //BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST |
43558 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43559 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43560 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43561 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43562 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43563 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43564 | //BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP |
43565 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
43566 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
43567 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
43568 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
43569 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
43570 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
43571 | //BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL |
43572 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
43573 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
43574 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
43575 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
43576 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
43577 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
43578 | |
43579 | |
43580 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
43581 | //BIF_CFG_DEV0_EPF4_1_VENDOR_ID |
43582 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
43583 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
43584 | //BIF_CFG_DEV0_EPF4_1_DEVICE_ID |
43585 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
43586 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
43587 | //BIF_CFG_DEV0_EPF4_1_COMMAND |
43588 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
43589 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
43590 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
43591 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
43592 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
43593 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
43594 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
43595 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
43596 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN__SHIFT 0x8 |
43597 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
43598 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS__SHIFT 0xa |
43599 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
43600 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
43601 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
43602 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
43603 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
43604 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
43605 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
43606 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING_MASK 0x0080L |
43607 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN_MASK 0x0100L |
43608 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
43609 | #define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS_MASK 0x0400L |
43610 | //BIF_CFG_DEV0_EPF4_1_STATUS |
43611 | #define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS__SHIFT 0x3 |
43612 | #define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST__SHIFT 0x4 |
43613 | #define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN__SHIFT 0x5 |
43614 | #define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
43615 | #define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
43616 | #define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
43617 | #define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
43618 | #define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
43619 | #define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
43620 | #define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
43621 | #define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
43622 | #define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS_MASK 0x0008L |
43623 | #define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST_MASK 0x0010L |
43624 | #define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN_MASK 0x0020L |
43625 | #define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
43626 | #define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
43627 | #define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
43628 | #define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
43629 | #define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
43630 | #define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
43631 | #define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
43632 | #define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
43633 | //BIF_CFG_DEV0_EPF4_1_REVISION_ID |
43634 | #define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
43635 | #define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
43636 | #define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
43637 | #define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
43638 | //BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE |
43639 | #define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
43640 | #define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
43641 | //BIF_CFG_DEV0_EPF4_1_SUB_CLASS |
43642 | #define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
43643 | #define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
43644 | //BIF_CFG_DEV0_EPF4_1_BASE_CLASS |
43645 | #define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
43646 | #define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
43647 | //BIF_CFG_DEV0_EPF4_1_CACHE_LINE |
43648 | #define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
43649 | #define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
43650 | //BIF_CFG_DEV0_EPF4_1_LATENCY |
43651 | #define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
43652 | #define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
43653 | //BIF_CFG_DEV0_EPF4_1_HEADER |
43654 | #define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
43655 | #define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
43656 | #define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE_MASK 0x7FL |
43657 | #define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE_MASK 0x80L |
43658 | //BIF_CFG_DEV0_EPF4_1_BIST |
43659 | #define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP__SHIFT 0x0 |
43660 | #define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT__SHIFT 0x6 |
43661 | #define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP__SHIFT 0x7 |
43662 | #define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP_MASK 0x0FL |
43663 | #define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT_MASK 0x40L |
43664 | #define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP_MASK 0x80L |
43665 | //BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1 |
43666 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
43667 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
43668 | //BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2 |
43669 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
43670 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
43671 | //BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3 |
43672 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
43673 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
43674 | //BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4 |
43675 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
43676 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
43677 | //BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5 |
43678 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
43679 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
43680 | //BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6 |
43681 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
43682 | #define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
43683 | //BIF_CFG_DEV0_EPF4_1_ADAPTER_ID |
43684 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
43685 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
43686 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
43687 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
43688 | //BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR |
43689 | #define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
43690 | #define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
43691 | //BIF_CFG_DEV0_EPF4_1_CAP_PTR |
43692 | #define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
43693 | #define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
43694 | //BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE |
43695 | #define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
43696 | #define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
43697 | //BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN |
43698 | #define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
43699 | #define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
43700 | //BIF_CFG_DEV0_EPF4_1_MIN_GRANT |
43701 | #define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
43702 | #define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
43703 | //BIF_CFG_DEV0_EPF4_1_MAX_LATENCY |
43704 | #define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
43705 | #define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
43706 | //BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST |
43707 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
43708 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
43709 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
43710 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
43711 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
43712 | #define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
43713 | //BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W |
43714 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
43715 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
43716 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
43717 | #define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
43718 | //BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST |
43719 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
43720 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
43721 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
43722 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
43723 | //BIF_CFG_DEV0_EPF4_1_PMI_CAP |
43724 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION__SHIFT 0x0 |
43725 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
43726 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
43727 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
43728 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
43729 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
43730 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
43731 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION_MASK 0x0007L |
43732 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
43733 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
43734 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
43735 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
43736 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
43737 | #define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
43738 | //BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL |
43739 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
43740 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
43741 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
43742 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
43743 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
43744 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
43745 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
43746 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
43747 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
43748 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
43749 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
43750 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
43751 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
43752 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
43753 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
43754 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
43755 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
43756 | #define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
43757 | //BIF_CFG_DEV0_EPF4_1_SBRN |
43758 | #define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN__SHIFT 0x0 |
43759 | #define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN_MASK 0xFFL |
43760 | //BIF_CFG_DEV0_EPF4_1_FLADJ |
43761 | #define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ__SHIFT 0x0 |
43762 | #define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ_MASK 0x3FL |
43763 | //BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD |
43764 | #define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
43765 | #define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
43766 | #define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
43767 | #define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
43768 | //BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST |
43769 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
43770 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
43771 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
43772 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
43773 | //BIF_CFG_DEV0_EPF4_1_PCIE_CAP |
43774 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION__SHIFT 0x0 |
43775 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
43776 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
43777 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
43778 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION_MASK 0x000FL |
43779 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
43780 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
43781 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
43782 | //BIF_CFG_DEV0_EPF4_1_DEVICE_CAP |
43783 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
43784 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
43785 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
43786 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
43787 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
43788 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
43789 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
43790 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
43791 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
43792 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
43793 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
43794 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
43795 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
43796 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
43797 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
43798 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
43799 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
43800 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
43801 | //BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL |
43802 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
43803 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
43804 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
43805 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
43806 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
43807 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
43808 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
43809 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
43810 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
43811 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
43812 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
43813 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
43814 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
43815 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
43816 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
43817 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
43818 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
43819 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
43820 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
43821 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
43822 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
43823 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
43824 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
43825 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
43826 | //BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS |
43827 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
43828 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
43829 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
43830 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
43831 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
43832 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
43833 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
43834 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
43835 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
43836 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
43837 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
43838 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
43839 | //BIF_CFG_DEV0_EPF4_1_LINK_CAP |
43840 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
43841 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
43842 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
43843 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
43844 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
43845 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
43846 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
43847 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
43848 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
43849 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
43850 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
43851 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
43852 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
43853 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
43854 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
43855 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
43856 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
43857 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
43858 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
43859 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
43860 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
43861 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
43862 | //BIF_CFG_DEV0_EPF4_1_LINK_CNTL |
43863 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
43864 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
43865 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
43866 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
43867 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
43868 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
43869 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
43870 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
43871 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
43872 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
43873 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
43874 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
43875 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
43876 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
43877 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
43878 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
43879 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
43880 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
43881 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
43882 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
43883 | //BIF_CFG_DEV0_EPF4_1_LINK_STATUS |
43884 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
43885 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
43886 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
43887 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
43888 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
43889 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
43890 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
43891 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
43892 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
43893 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
43894 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
43895 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
43896 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
43897 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
43898 | //BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2 |
43899 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
43900 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
43901 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
43902 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
43903 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
43904 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
43905 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
43906 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
43907 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
43908 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
43909 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
43910 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
43911 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
43912 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
43913 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
43914 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
43915 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
43916 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
43917 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
43918 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
43919 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
43920 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
43921 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
43922 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
43923 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
43924 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
43925 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
43926 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
43927 | //BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2 |
43928 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
43929 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
43930 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
43931 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
43932 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
43933 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
43934 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
43935 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
43936 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
43937 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
43938 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
43939 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
43940 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
43941 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
43942 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
43943 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
43944 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
43945 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
43946 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
43947 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
43948 | //BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2 |
43949 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
43950 | #define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
43951 | //BIF_CFG_DEV0_EPF4_1_LINK_CAP2 |
43952 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
43953 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
43954 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
43955 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
43956 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
43957 | #define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
43958 | //BIF_CFG_DEV0_EPF4_1_LINK_CNTL2 |
43959 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
43960 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
43961 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
43962 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
43963 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
43964 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
43965 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
43966 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
43967 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
43968 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
43969 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
43970 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
43971 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
43972 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
43973 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
43974 | #define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
43975 | //BIF_CFG_DEV0_EPF4_1_LINK_STATUS2 |
43976 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
43977 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
43978 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
43979 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
43980 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
43981 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
43982 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
43983 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
43984 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
43985 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
43986 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
43987 | #define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
43988 | //BIF_CFG_DEV0_EPF4_1_SLOT_CAP2 |
43989 | #define BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
43990 | #define BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
43991 | //BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2 |
43992 | #define BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
43993 | #define BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
43994 | //BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2 |
43995 | #define BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
43996 | #define BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
43997 | //BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST |
43998 | #define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
43999 | #define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44000 | #define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
44001 | #define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44002 | //BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL |
44003 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
44004 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
44005 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
44006 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
44007 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
44008 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
44009 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
44010 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
44011 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
44012 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
44013 | //BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO |
44014 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
44015 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
44016 | //BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI |
44017 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
44018 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
44019 | //BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA |
44020 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
44021 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
44022 | //BIF_CFG_DEV0_EPF4_1_MSI_MASK |
44023 | #define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
44024 | #define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
44025 | //BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64 |
44026 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
44027 | #define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
44028 | //BIF_CFG_DEV0_EPF4_1_MSI_MASK_64 |
44029 | #define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
44030 | #define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
44031 | //BIF_CFG_DEV0_EPF4_1_MSI_PENDING |
44032 | #define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
44033 | #define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
44034 | //BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64 |
44035 | #define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
44036 | #define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
44037 | //BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST |
44038 | #define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
44039 | #define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44040 | #define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
44041 | #define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44042 | //BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL |
44043 | #define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
44044 | #define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
44045 | #define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
44046 | #define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
44047 | #define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
44048 | #define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
44049 | //BIF_CFG_DEV0_EPF4_1_MSIX_TABLE |
44050 | #define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
44051 | #define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
44052 | #define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
44053 | #define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
44054 | //BIF_CFG_DEV0_EPF4_1_MSIX_PBA |
44055 | #define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
44056 | #define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
44057 | #define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
44058 | #define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
44059 | //BIF_CFG_DEV0_EPF4_1_SATA_CAP_0 |
44060 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
44061 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
44062 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
44063 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
44064 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
44065 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
44066 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
44067 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
44068 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
44069 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
44070 | //BIF_CFG_DEV0_EPF4_1_SATA_CAP_1 |
44071 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
44072 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
44073 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
44074 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
44075 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
44076 | #define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
44077 | //BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX |
44078 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
44079 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
44080 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
44081 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
44082 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
44083 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
44084 | //BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA |
44085 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
44086 | #define BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
44087 | //BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
44088 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44089 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44090 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44091 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44092 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44093 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44094 | //BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR |
44095 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
44096 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
44097 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
44098 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
44099 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
44100 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
44101 | //BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1 |
44102 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
44103 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
44104 | //BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2 |
44105 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
44106 | #define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
44107 | //BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
44108 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44109 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44110 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44111 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44112 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44113 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44114 | //BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS |
44115 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
44116 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
44117 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
44118 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
44119 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
44120 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
44121 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
44122 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
44123 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
44124 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
44125 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
44126 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
44127 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
44128 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
44129 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
44130 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
44131 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
44132 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
44133 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
44134 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
44135 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
44136 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
44137 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
44138 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
44139 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
44140 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
44141 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
44142 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
44143 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
44144 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
44145 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
44146 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
44147 | //BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK |
44148 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
44149 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
44150 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
44151 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
44152 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
44153 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
44154 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
44155 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
44156 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
44157 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
44158 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
44159 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
44160 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
44161 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
44162 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
44163 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
44164 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
44165 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
44166 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
44167 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
44168 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
44169 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
44170 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
44171 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
44172 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
44173 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
44174 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
44175 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
44176 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
44177 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
44178 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
44179 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
44180 | //BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY |
44181 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
44182 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
44183 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
44184 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
44185 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
44186 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
44187 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
44188 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
44189 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
44190 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
44191 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
44192 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
44193 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
44194 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
44195 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
44196 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
44197 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
44198 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
44199 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
44200 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
44201 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
44202 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
44203 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
44204 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
44205 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
44206 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
44207 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
44208 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
44209 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
44210 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
44211 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
44212 | #define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
44213 | //BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS |
44214 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
44215 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
44216 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
44217 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
44218 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
44219 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
44220 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
44221 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
44222 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
44223 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
44224 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
44225 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
44226 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
44227 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
44228 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
44229 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
44230 | //BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK |
44231 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
44232 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
44233 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
44234 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
44235 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
44236 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
44237 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
44238 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
44239 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
44240 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
44241 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
44242 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
44243 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
44244 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
44245 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
44246 | #define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
44247 | //BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL |
44248 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
44249 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
44250 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
44251 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
44252 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
44253 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
44254 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
44255 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
44256 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
44257 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
44258 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
44259 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
44260 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
44261 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
44262 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
44263 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
44264 | //BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0 |
44265 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
44266 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
44267 | //BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1 |
44268 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
44269 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
44270 | //BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2 |
44271 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
44272 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
44273 | //BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3 |
44274 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
44275 | #define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
44276 | //BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0 |
44277 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
44278 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
44279 | //BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1 |
44280 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
44281 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
44282 | //BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2 |
44283 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
44284 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
44285 | //BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3 |
44286 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
44287 | #define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
44288 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST |
44289 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44290 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44291 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44292 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44293 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44294 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44295 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP |
44296 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44297 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
44298 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL |
44299 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
44300 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44301 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
44302 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
44303 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
44304 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
44305 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP |
44306 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44307 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
44308 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL |
44309 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
44310 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44311 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
44312 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
44313 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
44314 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
44315 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP |
44316 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44317 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
44318 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL |
44319 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
44320 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44321 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
44322 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
44323 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
44324 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
44325 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP |
44326 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44327 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
44328 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL |
44329 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
44330 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44331 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
44332 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
44333 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
44334 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
44335 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP |
44336 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44337 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
44338 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL |
44339 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
44340 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44341 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
44342 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
44343 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
44344 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
44345 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP |
44346 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44347 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
44348 | //BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL |
44349 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
44350 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44351 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
44352 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
44353 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
44354 | #define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
44355 | //BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
44356 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44357 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44358 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44359 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44360 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44361 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44362 | //BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT |
44363 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
44364 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
44365 | //BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA |
44366 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
44367 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
44368 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
44369 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
44370 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
44371 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
44372 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
44373 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
44374 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
44375 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
44376 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
44377 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
44378 | //BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP |
44379 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
44380 | #define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
44381 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST |
44382 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44383 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44384 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44385 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44386 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44387 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44388 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP |
44389 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
44390 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
44391 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
44392 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
44393 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
44394 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
44395 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
44396 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
44397 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
44398 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
44399 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR |
44400 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
44401 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
44402 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS |
44403 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
44404 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
44405 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
44406 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
44407 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL |
44408 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
44409 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
44410 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
44411 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44412 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44413 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
44414 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44415 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44416 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
44417 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44418 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44419 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
44420 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44421 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44422 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
44423 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44424 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44425 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
44426 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44427 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44428 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
44429 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44430 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44431 | //BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
44432 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44433 | #define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44434 | //BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST |
44435 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44436 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44437 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44438 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44439 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44440 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44441 | //BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP |
44442 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
44443 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
44444 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
44445 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
44446 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
44447 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
44448 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
44449 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
44450 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
44451 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
44452 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
44453 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
44454 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
44455 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
44456 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
44457 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
44458 | //BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL |
44459 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
44460 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
44461 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
44462 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
44463 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
44464 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
44465 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
44466 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
44467 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
44468 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
44469 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
44470 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
44471 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
44472 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
44473 | //BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST |
44474 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44475 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44476 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44477 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44478 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44479 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44480 | //BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP |
44481 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
44482 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
44483 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
44484 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
44485 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
44486 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
44487 | //BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL |
44488 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
44489 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
44490 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
44491 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
44492 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
44493 | #define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
44494 | |
44495 | |
44496 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
44497 | //BIF_CFG_DEV0_EPF5_1_VENDOR_ID |
44498 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
44499 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
44500 | //BIF_CFG_DEV0_EPF5_1_DEVICE_ID |
44501 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
44502 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
44503 | //BIF_CFG_DEV0_EPF5_1_COMMAND |
44504 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
44505 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
44506 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
44507 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
44508 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
44509 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
44510 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
44511 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
44512 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN__SHIFT 0x8 |
44513 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
44514 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS__SHIFT 0xa |
44515 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
44516 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
44517 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
44518 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
44519 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
44520 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
44521 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
44522 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING_MASK 0x0080L |
44523 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN_MASK 0x0100L |
44524 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
44525 | #define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS_MASK 0x0400L |
44526 | //BIF_CFG_DEV0_EPF5_1_STATUS |
44527 | #define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS__SHIFT 0x3 |
44528 | #define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST__SHIFT 0x4 |
44529 | #define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN__SHIFT 0x5 |
44530 | #define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
44531 | #define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
44532 | #define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
44533 | #define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
44534 | #define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
44535 | #define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
44536 | #define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
44537 | #define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
44538 | #define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS_MASK 0x0008L |
44539 | #define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST_MASK 0x0010L |
44540 | #define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN_MASK 0x0020L |
44541 | #define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
44542 | #define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
44543 | #define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
44544 | #define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
44545 | #define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
44546 | #define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
44547 | #define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
44548 | #define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
44549 | //BIF_CFG_DEV0_EPF5_1_REVISION_ID |
44550 | #define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
44551 | #define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
44552 | #define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
44553 | #define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
44554 | //BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE |
44555 | #define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
44556 | #define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
44557 | //BIF_CFG_DEV0_EPF5_1_SUB_CLASS |
44558 | #define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
44559 | #define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
44560 | //BIF_CFG_DEV0_EPF5_1_BASE_CLASS |
44561 | #define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
44562 | #define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
44563 | //BIF_CFG_DEV0_EPF5_1_CACHE_LINE |
44564 | #define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
44565 | #define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
44566 | //BIF_CFG_DEV0_EPF5_1_LATENCY |
44567 | #define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
44568 | #define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
44569 | //BIF_CFG_DEV0_EPF5_1_HEADER |
44570 | #define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
44571 | #define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
44572 | #define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE_MASK 0x7FL |
44573 | #define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE_MASK 0x80L |
44574 | //BIF_CFG_DEV0_EPF5_1_BIST |
44575 | #define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP__SHIFT 0x0 |
44576 | #define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT__SHIFT 0x6 |
44577 | #define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP__SHIFT 0x7 |
44578 | #define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP_MASK 0x0FL |
44579 | #define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT_MASK 0x40L |
44580 | #define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP_MASK 0x80L |
44581 | //BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1 |
44582 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
44583 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
44584 | //BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2 |
44585 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
44586 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
44587 | //BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3 |
44588 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
44589 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
44590 | //BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4 |
44591 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
44592 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
44593 | //BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5 |
44594 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
44595 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
44596 | //BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6 |
44597 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
44598 | #define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
44599 | //BIF_CFG_DEV0_EPF5_1_ADAPTER_ID |
44600 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
44601 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
44602 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
44603 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
44604 | //BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR |
44605 | #define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
44606 | #define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
44607 | //BIF_CFG_DEV0_EPF5_1_CAP_PTR |
44608 | #define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
44609 | #define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
44610 | //BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE |
44611 | #define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
44612 | #define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
44613 | //BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN |
44614 | #define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
44615 | #define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
44616 | //BIF_CFG_DEV0_EPF5_1_MIN_GRANT |
44617 | #define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
44618 | #define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
44619 | //BIF_CFG_DEV0_EPF5_1_MAX_LATENCY |
44620 | #define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
44621 | #define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
44622 | //BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST |
44623 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
44624 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44625 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
44626 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
44627 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
44628 | #define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
44629 | //BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W |
44630 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
44631 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
44632 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
44633 | #define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
44634 | //BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST |
44635 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
44636 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44637 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
44638 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44639 | //BIF_CFG_DEV0_EPF5_1_PMI_CAP |
44640 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION__SHIFT 0x0 |
44641 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
44642 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
44643 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
44644 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
44645 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
44646 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
44647 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION_MASK 0x0007L |
44648 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
44649 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
44650 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
44651 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
44652 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
44653 | #define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
44654 | //BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL |
44655 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
44656 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
44657 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
44658 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
44659 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
44660 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
44661 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
44662 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
44663 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
44664 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
44665 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
44666 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
44667 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
44668 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
44669 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
44670 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
44671 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
44672 | #define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
44673 | //BIF_CFG_DEV0_EPF5_1_SBRN |
44674 | #define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN__SHIFT 0x0 |
44675 | #define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN_MASK 0xFFL |
44676 | //BIF_CFG_DEV0_EPF5_1_FLADJ |
44677 | #define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ__SHIFT 0x0 |
44678 | #define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ_MASK 0x3FL |
44679 | //BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD |
44680 | #define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
44681 | #define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
44682 | #define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
44683 | #define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
44684 | //BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST |
44685 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
44686 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44687 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
44688 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44689 | //BIF_CFG_DEV0_EPF5_1_PCIE_CAP |
44690 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION__SHIFT 0x0 |
44691 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
44692 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
44693 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
44694 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION_MASK 0x000FL |
44695 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
44696 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
44697 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
44698 | //BIF_CFG_DEV0_EPF5_1_DEVICE_CAP |
44699 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
44700 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
44701 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
44702 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
44703 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
44704 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
44705 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
44706 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
44707 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
44708 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
44709 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
44710 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
44711 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
44712 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
44713 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
44714 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
44715 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
44716 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
44717 | //BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL |
44718 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
44719 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
44720 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
44721 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
44722 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
44723 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
44724 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
44725 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
44726 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
44727 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
44728 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
44729 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
44730 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
44731 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
44732 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
44733 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
44734 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
44735 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
44736 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
44737 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
44738 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
44739 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
44740 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
44741 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
44742 | //BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS |
44743 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
44744 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
44745 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
44746 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
44747 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
44748 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
44749 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
44750 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
44751 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
44752 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
44753 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
44754 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
44755 | //BIF_CFG_DEV0_EPF5_1_LINK_CAP |
44756 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
44757 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
44758 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
44759 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
44760 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
44761 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
44762 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
44763 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
44764 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
44765 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
44766 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
44767 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
44768 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
44769 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
44770 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
44771 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
44772 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
44773 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
44774 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
44775 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
44776 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
44777 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
44778 | //BIF_CFG_DEV0_EPF5_1_LINK_CNTL |
44779 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
44780 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
44781 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
44782 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
44783 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
44784 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
44785 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
44786 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
44787 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
44788 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
44789 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
44790 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
44791 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
44792 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
44793 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
44794 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
44795 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
44796 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
44797 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
44798 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
44799 | //BIF_CFG_DEV0_EPF5_1_LINK_STATUS |
44800 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
44801 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
44802 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
44803 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
44804 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
44805 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
44806 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
44807 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
44808 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
44809 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
44810 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
44811 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
44812 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
44813 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
44814 | //BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2 |
44815 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
44816 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
44817 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
44818 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
44819 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
44820 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
44821 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
44822 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
44823 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
44824 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
44825 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
44826 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
44827 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
44828 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
44829 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
44830 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
44831 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
44832 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
44833 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
44834 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
44835 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
44836 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
44837 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
44838 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
44839 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
44840 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
44841 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
44842 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
44843 | //BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2 |
44844 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
44845 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
44846 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
44847 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
44848 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
44849 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
44850 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
44851 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
44852 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
44853 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
44854 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
44855 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
44856 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
44857 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
44858 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
44859 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
44860 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
44861 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
44862 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
44863 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
44864 | //BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2 |
44865 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
44866 | #define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
44867 | //BIF_CFG_DEV0_EPF5_1_LINK_CAP2 |
44868 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
44869 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
44870 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
44871 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
44872 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
44873 | #define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
44874 | //BIF_CFG_DEV0_EPF5_1_LINK_CNTL2 |
44875 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
44876 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
44877 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
44878 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
44879 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
44880 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
44881 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
44882 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
44883 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
44884 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
44885 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
44886 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
44887 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
44888 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
44889 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
44890 | #define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
44891 | //BIF_CFG_DEV0_EPF5_1_LINK_STATUS2 |
44892 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
44893 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
44894 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
44895 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
44896 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
44897 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
44898 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
44899 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
44900 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
44901 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
44902 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
44903 | #define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
44904 | //BIF_CFG_DEV0_EPF5_1_SLOT_CAP2 |
44905 | #define BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
44906 | #define BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
44907 | //BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2 |
44908 | #define BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
44909 | #define BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
44910 | //BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2 |
44911 | #define BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
44912 | #define BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
44913 | //BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST |
44914 | #define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
44915 | #define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44916 | #define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
44917 | #define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44918 | //BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL |
44919 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
44920 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
44921 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
44922 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
44923 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
44924 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
44925 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
44926 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
44927 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
44928 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
44929 | //BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO |
44930 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
44931 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
44932 | //BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI |
44933 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
44934 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
44935 | //BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA |
44936 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
44937 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
44938 | //BIF_CFG_DEV0_EPF5_1_MSI_MASK |
44939 | #define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
44940 | #define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
44941 | //BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64 |
44942 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
44943 | #define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
44944 | //BIF_CFG_DEV0_EPF5_1_MSI_MASK_64 |
44945 | #define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
44946 | #define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
44947 | //BIF_CFG_DEV0_EPF5_1_MSI_PENDING |
44948 | #define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
44949 | #define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
44950 | //BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64 |
44951 | #define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
44952 | #define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
44953 | //BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST |
44954 | #define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
44955 | #define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44956 | #define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
44957 | #define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44958 | //BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL |
44959 | #define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
44960 | #define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
44961 | #define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
44962 | #define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
44963 | #define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
44964 | #define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
44965 | //BIF_CFG_DEV0_EPF5_1_MSIX_TABLE |
44966 | #define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
44967 | #define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
44968 | #define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
44969 | #define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
44970 | //BIF_CFG_DEV0_EPF5_1_MSIX_PBA |
44971 | #define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
44972 | #define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
44973 | #define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
44974 | #define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
44975 | //BIF_CFG_DEV0_EPF5_1_SATA_CAP_0 |
44976 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
44977 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
44978 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
44979 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
44980 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
44981 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
44982 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
44983 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
44984 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
44985 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
44986 | //BIF_CFG_DEV0_EPF5_1_SATA_CAP_1 |
44987 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
44988 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
44989 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
44990 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
44991 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
44992 | #define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
44993 | //BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX |
44994 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
44995 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
44996 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
44997 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
44998 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
44999 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
45000 | //BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA |
45001 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
45002 | #define BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
45003 | //BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
45004 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45005 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45006 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45007 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45008 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45009 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45010 | //BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR |
45011 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
45012 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
45013 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
45014 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
45015 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
45016 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
45017 | //BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1 |
45018 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
45019 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
45020 | //BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2 |
45021 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
45022 | #define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
45023 | //BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
45024 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45025 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45026 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45027 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45028 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45029 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45030 | //BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS |
45031 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
45032 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
45033 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
45034 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
45035 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
45036 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
45037 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
45038 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
45039 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
45040 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
45041 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
45042 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
45043 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
45044 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
45045 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
45046 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
45047 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
45048 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
45049 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
45050 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
45051 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
45052 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
45053 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
45054 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
45055 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
45056 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
45057 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
45058 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
45059 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
45060 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
45061 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
45062 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
45063 | //BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK |
45064 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
45065 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
45066 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
45067 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
45068 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
45069 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
45070 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
45071 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
45072 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
45073 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
45074 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
45075 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
45076 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
45077 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
45078 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
45079 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
45080 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
45081 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
45082 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
45083 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
45084 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
45085 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
45086 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
45087 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
45088 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
45089 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
45090 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
45091 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
45092 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
45093 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
45094 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
45095 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
45096 | //BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY |
45097 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
45098 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
45099 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
45100 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
45101 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
45102 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
45103 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
45104 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
45105 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
45106 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
45107 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
45108 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
45109 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
45110 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
45111 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
45112 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
45113 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
45114 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
45115 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
45116 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
45117 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
45118 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
45119 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
45120 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
45121 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
45122 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
45123 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
45124 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
45125 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
45126 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
45127 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
45128 | #define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
45129 | //BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS |
45130 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
45131 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
45132 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
45133 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
45134 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
45135 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
45136 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
45137 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
45138 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
45139 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
45140 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
45141 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
45142 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
45143 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
45144 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
45145 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
45146 | //BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK |
45147 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
45148 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
45149 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
45150 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
45151 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
45152 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
45153 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
45154 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
45155 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
45156 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
45157 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
45158 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
45159 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
45160 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
45161 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
45162 | #define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
45163 | //BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL |
45164 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
45165 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
45166 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
45167 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
45168 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
45169 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
45170 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
45171 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
45172 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
45173 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
45174 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
45175 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
45176 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
45177 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
45178 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
45179 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
45180 | //BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0 |
45181 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
45182 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
45183 | //BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1 |
45184 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
45185 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
45186 | //BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2 |
45187 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
45188 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
45189 | //BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3 |
45190 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
45191 | #define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
45192 | //BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0 |
45193 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
45194 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
45195 | //BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1 |
45196 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
45197 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
45198 | //BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2 |
45199 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
45200 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
45201 | //BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3 |
45202 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
45203 | #define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
45204 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST |
45205 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45206 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45207 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45208 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45209 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45210 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45211 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP |
45212 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45213 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
45214 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL |
45215 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
45216 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45217 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
45218 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
45219 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
45220 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
45221 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP |
45222 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45223 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
45224 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL |
45225 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
45226 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45227 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
45228 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
45229 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
45230 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
45231 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP |
45232 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45233 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
45234 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL |
45235 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
45236 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45237 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
45238 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
45239 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
45240 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
45241 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP |
45242 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45243 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
45244 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL |
45245 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
45246 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45247 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
45248 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
45249 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
45250 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
45251 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP |
45252 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45253 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
45254 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL |
45255 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
45256 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45257 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
45258 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
45259 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
45260 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
45261 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP |
45262 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45263 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
45264 | //BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL |
45265 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
45266 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45267 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
45268 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
45269 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
45270 | #define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
45271 | //BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
45272 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45273 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45274 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45275 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45276 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45277 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45278 | //BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT |
45279 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
45280 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
45281 | //BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA |
45282 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
45283 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
45284 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
45285 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
45286 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
45287 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
45288 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
45289 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
45290 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
45291 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
45292 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
45293 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
45294 | //BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP |
45295 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
45296 | #define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
45297 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST |
45298 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45299 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45300 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45301 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45302 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45303 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45304 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP |
45305 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
45306 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
45307 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
45308 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
45309 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
45310 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
45311 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
45312 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
45313 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
45314 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
45315 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR |
45316 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
45317 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
45318 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS |
45319 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
45320 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
45321 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
45322 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
45323 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL |
45324 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
45325 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
45326 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
45327 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45328 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45329 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
45330 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45331 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45332 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
45333 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45334 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45335 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
45336 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45337 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45338 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
45339 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45340 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45341 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
45342 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45343 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45344 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
45345 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45346 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45347 | //BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
45348 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45349 | #define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45350 | //BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST |
45351 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45352 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45353 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45354 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45355 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45356 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45357 | //BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP |
45358 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
45359 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
45360 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
45361 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
45362 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
45363 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
45364 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
45365 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
45366 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
45367 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
45368 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
45369 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
45370 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
45371 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
45372 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
45373 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
45374 | //BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL |
45375 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
45376 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
45377 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
45378 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
45379 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
45380 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
45381 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
45382 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
45383 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
45384 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
45385 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
45386 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
45387 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
45388 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
45389 | //BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST |
45390 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45391 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45392 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45393 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45394 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45395 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45396 | //BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP |
45397 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
45398 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
45399 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
45400 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
45401 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
45402 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
45403 | //BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL |
45404 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
45405 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
45406 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
45407 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
45408 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
45409 | #define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
45410 | |
45411 | |
45412 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
45413 | //BIF_CFG_DEV0_EPF6_1_VENDOR_ID |
45414 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
45415 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
45416 | //BIF_CFG_DEV0_EPF6_1_DEVICE_ID |
45417 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
45418 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
45419 | //BIF_CFG_DEV0_EPF6_1_COMMAND |
45420 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
45421 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
45422 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
45423 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
45424 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
45425 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
45426 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
45427 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
45428 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN__SHIFT 0x8 |
45429 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
45430 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS__SHIFT 0xa |
45431 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
45432 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
45433 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
45434 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
45435 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
45436 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
45437 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
45438 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING_MASK 0x0080L |
45439 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN_MASK 0x0100L |
45440 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
45441 | #define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS_MASK 0x0400L |
45442 | //BIF_CFG_DEV0_EPF6_1_STATUS |
45443 | #define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS__SHIFT 0x3 |
45444 | #define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST__SHIFT 0x4 |
45445 | #define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN__SHIFT 0x5 |
45446 | #define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
45447 | #define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
45448 | #define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
45449 | #define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
45450 | #define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
45451 | #define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
45452 | #define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
45453 | #define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
45454 | #define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS_MASK 0x0008L |
45455 | #define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST_MASK 0x0010L |
45456 | #define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN_MASK 0x0020L |
45457 | #define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
45458 | #define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
45459 | #define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
45460 | #define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
45461 | #define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
45462 | #define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
45463 | #define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
45464 | #define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
45465 | //BIF_CFG_DEV0_EPF6_1_REVISION_ID |
45466 | #define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
45467 | #define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
45468 | #define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
45469 | #define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
45470 | //BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE |
45471 | #define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
45472 | #define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
45473 | //BIF_CFG_DEV0_EPF6_1_SUB_CLASS |
45474 | #define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
45475 | #define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
45476 | //BIF_CFG_DEV0_EPF6_1_BASE_CLASS |
45477 | #define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
45478 | #define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
45479 | //BIF_CFG_DEV0_EPF6_1_CACHE_LINE |
45480 | #define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
45481 | #define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
45482 | //BIF_CFG_DEV0_EPF6_1_LATENCY |
45483 | #define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
45484 | #define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
45485 | //BIF_CFG_DEV0_EPF6_1_HEADER |
45486 | #define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
45487 | #define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
45488 | #define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE_MASK 0x7FL |
45489 | #define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE_MASK 0x80L |
45490 | //BIF_CFG_DEV0_EPF6_1_BIST |
45491 | #define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP__SHIFT 0x0 |
45492 | #define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT__SHIFT 0x6 |
45493 | #define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP__SHIFT 0x7 |
45494 | #define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP_MASK 0x0FL |
45495 | #define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT_MASK 0x40L |
45496 | #define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP_MASK 0x80L |
45497 | //BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1 |
45498 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
45499 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
45500 | //BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2 |
45501 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
45502 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
45503 | //BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3 |
45504 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
45505 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
45506 | //BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4 |
45507 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
45508 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
45509 | //BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5 |
45510 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
45511 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
45512 | //BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6 |
45513 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
45514 | #define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
45515 | //BIF_CFG_DEV0_EPF6_1_ADAPTER_ID |
45516 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
45517 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
45518 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
45519 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
45520 | //BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR |
45521 | #define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
45522 | #define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
45523 | //BIF_CFG_DEV0_EPF6_1_CAP_PTR |
45524 | #define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
45525 | #define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
45526 | //BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE |
45527 | #define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
45528 | #define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
45529 | //BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN |
45530 | #define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
45531 | #define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
45532 | //BIF_CFG_DEV0_EPF6_1_MIN_GRANT |
45533 | #define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
45534 | #define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
45535 | //BIF_CFG_DEV0_EPF6_1_MAX_LATENCY |
45536 | #define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
45537 | #define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
45538 | //BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST |
45539 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
45540 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45541 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
45542 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
45543 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
45544 | #define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
45545 | //BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W |
45546 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
45547 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
45548 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
45549 | #define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
45550 | //BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST |
45551 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
45552 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45553 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
45554 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45555 | //BIF_CFG_DEV0_EPF6_1_PMI_CAP |
45556 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION__SHIFT 0x0 |
45557 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
45558 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
45559 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
45560 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
45561 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
45562 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
45563 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION_MASK 0x0007L |
45564 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
45565 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
45566 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
45567 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
45568 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
45569 | #define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
45570 | //BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL |
45571 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
45572 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
45573 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
45574 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
45575 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
45576 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
45577 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
45578 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
45579 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
45580 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
45581 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
45582 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
45583 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
45584 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
45585 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
45586 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
45587 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
45588 | #define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
45589 | //BIF_CFG_DEV0_EPF6_1_SBRN |
45590 | #define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN__SHIFT 0x0 |
45591 | #define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN_MASK 0xFFL |
45592 | //BIF_CFG_DEV0_EPF6_1_FLADJ |
45593 | #define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ__SHIFT 0x0 |
45594 | #define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ_MASK 0x3FL |
45595 | //BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD |
45596 | #define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
45597 | #define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
45598 | #define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
45599 | #define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
45600 | //BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST |
45601 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
45602 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45603 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
45604 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45605 | //BIF_CFG_DEV0_EPF6_1_PCIE_CAP |
45606 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION__SHIFT 0x0 |
45607 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
45608 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
45609 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
45610 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION_MASK 0x000FL |
45611 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
45612 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
45613 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
45614 | //BIF_CFG_DEV0_EPF6_1_DEVICE_CAP |
45615 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
45616 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
45617 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
45618 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
45619 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
45620 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
45621 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
45622 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
45623 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
45624 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
45625 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
45626 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
45627 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
45628 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
45629 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
45630 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
45631 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
45632 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
45633 | //BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL |
45634 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
45635 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
45636 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
45637 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
45638 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
45639 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
45640 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
45641 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
45642 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
45643 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
45644 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
45645 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
45646 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
45647 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
45648 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
45649 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
45650 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
45651 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
45652 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
45653 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
45654 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
45655 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
45656 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
45657 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
45658 | //BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS |
45659 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
45660 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
45661 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
45662 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
45663 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
45664 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
45665 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
45666 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
45667 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
45668 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
45669 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
45670 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
45671 | //BIF_CFG_DEV0_EPF6_1_LINK_CAP |
45672 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
45673 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
45674 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
45675 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
45676 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
45677 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
45678 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
45679 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
45680 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
45681 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
45682 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
45683 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
45684 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
45685 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
45686 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
45687 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
45688 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
45689 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
45690 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
45691 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
45692 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
45693 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
45694 | //BIF_CFG_DEV0_EPF6_1_LINK_CNTL |
45695 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
45696 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
45697 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
45698 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
45699 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
45700 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
45701 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
45702 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
45703 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
45704 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
45705 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
45706 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
45707 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
45708 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
45709 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
45710 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
45711 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
45712 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
45713 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
45714 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
45715 | //BIF_CFG_DEV0_EPF6_1_LINK_STATUS |
45716 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
45717 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
45718 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
45719 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
45720 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
45721 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
45722 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
45723 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
45724 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
45725 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
45726 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
45727 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
45728 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
45729 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
45730 | //BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2 |
45731 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
45732 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
45733 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
45734 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
45735 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
45736 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
45737 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
45738 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
45739 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
45740 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
45741 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
45742 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
45743 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
45744 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
45745 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
45746 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
45747 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
45748 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
45749 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
45750 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
45751 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
45752 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
45753 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
45754 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
45755 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
45756 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
45757 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
45758 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
45759 | //BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2 |
45760 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
45761 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
45762 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
45763 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
45764 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
45765 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
45766 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
45767 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
45768 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
45769 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
45770 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
45771 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
45772 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
45773 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
45774 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
45775 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
45776 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
45777 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
45778 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
45779 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
45780 | //BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2 |
45781 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
45782 | #define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
45783 | //BIF_CFG_DEV0_EPF6_1_LINK_CAP2 |
45784 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
45785 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
45786 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
45787 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
45788 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
45789 | #define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
45790 | //BIF_CFG_DEV0_EPF6_1_LINK_CNTL2 |
45791 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
45792 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
45793 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
45794 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
45795 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
45796 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
45797 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
45798 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
45799 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
45800 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
45801 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
45802 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
45803 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
45804 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
45805 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
45806 | #define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
45807 | //BIF_CFG_DEV0_EPF6_1_LINK_STATUS2 |
45808 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
45809 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
45810 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
45811 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
45812 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
45813 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
45814 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
45815 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
45816 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
45817 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
45818 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
45819 | #define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
45820 | //BIF_CFG_DEV0_EPF6_1_SLOT_CAP2 |
45821 | #define BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
45822 | #define BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
45823 | //BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2 |
45824 | #define BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
45825 | #define BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
45826 | //BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2 |
45827 | #define BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
45828 | #define BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
45829 | //BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST |
45830 | #define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
45831 | #define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45832 | #define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
45833 | #define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45834 | //BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL |
45835 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
45836 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
45837 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
45838 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
45839 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
45840 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
45841 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
45842 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
45843 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
45844 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
45845 | //BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO |
45846 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
45847 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
45848 | //BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI |
45849 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
45850 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
45851 | //BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA |
45852 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
45853 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
45854 | //BIF_CFG_DEV0_EPF6_1_MSI_MASK |
45855 | #define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
45856 | #define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
45857 | //BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64 |
45858 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
45859 | #define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
45860 | //BIF_CFG_DEV0_EPF6_1_MSI_MASK_64 |
45861 | #define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
45862 | #define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
45863 | //BIF_CFG_DEV0_EPF6_1_MSI_PENDING |
45864 | #define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
45865 | #define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
45866 | //BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64 |
45867 | #define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
45868 | #define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
45869 | //BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST |
45870 | #define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
45871 | #define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45872 | #define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
45873 | #define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45874 | //BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL |
45875 | #define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
45876 | #define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
45877 | #define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
45878 | #define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
45879 | #define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
45880 | #define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
45881 | //BIF_CFG_DEV0_EPF6_1_MSIX_TABLE |
45882 | #define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
45883 | #define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
45884 | #define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
45885 | #define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
45886 | //BIF_CFG_DEV0_EPF6_1_MSIX_PBA |
45887 | #define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
45888 | #define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
45889 | #define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
45890 | #define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
45891 | //BIF_CFG_DEV0_EPF6_1_SATA_CAP_0 |
45892 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
45893 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
45894 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
45895 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
45896 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
45897 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
45898 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
45899 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
45900 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
45901 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
45902 | //BIF_CFG_DEV0_EPF6_1_SATA_CAP_1 |
45903 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
45904 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
45905 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
45906 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
45907 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
45908 | #define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
45909 | //BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX |
45910 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
45911 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
45912 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
45913 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
45914 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
45915 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
45916 | //BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA |
45917 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
45918 | #define BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
45919 | //BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
45920 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45921 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45922 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45923 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45924 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45925 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45926 | //BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR |
45927 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
45928 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
45929 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
45930 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
45931 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
45932 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
45933 | //BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1 |
45934 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
45935 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
45936 | //BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2 |
45937 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
45938 | #define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
45939 | //BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
45940 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45941 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45942 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45943 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45944 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45945 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45946 | //BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS |
45947 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
45948 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
45949 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
45950 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
45951 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
45952 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
45953 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
45954 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
45955 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
45956 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
45957 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
45958 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
45959 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
45960 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
45961 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
45962 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
45963 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
45964 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
45965 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
45966 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
45967 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
45968 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
45969 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
45970 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
45971 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
45972 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
45973 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
45974 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
45975 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
45976 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
45977 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
45978 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
45979 | //BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK |
45980 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
45981 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
45982 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
45983 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
45984 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
45985 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
45986 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
45987 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
45988 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
45989 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
45990 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
45991 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
45992 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
45993 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
45994 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
45995 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
45996 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
45997 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
45998 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
45999 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
46000 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
46001 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
46002 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
46003 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
46004 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
46005 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
46006 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
46007 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
46008 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
46009 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
46010 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
46011 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
46012 | //BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY |
46013 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
46014 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
46015 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
46016 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
46017 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
46018 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
46019 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
46020 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
46021 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
46022 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
46023 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
46024 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
46025 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
46026 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
46027 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
46028 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
46029 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
46030 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
46031 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
46032 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
46033 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
46034 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
46035 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
46036 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
46037 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
46038 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
46039 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
46040 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
46041 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
46042 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
46043 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
46044 | #define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
46045 | //BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS |
46046 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
46047 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
46048 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
46049 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
46050 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
46051 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
46052 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
46053 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
46054 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
46055 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
46056 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
46057 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
46058 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
46059 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
46060 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
46061 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
46062 | //BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK |
46063 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
46064 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
46065 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
46066 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
46067 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
46068 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
46069 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
46070 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
46071 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
46072 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
46073 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
46074 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
46075 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
46076 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
46077 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
46078 | #define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
46079 | //BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL |
46080 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
46081 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
46082 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
46083 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
46084 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
46085 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
46086 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
46087 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
46088 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
46089 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
46090 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
46091 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
46092 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
46093 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
46094 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
46095 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
46096 | //BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0 |
46097 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
46098 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
46099 | //BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1 |
46100 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
46101 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
46102 | //BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2 |
46103 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
46104 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
46105 | //BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3 |
46106 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
46107 | #define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
46108 | //BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0 |
46109 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
46110 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
46111 | //BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1 |
46112 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
46113 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
46114 | //BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2 |
46115 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
46116 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
46117 | //BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3 |
46118 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
46119 | #define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
46120 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST |
46121 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46122 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46123 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46124 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46125 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46126 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46127 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP |
46128 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46129 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
46130 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL |
46131 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
46132 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46133 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
46134 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
46135 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
46136 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
46137 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP |
46138 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46139 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
46140 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL |
46141 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
46142 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46143 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
46144 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
46145 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
46146 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
46147 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP |
46148 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46149 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
46150 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL |
46151 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
46152 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46153 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
46154 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
46155 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
46156 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
46157 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP |
46158 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46159 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
46160 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL |
46161 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
46162 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46163 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
46164 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
46165 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
46166 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
46167 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP |
46168 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46169 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
46170 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL |
46171 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
46172 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46173 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
46174 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
46175 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
46176 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
46177 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP |
46178 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46179 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
46180 | //BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL |
46181 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
46182 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46183 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
46184 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
46185 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
46186 | #define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
46187 | //BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
46188 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46189 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46190 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46191 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46192 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46193 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46194 | //BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT |
46195 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
46196 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
46197 | //BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA |
46198 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
46199 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
46200 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
46201 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
46202 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
46203 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
46204 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
46205 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
46206 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
46207 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
46208 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
46209 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
46210 | //BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP |
46211 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
46212 | #define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
46213 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST |
46214 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46215 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46216 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46217 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46218 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46219 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46220 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP |
46221 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
46222 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
46223 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
46224 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
46225 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
46226 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
46227 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
46228 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
46229 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
46230 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
46231 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR |
46232 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
46233 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
46234 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS |
46235 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
46236 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
46237 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
46238 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
46239 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL |
46240 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
46241 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
46242 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
46243 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46244 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46245 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
46246 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46247 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46248 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
46249 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46250 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46251 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
46252 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46253 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46254 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
46255 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46256 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46257 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
46258 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46259 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46260 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
46261 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46262 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46263 | //BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
46264 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46265 | #define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46266 | //BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST |
46267 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46268 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46269 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46270 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46271 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46272 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46273 | //BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP |
46274 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
46275 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
46276 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
46277 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
46278 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
46279 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
46280 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
46281 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
46282 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
46283 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
46284 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
46285 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
46286 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
46287 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
46288 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
46289 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
46290 | //BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL |
46291 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
46292 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
46293 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
46294 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
46295 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
46296 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
46297 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
46298 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
46299 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
46300 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
46301 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
46302 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
46303 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
46304 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
46305 | //BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST |
46306 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46307 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46308 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46309 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46310 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46311 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46312 | //BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP |
46313 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
46314 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
46315 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
46316 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
46317 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
46318 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
46319 | //BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL |
46320 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
46321 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
46322 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
46323 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
46324 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
46325 | #define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
46326 | |
46327 | |
46328 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
46329 | //BIF_CFG_DEV0_EPF7_1_VENDOR_ID |
46330 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
46331 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
46332 | //BIF_CFG_DEV0_EPF7_1_DEVICE_ID |
46333 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
46334 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
46335 | //BIF_CFG_DEV0_EPF7_1_COMMAND |
46336 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
46337 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
46338 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
46339 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
46340 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
46341 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
46342 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
46343 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
46344 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN__SHIFT 0x8 |
46345 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
46346 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS__SHIFT 0xa |
46347 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
46348 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
46349 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
46350 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
46351 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
46352 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
46353 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
46354 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING_MASK 0x0080L |
46355 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN_MASK 0x0100L |
46356 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
46357 | #define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS_MASK 0x0400L |
46358 | //BIF_CFG_DEV0_EPF7_1_STATUS |
46359 | #define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS__SHIFT 0x3 |
46360 | #define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST__SHIFT 0x4 |
46361 | #define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN__SHIFT 0x5 |
46362 | #define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
46363 | #define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
46364 | #define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
46365 | #define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
46366 | #define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
46367 | #define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
46368 | #define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
46369 | #define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
46370 | #define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS_MASK 0x0008L |
46371 | #define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST_MASK 0x0010L |
46372 | #define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN_MASK 0x0020L |
46373 | #define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
46374 | #define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
46375 | #define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
46376 | #define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
46377 | #define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
46378 | #define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
46379 | #define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
46380 | #define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
46381 | //BIF_CFG_DEV0_EPF7_1_REVISION_ID |
46382 | #define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
46383 | #define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
46384 | #define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
46385 | #define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
46386 | //BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE |
46387 | #define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
46388 | #define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
46389 | //BIF_CFG_DEV0_EPF7_1_SUB_CLASS |
46390 | #define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
46391 | #define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
46392 | //BIF_CFG_DEV0_EPF7_1_BASE_CLASS |
46393 | #define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
46394 | #define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
46395 | //BIF_CFG_DEV0_EPF7_1_CACHE_LINE |
46396 | #define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
46397 | #define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
46398 | //BIF_CFG_DEV0_EPF7_1_LATENCY |
46399 | #define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
46400 | #define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
46401 | //BIF_CFG_DEV0_EPF7_1_HEADER |
46402 | #define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
46403 | #define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
46404 | #define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE_MASK 0x7FL |
46405 | #define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE_MASK 0x80L |
46406 | //BIF_CFG_DEV0_EPF7_1_BIST |
46407 | #define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP__SHIFT 0x0 |
46408 | #define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT__SHIFT 0x6 |
46409 | #define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP__SHIFT 0x7 |
46410 | #define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP_MASK 0x0FL |
46411 | #define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT_MASK 0x40L |
46412 | #define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP_MASK 0x80L |
46413 | //BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1 |
46414 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
46415 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
46416 | //BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2 |
46417 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
46418 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
46419 | //BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3 |
46420 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
46421 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
46422 | //BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4 |
46423 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
46424 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
46425 | //BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5 |
46426 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
46427 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
46428 | //BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6 |
46429 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
46430 | #define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
46431 | //BIF_CFG_DEV0_EPF7_1_ADAPTER_ID |
46432 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
46433 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
46434 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
46435 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
46436 | //BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR |
46437 | #define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
46438 | #define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
46439 | //BIF_CFG_DEV0_EPF7_1_CAP_PTR |
46440 | #define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
46441 | #define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
46442 | //BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE |
46443 | #define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
46444 | #define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
46445 | //BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN |
46446 | #define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
46447 | #define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
46448 | //BIF_CFG_DEV0_EPF7_1_MIN_GRANT |
46449 | #define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
46450 | #define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
46451 | //BIF_CFG_DEV0_EPF7_1_MAX_LATENCY |
46452 | #define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
46453 | #define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
46454 | //BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST |
46455 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
46456 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46457 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
46458 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
46459 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
46460 | #define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
46461 | //BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W |
46462 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
46463 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
46464 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
46465 | #define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
46466 | //BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST |
46467 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
46468 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46469 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
46470 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46471 | //BIF_CFG_DEV0_EPF7_1_PMI_CAP |
46472 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION__SHIFT 0x0 |
46473 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
46474 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
46475 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
46476 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
46477 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
46478 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
46479 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION_MASK 0x0007L |
46480 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
46481 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
46482 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
46483 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
46484 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
46485 | #define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
46486 | //BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL |
46487 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
46488 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
46489 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
46490 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
46491 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
46492 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
46493 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
46494 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
46495 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
46496 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
46497 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
46498 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
46499 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
46500 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
46501 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
46502 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
46503 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
46504 | #define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
46505 | //BIF_CFG_DEV0_EPF7_1_SBRN |
46506 | #define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN__SHIFT 0x0 |
46507 | #define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN_MASK 0xFFL |
46508 | //BIF_CFG_DEV0_EPF7_1_FLADJ |
46509 | #define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ__SHIFT 0x0 |
46510 | #define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ_MASK 0x3FL |
46511 | //BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD |
46512 | #define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
46513 | #define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
46514 | #define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
46515 | #define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
46516 | //BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST |
46517 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
46518 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46519 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
46520 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46521 | //BIF_CFG_DEV0_EPF7_1_PCIE_CAP |
46522 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION__SHIFT 0x0 |
46523 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
46524 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
46525 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
46526 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION_MASK 0x000FL |
46527 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
46528 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
46529 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
46530 | //BIF_CFG_DEV0_EPF7_1_DEVICE_CAP |
46531 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
46532 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
46533 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
46534 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
46535 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
46536 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
46537 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
46538 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
46539 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
46540 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
46541 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
46542 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
46543 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
46544 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
46545 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
46546 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
46547 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
46548 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
46549 | //BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL |
46550 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
46551 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
46552 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
46553 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
46554 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
46555 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
46556 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
46557 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
46558 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
46559 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
46560 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
46561 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
46562 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
46563 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
46564 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
46565 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
46566 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
46567 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
46568 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
46569 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
46570 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
46571 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
46572 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
46573 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
46574 | //BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS |
46575 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
46576 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
46577 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
46578 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
46579 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
46580 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
46581 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
46582 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
46583 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
46584 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
46585 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
46586 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
46587 | //BIF_CFG_DEV0_EPF7_1_LINK_CAP |
46588 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
46589 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
46590 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
46591 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
46592 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
46593 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
46594 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
46595 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
46596 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
46597 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
46598 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
46599 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
46600 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
46601 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
46602 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
46603 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
46604 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
46605 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
46606 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
46607 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
46608 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
46609 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
46610 | //BIF_CFG_DEV0_EPF7_1_LINK_CNTL |
46611 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
46612 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
46613 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
46614 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
46615 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
46616 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
46617 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
46618 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
46619 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
46620 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
46621 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
46622 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
46623 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
46624 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
46625 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
46626 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
46627 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
46628 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
46629 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
46630 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
46631 | //BIF_CFG_DEV0_EPF7_1_LINK_STATUS |
46632 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
46633 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
46634 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
46635 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
46636 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
46637 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
46638 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
46639 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
46640 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
46641 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
46642 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
46643 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
46644 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
46645 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
46646 | //BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2 |
46647 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
46648 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
46649 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
46650 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
46651 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
46652 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
46653 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
46654 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
46655 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
46656 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
46657 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
46658 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
46659 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
46660 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
46661 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
46662 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
46663 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
46664 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
46665 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
46666 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
46667 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
46668 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
46669 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
46670 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
46671 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
46672 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
46673 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
46674 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
46675 | //BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2 |
46676 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
46677 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
46678 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
46679 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
46680 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
46681 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
46682 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
46683 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
46684 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
46685 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
46686 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
46687 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
46688 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
46689 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
46690 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
46691 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
46692 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
46693 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
46694 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
46695 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
46696 | //BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2 |
46697 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
46698 | #define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
46699 | //BIF_CFG_DEV0_EPF7_1_LINK_CAP2 |
46700 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
46701 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
46702 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
46703 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
46704 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
46705 | #define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
46706 | //BIF_CFG_DEV0_EPF7_1_LINK_CNTL2 |
46707 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
46708 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
46709 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
46710 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
46711 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
46712 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
46713 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
46714 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
46715 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
46716 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
46717 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
46718 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
46719 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
46720 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
46721 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
46722 | #define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
46723 | //BIF_CFG_DEV0_EPF7_1_LINK_STATUS2 |
46724 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
46725 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
46726 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
46727 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
46728 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
46729 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
46730 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
46731 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
46732 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
46733 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
46734 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
46735 | #define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
46736 | //BIF_CFG_DEV0_EPF7_1_SLOT_CAP2 |
46737 | #define BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
46738 | #define BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
46739 | //BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2 |
46740 | #define BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
46741 | #define BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
46742 | //BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2 |
46743 | #define BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
46744 | #define BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
46745 | //BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST |
46746 | #define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
46747 | #define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46748 | #define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
46749 | #define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46750 | //BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL |
46751 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
46752 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
46753 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
46754 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
46755 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
46756 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
46757 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
46758 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
46759 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
46760 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
46761 | //BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO |
46762 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
46763 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
46764 | //BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI |
46765 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
46766 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
46767 | //BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA |
46768 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
46769 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
46770 | //BIF_CFG_DEV0_EPF7_1_MSI_MASK |
46771 | #define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
46772 | #define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
46773 | //BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64 |
46774 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
46775 | #define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
46776 | //BIF_CFG_DEV0_EPF7_1_MSI_MASK_64 |
46777 | #define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
46778 | #define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
46779 | //BIF_CFG_DEV0_EPF7_1_MSI_PENDING |
46780 | #define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
46781 | #define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
46782 | //BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64 |
46783 | #define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
46784 | #define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
46785 | //BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST |
46786 | #define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
46787 | #define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46788 | #define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
46789 | #define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46790 | //BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL |
46791 | #define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
46792 | #define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
46793 | #define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
46794 | #define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
46795 | #define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
46796 | #define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
46797 | //BIF_CFG_DEV0_EPF7_1_MSIX_TABLE |
46798 | #define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
46799 | #define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
46800 | #define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
46801 | #define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
46802 | //BIF_CFG_DEV0_EPF7_1_MSIX_PBA |
46803 | #define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
46804 | #define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
46805 | #define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
46806 | #define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
46807 | //BIF_CFG_DEV0_EPF7_1_SATA_CAP_0 |
46808 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
46809 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
46810 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
46811 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
46812 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
46813 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
46814 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
46815 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
46816 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
46817 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
46818 | //BIF_CFG_DEV0_EPF7_1_SATA_CAP_1 |
46819 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
46820 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
46821 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
46822 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
46823 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
46824 | #define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
46825 | //BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX |
46826 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
46827 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
46828 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
46829 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
46830 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
46831 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
46832 | //BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA |
46833 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
46834 | #define BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
46835 | //BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
46836 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46837 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46838 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46839 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46840 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46841 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46842 | //BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR |
46843 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
46844 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
46845 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
46846 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
46847 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
46848 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
46849 | //BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1 |
46850 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
46851 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
46852 | //BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2 |
46853 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
46854 | #define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
46855 | //BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
46856 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46857 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46858 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46859 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46860 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46861 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46862 | //BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS |
46863 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
46864 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
46865 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
46866 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
46867 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
46868 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
46869 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
46870 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
46871 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
46872 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
46873 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
46874 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
46875 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
46876 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
46877 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
46878 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
46879 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
46880 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
46881 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
46882 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
46883 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
46884 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
46885 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
46886 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
46887 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
46888 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
46889 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
46890 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
46891 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
46892 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
46893 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
46894 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
46895 | //BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK |
46896 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
46897 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
46898 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
46899 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
46900 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
46901 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
46902 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
46903 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
46904 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
46905 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
46906 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
46907 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
46908 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
46909 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
46910 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
46911 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
46912 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
46913 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
46914 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
46915 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
46916 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
46917 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
46918 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
46919 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
46920 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
46921 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
46922 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
46923 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
46924 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
46925 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
46926 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
46927 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
46928 | //BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY |
46929 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
46930 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
46931 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
46932 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
46933 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
46934 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
46935 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
46936 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
46937 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
46938 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
46939 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
46940 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
46941 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
46942 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
46943 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
46944 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
46945 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
46946 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
46947 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
46948 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
46949 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
46950 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
46951 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
46952 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
46953 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
46954 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
46955 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
46956 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
46957 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
46958 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
46959 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
46960 | #define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
46961 | //BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS |
46962 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
46963 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
46964 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
46965 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
46966 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
46967 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
46968 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
46969 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
46970 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
46971 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
46972 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
46973 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
46974 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
46975 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
46976 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
46977 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
46978 | //BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK |
46979 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
46980 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
46981 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
46982 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
46983 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
46984 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
46985 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
46986 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
46987 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
46988 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
46989 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
46990 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
46991 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
46992 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
46993 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
46994 | #define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
46995 | //BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL |
46996 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
46997 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
46998 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
46999 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
47000 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
47001 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
47002 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
47003 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
47004 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
47005 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
47006 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
47007 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
47008 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
47009 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
47010 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
47011 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
47012 | //BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0 |
47013 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
47014 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
47015 | //BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1 |
47016 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
47017 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
47018 | //BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2 |
47019 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
47020 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
47021 | //BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3 |
47022 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
47023 | #define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
47024 | //BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0 |
47025 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
47026 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
47027 | //BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1 |
47028 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
47029 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
47030 | //BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2 |
47031 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
47032 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
47033 | //BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3 |
47034 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
47035 | #define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
47036 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST |
47037 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47038 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47039 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47040 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47041 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47042 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47043 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP |
47044 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47045 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
47046 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL |
47047 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
47048 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47049 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
47050 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
47051 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
47052 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
47053 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP |
47054 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47055 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
47056 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL |
47057 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
47058 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47059 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
47060 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
47061 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
47062 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
47063 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP |
47064 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47065 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
47066 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL |
47067 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
47068 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47069 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
47070 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
47071 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
47072 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
47073 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP |
47074 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47075 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
47076 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL |
47077 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
47078 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47079 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
47080 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
47081 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
47082 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
47083 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP |
47084 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47085 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
47086 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL |
47087 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
47088 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47089 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
47090 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
47091 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
47092 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
47093 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP |
47094 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47095 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
47096 | //BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL |
47097 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
47098 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47099 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
47100 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
47101 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
47102 | #define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
47103 | //BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
47104 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47105 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47106 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47107 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47108 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47109 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47110 | //BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT |
47111 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
47112 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
47113 | //BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA |
47114 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
47115 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
47116 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
47117 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
47118 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
47119 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
47120 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
47121 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
47122 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
47123 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
47124 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
47125 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
47126 | //BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP |
47127 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
47128 | #define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
47129 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST |
47130 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47131 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47132 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47133 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47134 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47135 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47136 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP |
47137 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
47138 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
47139 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
47140 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
47141 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
47142 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
47143 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
47144 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
47145 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
47146 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
47147 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR |
47148 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
47149 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
47150 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS |
47151 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
47152 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
47153 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
47154 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
47155 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL |
47156 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
47157 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
47158 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
47159 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47160 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47161 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
47162 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47163 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47164 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
47165 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47166 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47167 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
47168 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47169 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47170 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
47171 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47172 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47173 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
47174 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47175 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47176 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
47177 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47178 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47179 | //BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
47180 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47181 | #define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47182 | //BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST |
47183 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47184 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47185 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47186 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47187 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47188 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47189 | //BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP |
47190 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
47191 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
47192 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
47193 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
47194 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
47195 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
47196 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
47197 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
47198 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
47199 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
47200 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
47201 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
47202 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
47203 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
47204 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
47205 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
47206 | //BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL |
47207 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
47208 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
47209 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
47210 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
47211 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
47212 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
47213 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
47214 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
47215 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
47216 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
47217 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
47218 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
47219 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
47220 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
47221 | //BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST |
47222 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47223 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47224 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47225 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47226 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47227 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47228 | //BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP |
47229 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
47230 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
47231 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
47232 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
47233 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
47234 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
47235 | //BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL |
47236 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
47237 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
47238 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
47239 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
47240 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
47241 | #define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
47242 | |
47243 | |
47244 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
47245 | //BIF_CFG_DEV1_EPF0_1_VENDOR_ID |
47246 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
47247 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
47248 | //BIF_CFG_DEV1_EPF0_1_DEVICE_ID |
47249 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
47250 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
47251 | //BIF_CFG_DEV1_EPF0_1_COMMAND |
47252 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
47253 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
47254 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
47255 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
47256 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
47257 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
47258 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
47259 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
47260 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8 |
47261 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
47262 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa |
47263 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
47264 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
47265 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
47266 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
47267 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
47268 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
47269 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
47270 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L |
47271 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L |
47272 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
47273 | #define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L |
47274 | //BIF_CFG_DEV1_EPF0_1_STATUS |
47275 | #define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3 |
47276 | #define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4 |
47277 | #define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN__SHIFT 0x5 |
47278 | #define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
47279 | #define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
47280 | #define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
47281 | #define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
47282 | #define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
47283 | #define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
47284 | #define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
47285 | #define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
47286 | #define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L |
47287 | #define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L |
47288 | #define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN_MASK 0x0020L |
47289 | #define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
47290 | #define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
47291 | #define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
47292 | #define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
47293 | #define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
47294 | #define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
47295 | #define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
47296 | #define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
47297 | //BIF_CFG_DEV1_EPF0_1_REVISION_ID |
47298 | #define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
47299 | #define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
47300 | #define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
47301 | #define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
47302 | //BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE |
47303 | #define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
47304 | #define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
47305 | //BIF_CFG_DEV1_EPF0_1_SUB_CLASS |
47306 | #define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
47307 | #define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
47308 | //BIF_CFG_DEV1_EPF0_1_BASE_CLASS |
47309 | #define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
47310 | #define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
47311 | //BIF_CFG_DEV1_EPF0_1_CACHE_LINE |
47312 | #define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
47313 | #define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
47314 | //BIF_CFG_DEV1_EPF0_1_LATENCY |
47315 | #define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
47316 | #define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
47317 | //BIF_CFG_DEV1_EPF0_1_HEADER |
47318 | #define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
47319 | #define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
47320 | #define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL |
47321 | #define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L |
47322 | //BIF_CFG_DEV1_EPF0_1_BIST |
47323 | #define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP__SHIFT 0x0 |
47324 | #define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT__SHIFT 0x6 |
47325 | #define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP__SHIFT 0x7 |
47326 | #define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP_MASK 0x0FL |
47327 | #define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT_MASK 0x40L |
47328 | #define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP_MASK 0x80L |
47329 | //BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1 |
47330 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
47331 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
47332 | //BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2 |
47333 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
47334 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
47335 | //BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3 |
47336 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
47337 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
47338 | //BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4 |
47339 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
47340 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
47341 | //BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5 |
47342 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
47343 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
47344 | //BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6 |
47345 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
47346 | #define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
47347 | //BIF_CFG_DEV1_EPF0_1_ADAPTER_ID |
47348 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
47349 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
47350 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
47351 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
47352 | //BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR |
47353 | #define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
47354 | #define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
47355 | //BIF_CFG_DEV1_EPF0_1_CAP_PTR |
47356 | #define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
47357 | #define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
47358 | //BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE |
47359 | #define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
47360 | #define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
47361 | //BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN |
47362 | #define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
47363 | #define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
47364 | //BIF_CFG_DEV1_EPF0_1_MIN_GRANT |
47365 | #define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
47366 | #define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
47367 | //BIF_CFG_DEV1_EPF0_1_MAX_LATENCY |
47368 | #define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
47369 | #define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
47370 | //BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST |
47371 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
47372 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47373 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
47374 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
47375 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
47376 | #define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
47377 | //BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W |
47378 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
47379 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
47380 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
47381 | #define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
47382 | //BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST |
47383 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
47384 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47385 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
47386 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47387 | //BIF_CFG_DEV1_EPF0_1_PMI_CAP |
47388 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0 |
47389 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
47390 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
47391 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
47392 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
47393 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
47394 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
47395 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L |
47396 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
47397 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
47398 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
47399 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
47400 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
47401 | #define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
47402 | //BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL |
47403 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
47404 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
47405 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
47406 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
47407 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
47408 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
47409 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
47410 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
47411 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
47412 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
47413 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
47414 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
47415 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
47416 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
47417 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
47418 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
47419 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
47420 | #define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
47421 | //BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST |
47422 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
47423 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47424 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
47425 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47426 | //BIF_CFG_DEV1_EPF0_1_PCIE_CAP |
47427 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0 |
47428 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
47429 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
47430 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
47431 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL |
47432 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
47433 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
47434 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
47435 | //BIF_CFG_DEV1_EPF0_1_DEVICE_CAP |
47436 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
47437 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
47438 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
47439 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
47440 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
47441 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
47442 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
47443 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
47444 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
47445 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
47446 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
47447 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
47448 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
47449 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
47450 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
47451 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
47452 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
47453 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
47454 | //BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL |
47455 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
47456 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
47457 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
47458 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
47459 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
47460 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
47461 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
47462 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
47463 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
47464 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
47465 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
47466 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
47467 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
47468 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
47469 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
47470 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
47471 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
47472 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
47473 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
47474 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
47475 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
47476 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
47477 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
47478 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
47479 | //BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS |
47480 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
47481 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
47482 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
47483 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
47484 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
47485 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
47486 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
47487 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
47488 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
47489 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
47490 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
47491 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
47492 | //BIF_CFG_DEV1_EPF0_1_LINK_CAP |
47493 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
47494 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
47495 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
47496 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
47497 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
47498 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
47499 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
47500 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
47501 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
47502 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
47503 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
47504 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
47505 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
47506 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
47507 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
47508 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
47509 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
47510 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
47511 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
47512 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
47513 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
47514 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
47515 | //BIF_CFG_DEV1_EPF0_1_LINK_CNTL |
47516 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
47517 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
47518 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
47519 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
47520 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
47521 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
47522 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
47523 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
47524 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
47525 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
47526 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
47527 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
47528 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
47529 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
47530 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
47531 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
47532 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
47533 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
47534 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
47535 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
47536 | //BIF_CFG_DEV1_EPF0_1_LINK_STATUS |
47537 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
47538 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
47539 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
47540 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
47541 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
47542 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
47543 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
47544 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
47545 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
47546 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
47547 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
47548 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
47549 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
47550 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
47551 | //BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2 |
47552 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
47553 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
47554 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
47555 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
47556 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
47557 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
47558 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
47559 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
47560 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
47561 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
47562 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
47563 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
47564 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
47565 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
47566 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
47567 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
47568 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
47569 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
47570 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
47571 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
47572 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
47573 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
47574 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
47575 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
47576 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
47577 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
47578 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
47579 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
47580 | //BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2 |
47581 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
47582 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
47583 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
47584 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
47585 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
47586 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
47587 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
47588 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
47589 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
47590 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
47591 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
47592 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
47593 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
47594 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
47595 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
47596 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
47597 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
47598 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
47599 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
47600 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
47601 | //BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2 |
47602 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
47603 | #define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
47604 | //BIF_CFG_DEV1_EPF0_1_LINK_CAP2 |
47605 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
47606 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
47607 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
47608 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
47609 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
47610 | #define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
47611 | //BIF_CFG_DEV1_EPF0_1_LINK_CNTL2 |
47612 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
47613 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
47614 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
47615 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
47616 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
47617 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
47618 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
47619 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
47620 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
47621 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
47622 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
47623 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
47624 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
47625 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
47626 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
47627 | #define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
47628 | //BIF_CFG_DEV1_EPF0_1_LINK_STATUS2 |
47629 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
47630 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
47631 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
47632 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
47633 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
47634 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
47635 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
47636 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
47637 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
47638 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
47639 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
47640 | #define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
47641 | //BIF_CFG_DEV1_EPF0_1_SLOT_CAP2 |
47642 | #define BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
47643 | #define BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
47644 | //BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2 |
47645 | #define BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
47646 | #define BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
47647 | //BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2 |
47648 | #define BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
47649 | #define BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
47650 | //BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST |
47651 | #define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
47652 | #define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47653 | #define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
47654 | #define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47655 | //BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL |
47656 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
47657 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
47658 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
47659 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
47660 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
47661 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
47662 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
47663 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
47664 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
47665 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
47666 | //BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO |
47667 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
47668 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
47669 | //BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI |
47670 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
47671 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
47672 | //BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA |
47673 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
47674 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
47675 | //BIF_CFG_DEV1_EPF0_1_MSI_MASK |
47676 | #define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
47677 | #define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
47678 | //BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64 |
47679 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
47680 | #define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
47681 | //BIF_CFG_DEV1_EPF0_1_MSI_MASK_64 |
47682 | #define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
47683 | #define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
47684 | //BIF_CFG_DEV1_EPF0_1_MSI_PENDING |
47685 | #define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
47686 | #define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
47687 | //BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64 |
47688 | #define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
47689 | #define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
47690 | //BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST |
47691 | #define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
47692 | #define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47693 | #define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
47694 | #define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47695 | //BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL |
47696 | #define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
47697 | #define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
47698 | #define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
47699 | #define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
47700 | #define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
47701 | #define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
47702 | //BIF_CFG_DEV1_EPF0_1_MSIX_TABLE |
47703 | #define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
47704 | #define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
47705 | #define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
47706 | #define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
47707 | //BIF_CFG_DEV1_EPF0_1_MSIX_PBA |
47708 | #define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
47709 | #define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
47710 | #define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
47711 | #define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
47712 | //BIF_CFG_DEV1_EPF0_1_SATA_CAP_0 |
47713 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
47714 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
47715 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
47716 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
47717 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
47718 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
47719 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
47720 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
47721 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
47722 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
47723 | //BIF_CFG_DEV1_EPF0_1_SATA_CAP_1 |
47724 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
47725 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
47726 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
47727 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
47728 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
47729 | #define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
47730 | //BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX |
47731 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
47732 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
47733 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
47734 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
47735 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
47736 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
47737 | //BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA |
47738 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
47739 | #define BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
47740 | //BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
47741 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47742 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47743 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47744 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47745 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47746 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47747 | //BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR |
47748 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
47749 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
47750 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
47751 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
47752 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
47753 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
47754 | //BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1 |
47755 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
47756 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
47757 | //BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2 |
47758 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
47759 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
47760 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST |
47761 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47762 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47763 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47764 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47765 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47766 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47767 | //BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1 |
47768 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
47769 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
47770 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
47771 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
47772 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
47773 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
47774 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
47775 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
47776 | //BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2 |
47777 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
47778 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
47779 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
47780 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
47781 | //BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL |
47782 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
47783 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
47784 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
47785 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
47786 | //BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS |
47787 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
47788 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
47789 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP |
47790 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
47791 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
47792 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
47793 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
47794 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
47795 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
47796 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
47797 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
47798 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL |
47799 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
47800 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
47801 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
47802 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
47803 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
47804 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
47805 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
47806 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
47807 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
47808 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
47809 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
47810 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
47811 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS |
47812 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
47813 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
47814 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
47815 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
47816 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP |
47817 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
47818 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
47819 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
47820 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
47821 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
47822 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
47823 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
47824 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
47825 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL |
47826 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
47827 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
47828 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
47829 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
47830 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
47831 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
47832 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
47833 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
47834 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
47835 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
47836 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
47837 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
47838 | //BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS |
47839 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
47840 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
47841 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
47842 | #define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
47843 | //BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
47844 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47845 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47846 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47847 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47848 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47849 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47850 | //BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS |
47851 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
47852 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
47853 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
47854 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
47855 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
47856 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
47857 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
47858 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
47859 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
47860 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
47861 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
47862 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
47863 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
47864 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
47865 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
47866 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
47867 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
47868 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
47869 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
47870 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
47871 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
47872 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
47873 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
47874 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
47875 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
47876 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
47877 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
47878 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
47879 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
47880 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
47881 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
47882 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
47883 | //BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK |
47884 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
47885 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
47886 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
47887 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
47888 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
47889 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
47890 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
47891 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
47892 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
47893 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
47894 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
47895 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
47896 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
47897 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
47898 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
47899 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
47900 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
47901 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
47902 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
47903 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
47904 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
47905 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
47906 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
47907 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
47908 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
47909 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
47910 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
47911 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
47912 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
47913 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
47914 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
47915 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
47916 | //BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY |
47917 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
47918 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
47919 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
47920 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
47921 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
47922 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
47923 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
47924 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
47925 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
47926 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
47927 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
47928 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
47929 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
47930 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
47931 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
47932 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
47933 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
47934 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
47935 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
47936 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
47937 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
47938 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
47939 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
47940 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
47941 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
47942 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
47943 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
47944 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
47945 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
47946 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
47947 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
47948 | #define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
47949 | //BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS |
47950 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
47951 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
47952 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
47953 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
47954 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
47955 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
47956 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
47957 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
47958 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
47959 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
47960 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
47961 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
47962 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
47963 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
47964 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
47965 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
47966 | //BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK |
47967 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
47968 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
47969 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
47970 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
47971 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
47972 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
47973 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
47974 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
47975 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
47976 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
47977 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
47978 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
47979 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
47980 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
47981 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
47982 | #define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
47983 | //BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL |
47984 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
47985 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
47986 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
47987 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
47988 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
47989 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
47990 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
47991 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
47992 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
47993 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
47994 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
47995 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
47996 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
47997 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
47998 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
47999 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
48000 | //BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0 |
48001 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
48002 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
48003 | //BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1 |
48004 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
48005 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
48006 | //BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2 |
48007 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
48008 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
48009 | //BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3 |
48010 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
48011 | #define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
48012 | //BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0 |
48013 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
48014 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
48015 | //BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1 |
48016 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
48017 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
48018 | //BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2 |
48019 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
48020 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
48021 | //BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3 |
48022 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
48023 | #define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
48024 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST |
48025 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48026 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48027 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48028 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48029 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48030 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48031 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP |
48032 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48033 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
48034 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL |
48035 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
48036 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48037 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
48038 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
48039 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
48040 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
48041 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP |
48042 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48043 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
48044 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL |
48045 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
48046 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48047 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
48048 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
48049 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
48050 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
48051 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP |
48052 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48053 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
48054 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL |
48055 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
48056 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48057 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
48058 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
48059 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
48060 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
48061 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP |
48062 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48063 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
48064 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL |
48065 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
48066 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48067 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
48068 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
48069 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
48070 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
48071 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP |
48072 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48073 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
48074 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL |
48075 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
48076 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48077 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
48078 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
48079 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
48080 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
48081 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP |
48082 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48083 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
48084 | //BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL |
48085 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
48086 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48087 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
48088 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
48089 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
48090 | #define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
48091 | //BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
48092 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48093 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48094 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48095 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48096 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48097 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48098 | //BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT |
48099 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
48100 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
48101 | //BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA |
48102 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
48103 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
48104 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
48105 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
48106 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
48107 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
48108 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
48109 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
48110 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
48111 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
48112 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
48113 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
48114 | //BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP |
48115 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
48116 | #define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
48117 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST |
48118 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48119 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48120 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48121 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48122 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48123 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48124 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP |
48125 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
48126 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
48127 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
48128 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
48129 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
48130 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
48131 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
48132 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
48133 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
48134 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
48135 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR |
48136 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
48137 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
48138 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS |
48139 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
48140 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
48141 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
48142 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
48143 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL |
48144 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
48145 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
48146 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
48147 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48148 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48149 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
48150 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48151 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48152 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
48153 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48154 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48155 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
48156 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48157 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48158 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
48159 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48160 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48161 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
48162 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48163 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48164 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
48165 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48166 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48167 | //BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
48168 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48169 | #define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48170 | //BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST |
48171 | #define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48172 | #define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48173 | #define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48174 | #define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48175 | #define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48176 | #define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48177 | //BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3 |
48178 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
48179 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
48180 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
48181 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
48182 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
48183 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
48184 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS |
48185 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
48186 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
48187 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
48188 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
48189 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL |
48190 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48191 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48192 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48193 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48194 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48195 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48196 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48197 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48198 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48199 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48200 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL |
48201 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48202 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48203 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48204 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48205 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48206 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48207 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48208 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48209 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48210 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48211 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL |
48212 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48213 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48214 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48215 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48216 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48217 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48218 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48219 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48220 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48221 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48222 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL |
48223 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48224 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48225 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48226 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48227 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48228 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48229 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48230 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48231 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48232 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48233 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL |
48234 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48235 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48236 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48237 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48238 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48239 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48240 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48241 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48242 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48243 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48244 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL |
48245 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48246 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48247 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48248 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48249 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48250 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48251 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48252 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48253 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48254 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48255 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL |
48256 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48257 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48258 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48259 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48260 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48261 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48262 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48263 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48264 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48265 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48266 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL |
48267 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48268 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48269 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48270 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48271 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48272 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48273 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48274 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48275 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48276 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48277 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL |
48278 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48279 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48280 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48281 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48282 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48283 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48284 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48285 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48286 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48287 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48288 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL |
48289 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48290 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48291 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48292 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48293 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48294 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48295 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48296 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48297 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48298 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48299 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL |
48300 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48301 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48302 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48303 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48304 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48305 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48306 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48307 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48308 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48309 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48310 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL |
48311 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48312 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48313 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48314 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48315 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48316 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48317 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48318 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48319 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48320 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48321 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL |
48322 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48323 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48324 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48325 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48326 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48327 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48328 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48329 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48330 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48331 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48332 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL |
48333 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48334 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48335 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48336 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48337 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48338 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48339 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48340 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48341 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48342 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48343 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL |
48344 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48345 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48346 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48347 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48348 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48349 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48350 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48351 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48352 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48353 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48354 | //BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL |
48355 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
48356 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
48357 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
48358 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
48359 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
48360 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
48361 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
48362 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
48363 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
48364 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
48365 | //BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST |
48366 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48367 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48368 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48369 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48370 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48371 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48372 | //BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP |
48373 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
48374 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
48375 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
48376 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
48377 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
48378 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
48379 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
48380 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
48381 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
48382 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
48383 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
48384 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
48385 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
48386 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
48387 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
48388 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
48389 | //BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL |
48390 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
48391 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
48392 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
48393 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
48394 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
48395 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
48396 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
48397 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
48398 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
48399 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
48400 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
48401 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
48402 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
48403 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
48404 | //BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST |
48405 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48406 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48407 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48408 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48409 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48410 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48411 | //BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP |
48412 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
48413 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
48414 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
48415 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
48416 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
48417 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
48418 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
48419 | #define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
48420 | //BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST |
48421 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48422 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48423 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48424 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48425 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48426 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48427 | //BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP |
48428 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
48429 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
48430 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
48431 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
48432 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
48433 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
48434 | //BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL |
48435 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
48436 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
48437 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
48438 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
48439 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
48440 | #define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
48441 | |
48442 | |
48443 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
48444 | //BIF_CFG_DEV1_EPF1_1_VENDOR_ID |
48445 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
48446 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
48447 | //BIF_CFG_DEV1_EPF1_1_DEVICE_ID |
48448 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
48449 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
48450 | //BIF_CFG_DEV1_EPF1_1_COMMAND |
48451 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
48452 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
48453 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
48454 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
48455 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
48456 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
48457 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
48458 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
48459 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8 |
48460 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
48461 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa |
48462 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
48463 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
48464 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
48465 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
48466 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
48467 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
48468 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
48469 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L |
48470 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L |
48471 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
48472 | #define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L |
48473 | //BIF_CFG_DEV1_EPF1_1_STATUS |
48474 | #define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3 |
48475 | #define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4 |
48476 | #define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5 |
48477 | #define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
48478 | #define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
48479 | #define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
48480 | #define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
48481 | #define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
48482 | #define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
48483 | #define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
48484 | #define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
48485 | #define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L |
48486 | #define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L |
48487 | #define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L |
48488 | #define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
48489 | #define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
48490 | #define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
48491 | #define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
48492 | #define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
48493 | #define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
48494 | #define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
48495 | #define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
48496 | //BIF_CFG_DEV1_EPF1_1_REVISION_ID |
48497 | #define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
48498 | #define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
48499 | #define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
48500 | #define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
48501 | //BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE |
48502 | #define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
48503 | #define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
48504 | //BIF_CFG_DEV1_EPF1_1_SUB_CLASS |
48505 | #define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
48506 | #define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
48507 | //BIF_CFG_DEV1_EPF1_1_BASE_CLASS |
48508 | #define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
48509 | #define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
48510 | //BIF_CFG_DEV1_EPF1_1_CACHE_LINE |
48511 | #define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
48512 | #define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
48513 | //BIF_CFG_DEV1_EPF1_1_LATENCY |
48514 | #define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
48515 | #define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
48516 | //BIF_CFG_DEV1_EPF1_1_HEADER |
48517 | #define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
48518 | #define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
48519 | #define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL |
48520 | #define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L |
48521 | //BIF_CFG_DEV1_EPF1_1_BIST |
48522 | #define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP__SHIFT 0x0 |
48523 | #define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT__SHIFT 0x6 |
48524 | #define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP__SHIFT 0x7 |
48525 | #define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP_MASK 0x0FL |
48526 | #define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT_MASK 0x40L |
48527 | #define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP_MASK 0x80L |
48528 | //BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1 |
48529 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
48530 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
48531 | //BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2 |
48532 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
48533 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
48534 | //BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3 |
48535 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
48536 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
48537 | //BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4 |
48538 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
48539 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
48540 | //BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5 |
48541 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
48542 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
48543 | //BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6 |
48544 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
48545 | #define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
48546 | //BIF_CFG_DEV1_EPF1_1_ADAPTER_ID |
48547 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
48548 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
48549 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
48550 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
48551 | //BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR |
48552 | #define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
48553 | #define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
48554 | //BIF_CFG_DEV1_EPF1_1_CAP_PTR |
48555 | #define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
48556 | #define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
48557 | //BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE |
48558 | #define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
48559 | #define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
48560 | //BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN |
48561 | #define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
48562 | #define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
48563 | //BIF_CFG_DEV1_EPF1_1_MIN_GRANT |
48564 | #define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
48565 | #define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
48566 | //BIF_CFG_DEV1_EPF1_1_MAX_LATENCY |
48567 | #define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
48568 | #define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
48569 | //BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST |
48570 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
48571 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48572 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
48573 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
48574 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
48575 | #define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
48576 | //BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W |
48577 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
48578 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
48579 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
48580 | #define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
48581 | //BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST |
48582 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
48583 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48584 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
48585 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48586 | //BIF_CFG_DEV1_EPF1_1_PMI_CAP |
48587 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0 |
48588 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
48589 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
48590 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
48591 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
48592 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
48593 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
48594 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L |
48595 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
48596 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
48597 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
48598 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
48599 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
48600 | #define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
48601 | //BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL |
48602 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
48603 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
48604 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
48605 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
48606 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
48607 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
48608 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
48609 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
48610 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
48611 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
48612 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
48613 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
48614 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
48615 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
48616 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
48617 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
48618 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
48619 | #define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
48620 | //BIF_CFG_DEV1_EPF1_1_SBRN |
48621 | #define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN__SHIFT 0x0 |
48622 | #define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN_MASK 0xFFL |
48623 | //BIF_CFG_DEV1_EPF1_1_FLADJ |
48624 | #define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ__SHIFT 0x0 |
48625 | #define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ_MASK 0x3FL |
48626 | //BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD |
48627 | #define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
48628 | #define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
48629 | #define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
48630 | #define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
48631 | //BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST |
48632 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
48633 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48634 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
48635 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48636 | //BIF_CFG_DEV1_EPF1_1_PCIE_CAP |
48637 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0 |
48638 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
48639 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
48640 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
48641 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL |
48642 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
48643 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
48644 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
48645 | //BIF_CFG_DEV1_EPF1_1_DEVICE_CAP |
48646 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
48647 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
48648 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
48649 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
48650 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
48651 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
48652 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
48653 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
48654 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
48655 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
48656 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
48657 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
48658 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
48659 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
48660 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
48661 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
48662 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
48663 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
48664 | //BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL |
48665 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
48666 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
48667 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
48668 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
48669 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
48670 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
48671 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
48672 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
48673 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
48674 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
48675 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
48676 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
48677 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
48678 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
48679 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
48680 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
48681 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
48682 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
48683 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
48684 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
48685 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
48686 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
48687 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
48688 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
48689 | //BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS |
48690 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
48691 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
48692 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
48693 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
48694 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
48695 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
48696 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
48697 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
48698 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
48699 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
48700 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
48701 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
48702 | //BIF_CFG_DEV1_EPF1_1_LINK_CAP |
48703 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
48704 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
48705 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
48706 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
48707 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
48708 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
48709 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
48710 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
48711 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
48712 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
48713 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
48714 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
48715 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
48716 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
48717 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
48718 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
48719 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
48720 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
48721 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
48722 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
48723 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
48724 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
48725 | //BIF_CFG_DEV1_EPF1_1_LINK_CNTL |
48726 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
48727 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
48728 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
48729 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
48730 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
48731 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
48732 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
48733 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
48734 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
48735 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
48736 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
48737 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
48738 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
48739 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
48740 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
48741 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
48742 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
48743 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
48744 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
48745 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
48746 | //BIF_CFG_DEV1_EPF1_1_LINK_STATUS |
48747 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
48748 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
48749 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
48750 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
48751 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
48752 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
48753 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
48754 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
48755 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
48756 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
48757 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
48758 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
48759 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
48760 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
48761 | //BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2 |
48762 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
48763 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
48764 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
48765 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
48766 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
48767 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
48768 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
48769 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
48770 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
48771 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
48772 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
48773 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
48774 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
48775 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
48776 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
48777 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
48778 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
48779 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
48780 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
48781 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
48782 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
48783 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
48784 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
48785 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
48786 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
48787 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
48788 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
48789 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
48790 | //BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2 |
48791 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
48792 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
48793 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
48794 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
48795 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
48796 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
48797 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
48798 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
48799 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
48800 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
48801 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
48802 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
48803 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
48804 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
48805 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
48806 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
48807 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
48808 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
48809 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
48810 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
48811 | //BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2 |
48812 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
48813 | #define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
48814 | //BIF_CFG_DEV1_EPF1_1_LINK_CAP2 |
48815 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
48816 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
48817 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
48818 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
48819 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
48820 | #define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
48821 | //BIF_CFG_DEV1_EPF1_1_LINK_CNTL2 |
48822 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
48823 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
48824 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
48825 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
48826 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
48827 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
48828 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
48829 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
48830 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
48831 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
48832 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
48833 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
48834 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
48835 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
48836 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
48837 | #define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
48838 | //BIF_CFG_DEV1_EPF1_1_LINK_STATUS2 |
48839 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
48840 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
48841 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
48842 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
48843 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
48844 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
48845 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
48846 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
48847 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
48848 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
48849 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
48850 | #define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
48851 | //BIF_CFG_DEV1_EPF1_1_SLOT_CAP2 |
48852 | #define BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
48853 | #define BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
48854 | //BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2 |
48855 | #define BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
48856 | #define BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
48857 | //BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2 |
48858 | #define BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
48859 | #define BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
48860 | //BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST |
48861 | #define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
48862 | #define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48863 | #define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
48864 | #define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48865 | //BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL |
48866 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
48867 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
48868 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
48869 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
48870 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
48871 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
48872 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
48873 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
48874 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
48875 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
48876 | //BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO |
48877 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
48878 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
48879 | //BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI |
48880 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
48881 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
48882 | //BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA |
48883 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
48884 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
48885 | //BIF_CFG_DEV1_EPF1_1_MSI_MASK |
48886 | #define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
48887 | #define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
48888 | //BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64 |
48889 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
48890 | #define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
48891 | //BIF_CFG_DEV1_EPF1_1_MSI_MASK_64 |
48892 | #define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
48893 | #define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
48894 | //BIF_CFG_DEV1_EPF1_1_MSI_PENDING |
48895 | #define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
48896 | #define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
48897 | //BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64 |
48898 | #define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
48899 | #define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
48900 | //BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST |
48901 | #define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
48902 | #define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48903 | #define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
48904 | #define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48905 | //BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL |
48906 | #define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
48907 | #define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
48908 | #define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
48909 | #define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
48910 | #define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
48911 | #define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
48912 | //BIF_CFG_DEV1_EPF1_1_MSIX_TABLE |
48913 | #define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
48914 | #define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
48915 | #define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
48916 | #define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
48917 | //BIF_CFG_DEV1_EPF1_1_MSIX_PBA |
48918 | #define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
48919 | #define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
48920 | #define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
48921 | #define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
48922 | //BIF_CFG_DEV1_EPF1_1_SATA_CAP_0 |
48923 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
48924 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
48925 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
48926 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
48927 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
48928 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
48929 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
48930 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
48931 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
48932 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
48933 | //BIF_CFG_DEV1_EPF1_1_SATA_CAP_1 |
48934 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
48935 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
48936 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
48937 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
48938 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
48939 | #define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
48940 | //BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX |
48941 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
48942 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
48943 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
48944 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
48945 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
48946 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
48947 | //BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA |
48948 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
48949 | #define BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
48950 | //BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
48951 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48952 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48953 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48954 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48955 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48956 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48957 | //BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR |
48958 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
48959 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
48960 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
48961 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
48962 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
48963 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
48964 | //BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1 |
48965 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
48966 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
48967 | //BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2 |
48968 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
48969 | #define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
48970 | //BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
48971 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48972 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48973 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48974 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48975 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48976 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48977 | //BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS |
48978 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
48979 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
48980 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
48981 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
48982 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
48983 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
48984 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
48985 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
48986 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
48987 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
48988 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
48989 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
48990 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
48991 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
48992 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
48993 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
48994 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
48995 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
48996 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
48997 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
48998 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
48999 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
49000 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
49001 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
49002 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
49003 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
49004 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
49005 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
49006 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
49007 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
49008 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
49009 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
49010 | //BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK |
49011 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
49012 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
49013 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
49014 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
49015 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
49016 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
49017 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
49018 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
49019 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
49020 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
49021 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
49022 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
49023 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
49024 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
49025 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
49026 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
49027 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
49028 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
49029 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
49030 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
49031 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
49032 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
49033 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
49034 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
49035 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
49036 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
49037 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
49038 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
49039 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
49040 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
49041 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
49042 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
49043 | //BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY |
49044 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
49045 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
49046 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
49047 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
49048 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
49049 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
49050 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
49051 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
49052 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
49053 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
49054 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
49055 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
49056 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
49057 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
49058 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
49059 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
49060 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
49061 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
49062 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
49063 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
49064 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
49065 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
49066 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
49067 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
49068 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
49069 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
49070 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
49071 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
49072 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
49073 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
49074 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
49075 | #define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
49076 | //BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS |
49077 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
49078 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
49079 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
49080 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
49081 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
49082 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
49083 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
49084 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
49085 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
49086 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
49087 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
49088 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
49089 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
49090 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
49091 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
49092 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
49093 | //BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK |
49094 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
49095 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
49096 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
49097 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
49098 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
49099 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
49100 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
49101 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
49102 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
49103 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
49104 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
49105 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
49106 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
49107 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
49108 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
49109 | #define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
49110 | //BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL |
49111 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
49112 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
49113 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
49114 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
49115 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
49116 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
49117 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
49118 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
49119 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
49120 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
49121 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
49122 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
49123 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
49124 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
49125 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
49126 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
49127 | //BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0 |
49128 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
49129 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
49130 | //BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1 |
49131 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
49132 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
49133 | //BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2 |
49134 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
49135 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
49136 | //BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3 |
49137 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
49138 | #define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
49139 | //BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0 |
49140 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
49141 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
49142 | //BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1 |
49143 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
49144 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
49145 | //BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2 |
49146 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
49147 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
49148 | //BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3 |
49149 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
49150 | #define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
49151 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST |
49152 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49153 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49154 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49155 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49156 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49157 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49158 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP |
49159 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49160 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
49161 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL |
49162 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
49163 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49164 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
49165 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
49166 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
49167 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
49168 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP |
49169 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49170 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
49171 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL |
49172 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
49173 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49174 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
49175 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
49176 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
49177 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
49178 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP |
49179 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49180 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
49181 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL |
49182 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
49183 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49184 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
49185 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
49186 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
49187 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
49188 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP |
49189 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49190 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
49191 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL |
49192 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
49193 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49194 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
49195 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
49196 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
49197 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
49198 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP |
49199 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49200 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
49201 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL |
49202 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
49203 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49204 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
49205 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
49206 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
49207 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
49208 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP |
49209 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49210 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
49211 | //BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL |
49212 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
49213 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49214 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
49215 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
49216 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
49217 | #define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
49218 | //BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
49219 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49220 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49221 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49222 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49223 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49224 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49225 | //BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT |
49226 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
49227 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
49228 | //BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA |
49229 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
49230 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
49231 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
49232 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
49233 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
49234 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
49235 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
49236 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
49237 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
49238 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
49239 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
49240 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
49241 | //BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP |
49242 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
49243 | #define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
49244 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST |
49245 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49246 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49247 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49248 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49249 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49250 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49251 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP |
49252 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
49253 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
49254 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
49255 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
49256 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
49257 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
49258 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
49259 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
49260 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
49261 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
49262 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR |
49263 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
49264 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
49265 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS |
49266 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
49267 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
49268 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
49269 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
49270 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL |
49271 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
49272 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
49273 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
49274 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49275 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49276 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
49277 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49278 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49279 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
49280 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49281 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49282 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
49283 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49284 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49285 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
49286 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49287 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49288 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
49289 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49290 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49291 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
49292 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49293 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49294 | //BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
49295 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49296 | #define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49297 | //BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST |
49298 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49299 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49300 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49301 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49302 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49303 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49304 | //BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP |
49305 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
49306 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
49307 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
49308 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
49309 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
49310 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
49311 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
49312 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
49313 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
49314 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
49315 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
49316 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
49317 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
49318 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
49319 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
49320 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
49321 | //BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL |
49322 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
49323 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
49324 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
49325 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
49326 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
49327 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
49328 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
49329 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
49330 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
49331 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
49332 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
49333 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
49334 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
49335 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
49336 | //BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST |
49337 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49338 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49339 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49340 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49341 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49342 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49343 | //BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP |
49344 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
49345 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
49346 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
49347 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
49348 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
49349 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
49350 | //BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL |
49351 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
49352 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
49353 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
49354 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
49355 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
49356 | #define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
49357 | |
49358 | |
49359 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
49360 | //BIF_CFG_DEV1_EPF2_1_VENDOR_ID |
49361 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
49362 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
49363 | //BIF_CFG_DEV1_EPF2_1_DEVICE_ID |
49364 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
49365 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
49366 | //BIF_CFG_DEV1_EPF2_1_COMMAND |
49367 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
49368 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
49369 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
49370 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
49371 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
49372 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
49373 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
49374 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
49375 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8 |
49376 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
49377 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa |
49378 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
49379 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
49380 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
49381 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
49382 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
49383 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
49384 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
49385 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L |
49386 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L |
49387 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
49388 | #define BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L |
49389 | //BIF_CFG_DEV1_EPF2_1_STATUS |
49390 | #define BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3 |
49391 | #define BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4 |
49392 | #define BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN__SHIFT 0x5 |
49393 | #define BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
49394 | #define BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
49395 | #define BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
49396 | #define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
49397 | #define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
49398 | #define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
49399 | #define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
49400 | #define BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
49401 | #define BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L |
49402 | #define BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L |
49403 | #define BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN_MASK 0x0020L |
49404 | #define BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
49405 | #define BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
49406 | #define BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
49407 | #define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
49408 | #define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
49409 | #define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
49410 | #define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
49411 | #define BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
49412 | //BIF_CFG_DEV1_EPF2_1_REVISION_ID |
49413 | #define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
49414 | #define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
49415 | #define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
49416 | #define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
49417 | //BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE |
49418 | #define BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
49419 | #define BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
49420 | //BIF_CFG_DEV1_EPF2_1_SUB_CLASS |
49421 | #define BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
49422 | #define BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
49423 | //BIF_CFG_DEV1_EPF2_1_BASE_CLASS |
49424 | #define BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
49425 | #define BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
49426 | //BIF_CFG_DEV1_EPF2_1_CACHE_LINE |
49427 | #define BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
49428 | #define BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
49429 | //BIF_CFG_DEV1_EPF2_1_LATENCY |
49430 | #define BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
49431 | #define BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
49432 | //BIF_CFG_DEV1_EPF2_1_HEADER |
49433 | #define BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
49434 | #define BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
49435 | #define BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL |
49436 | #define BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L |
49437 | //BIF_CFG_DEV1_EPF2_1_BIST |
49438 | #define BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP__SHIFT 0x0 |
49439 | #define BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT__SHIFT 0x6 |
49440 | #define BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP__SHIFT 0x7 |
49441 | #define BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP_MASK 0x0FL |
49442 | #define BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT_MASK 0x40L |
49443 | #define BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP_MASK 0x80L |
49444 | //BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1 |
49445 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
49446 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
49447 | //BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2 |
49448 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
49449 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
49450 | //BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3 |
49451 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
49452 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
49453 | //BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4 |
49454 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
49455 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
49456 | //BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5 |
49457 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
49458 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
49459 | //BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6 |
49460 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
49461 | #define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
49462 | //BIF_CFG_DEV1_EPF2_1_ADAPTER_ID |
49463 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
49464 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
49465 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
49466 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
49467 | //BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR |
49468 | #define BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
49469 | #define BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
49470 | //BIF_CFG_DEV1_EPF2_1_CAP_PTR |
49471 | #define BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
49472 | #define BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
49473 | //BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE |
49474 | #define BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
49475 | #define BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
49476 | //BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN |
49477 | #define BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
49478 | #define BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
49479 | //BIF_CFG_DEV1_EPF2_1_MIN_GRANT |
49480 | #define BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
49481 | #define BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
49482 | //BIF_CFG_DEV1_EPF2_1_MAX_LATENCY |
49483 | #define BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
49484 | #define BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
49485 | //BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST |
49486 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
49487 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49488 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
49489 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
49490 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
49491 | #define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
49492 | //BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W |
49493 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
49494 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
49495 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
49496 | #define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
49497 | //BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST |
49498 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
49499 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49500 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
49501 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49502 | //BIF_CFG_DEV1_EPF2_1_PMI_CAP |
49503 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0 |
49504 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
49505 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
49506 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
49507 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
49508 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
49509 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
49510 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L |
49511 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
49512 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
49513 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
49514 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
49515 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
49516 | #define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
49517 | //BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL |
49518 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
49519 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
49520 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
49521 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
49522 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
49523 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
49524 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
49525 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
49526 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
49527 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
49528 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
49529 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
49530 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
49531 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
49532 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
49533 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
49534 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
49535 | #define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
49536 | //BIF_CFG_DEV1_EPF2_1_SBRN |
49537 | #define BIF_CFG_DEV1_EPF2_1_SBRN__SBRN__SHIFT 0x0 |
49538 | #define BIF_CFG_DEV1_EPF2_1_SBRN__SBRN_MASK 0xFFL |
49539 | //BIF_CFG_DEV1_EPF2_1_FLADJ |
49540 | #define BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ__SHIFT 0x0 |
49541 | #define BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ_MASK 0x3FL |
49542 | //BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD |
49543 | #define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
49544 | #define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
49545 | #define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
49546 | #define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
49547 | //BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST |
49548 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
49549 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49550 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
49551 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49552 | //BIF_CFG_DEV1_EPF2_1_PCIE_CAP |
49553 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0 |
49554 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
49555 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
49556 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
49557 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL |
49558 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
49559 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
49560 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
49561 | //BIF_CFG_DEV1_EPF2_1_DEVICE_CAP |
49562 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
49563 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
49564 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
49565 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
49566 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
49567 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
49568 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
49569 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
49570 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
49571 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
49572 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
49573 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
49574 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
49575 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
49576 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
49577 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
49578 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
49579 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
49580 | //BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL |
49581 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
49582 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
49583 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
49584 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
49585 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
49586 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
49587 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
49588 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
49589 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
49590 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
49591 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
49592 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
49593 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
49594 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
49595 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
49596 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
49597 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
49598 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
49599 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
49600 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
49601 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
49602 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
49603 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
49604 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
49605 | //BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS |
49606 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
49607 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
49608 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
49609 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
49610 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
49611 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
49612 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
49613 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
49614 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
49615 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
49616 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
49617 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
49618 | //BIF_CFG_DEV1_EPF2_1_LINK_CAP |
49619 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
49620 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
49621 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
49622 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
49623 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
49624 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
49625 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
49626 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
49627 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
49628 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
49629 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
49630 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
49631 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
49632 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
49633 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
49634 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
49635 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
49636 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
49637 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
49638 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
49639 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
49640 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
49641 | //BIF_CFG_DEV1_EPF2_1_LINK_CNTL |
49642 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
49643 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
49644 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
49645 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
49646 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
49647 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
49648 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
49649 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
49650 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
49651 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
49652 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
49653 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
49654 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
49655 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
49656 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
49657 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
49658 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
49659 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
49660 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
49661 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
49662 | //BIF_CFG_DEV1_EPF2_1_LINK_STATUS |
49663 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
49664 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
49665 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
49666 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
49667 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
49668 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
49669 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
49670 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
49671 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
49672 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
49673 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
49674 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
49675 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
49676 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
49677 | //BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2 |
49678 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
49679 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
49680 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
49681 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
49682 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
49683 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
49684 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
49685 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
49686 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
49687 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
49688 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
49689 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
49690 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
49691 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
49692 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
49693 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
49694 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
49695 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
49696 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
49697 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
49698 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
49699 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
49700 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
49701 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
49702 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
49703 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
49704 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
49705 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
49706 | //BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2 |
49707 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
49708 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
49709 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
49710 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
49711 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
49712 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
49713 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
49714 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
49715 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
49716 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
49717 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
49718 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
49719 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
49720 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
49721 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
49722 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
49723 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
49724 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
49725 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
49726 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
49727 | //BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2 |
49728 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
49729 | #define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
49730 | //BIF_CFG_DEV1_EPF2_1_LINK_CAP2 |
49731 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
49732 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
49733 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED__SHIFT 0x9 |
49734 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
49735 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
49736 | #define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
49737 | //BIF_CFG_DEV1_EPF2_1_LINK_CNTL2 |
49738 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
49739 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
49740 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
49741 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
49742 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
49743 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
49744 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
49745 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
49746 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
49747 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
49748 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
49749 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
49750 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
49751 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
49752 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
49753 | #define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
49754 | //BIF_CFG_DEV1_EPF2_1_LINK_STATUS2 |
49755 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
49756 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
49757 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
49758 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
49759 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
49760 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
49761 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
49762 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
49763 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
49764 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
49765 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
49766 | #define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
49767 | //BIF_CFG_DEV1_EPF2_1_SLOT_CAP2 |
49768 | #define BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
49769 | #define BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
49770 | //BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2 |
49771 | #define BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
49772 | #define BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
49773 | //BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2 |
49774 | #define BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
49775 | #define BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
49776 | //BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST |
49777 | #define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
49778 | #define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49779 | #define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
49780 | #define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49781 | //BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL |
49782 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
49783 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
49784 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
49785 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
49786 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
49787 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
49788 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
49789 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
49790 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
49791 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
49792 | //BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO |
49793 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
49794 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
49795 | //BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI |
49796 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
49797 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
49798 | //BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA |
49799 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
49800 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
49801 | //BIF_CFG_DEV1_EPF2_1_MSI_MASK |
49802 | #define BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
49803 | #define BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
49804 | //BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64 |
49805 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
49806 | #define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
49807 | //BIF_CFG_DEV1_EPF2_1_MSI_MASK_64 |
49808 | #define BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
49809 | #define BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
49810 | //BIF_CFG_DEV1_EPF2_1_MSI_PENDING |
49811 | #define BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
49812 | #define BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
49813 | //BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64 |
49814 | #define BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
49815 | #define BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
49816 | //BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST |
49817 | #define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
49818 | #define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49819 | #define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
49820 | #define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49821 | //BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL |
49822 | #define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
49823 | #define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
49824 | #define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
49825 | #define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
49826 | #define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
49827 | #define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
49828 | //BIF_CFG_DEV1_EPF2_1_MSIX_TABLE |
49829 | #define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
49830 | #define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
49831 | #define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
49832 | #define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
49833 | //BIF_CFG_DEV1_EPF2_1_MSIX_PBA |
49834 | #define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
49835 | #define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
49836 | #define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
49837 | #define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
49838 | //BIF_CFG_DEV1_EPF2_1_SATA_CAP_0 |
49839 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
49840 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
49841 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
49842 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
49843 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
49844 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
49845 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
49846 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
49847 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
49848 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
49849 | //BIF_CFG_DEV1_EPF2_1_SATA_CAP_1 |
49850 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
49851 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
49852 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
49853 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
49854 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
49855 | #define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
49856 | //BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX |
49857 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
49858 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
49859 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
49860 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
49861 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
49862 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
49863 | //BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA |
49864 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
49865 | #define BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
49866 | //BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
49867 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49868 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49869 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49870 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49871 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49872 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49873 | //BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR |
49874 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
49875 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
49876 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
49877 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
49878 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
49879 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
49880 | //BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1 |
49881 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
49882 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
49883 | //BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2 |
49884 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
49885 | #define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
49886 | //BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
49887 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49888 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49889 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49890 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49891 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49892 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49893 | //BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS |
49894 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
49895 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
49896 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
49897 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
49898 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
49899 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
49900 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
49901 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
49902 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
49903 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
49904 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
49905 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
49906 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
49907 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
49908 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
49909 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
49910 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
49911 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
49912 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
49913 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
49914 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
49915 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
49916 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
49917 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
49918 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
49919 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
49920 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
49921 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
49922 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
49923 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
49924 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
49925 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
49926 | //BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK |
49927 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
49928 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
49929 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
49930 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
49931 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
49932 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
49933 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
49934 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
49935 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
49936 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
49937 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
49938 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
49939 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
49940 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
49941 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
49942 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
49943 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
49944 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
49945 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
49946 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
49947 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
49948 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
49949 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
49950 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
49951 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
49952 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
49953 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
49954 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
49955 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
49956 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
49957 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
49958 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
49959 | //BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY |
49960 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
49961 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
49962 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
49963 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
49964 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
49965 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
49966 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
49967 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
49968 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
49969 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
49970 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
49971 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
49972 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
49973 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
49974 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
49975 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
49976 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
49977 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
49978 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
49979 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
49980 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
49981 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
49982 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
49983 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
49984 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
49985 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
49986 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
49987 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
49988 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
49989 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
49990 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
49991 | #define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
49992 | //BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS |
49993 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
49994 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
49995 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
49996 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
49997 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
49998 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
49999 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
50000 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
50001 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
50002 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
50003 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
50004 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
50005 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
50006 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
50007 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
50008 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
50009 | //BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK |
50010 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
50011 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
50012 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
50013 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
50014 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
50015 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
50016 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
50017 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
50018 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
50019 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
50020 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
50021 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
50022 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
50023 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
50024 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
50025 | #define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
50026 | //BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL |
50027 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
50028 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
50029 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
50030 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
50031 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
50032 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
50033 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
50034 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
50035 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
50036 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
50037 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
50038 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
50039 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
50040 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
50041 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
50042 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
50043 | //BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0 |
50044 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
50045 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
50046 | //BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1 |
50047 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
50048 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
50049 | //BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2 |
50050 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
50051 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
50052 | //BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3 |
50053 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
50054 | #define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
50055 | //BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0 |
50056 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
50057 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
50058 | //BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1 |
50059 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
50060 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
50061 | //BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2 |
50062 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
50063 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
50064 | //BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3 |
50065 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
50066 | #define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
50067 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST |
50068 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
50069 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
50070 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
50071 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
50072 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
50073 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
50074 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP |
50075 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
50076 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
50077 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL |
50078 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
50079 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
50080 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
50081 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
50082 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
50083 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
50084 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP |
50085 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
50086 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
50087 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL |
50088 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
50089 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
50090 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
50091 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
50092 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
50093 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
50094 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP |
50095 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
50096 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
50097 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL |
50098 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
50099 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
50100 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
50101 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
50102 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
50103 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
50104 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP |
50105 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
50106 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
50107 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL |
50108 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
50109 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
50110 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
50111 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
50112 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
50113 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
50114 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP |
50115 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
50116 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
50117 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL |
50118 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
50119 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
50120 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
50121 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
50122 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
50123 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
50124 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP |
50125 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
50126 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
50127 | //BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL |
50128 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
50129 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
50130 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
50131 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
50132 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
50133 | #define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
50134 | //BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
50135 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
50136 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
50137 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
50138 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
50139 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
50140 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
50141 | //BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT |
50142 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
50143 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
50144 | //BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA |
50145 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
50146 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
50147 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
50148 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
50149 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
50150 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
50151 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
50152 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
50153 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
50154 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
50155 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
50156 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
50157 | //BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP |
50158 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
50159 | #define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
50160 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST |
50161 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
50162 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
50163 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
50164 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
50165 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
50166 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
50167 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP |
50168 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
50169 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
50170 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
50171 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
50172 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
50173 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
50174 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
50175 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
50176 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
50177 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
50178 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR |
50179 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
50180 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
50181 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS |
50182 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
50183 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
50184 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
50185 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
50186 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL |
50187 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
50188 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
50189 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
50190 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50191 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50192 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
50193 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50194 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50195 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
50196 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50197 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50198 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
50199 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50200 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50201 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
50202 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50203 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50204 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
50205 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50206 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50207 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
50208 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50209 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50210 | //BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
50211 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50212 | #define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50213 | //BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST |
50214 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
50215 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
50216 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
50217 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
50218 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
50219 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
50220 | //BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP |
50221 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
50222 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
50223 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
50224 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
50225 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
50226 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
50227 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
50228 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
50229 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
50230 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
50231 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
50232 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
50233 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
50234 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
50235 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
50236 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
50237 | //BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL |
50238 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
50239 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
50240 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
50241 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
50242 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
50243 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
50244 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
50245 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
50246 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
50247 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
50248 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
50249 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
50250 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
50251 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
50252 | //BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST |
50253 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
50254 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
50255 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
50256 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
50257 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
50258 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
50259 | //BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP |
50260 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
50261 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
50262 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
50263 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
50264 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
50265 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
50266 | //BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL |
50267 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
50268 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
50269 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
50270 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
50271 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
50272 | #define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
50273 | |
50274 | |
50275 | // addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXTDEC |
50276 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO |
50277 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50278 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50279 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI |
50280 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50281 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50282 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA |
50283 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50284 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50285 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL |
50286 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
50287 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
50288 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO |
50289 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50290 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50291 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI |
50292 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50293 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50294 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA |
50295 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50296 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50297 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL |
50298 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
50299 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
50300 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO |
50301 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50302 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50303 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI |
50304 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50305 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50306 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA |
50307 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50308 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50309 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL |
50310 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
50311 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
50312 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO |
50313 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50314 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50315 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI |
50316 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50317 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50318 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA |
50319 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50320 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50321 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL |
50322 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
50323 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
50324 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO |
50325 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50326 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50327 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI |
50328 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50329 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50330 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA |
50331 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50332 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50333 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL |
50334 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
50335 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
50336 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO |
50337 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50338 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50339 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI |
50340 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50341 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50342 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA |
50343 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50344 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50345 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL |
50346 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
50347 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
50348 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO |
50349 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50350 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50351 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI |
50352 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50353 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50354 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA |
50355 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50356 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50357 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL |
50358 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
50359 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
50360 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO |
50361 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50362 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50363 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI |
50364 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50365 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50366 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA |
50367 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50368 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50369 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL |
50370 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
50371 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
50372 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO |
50373 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50374 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50375 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI |
50376 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50377 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50378 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA |
50379 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50380 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50381 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL |
50382 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
50383 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
50384 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO |
50385 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50386 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50387 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI |
50388 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50389 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50390 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA |
50391 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50392 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50393 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL |
50394 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
50395 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
50396 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO |
50397 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50398 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50399 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI |
50400 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50401 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50402 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA |
50403 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50404 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50405 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL |
50406 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
50407 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
50408 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO |
50409 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50410 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50411 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI |
50412 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50413 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50414 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA |
50415 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50416 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50417 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL |
50418 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
50419 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
50420 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO |
50421 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50422 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50423 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI |
50424 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50425 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50426 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA |
50427 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50428 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50429 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL |
50430 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
50431 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
50432 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO |
50433 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50434 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50435 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI |
50436 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50437 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50438 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA |
50439 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50440 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50441 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL |
50442 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
50443 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
50444 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO |
50445 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50446 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50447 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI |
50448 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50449 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50450 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA |
50451 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50452 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50453 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL |
50454 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
50455 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
50456 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO |
50457 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50458 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50459 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI |
50460 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50461 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50462 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA |
50463 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50464 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50465 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL |
50466 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
50467 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
50468 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO |
50469 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50470 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50471 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI |
50472 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50473 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50474 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA |
50475 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50476 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50477 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL |
50478 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
50479 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
50480 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO |
50481 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50482 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50483 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI |
50484 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50485 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50486 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA |
50487 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50488 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50489 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL |
50490 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
50491 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
50492 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO |
50493 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50494 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50495 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI |
50496 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50497 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50498 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA |
50499 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50500 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50501 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL |
50502 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
50503 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
50504 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO |
50505 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50506 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50507 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI |
50508 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50509 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50510 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA |
50511 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50512 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50513 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL |
50514 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
50515 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
50516 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO |
50517 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50518 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50519 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI |
50520 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50521 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50522 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA |
50523 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50524 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50525 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL |
50526 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
50527 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
50528 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO |
50529 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50530 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50531 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI |
50532 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50533 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50534 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA |
50535 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50536 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50537 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL |
50538 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
50539 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
50540 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO |
50541 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50542 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50543 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI |
50544 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50545 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50546 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA |
50547 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50548 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50549 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL |
50550 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
50551 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
50552 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO |
50553 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50554 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50555 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI |
50556 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50557 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50558 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA |
50559 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50560 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50561 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL |
50562 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
50563 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
50564 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO |
50565 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50566 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50567 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI |
50568 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50569 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50570 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA |
50571 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50572 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50573 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL |
50574 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
50575 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
50576 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO |
50577 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50578 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50579 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI |
50580 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50581 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50582 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA |
50583 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50584 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50585 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL |
50586 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
50587 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
50588 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO |
50589 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50590 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50591 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI |
50592 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50593 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50594 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA |
50595 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50596 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50597 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL |
50598 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
50599 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
50600 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO |
50601 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50602 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50603 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI |
50604 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50605 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50606 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA |
50607 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50608 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50609 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL |
50610 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
50611 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
50612 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO |
50613 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50614 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50615 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI |
50616 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50617 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50618 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA |
50619 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50620 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50621 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL |
50622 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
50623 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
50624 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO |
50625 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50626 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50627 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI |
50628 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50629 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50630 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA |
50631 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50632 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50633 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL |
50634 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
50635 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
50636 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO |
50637 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50638 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50639 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI |
50640 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50641 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50642 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA |
50643 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50644 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50645 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL |
50646 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
50647 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
50648 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO |
50649 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50650 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50651 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI |
50652 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50653 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50654 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA |
50655 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50656 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50657 | //PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL |
50658 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
50659 | #define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
50660 | |
50661 | |
50662 | // addressBlock: nbio_nbif0_pciemsix_psp_MSIXTDEC |
50663 | //PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO |
50664 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50665 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50666 | //PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI |
50667 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50668 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50669 | //PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA |
50670 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50671 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50672 | //PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL |
50673 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
50674 | #define PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
50675 | //PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO |
50676 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50677 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50678 | //PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI |
50679 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50680 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50681 | //PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA |
50682 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50683 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50684 | //PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL |
50685 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
50686 | #define PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
50687 | //PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO |
50688 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50689 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50690 | //PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI |
50691 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50692 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50693 | //PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA |
50694 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50695 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50696 | //PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL |
50697 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
50698 | #define PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
50699 | //PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO |
50700 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50701 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50702 | //PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI |
50703 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50704 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50705 | //PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA |
50706 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50707 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50708 | //PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL |
50709 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
50710 | #define PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
50711 | //PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO |
50712 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50713 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50714 | //PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI |
50715 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50716 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50717 | //PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA |
50718 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50719 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50720 | //PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL |
50721 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
50722 | #define PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
50723 | //PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO |
50724 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50725 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50726 | //PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI |
50727 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50728 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50729 | //PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA |
50730 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50731 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50732 | //PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL |
50733 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
50734 | #define PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
50735 | //PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO |
50736 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50737 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50738 | //PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI |
50739 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50740 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50741 | //PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA |
50742 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50743 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50744 | //PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL |
50745 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
50746 | #define PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
50747 | //PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO |
50748 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50749 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50750 | //PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI |
50751 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50752 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50753 | //PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA |
50754 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50755 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50756 | //PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL |
50757 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
50758 | #define PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
50759 | //PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO |
50760 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50761 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50762 | //PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI |
50763 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50764 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50765 | //PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA |
50766 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50767 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50768 | //PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL |
50769 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
50770 | #define PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
50771 | //PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO |
50772 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50773 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50774 | //PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI |
50775 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50776 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50777 | //PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA |
50778 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50779 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50780 | //PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL |
50781 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
50782 | #define PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
50783 | //PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO |
50784 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50785 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50786 | //PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI |
50787 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50788 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50789 | //PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA |
50790 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50791 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50792 | //PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL |
50793 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
50794 | #define PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
50795 | //PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO |
50796 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50797 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50798 | //PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI |
50799 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50800 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50801 | //PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA |
50802 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50803 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50804 | //PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL |
50805 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
50806 | #define PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
50807 | //PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO |
50808 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50809 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50810 | //PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI |
50811 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50812 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50813 | //PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA |
50814 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50815 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50816 | //PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL |
50817 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
50818 | #define PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
50819 | //PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO |
50820 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50821 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50822 | //PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI |
50823 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50824 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50825 | //PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA |
50826 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50827 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50828 | //PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL |
50829 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
50830 | #define PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
50831 | //PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO |
50832 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50833 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50834 | //PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI |
50835 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50836 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50837 | //PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA |
50838 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50839 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50840 | //PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL |
50841 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
50842 | #define PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
50843 | //PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO |
50844 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50845 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50846 | //PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI |
50847 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50848 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50849 | //PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA |
50850 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50851 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50852 | //PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL |
50853 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
50854 | #define PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
50855 | //PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO |
50856 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50857 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50858 | //PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI |
50859 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50860 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50861 | //PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA |
50862 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50863 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50864 | //PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL |
50865 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
50866 | #define PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
50867 | //PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO |
50868 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50869 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50870 | //PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI |
50871 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50872 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50873 | //PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA |
50874 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50875 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50876 | //PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL |
50877 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
50878 | #define PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
50879 | //PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO |
50880 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50881 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50882 | //PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI |
50883 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50884 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50885 | //PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA |
50886 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50887 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50888 | //PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL |
50889 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
50890 | #define PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
50891 | //PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO |
50892 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50893 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50894 | //PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI |
50895 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50896 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50897 | //PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA |
50898 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50899 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50900 | //PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL |
50901 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
50902 | #define PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
50903 | //PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO |
50904 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50905 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50906 | //PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI |
50907 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50908 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50909 | //PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA |
50910 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50911 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50912 | //PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL |
50913 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
50914 | #define PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
50915 | //PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO |
50916 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50917 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50918 | //PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI |
50919 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50920 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50921 | //PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA |
50922 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50923 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50924 | //PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL |
50925 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
50926 | #define PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
50927 | //PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO |
50928 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50929 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50930 | //PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI |
50931 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50932 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50933 | //PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA |
50934 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50935 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50936 | //PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL |
50937 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
50938 | #define PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
50939 | //PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO |
50940 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50941 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50942 | //PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI |
50943 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50944 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50945 | //PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA |
50946 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50947 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50948 | //PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL |
50949 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
50950 | #define PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
50951 | //PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO |
50952 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50953 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50954 | //PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI |
50955 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50956 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50957 | //PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA |
50958 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50959 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50960 | //PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL |
50961 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
50962 | #define PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
50963 | //PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO |
50964 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50965 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50966 | //PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI |
50967 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50968 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50969 | //PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA |
50970 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50971 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50972 | //PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL |
50973 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
50974 | #define PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
50975 | //PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO |
50976 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50977 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50978 | //PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI |
50979 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50980 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50981 | //PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA |
50982 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50983 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50984 | //PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL |
50985 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
50986 | #define PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
50987 | //PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO |
50988 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
50989 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
50990 | //PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI |
50991 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
50992 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
50993 | //PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA |
50994 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
50995 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
50996 | //PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL |
50997 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
50998 | #define PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
50999 | //PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO |
51000 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51001 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51002 | //PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI |
51003 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51004 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51005 | //PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA |
51006 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51007 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51008 | //PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL |
51009 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
51010 | #define PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
51011 | //PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO |
51012 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51013 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51014 | //PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI |
51015 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51016 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51017 | //PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA |
51018 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51019 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51020 | //PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL |
51021 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
51022 | #define PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
51023 | //PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO |
51024 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51025 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51026 | //PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI |
51027 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51028 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51029 | //PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA |
51030 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51031 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51032 | //PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL |
51033 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
51034 | #define PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
51035 | //PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO |
51036 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51037 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51038 | //PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI |
51039 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51040 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51041 | //PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA |
51042 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51043 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51044 | //PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL |
51045 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
51046 | #define PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
51047 | |
51048 | |
51049 | // addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXTDEC |
51050 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO |
51051 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51052 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51053 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI |
51054 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51055 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51056 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA |
51057 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51058 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51059 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL |
51060 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
51061 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
51062 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO |
51063 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51064 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51065 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI |
51066 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51067 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51068 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA |
51069 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51070 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51071 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL |
51072 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
51073 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
51074 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO |
51075 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51076 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51077 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI |
51078 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51079 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51080 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA |
51081 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51082 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51083 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL |
51084 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
51085 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
51086 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO |
51087 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51088 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51089 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI |
51090 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51091 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51092 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA |
51093 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51094 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51095 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL |
51096 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
51097 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
51098 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO |
51099 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51100 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51101 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI |
51102 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51103 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51104 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA |
51105 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51106 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51107 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL |
51108 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
51109 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
51110 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO |
51111 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51112 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51113 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI |
51114 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51115 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51116 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA |
51117 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51118 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51119 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL |
51120 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
51121 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
51122 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO |
51123 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51124 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51125 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI |
51126 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51127 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51128 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA |
51129 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51130 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51131 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL |
51132 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
51133 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
51134 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO |
51135 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51136 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51137 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI |
51138 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51139 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51140 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA |
51141 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51142 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51143 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL |
51144 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
51145 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
51146 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO |
51147 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51148 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51149 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI |
51150 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51151 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51152 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA |
51153 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51154 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51155 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL |
51156 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
51157 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
51158 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO |
51159 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51160 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51161 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI |
51162 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51163 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51164 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA |
51165 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51166 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51167 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL |
51168 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
51169 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
51170 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO |
51171 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51172 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51173 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI |
51174 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51175 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51176 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA |
51177 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51178 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51179 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL |
51180 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
51181 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
51182 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO |
51183 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51184 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51185 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI |
51186 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51187 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51188 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA |
51189 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51190 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51191 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL |
51192 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
51193 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
51194 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO |
51195 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51196 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51197 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI |
51198 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51199 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51200 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA |
51201 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51202 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51203 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL |
51204 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
51205 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
51206 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO |
51207 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51208 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51209 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI |
51210 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51211 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51212 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA |
51213 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51214 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51215 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL |
51216 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
51217 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
51218 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO |
51219 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51220 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51221 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI |
51222 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51223 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51224 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA |
51225 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51226 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51227 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL |
51228 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
51229 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
51230 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO |
51231 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51232 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51233 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI |
51234 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51235 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51236 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA |
51237 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51238 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51239 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL |
51240 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
51241 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
51242 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO |
51243 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51244 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51245 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI |
51246 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51247 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51248 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA |
51249 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51250 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51251 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL |
51252 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
51253 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
51254 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO |
51255 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51256 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51257 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI |
51258 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51259 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51260 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA |
51261 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51262 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51263 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL |
51264 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
51265 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
51266 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO |
51267 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51268 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51269 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI |
51270 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51271 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51272 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA |
51273 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51274 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51275 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL |
51276 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
51277 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
51278 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO |
51279 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51280 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51281 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI |
51282 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51283 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51284 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA |
51285 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51286 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51287 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL |
51288 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
51289 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
51290 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO |
51291 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51292 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51293 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI |
51294 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51295 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51296 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA |
51297 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51298 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51299 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL |
51300 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
51301 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
51302 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO |
51303 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51304 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51305 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI |
51306 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51307 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51308 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA |
51309 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51310 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51311 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL |
51312 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
51313 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
51314 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO |
51315 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51316 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51317 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI |
51318 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51319 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51320 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA |
51321 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51322 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51323 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL |
51324 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
51325 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
51326 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO |
51327 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51328 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51329 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI |
51330 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51331 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51332 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA |
51333 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51334 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51335 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL |
51336 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
51337 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
51338 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO |
51339 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51340 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51341 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI |
51342 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51343 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51344 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA |
51345 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51346 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51347 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL |
51348 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
51349 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
51350 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO |
51351 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51352 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51353 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI |
51354 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51355 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51356 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA |
51357 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51358 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51359 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL |
51360 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
51361 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
51362 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO |
51363 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51364 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51365 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI |
51366 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51367 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51368 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA |
51369 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51370 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51371 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL |
51372 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
51373 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
51374 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO |
51375 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51376 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51377 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI |
51378 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51379 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51380 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA |
51381 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51382 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51383 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL |
51384 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
51385 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
51386 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO |
51387 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51388 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51389 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI |
51390 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51391 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51392 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA |
51393 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51394 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51395 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL |
51396 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
51397 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
51398 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO |
51399 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51400 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51401 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI |
51402 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51403 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51404 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA |
51405 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51406 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51407 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL |
51408 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
51409 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
51410 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO |
51411 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51412 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51413 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI |
51414 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51415 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51416 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA |
51417 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51418 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51419 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL |
51420 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
51421 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
51422 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO |
51423 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51424 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51425 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI |
51426 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51427 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51428 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA |
51429 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51430 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51431 | //PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL |
51432 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
51433 | #define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
51434 | |
51435 | |
51436 | // addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXTDEC |
51437 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO |
51438 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51439 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51440 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI |
51441 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51442 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51443 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA |
51444 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51445 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51446 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL |
51447 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
51448 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
51449 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO |
51450 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51451 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51452 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI |
51453 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51454 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51455 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA |
51456 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51457 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51458 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL |
51459 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
51460 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
51461 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO |
51462 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51463 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51464 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI |
51465 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51466 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51467 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA |
51468 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51469 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51470 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL |
51471 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
51472 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
51473 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO |
51474 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51475 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51476 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI |
51477 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51478 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51479 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA |
51480 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51481 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51482 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL |
51483 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
51484 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
51485 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO |
51486 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51487 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51488 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI |
51489 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51490 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51491 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA |
51492 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51493 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51494 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL |
51495 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
51496 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
51497 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO |
51498 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51499 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51500 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI |
51501 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51502 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51503 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA |
51504 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51505 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51506 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL |
51507 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
51508 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
51509 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO |
51510 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51511 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51512 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI |
51513 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51514 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51515 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA |
51516 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51517 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51518 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL |
51519 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
51520 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
51521 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO |
51522 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51523 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51524 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI |
51525 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51526 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51527 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA |
51528 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51529 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51530 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL |
51531 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
51532 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
51533 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO |
51534 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51535 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51536 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI |
51537 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51538 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51539 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA |
51540 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51541 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51542 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL |
51543 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
51544 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
51545 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO |
51546 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51547 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51548 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI |
51549 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51550 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51551 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA |
51552 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51553 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51554 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL |
51555 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
51556 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
51557 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO |
51558 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51559 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51560 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI |
51561 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51562 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51563 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA |
51564 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51565 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51566 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL |
51567 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
51568 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
51569 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO |
51570 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51571 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51572 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI |
51573 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51574 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51575 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA |
51576 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51577 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51578 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL |
51579 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
51580 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
51581 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO |
51582 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51583 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51584 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI |
51585 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51586 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51587 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA |
51588 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51589 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51590 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL |
51591 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
51592 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
51593 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO |
51594 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51595 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51596 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI |
51597 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51598 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51599 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA |
51600 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51601 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51602 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL |
51603 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
51604 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
51605 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO |
51606 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51607 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51608 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI |
51609 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51610 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51611 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA |
51612 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51613 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51614 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL |
51615 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
51616 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
51617 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO |
51618 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51619 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51620 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI |
51621 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51622 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51623 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA |
51624 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51625 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51626 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL |
51627 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
51628 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
51629 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO |
51630 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51631 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51632 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI |
51633 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51634 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51635 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA |
51636 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51637 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51638 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL |
51639 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
51640 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
51641 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO |
51642 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51643 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51644 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI |
51645 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51646 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51647 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA |
51648 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51649 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51650 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL |
51651 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
51652 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
51653 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO |
51654 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51655 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51656 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI |
51657 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51658 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51659 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA |
51660 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51661 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51662 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL |
51663 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
51664 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
51665 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO |
51666 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51667 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51668 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI |
51669 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51670 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51671 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA |
51672 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51673 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51674 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL |
51675 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
51676 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
51677 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO |
51678 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51679 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51680 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI |
51681 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51682 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51683 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA |
51684 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51685 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51686 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL |
51687 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
51688 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
51689 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO |
51690 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51691 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51692 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI |
51693 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51694 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51695 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA |
51696 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51697 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51698 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL |
51699 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
51700 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
51701 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO |
51702 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51703 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51704 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI |
51705 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51706 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51707 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA |
51708 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51709 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51710 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL |
51711 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
51712 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
51713 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO |
51714 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51715 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51716 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI |
51717 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51718 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51719 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA |
51720 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51721 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51722 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL |
51723 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
51724 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
51725 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO |
51726 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51727 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51728 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI |
51729 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51730 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51731 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA |
51732 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51733 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51734 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL |
51735 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
51736 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
51737 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO |
51738 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51739 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51740 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI |
51741 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51742 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51743 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA |
51744 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51745 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51746 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL |
51747 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
51748 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
51749 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO |
51750 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51751 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51752 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI |
51753 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51754 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51755 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA |
51756 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51757 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51758 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL |
51759 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
51760 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
51761 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO |
51762 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51763 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51764 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI |
51765 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51766 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51767 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA |
51768 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51769 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51770 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL |
51771 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
51772 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
51773 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO |
51774 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51775 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51776 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI |
51777 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51778 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51779 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA |
51780 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51781 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51782 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL |
51783 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
51784 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
51785 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO |
51786 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51787 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51788 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI |
51789 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51790 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51791 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA |
51792 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51793 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51794 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL |
51795 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
51796 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
51797 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO |
51798 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51799 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51800 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI |
51801 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51802 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51803 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA |
51804 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51805 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51806 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL |
51807 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
51808 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
51809 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO |
51810 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51811 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51812 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI |
51813 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51814 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51815 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA |
51816 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51817 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51818 | //PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL |
51819 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
51820 | #define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
51821 | |
51822 | |
51823 | // addressBlock: nbio_nbif0_pciemsix_mp2_MSIXTDEC |
51824 | //PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO |
51825 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51826 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51827 | //PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI |
51828 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51829 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51830 | //PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA |
51831 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51832 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51833 | //PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL |
51834 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
51835 | #define PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
51836 | //PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO |
51837 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51838 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51839 | //PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI |
51840 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51841 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51842 | //PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA |
51843 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51844 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51845 | //PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL |
51846 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
51847 | #define PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
51848 | //PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO |
51849 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51850 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51851 | //PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI |
51852 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51853 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51854 | //PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA |
51855 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51856 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51857 | //PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL |
51858 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
51859 | #define PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
51860 | //PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO |
51861 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51862 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51863 | //PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI |
51864 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51865 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51866 | //PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA |
51867 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51868 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51869 | //PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL |
51870 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
51871 | #define PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
51872 | //PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO |
51873 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51874 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51875 | //PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI |
51876 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51877 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51878 | //PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA |
51879 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51880 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51881 | //PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL |
51882 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
51883 | #define PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
51884 | //PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO |
51885 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51886 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51887 | //PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI |
51888 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51889 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51890 | //PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA |
51891 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51892 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51893 | //PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL |
51894 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
51895 | #define PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
51896 | //PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO |
51897 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51898 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51899 | //PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI |
51900 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51901 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51902 | //PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA |
51903 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51904 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51905 | //PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL |
51906 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
51907 | #define PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
51908 | //PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO |
51909 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51910 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51911 | //PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI |
51912 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51913 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51914 | //PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA |
51915 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51916 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51917 | //PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL |
51918 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
51919 | #define PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
51920 | //PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO |
51921 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51922 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51923 | //PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI |
51924 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51925 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51926 | //PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA |
51927 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51928 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51929 | //PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL |
51930 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
51931 | #define PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
51932 | //PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO |
51933 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51934 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51935 | //PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI |
51936 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51937 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51938 | //PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA |
51939 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51940 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51941 | //PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL |
51942 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
51943 | #define PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
51944 | //PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO |
51945 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51946 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51947 | //PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI |
51948 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51949 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51950 | //PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA |
51951 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51952 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51953 | //PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL |
51954 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
51955 | #define PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
51956 | //PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO |
51957 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51958 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51959 | //PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI |
51960 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51961 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51962 | //PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA |
51963 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51964 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51965 | //PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL |
51966 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
51967 | #define PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
51968 | //PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO |
51969 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51970 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51971 | //PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI |
51972 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51973 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51974 | //PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA |
51975 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51976 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51977 | //PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL |
51978 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
51979 | #define PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
51980 | //PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO |
51981 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51982 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51983 | //PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI |
51984 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51985 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51986 | //PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA |
51987 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
51988 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
51989 | //PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL |
51990 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
51991 | #define PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
51992 | //PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO |
51993 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
51994 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
51995 | //PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI |
51996 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
51997 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
51998 | //PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA |
51999 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52000 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52001 | //PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL |
52002 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
52003 | #define PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
52004 | //PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO |
52005 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52006 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52007 | //PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI |
52008 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52009 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52010 | //PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA |
52011 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52012 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52013 | //PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL |
52014 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
52015 | #define PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
52016 | //PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO |
52017 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52018 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52019 | //PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI |
52020 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52021 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52022 | //PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA |
52023 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52024 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52025 | //PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL |
52026 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
52027 | #define PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
52028 | //PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO |
52029 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52030 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52031 | //PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI |
52032 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52033 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52034 | //PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA |
52035 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52036 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52037 | //PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL |
52038 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
52039 | #define PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
52040 | //PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO |
52041 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52042 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52043 | //PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI |
52044 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52045 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52046 | //PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA |
52047 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52048 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52049 | //PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL |
52050 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
52051 | #define PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
52052 | //PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO |
52053 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52054 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52055 | //PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI |
52056 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52057 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52058 | //PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA |
52059 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52060 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52061 | //PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL |
52062 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
52063 | #define PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
52064 | //PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO |
52065 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52066 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52067 | //PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI |
52068 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52069 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52070 | //PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA |
52071 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52072 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52073 | //PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL |
52074 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
52075 | #define PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
52076 | //PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO |
52077 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52078 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52079 | //PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI |
52080 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52081 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52082 | //PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA |
52083 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52084 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52085 | //PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL |
52086 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
52087 | #define PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
52088 | //PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO |
52089 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52090 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52091 | //PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI |
52092 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52093 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52094 | //PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA |
52095 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52096 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52097 | //PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL |
52098 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
52099 | #define PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
52100 | //PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO |
52101 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52102 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52103 | //PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI |
52104 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52105 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52106 | //PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA |
52107 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52108 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52109 | //PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL |
52110 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
52111 | #define PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
52112 | //PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO |
52113 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52114 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52115 | //PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI |
52116 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52117 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52118 | //PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA |
52119 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52120 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52121 | //PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL |
52122 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
52123 | #define PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
52124 | //PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO |
52125 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52126 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52127 | //PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI |
52128 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52129 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52130 | //PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA |
52131 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52132 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52133 | //PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL |
52134 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
52135 | #define PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
52136 | //PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO |
52137 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52138 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52139 | //PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI |
52140 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52141 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52142 | //PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA |
52143 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52144 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52145 | //PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL |
52146 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
52147 | #define PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
52148 | //PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO |
52149 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52150 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52151 | //PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI |
52152 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52153 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52154 | //PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA |
52155 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52156 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52157 | //PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL |
52158 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
52159 | #define PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
52160 | //PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO |
52161 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52162 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52163 | //PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI |
52164 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52165 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52166 | //PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA |
52167 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52168 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52169 | //PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL |
52170 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
52171 | #define PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
52172 | //PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO |
52173 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52174 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52175 | //PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI |
52176 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52177 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52178 | //PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA |
52179 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52180 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52181 | //PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL |
52182 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
52183 | #define PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
52184 | //PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO |
52185 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52186 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52187 | //PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI |
52188 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52189 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52190 | //PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA |
52191 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52192 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52193 | //PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL |
52194 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
52195 | #define PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
52196 | //PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO |
52197 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52198 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52199 | //PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI |
52200 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52201 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52202 | //PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA |
52203 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52204 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52205 | //PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL |
52206 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
52207 | #define PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
52208 | |
52209 | |
52210 | // addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXTDEC |
52211 | //PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO |
52212 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52213 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52214 | //PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI |
52215 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52216 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52217 | //PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA |
52218 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52219 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52220 | //PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL |
52221 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
52222 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
52223 | //PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO |
52224 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52225 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52226 | //PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI |
52227 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52228 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52229 | //PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA |
52230 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52231 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52232 | //PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL |
52233 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
52234 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
52235 | //PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO |
52236 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52237 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52238 | //PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI |
52239 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52240 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52241 | //PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA |
52242 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52243 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52244 | //PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL |
52245 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
52246 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
52247 | //PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO |
52248 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52249 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52250 | //PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI |
52251 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52252 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52253 | //PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA |
52254 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52255 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52256 | //PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL |
52257 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
52258 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
52259 | //PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO |
52260 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52261 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52262 | //PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI |
52263 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52264 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52265 | //PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA |
52266 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52267 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52268 | //PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL |
52269 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
52270 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
52271 | //PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO |
52272 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52273 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52274 | //PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI |
52275 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52276 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52277 | //PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA |
52278 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52279 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52280 | //PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL |
52281 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
52282 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
52283 | //PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO |
52284 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52285 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52286 | //PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI |
52287 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52288 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52289 | //PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA |
52290 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52291 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52292 | //PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL |
52293 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
52294 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
52295 | //PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO |
52296 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52297 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52298 | //PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI |
52299 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52300 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52301 | //PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA |
52302 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52303 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52304 | //PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL |
52305 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
52306 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
52307 | //PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO |
52308 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52309 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52310 | //PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI |
52311 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52312 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52313 | //PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA |
52314 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52315 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52316 | //PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL |
52317 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
52318 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
52319 | //PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO |
52320 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52321 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52322 | //PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI |
52323 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52324 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52325 | //PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA |
52326 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52327 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52328 | //PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL |
52329 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
52330 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
52331 | //PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO |
52332 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52333 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52334 | //PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI |
52335 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52336 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52337 | //PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA |
52338 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52339 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52340 | //PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL |
52341 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
52342 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
52343 | //PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO |
52344 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52345 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52346 | //PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI |
52347 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52348 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52349 | //PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA |
52350 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52351 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52352 | //PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL |
52353 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
52354 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
52355 | //PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO |
52356 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52357 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52358 | //PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI |
52359 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52360 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52361 | //PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA |
52362 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52363 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52364 | //PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL |
52365 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
52366 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
52367 | //PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO |
52368 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52369 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52370 | //PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI |
52371 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52372 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52373 | //PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA |
52374 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52375 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52376 | //PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL |
52377 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
52378 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
52379 | //PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO |
52380 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52381 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52382 | //PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI |
52383 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52384 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52385 | //PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA |
52386 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52387 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52388 | //PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL |
52389 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
52390 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
52391 | //PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO |
52392 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52393 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52394 | //PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI |
52395 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52396 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52397 | //PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA |
52398 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52399 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52400 | //PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL |
52401 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
52402 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
52403 | //PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO |
52404 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52405 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52406 | //PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI |
52407 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52408 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52409 | //PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA |
52410 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52411 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52412 | //PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL |
52413 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
52414 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
52415 | //PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO |
52416 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52417 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52418 | //PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI |
52419 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52420 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52421 | //PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA |
52422 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52423 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52424 | //PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL |
52425 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
52426 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
52427 | //PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO |
52428 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52429 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52430 | //PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI |
52431 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52432 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52433 | //PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA |
52434 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52435 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52436 | //PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL |
52437 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
52438 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
52439 | //PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO |
52440 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52441 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52442 | //PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI |
52443 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52444 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52445 | //PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA |
52446 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52447 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52448 | //PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL |
52449 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
52450 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
52451 | //PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO |
52452 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52453 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52454 | //PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI |
52455 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52456 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52457 | //PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA |
52458 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52459 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52460 | //PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL |
52461 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
52462 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
52463 | //PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO |
52464 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52465 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52466 | //PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI |
52467 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52468 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52469 | //PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA |
52470 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52471 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52472 | //PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL |
52473 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
52474 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
52475 | //PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO |
52476 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52477 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52478 | //PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI |
52479 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52480 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52481 | //PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA |
52482 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52483 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52484 | //PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL |
52485 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
52486 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
52487 | //PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO |
52488 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52489 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52490 | //PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI |
52491 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52492 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52493 | //PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA |
52494 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52495 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52496 | //PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL |
52497 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
52498 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
52499 | //PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO |
52500 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52501 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52502 | //PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI |
52503 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52504 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52505 | //PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA |
52506 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52507 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52508 | //PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL |
52509 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
52510 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
52511 | //PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO |
52512 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52513 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52514 | //PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI |
52515 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52516 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52517 | //PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA |
52518 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52519 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52520 | //PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL |
52521 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
52522 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
52523 | //PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO |
52524 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52525 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52526 | //PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI |
52527 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52528 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52529 | //PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA |
52530 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52531 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52532 | //PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL |
52533 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
52534 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
52535 | //PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO |
52536 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52537 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52538 | //PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI |
52539 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52540 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52541 | //PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA |
52542 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52543 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52544 | //PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL |
52545 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
52546 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
52547 | //PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO |
52548 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52549 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52550 | //PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI |
52551 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52552 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52553 | //PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA |
52554 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52555 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52556 | //PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL |
52557 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
52558 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
52559 | //PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO |
52560 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52561 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52562 | //PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI |
52563 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52564 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52565 | //PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA |
52566 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52567 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52568 | //PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL |
52569 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
52570 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
52571 | //PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO |
52572 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52573 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52574 | //PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI |
52575 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52576 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52577 | //PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA |
52578 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52579 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52580 | //PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL |
52581 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
52582 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
52583 | //PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO |
52584 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52585 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52586 | //PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI |
52587 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52588 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52589 | //PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA |
52590 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52591 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52592 | //PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL |
52593 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
52594 | #define PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
52595 | |
52596 | |
52597 | // addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXTDEC |
52598 | //PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO |
52599 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52600 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52601 | //PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI |
52602 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52603 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52604 | //PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA |
52605 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52606 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52607 | //PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL |
52608 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
52609 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
52610 | //PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO |
52611 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52612 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52613 | //PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI |
52614 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52615 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52616 | //PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA |
52617 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52618 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52619 | //PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL |
52620 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
52621 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
52622 | //PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO |
52623 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52624 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52625 | //PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI |
52626 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52627 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52628 | //PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA |
52629 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52630 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52631 | //PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL |
52632 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
52633 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
52634 | //PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO |
52635 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52636 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52637 | //PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI |
52638 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52639 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52640 | //PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA |
52641 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52642 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52643 | //PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL |
52644 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
52645 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
52646 | //PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO |
52647 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52648 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52649 | //PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI |
52650 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52651 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52652 | //PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA |
52653 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52654 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52655 | //PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL |
52656 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
52657 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
52658 | //PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO |
52659 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52660 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52661 | //PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI |
52662 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52663 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52664 | //PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA |
52665 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52666 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52667 | //PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL |
52668 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
52669 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
52670 | //PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO |
52671 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52672 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52673 | //PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI |
52674 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52675 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52676 | //PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA |
52677 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52678 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52679 | //PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL |
52680 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
52681 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
52682 | //PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO |
52683 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52684 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52685 | //PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI |
52686 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52687 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52688 | //PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA |
52689 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52690 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52691 | //PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL |
52692 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
52693 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
52694 | //PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO |
52695 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52696 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52697 | //PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI |
52698 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52699 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52700 | //PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA |
52701 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52702 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52703 | //PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL |
52704 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
52705 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
52706 | //PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO |
52707 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52708 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52709 | //PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI |
52710 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52711 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52712 | //PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA |
52713 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52714 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52715 | //PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL |
52716 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
52717 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
52718 | //PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO |
52719 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52720 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52721 | //PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI |
52722 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52723 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52724 | //PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA |
52725 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52726 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52727 | //PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL |
52728 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
52729 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
52730 | //PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO |
52731 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52732 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52733 | //PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI |
52734 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52735 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52736 | //PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA |
52737 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52738 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52739 | //PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL |
52740 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
52741 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
52742 | //PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO |
52743 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52744 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52745 | //PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI |
52746 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52747 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52748 | //PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA |
52749 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52750 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52751 | //PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL |
52752 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
52753 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
52754 | //PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO |
52755 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52756 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52757 | //PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI |
52758 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52759 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52760 | //PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA |
52761 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52762 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52763 | //PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL |
52764 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
52765 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
52766 | //PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO |
52767 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52768 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52769 | //PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI |
52770 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52771 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52772 | //PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA |
52773 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52774 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52775 | //PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL |
52776 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
52777 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
52778 | //PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO |
52779 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52780 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52781 | //PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI |
52782 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52783 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52784 | //PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA |
52785 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52786 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52787 | //PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL |
52788 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
52789 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
52790 | //PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO |
52791 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52792 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52793 | //PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI |
52794 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52795 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52796 | //PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA |
52797 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52798 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52799 | //PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL |
52800 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
52801 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
52802 | //PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO |
52803 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52804 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52805 | //PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI |
52806 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52807 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52808 | //PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA |
52809 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52810 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52811 | //PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL |
52812 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
52813 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
52814 | //PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO |
52815 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52816 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52817 | //PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI |
52818 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52819 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52820 | //PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA |
52821 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52822 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52823 | //PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL |
52824 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
52825 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
52826 | //PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO |
52827 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52828 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52829 | //PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI |
52830 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52831 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52832 | //PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA |
52833 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52834 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52835 | //PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL |
52836 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
52837 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
52838 | //PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO |
52839 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52840 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52841 | //PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI |
52842 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52843 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52844 | //PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA |
52845 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52846 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52847 | //PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL |
52848 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
52849 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
52850 | //PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO |
52851 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52852 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52853 | //PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI |
52854 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52855 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52856 | //PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA |
52857 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52858 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52859 | //PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL |
52860 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
52861 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
52862 | //PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO |
52863 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52864 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52865 | //PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI |
52866 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52867 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52868 | //PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA |
52869 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52870 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52871 | //PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL |
52872 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
52873 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
52874 | //PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO |
52875 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52876 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52877 | //PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI |
52878 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52879 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52880 | //PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA |
52881 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52882 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52883 | //PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL |
52884 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
52885 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
52886 | //PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO |
52887 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52888 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52889 | //PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI |
52890 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52891 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52892 | //PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA |
52893 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52894 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52895 | //PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL |
52896 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
52897 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
52898 | //PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO |
52899 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52900 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52901 | //PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI |
52902 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52903 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52904 | //PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA |
52905 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52906 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52907 | //PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL |
52908 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
52909 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
52910 | //PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO |
52911 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52912 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52913 | //PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI |
52914 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52915 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52916 | //PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA |
52917 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52918 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52919 | //PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL |
52920 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
52921 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
52922 | //PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO |
52923 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52924 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52925 | //PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI |
52926 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52927 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52928 | //PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA |
52929 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52930 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52931 | //PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL |
52932 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
52933 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
52934 | //PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO |
52935 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52936 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52937 | //PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI |
52938 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52939 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52940 | //PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA |
52941 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52942 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52943 | //PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL |
52944 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
52945 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
52946 | //PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO |
52947 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52948 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52949 | //PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI |
52950 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52951 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52952 | //PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA |
52953 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52954 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52955 | //PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL |
52956 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
52957 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
52958 | //PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO |
52959 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52960 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52961 | //PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI |
52962 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52963 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52964 | //PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA |
52965 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52966 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52967 | //PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL |
52968 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
52969 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
52970 | //PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO |
52971 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
52972 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
52973 | //PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI |
52974 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
52975 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
52976 | //PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA |
52977 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
52978 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
52979 | //PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL |
52980 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
52981 | #define PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
52982 | |
52983 | |
52984 | // addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXPDEC |
52985 | //PCIEMSIX_AMDGFX_PCIEMSIX_PBA |
52986 | #define PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
52987 | #define PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
52988 | |
52989 | |
52990 | // addressBlock: nbio_nbif0_pciemsix_psp_MSIXPDEC |
52991 | //PCIEMSIX_PSP_PCIEMSIX_PBA |
52992 | #define PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
52993 | #define PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
52994 | |
52995 | |
52996 | // addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXPDEC |
52997 | //PCIEMSIX_USB3_0_PCIEMSIX_PBA |
52998 | #define PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
52999 | #define PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
53000 | |
53001 | |
53002 | // addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXPDEC |
53003 | //PCIEMSIX_USB3_1_PCIEMSIX_PBA |
53004 | #define PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
53005 | #define PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
53006 | |
53007 | |
53008 | // addressBlock: nbio_nbif0_pciemsix_mp2_MSIXPDEC |
53009 | //PCIEMSIX_MP2_PCIEMSIX_PBA |
53010 | #define PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
53011 | #define PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
53012 | |
53013 | |
53014 | // addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXPDEC |
53015 | //PCIEMSIX_GBE0_PCIEMSIX_PBA |
53016 | #define PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
53017 | #define PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
53018 | |
53019 | |
53020 | // addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXPDEC |
53021 | //PCIEMSIX_GBE1_PCIEMSIX_PBA |
53022 | #define PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 |
53023 | #define PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
53024 | |
53025 | |
53026 | // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
53027 | //BIFPLR0_1_VENDOR_ID |
53028 | #define BIFPLR0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
53029 | #define BIFPLR0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
53030 | //BIFPLR0_1_DEVICE_ID |
53031 | #define BIFPLR0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
53032 | #define BIFPLR0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
53033 | //BIFPLR0_1_COMMAND |
53034 | #define BIFPLR0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
53035 | #define BIFPLR0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
53036 | #define BIFPLR0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
53037 | #define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
53038 | #define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
53039 | #define BIFPLR0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
53040 | #define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
53041 | #define BIFPLR0_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
53042 | #define BIFPLR0_1_COMMAND__SERR_EN__SHIFT 0x8 |
53043 | #define BIFPLR0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
53044 | #define BIFPLR0_1_COMMAND__INT_DIS__SHIFT 0xa |
53045 | #define BIFPLR0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
53046 | #define BIFPLR0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
53047 | #define BIFPLR0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
53048 | #define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
53049 | #define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
53050 | #define BIFPLR0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
53051 | #define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
53052 | #define BIFPLR0_1_COMMAND__AD_STEPPING_MASK 0x0080L |
53053 | #define BIFPLR0_1_COMMAND__SERR_EN_MASK 0x0100L |
53054 | #define BIFPLR0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
53055 | #define BIFPLR0_1_COMMAND__INT_DIS_MASK 0x0400L |
53056 | //BIFPLR0_1_STATUS |
53057 | #define BIFPLR0_1_STATUS__INT_STATUS__SHIFT 0x3 |
53058 | #define BIFPLR0_1_STATUS__CAP_LIST__SHIFT 0x4 |
53059 | #define BIFPLR0_1_STATUS__PCI_66_EN__SHIFT 0x5 |
53060 | #define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
53061 | #define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
53062 | #define BIFPLR0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
53063 | #define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
53064 | #define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
53065 | #define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
53066 | #define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
53067 | #define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
53068 | #define BIFPLR0_1_STATUS__INT_STATUS_MASK 0x0008L |
53069 | #define BIFPLR0_1_STATUS__CAP_LIST_MASK 0x0010L |
53070 | #define BIFPLR0_1_STATUS__PCI_66_EN_MASK 0x0020L |
53071 | #define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
53072 | #define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
53073 | #define BIFPLR0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
53074 | #define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
53075 | #define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
53076 | #define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
53077 | #define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
53078 | #define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
53079 | //BIFPLR0_1_REVISION_ID |
53080 | #define BIFPLR0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
53081 | #define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
53082 | #define BIFPLR0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
53083 | #define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
53084 | //BIFPLR0_1_PROG_INTERFACE |
53085 | #define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
53086 | #define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
53087 | //BIFPLR0_1_SUB_CLASS |
53088 | #define BIFPLR0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
53089 | #define BIFPLR0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
53090 | //BIFPLR0_1_BASE_CLASS |
53091 | #define BIFPLR0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
53092 | #define BIFPLR0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
53093 | //BIFPLR0_1_CACHE_LINE |
53094 | #define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
53095 | #define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
53096 | //BIFPLR0_1_LATENCY |
53097 | #define BIFPLR0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
53098 | #define BIFPLR0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
53099 | //BIFPLR0_1_HEADER |
53100 | #define BIFPLR0_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
53101 | #define BIFPLR0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
53102 | #define BIFPLR0_1_HEADER__HEADER_TYPE_MASK 0x7FL |
53103 | #define BIFPLR0_1_HEADER__DEVICE_TYPE_MASK 0x80L |
53104 | //BIFPLR0_1_BIST |
53105 | #define BIFPLR0_1_BIST__BIST_COMP__SHIFT 0x0 |
53106 | #define BIFPLR0_1_BIST__BIST_STRT__SHIFT 0x6 |
53107 | #define BIFPLR0_1_BIST__BIST_CAP__SHIFT 0x7 |
53108 | #define BIFPLR0_1_BIST__BIST_COMP_MASK 0x0FL |
53109 | #define BIFPLR0_1_BIST__BIST_STRT_MASK 0x40L |
53110 | #define BIFPLR0_1_BIST__BIST_CAP_MASK 0x80L |
53111 | //BIFPLR0_1_SUB_BUS_NUMBER_LATENCY |
53112 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
53113 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
53114 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
53115 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
53116 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
53117 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
53118 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
53119 | #define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
53120 | //BIFPLR0_1_IO_BASE_LIMIT |
53121 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
53122 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
53123 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
53124 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
53125 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
53126 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
53127 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
53128 | #define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
53129 | //BIFPLR0_1_SECONDARY_STATUS |
53130 | #define BIFPLR0_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
53131 | #define BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
53132 | #define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
53133 | #define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
53134 | #define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
53135 | #define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
53136 | #define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
53137 | #define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
53138 | #define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
53139 | #define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
53140 | #define BIFPLR0_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
53141 | #define BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
53142 | #define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
53143 | #define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
53144 | #define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
53145 | #define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
53146 | #define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
53147 | #define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
53148 | #define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
53149 | #define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
53150 | //BIFPLR0_1_MEM_BASE_LIMIT |
53151 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
53152 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
53153 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
53154 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
53155 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
53156 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
53157 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
53158 | #define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
53159 | //BIFPLR0_1_PREF_BASE_LIMIT |
53160 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
53161 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
53162 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
53163 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
53164 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
53165 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
53166 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
53167 | #define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
53168 | //BIFPLR0_1_PREF_BASE_UPPER |
53169 | #define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
53170 | #define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
53171 | //BIFPLR0_1_PREF_LIMIT_UPPER |
53172 | #define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
53173 | #define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
53174 | //BIFPLR0_1_IO_BASE_LIMIT_HI |
53175 | #define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
53176 | #define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
53177 | #define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
53178 | #define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
53179 | //BIFPLR0_1_CAP_PTR |
53180 | #define BIFPLR0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
53181 | #define BIFPLR0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
53182 | //BIFPLR0_1_INTERRUPT_LINE |
53183 | #define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
53184 | #define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
53185 | //BIFPLR0_1_INTERRUPT_PIN |
53186 | #define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
53187 | #define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
53188 | //BIFPLR0_1_IRQ_BRIDGE_CNTL |
53189 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
53190 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
53191 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
53192 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
53193 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
53194 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
53195 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
53196 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
53197 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
53198 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
53199 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
53200 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
53201 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
53202 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
53203 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
53204 | #define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
53205 | //BIFPLR0_1_EXT_BRIDGE_CNTL |
53206 | #define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
53207 | #define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
53208 | //BIFPLR0_1_PMI_CAP_LIST |
53209 | #define BIFPLR0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
53210 | #define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
53211 | #define BIFPLR0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
53212 | #define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
53213 | //BIFPLR0_1_PMI_CAP |
53214 | #define BIFPLR0_1_PMI_CAP__VERSION__SHIFT 0x0 |
53215 | #define BIFPLR0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
53216 | #define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
53217 | #define BIFPLR0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
53218 | #define BIFPLR0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
53219 | #define BIFPLR0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
53220 | #define BIFPLR0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
53221 | #define BIFPLR0_1_PMI_CAP__VERSION_MASK 0x0007L |
53222 | #define BIFPLR0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
53223 | #define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
53224 | #define BIFPLR0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
53225 | #define BIFPLR0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
53226 | #define BIFPLR0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
53227 | #define BIFPLR0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
53228 | //BIFPLR0_1_PMI_STATUS_CNTL |
53229 | #define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
53230 | #define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
53231 | #define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
53232 | #define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
53233 | #define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
53234 | #define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
53235 | #define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
53236 | #define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
53237 | #define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
53238 | #define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
53239 | #define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
53240 | #define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
53241 | #define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
53242 | #define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
53243 | #define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
53244 | #define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
53245 | #define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
53246 | #define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
53247 | //BIFPLR0_1_PCIE_CAP_LIST |
53248 | #define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
53249 | #define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
53250 | #define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
53251 | #define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
53252 | //BIFPLR0_1_PCIE_CAP |
53253 | #define BIFPLR0_1_PCIE_CAP__VERSION__SHIFT 0x0 |
53254 | #define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
53255 | #define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
53256 | #define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
53257 | #define BIFPLR0_1_PCIE_CAP__VERSION_MASK 0x000FL |
53258 | #define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
53259 | #define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
53260 | #define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
53261 | //BIFPLR0_1_DEVICE_CAP |
53262 | #define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
53263 | #define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
53264 | #define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
53265 | #define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
53266 | #define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
53267 | #define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
53268 | #define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
53269 | #define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
53270 | #define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
53271 | #define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
53272 | #define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
53273 | #define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
53274 | #define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
53275 | #define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
53276 | #define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
53277 | #define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
53278 | #define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
53279 | #define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
53280 | //BIFPLR0_1_DEVICE_CNTL |
53281 | #define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
53282 | #define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
53283 | #define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
53284 | #define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
53285 | #define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
53286 | #define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
53287 | #define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
53288 | #define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
53289 | #define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
53290 | #define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
53291 | #define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
53292 | #define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
53293 | #define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
53294 | #define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
53295 | #define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
53296 | #define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
53297 | #define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
53298 | #define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
53299 | #define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
53300 | #define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
53301 | #define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
53302 | #define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
53303 | #define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
53304 | #define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
53305 | //BIFPLR0_1_DEVICE_STATUS |
53306 | #define BIFPLR0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
53307 | #define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
53308 | #define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
53309 | #define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
53310 | #define BIFPLR0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
53311 | #define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
53312 | #define BIFPLR0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
53313 | #define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
53314 | #define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
53315 | #define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
53316 | #define BIFPLR0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
53317 | #define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
53318 | //BIFPLR0_1_LINK_CAP |
53319 | #define BIFPLR0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
53320 | #define BIFPLR0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
53321 | #define BIFPLR0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
53322 | #define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
53323 | #define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
53324 | #define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
53325 | #define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
53326 | #define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
53327 | #define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
53328 | #define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
53329 | #define BIFPLR0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
53330 | #define BIFPLR0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
53331 | #define BIFPLR0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
53332 | #define BIFPLR0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
53333 | #define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
53334 | #define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
53335 | #define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
53336 | #define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
53337 | #define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
53338 | #define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
53339 | #define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
53340 | #define BIFPLR0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
53341 | //BIFPLR0_1_LINK_CNTL |
53342 | #define BIFPLR0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
53343 | #define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
53344 | #define BIFPLR0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
53345 | #define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
53346 | #define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
53347 | #define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
53348 | #define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
53349 | #define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
53350 | #define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
53351 | #define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
53352 | #define BIFPLR0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
53353 | #define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
53354 | #define BIFPLR0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
53355 | #define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
53356 | #define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
53357 | #define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
53358 | #define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
53359 | #define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
53360 | #define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
53361 | #define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
53362 | //BIFPLR0_1_LINK_STATUS |
53363 | #define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
53364 | #define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
53365 | #define BIFPLR0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
53366 | #define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
53367 | #define BIFPLR0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
53368 | #define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
53369 | #define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
53370 | #define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
53371 | #define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
53372 | #define BIFPLR0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
53373 | #define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
53374 | #define BIFPLR0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
53375 | #define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
53376 | #define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
53377 | //BIFPLR0_1_SLOT_CAP |
53378 | #define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
53379 | #define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
53380 | #define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
53381 | #define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
53382 | #define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
53383 | #define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
53384 | #define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
53385 | #define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
53386 | #define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
53387 | #define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
53388 | #define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
53389 | #define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
53390 | #define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
53391 | #define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
53392 | #define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
53393 | #define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
53394 | #define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
53395 | #define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
53396 | #define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
53397 | #define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
53398 | #define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
53399 | #define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
53400 | #define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
53401 | #define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
53402 | //BIFPLR0_1_SLOT_CNTL |
53403 | #define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
53404 | #define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
53405 | #define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
53406 | #define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
53407 | #define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
53408 | #define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
53409 | #define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
53410 | #define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
53411 | #define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
53412 | #define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
53413 | #define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
53414 | #define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
53415 | #define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
53416 | #define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
53417 | #define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
53418 | #define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
53419 | #define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
53420 | #define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
53421 | #define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
53422 | #define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
53423 | #define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
53424 | #define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
53425 | #define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
53426 | #define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
53427 | //BIFPLR0_1_SLOT_STATUS |
53428 | #define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
53429 | #define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
53430 | #define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
53431 | #define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
53432 | #define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
53433 | #define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
53434 | #define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
53435 | #define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
53436 | #define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
53437 | #define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
53438 | #define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
53439 | #define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
53440 | #define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
53441 | #define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
53442 | #define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
53443 | #define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
53444 | #define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
53445 | #define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
53446 | //BIFPLR0_1_ROOT_CNTL |
53447 | #define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
53448 | #define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
53449 | #define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
53450 | #define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
53451 | #define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
53452 | #define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
53453 | #define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
53454 | #define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
53455 | #define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
53456 | #define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
53457 | //BIFPLR0_1_ROOT_CAP |
53458 | #define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
53459 | #define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
53460 | //BIFPLR0_1_ROOT_STATUS |
53461 | #define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
53462 | #define BIFPLR0_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
53463 | #define BIFPLR0_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
53464 | #define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
53465 | #define BIFPLR0_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
53466 | #define BIFPLR0_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
53467 | //BIFPLR0_1_DEVICE_CAP2 |
53468 | #define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
53469 | #define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
53470 | #define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
53471 | #define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
53472 | #define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
53473 | #define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
53474 | #define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
53475 | #define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
53476 | #define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
53477 | #define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
53478 | #define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
53479 | #define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
53480 | #define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
53481 | #define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
53482 | #define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
53483 | #define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
53484 | #define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
53485 | #define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
53486 | #define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
53487 | #define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
53488 | #define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
53489 | #define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
53490 | #define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
53491 | #define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
53492 | #define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
53493 | #define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
53494 | #define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
53495 | #define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
53496 | //BIFPLR0_1_DEVICE_CNTL2 |
53497 | #define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
53498 | #define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
53499 | #define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
53500 | #define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
53501 | #define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
53502 | #define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
53503 | #define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
53504 | #define BIFPLR0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
53505 | #define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
53506 | #define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
53507 | #define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
53508 | #define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
53509 | #define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
53510 | #define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
53511 | #define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
53512 | #define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
53513 | #define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
53514 | #define BIFPLR0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
53515 | #define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
53516 | #define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
53517 | //BIFPLR0_1_DEVICE_STATUS2 |
53518 | #define BIFPLR0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
53519 | #define BIFPLR0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
53520 | //BIFPLR0_1_LINK_CAP2 |
53521 | #define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
53522 | #define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
53523 | #define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
53524 | #define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
53525 | #define BIFPLR0_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
53526 | #define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
53527 | #define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
53528 | #define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
53529 | #define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
53530 | #define BIFPLR0_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
53531 | //BIFPLR0_1_LINK_CNTL2 |
53532 | #define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
53533 | #define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
53534 | #define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
53535 | #define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
53536 | #define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
53537 | #define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
53538 | #define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
53539 | #define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
53540 | #define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
53541 | #define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
53542 | #define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
53543 | #define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
53544 | #define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
53545 | #define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
53546 | #define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
53547 | #define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
53548 | //BIFPLR0_1_LINK_STATUS2 |
53549 | #define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
53550 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
53551 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
53552 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
53553 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
53554 | #define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
53555 | #define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
53556 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
53557 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
53558 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
53559 | #define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
53560 | #define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
53561 | //BIFPLR0_1_SLOT_CAP2 |
53562 | #define BIFPLR0_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
53563 | #define BIFPLR0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
53564 | //BIFPLR0_1_SLOT_CNTL2 |
53565 | #define BIFPLR0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
53566 | #define BIFPLR0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
53567 | //BIFPLR0_1_SLOT_STATUS2 |
53568 | #define BIFPLR0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
53569 | #define BIFPLR0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
53570 | //BIFPLR0_1_MSI_CAP_LIST |
53571 | #define BIFPLR0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
53572 | #define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
53573 | #define BIFPLR0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
53574 | #define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
53575 | //BIFPLR0_1_MSI_MSG_CNTL |
53576 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
53577 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
53578 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
53579 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
53580 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
53581 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
53582 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
53583 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
53584 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
53585 | #define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
53586 | //BIFPLR0_1_MSI_MSG_ADDR_LO |
53587 | #define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
53588 | #define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
53589 | //BIFPLR0_1_MSI_MSG_ADDR_HI |
53590 | #define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
53591 | #define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
53592 | //BIFPLR0_1_MSI_MSG_DATA |
53593 | #define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
53594 | #define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
53595 | //BIFPLR0_1_MSI_MSG_DATA_64 |
53596 | #define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
53597 | #define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
53598 | //BIFPLR0_1_SSID_CAP_LIST |
53599 | #define BIFPLR0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
53600 | #define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
53601 | #define BIFPLR0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
53602 | #define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
53603 | //BIFPLR0_1_SSID_CAP |
53604 | #define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
53605 | #define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
53606 | #define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
53607 | #define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
53608 | //BIFPLR0_1_MSI_MAP_CAP_LIST |
53609 | #define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
53610 | #define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
53611 | #define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
53612 | #define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
53613 | //BIFPLR0_1_MSI_MAP_CAP |
53614 | #define BIFPLR0_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
53615 | #define BIFPLR0_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
53616 | #define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
53617 | #define BIFPLR0_1_MSI_MAP_CAP__EN_MASK 0x0001L |
53618 | #define BIFPLR0_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
53619 | #define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
53620 | //BIFPLR0_1_MSI_MAP_ADDR_LO |
53621 | #define BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
53622 | #define BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
53623 | //BIFPLR0_1_MSI_MAP_ADDR_HI |
53624 | #define BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
53625 | #define BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
53626 | //BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
53627 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
53628 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
53629 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
53630 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
53631 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
53632 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
53633 | //BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR |
53634 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
53635 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
53636 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
53637 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
53638 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
53639 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
53640 | //BIFPLR0_1_PCIE_VENDOR_SPECIFIC1 |
53641 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
53642 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
53643 | //BIFPLR0_1_PCIE_VENDOR_SPECIFIC2 |
53644 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
53645 | #define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
53646 | //BIFPLR0_1_PCIE_VC_ENH_CAP_LIST |
53647 | #define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
53648 | #define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
53649 | #define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
53650 | #define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
53651 | #define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
53652 | #define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
53653 | //BIFPLR0_1_PCIE_PORT_VC_CAP_REG1 |
53654 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
53655 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
53656 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
53657 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
53658 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
53659 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
53660 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
53661 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
53662 | //BIFPLR0_1_PCIE_PORT_VC_CAP_REG2 |
53663 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
53664 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
53665 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
53666 | #define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
53667 | //BIFPLR0_1_PCIE_PORT_VC_CNTL |
53668 | #define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
53669 | #define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
53670 | #define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
53671 | #define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
53672 | //BIFPLR0_1_PCIE_PORT_VC_STATUS |
53673 | #define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
53674 | #define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
53675 | //BIFPLR0_1_PCIE_VC0_RESOURCE_CAP |
53676 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
53677 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
53678 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
53679 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
53680 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
53681 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
53682 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
53683 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
53684 | //BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL |
53685 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
53686 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
53687 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
53688 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
53689 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
53690 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
53691 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
53692 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
53693 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
53694 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
53695 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
53696 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
53697 | //BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS |
53698 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
53699 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
53700 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
53701 | #define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
53702 | //BIFPLR0_1_PCIE_VC1_RESOURCE_CAP |
53703 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
53704 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
53705 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
53706 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
53707 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
53708 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
53709 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
53710 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
53711 | //BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL |
53712 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
53713 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
53714 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
53715 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
53716 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
53717 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
53718 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
53719 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
53720 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
53721 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
53722 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
53723 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
53724 | //BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS |
53725 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
53726 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
53727 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
53728 | #define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
53729 | //BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
53730 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
53731 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
53732 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
53733 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
53734 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
53735 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
53736 | //BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1 |
53737 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
53738 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
53739 | //BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2 |
53740 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
53741 | #define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
53742 | //BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
53743 | #define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
53744 | #define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
53745 | #define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
53746 | #define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
53747 | #define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
53748 | #define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
53749 | //BIFPLR0_1_PCIE_UNCORR_ERR_STATUS |
53750 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
53751 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
53752 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
53753 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
53754 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
53755 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
53756 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
53757 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
53758 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
53759 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
53760 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
53761 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
53762 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
53763 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
53764 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
53765 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
53766 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
53767 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
53768 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
53769 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
53770 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
53771 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
53772 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
53773 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
53774 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
53775 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
53776 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
53777 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
53778 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
53779 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
53780 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
53781 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
53782 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
53783 | #define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
53784 | //BIFPLR0_1_PCIE_UNCORR_ERR_MASK |
53785 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
53786 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
53787 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
53788 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
53789 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
53790 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
53791 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
53792 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
53793 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
53794 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
53795 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
53796 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
53797 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
53798 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
53799 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
53800 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
53801 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
53802 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
53803 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
53804 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
53805 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
53806 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
53807 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
53808 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
53809 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
53810 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
53811 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
53812 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
53813 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
53814 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
53815 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
53816 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
53817 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
53818 | #define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
53819 | //BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY |
53820 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
53821 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
53822 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
53823 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
53824 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
53825 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
53826 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
53827 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
53828 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
53829 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
53830 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
53831 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
53832 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
53833 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
53834 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
53835 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
53836 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
53837 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
53838 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
53839 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
53840 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
53841 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
53842 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
53843 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
53844 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
53845 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
53846 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
53847 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
53848 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
53849 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
53850 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
53851 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
53852 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
53853 | #define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
53854 | //BIFPLR0_1_PCIE_CORR_ERR_STATUS |
53855 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
53856 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
53857 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
53858 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
53859 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
53860 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
53861 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
53862 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
53863 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
53864 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
53865 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
53866 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
53867 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
53868 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
53869 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
53870 | #define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
53871 | //BIFPLR0_1_PCIE_CORR_ERR_MASK |
53872 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
53873 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
53874 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
53875 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
53876 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
53877 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
53878 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
53879 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
53880 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
53881 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
53882 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
53883 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
53884 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
53885 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
53886 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
53887 | #define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
53888 | //BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL |
53889 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
53890 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
53891 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
53892 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
53893 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
53894 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
53895 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
53896 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
53897 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
53898 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
53899 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
53900 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
53901 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
53902 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
53903 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
53904 | #define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
53905 | //BIFPLR0_1_PCIE_HDR_LOG0 |
53906 | #define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
53907 | #define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
53908 | //BIFPLR0_1_PCIE_HDR_LOG1 |
53909 | #define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
53910 | #define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
53911 | //BIFPLR0_1_PCIE_HDR_LOG2 |
53912 | #define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
53913 | #define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
53914 | //BIFPLR0_1_PCIE_HDR_LOG3 |
53915 | #define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
53916 | #define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
53917 | //BIFPLR0_1_PCIE_ROOT_ERR_CMD |
53918 | #define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
53919 | #define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
53920 | #define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
53921 | #define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
53922 | #define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
53923 | #define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
53924 | //BIFPLR0_1_PCIE_ROOT_ERR_STATUS |
53925 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
53926 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
53927 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
53928 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
53929 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
53930 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
53931 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
53932 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
53933 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
53934 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
53935 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
53936 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
53937 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
53938 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
53939 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
53940 | #define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
53941 | //BIFPLR0_1_PCIE_ERR_SRC_ID |
53942 | #define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
53943 | #define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
53944 | #define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
53945 | #define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
53946 | //BIFPLR0_1_PCIE_TLP_PREFIX_LOG0 |
53947 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
53948 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
53949 | //BIFPLR0_1_PCIE_TLP_PREFIX_LOG1 |
53950 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
53951 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
53952 | //BIFPLR0_1_PCIE_TLP_PREFIX_LOG2 |
53953 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
53954 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
53955 | //BIFPLR0_1_PCIE_TLP_PREFIX_LOG3 |
53956 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
53957 | #define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
53958 | //BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST |
53959 | #define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
53960 | #define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
53961 | #define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
53962 | #define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
53963 | #define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
53964 | #define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
53965 | //BIFPLR0_1_PCIE_LINK_CNTL3 |
53966 | #define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
53967 | #define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
53968 | #define BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
53969 | #define BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
53970 | #define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
53971 | #define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
53972 | #define BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
53973 | #define BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
53974 | //BIFPLR0_1_PCIE_LANE_ERROR_STATUS |
53975 | #define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
53976 | #define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
53977 | #define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
53978 | #define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
53979 | //BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL |
53980 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
53981 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
53982 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
53983 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
53984 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
53985 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
53986 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
53987 | #define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
53988 | //BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL |
53989 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
53990 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
53991 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
53992 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
53993 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
53994 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
53995 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
53996 | #define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
53997 | //BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL |
53998 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
53999 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54000 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54001 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54002 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54003 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54004 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54005 | #define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54006 | //BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL |
54007 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54008 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54009 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54010 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54011 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54012 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54013 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54014 | #define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54015 | //BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL |
54016 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54017 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54018 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54019 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54020 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54021 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54022 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54023 | #define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54024 | //BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL |
54025 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54026 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54027 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54028 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54029 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54030 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54031 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54032 | #define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54033 | //BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL |
54034 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54035 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54036 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54037 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54038 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54039 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54040 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54041 | #define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54042 | //BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL |
54043 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54044 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54045 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54046 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54047 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54048 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54049 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54050 | #define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54051 | //BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL |
54052 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54053 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54054 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54055 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54056 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54057 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54058 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54059 | #define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54060 | //BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL |
54061 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54062 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54063 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54064 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54065 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54066 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54067 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54068 | #define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54069 | //BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL |
54070 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54071 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54072 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54073 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54074 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54075 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54076 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54077 | #define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54078 | //BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL |
54079 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54080 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54081 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54082 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54083 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54084 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54085 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54086 | #define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54087 | //BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL |
54088 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54089 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54090 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54091 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54092 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54093 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54094 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54095 | #define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54096 | //BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL |
54097 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54098 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54099 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54100 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54101 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54102 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54103 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54104 | #define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54105 | //BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL |
54106 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54107 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54108 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54109 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54110 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54111 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54112 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54113 | #define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54114 | //BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL |
54115 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
54116 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
54117 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
54118 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
54119 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
54120 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
54121 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
54122 | #define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
54123 | //BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST |
54124 | #define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
54125 | #define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
54126 | #define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
54127 | #define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
54128 | #define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
54129 | #define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
54130 | //BIFPLR0_1_PCIE_ACS_CAP |
54131 | #define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
54132 | #define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
54133 | #define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
54134 | #define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
54135 | #define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
54136 | #define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
54137 | #define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
54138 | #define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
54139 | #define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
54140 | #define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
54141 | #define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
54142 | #define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
54143 | #define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
54144 | #define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
54145 | #define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
54146 | #define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
54147 | //BIFPLR0_1_PCIE_ACS_CNTL |
54148 | #define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
54149 | #define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
54150 | #define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
54151 | #define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
54152 | #define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
54153 | #define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
54154 | #define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
54155 | #define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
54156 | #define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
54157 | #define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
54158 | #define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
54159 | #define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
54160 | #define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
54161 | #define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
54162 | //BIFPLR0_1_PCIE_MC_ENH_CAP_LIST |
54163 | #define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
54164 | #define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
54165 | #define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
54166 | #define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
54167 | #define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
54168 | #define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
54169 | //BIFPLR0_1_PCIE_MC_CAP |
54170 | #define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
54171 | #define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
54172 | #define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
54173 | #define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
54174 | //BIFPLR0_1_PCIE_MC_CNTL |
54175 | #define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
54176 | #define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
54177 | #define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
54178 | #define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
54179 | //BIFPLR0_1_PCIE_MC_ADDR0 |
54180 | #define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
54181 | #define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
54182 | #define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
54183 | #define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
54184 | //BIFPLR0_1_PCIE_MC_ADDR1 |
54185 | #define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
54186 | #define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
54187 | //BIFPLR0_1_PCIE_MC_RCV0 |
54188 | #define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
54189 | #define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
54190 | //BIFPLR0_1_PCIE_MC_RCV1 |
54191 | #define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
54192 | #define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
54193 | //BIFPLR0_1_PCIE_MC_BLOCK_ALL0 |
54194 | #define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
54195 | #define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
54196 | //BIFPLR0_1_PCIE_MC_BLOCK_ALL1 |
54197 | #define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
54198 | #define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
54199 | //BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
54200 | #define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
54201 | #define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
54202 | //BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
54203 | #define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
54204 | #define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
54205 | //BIFPLR0_1_PCIE_MC_OVERLAY_BAR0 |
54206 | #define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
54207 | #define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
54208 | #define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
54209 | #define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
54210 | //BIFPLR0_1_PCIE_MC_OVERLAY_BAR1 |
54211 | #define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
54212 | #define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
54213 | //BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST |
54214 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
54215 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
54216 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
54217 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
54218 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
54219 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
54220 | //BIFPLR0_1_PCIE_L1_PM_SUB_CAP |
54221 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
54222 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
54223 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
54224 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
54225 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
54226 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
54227 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
54228 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
54229 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
54230 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
54231 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
54232 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
54233 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
54234 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
54235 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
54236 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
54237 | //BIFPLR0_1_PCIE_L1_PM_SUB_CNTL |
54238 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
54239 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
54240 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
54241 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
54242 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
54243 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
54244 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
54245 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
54246 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
54247 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
54248 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
54249 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
54250 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
54251 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
54252 | //BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2 |
54253 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
54254 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
54255 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
54256 | #define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
54257 | //BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST |
54258 | #define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
54259 | #define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
54260 | #define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
54261 | #define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
54262 | #define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
54263 | #define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
54264 | //BIFPLR0_1_PCIE_DPC_CAP_LIST |
54265 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
54266 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
54267 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
54268 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
54269 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
54270 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
54271 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
54272 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
54273 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
54274 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
54275 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
54276 | #define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
54277 | //BIFPLR0_1_PCIE_DPC_CNTL |
54278 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
54279 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
54280 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
54281 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
54282 | #define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
54283 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
54284 | #define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
54285 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
54286 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
54287 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
54288 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
54289 | #define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
54290 | #define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
54291 | #define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
54292 | //BIFPLR0_1_PCIE_DPC_STATUS |
54293 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
54294 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
54295 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
54296 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
54297 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
54298 | #define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
54299 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
54300 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
54301 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
54302 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
54303 | #define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
54304 | #define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
54305 | //BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID |
54306 | #define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
54307 | #define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
54308 | //BIFPLR0_1_PCIE_RP_PIO_STATUS |
54309 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
54310 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
54311 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
54312 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
54313 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
54314 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
54315 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
54316 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
54317 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
54318 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
54319 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
54320 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
54321 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
54322 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
54323 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
54324 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
54325 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
54326 | #define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
54327 | //BIFPLR0_1_PCIE_RP_PIO_MASK |
54328 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
54329 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
54330 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
54331 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
54332 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
54333 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
54334 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
54335 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
54336 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
54337 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
54338 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
54339 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
54340 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
54341 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
54342 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
54343 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
54344 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
54345 | #define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
54346 | //BIFPLR0_1_PCIE_RP_PIO_SEVERITY |
54347 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
54348 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
54349 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
54350 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
54351 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
54352 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
54353 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
54354 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
54355 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
54356 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
54357 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
54358 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
54359 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
54360 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
54361 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
54362 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
54363 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
54364 | #define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
54365 | //BIFPLR0_1_PCIE_RP_PIO_SYSERROR |
54366 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
54367 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
54368 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
54369 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
54370 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
54371 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
54372 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
54373 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
54374 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
54375 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
54376 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
54377 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
54378 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
54379 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
54380 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
54381 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
54382 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
54383 | #define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
54384 | //BIFPLR0_1_PCIE_RP_PIO_EXCEPTION |
54385 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
54386 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
54387 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
54388 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
54389 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
54390 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
54391 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
54392 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
54393 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
54394 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
54395 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
54396 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
54397 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
54398 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
54399 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
54400 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
54401 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
54402 | #define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
54403 | //BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0 |
54404 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
54405 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
54406 | //BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1 |
54407 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
54408 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
54409 | //BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2 |
54410 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
54411 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
54412 | //BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3 |
54413 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
54414 | #define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
54415 | //BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG |
54416 | #define BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
54417 | #define BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
54418 | //BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0 |
54419 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
54420 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
54421 | //BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1 |
54422 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
54423 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
54424 | //BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2 |
54425 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
54426 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
54427 | //BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3 |
54428 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
54429 | #define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
54430 | //BIFPLR0_1_PCIE_ESM_CAP_LIST |
54431 | #define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
54432 | #define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
54433 | #define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
54434 | #define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
54435 | #define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
54436 | #define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
54437 | //BIFPLR0_1_PCIE_ESM_HEADER_1 |
54438 | #define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
54439 | #define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
54440 | #define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
54441 | #define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
54442 | #define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
54443 | #define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
54444 | //BIFPLR0_1_PCIE_ESM_HEADER_2 |
54445 | #define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
54446 | #define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
54447 | //BIFPLR0_1_PCIE_ESM_STATUS |
54448 | #define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
54449 | #define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
54450 | #define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
54451 | #define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
54452 | //BIFPLR0_1_PCIE_ESM_CTRL |
54453 | #define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
54454 | #define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
54455 | #define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
54456 | #define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
54457 | #define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
54458 | #define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
54459 | //BIFPLR0_1_PCIE_ESM_CAP_1 |
54460 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
54461 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
54462 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
54463 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
54464 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
54465 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
54466 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
54467 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
54468 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
54469 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
54470 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
54471 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
54472 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
54473 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
54474 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
54475 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
54476 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
54477 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
54478 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
54479 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
54480 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
54481 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
54482 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
54483 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
54484 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
54485 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
54486 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
54487 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
54488 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
54489 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
54490 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
54491 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
54492 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
54493 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
54494 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
54495 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
54496 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
54497 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
54498 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
54499 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
54500 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
54501 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
54502 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
54503 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
54504 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
54505 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
54506 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
54507 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
54508 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
54509 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
54510 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
54511 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
54512 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
54513 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
54514 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
54515 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
54516 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
54517 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
54518 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
54519 | #define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
54520 | //BIFPLR0_1_PCIE_ESM_CAP_2 |
54521 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
54522 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
54523 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
54524 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
54525 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
54526 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
54527 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
54528 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
54529 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
54530 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
54531 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
54532 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
54533 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
54534 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
54535 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
54536 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
54537 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
54538 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
54539 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
54540 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
54541 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
54542 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
54543 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
54544 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
54545 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
54546 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
54547 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
54548 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
54549 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
54550 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
54551 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
54552 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
54553 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
54554 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
54555 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
54556 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
54557 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
54558 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
54559 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
54560 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
54561 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
54562 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
54563 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
54564 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
54565 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
54566 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
54567 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
54568 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
54569 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
54570 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
54571 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
54572 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
54573 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
54574 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
54575 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
54576 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
54577 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
54578 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
54579 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
54580 | #define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
54581 | //BIFPLR0_1_PCIE_ESM_CAP_3 |
54582 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
54583 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
54584 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
54585 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
54586 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
54587 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
54588 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
54589 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
54590 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
54591 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
54592 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
54593 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
54594 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
54595 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
54596 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
54597 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
54598 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
54599 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
54600 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
54601 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
54602 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
54603 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
54604 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
54605 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
54606 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
54607 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
54608 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
54609 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
54610 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
54611 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
54612 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
54613 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
54614 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
54615 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
54616 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
54617 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
54618 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
54619 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
54620 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
54621 | #define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
54622 | //BIFPLR0_1_PCIE_ESM_CAP_4 |
54623 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
54624 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
54625 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
54626 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
54627 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
54628 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
54629 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
54630 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
54631 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
54632 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
54633 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
54634 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
54635 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
54636 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
54637 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
54638 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
54639 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
54640 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
54641 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
54642 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
54643 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
54644 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
54645 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
54646 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
54647 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
54648 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
54649 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
54650 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
54651 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
54652 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
54653 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
54654 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
54655 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
54656 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
54657 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
54658 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
54659 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
54660 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
54661 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
54662 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
54663 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
54664 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
54665 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
54666 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
54667 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
54668 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
54669 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
54670 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
54671 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
54672 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
54673 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
54674 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
54675 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
54676 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
54677 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
54678 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
54679 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
54680 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
54681 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
54682 | #define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
54683 | //BIFPLR0_1_PCIE_ESM_CAP_5 |
54684 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
54685 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
54686 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
54687 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
54688 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
54689 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
54690 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
54691 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
54692 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
54693 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
54694 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
54695 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
54696 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
54697 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
54698 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
54699 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
54700 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
54701 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
54702 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
54703 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
54704 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
54705 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
54706 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
54707 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
54708 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
54709 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
54710 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
54711 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
54712 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
54713 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
54714 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
54715 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
54716 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
54717 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
54718 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
54719 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
54720 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
54721 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
54722 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
54723 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
54724 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
54725 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
54726 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
54727 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
54728 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
54729 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
54730 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
54731 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
54732 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
54733 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
54734 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
54735 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
54736 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
54737 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
54738 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
54739 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
54740 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
54741 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
54742 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
54743 | #define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
54744 | //BIFPLR0_1_PCIE_ESM_CAP_6 |
54745 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
54746 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
54747 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
54748 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
54749 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
54750 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
54751 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
54752 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
54753 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
54754 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
54755 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
54756 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
54757 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
54758 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
54759 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
54760 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
54761 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
54762 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
54763 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
54764 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
54765 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
54766 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
54767 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
54768 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
54769 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
54770 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
54771 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
54772 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
54773 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
54774 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
54775 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
54776 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
54777 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
54778 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
54779 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
54780 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
54781 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
54782 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
54783 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
54784 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
54785 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
54786 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
54787 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
54788 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
54789 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
54790 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
54791 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
54792 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
54793 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
54794 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
54795 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
54796 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
54797 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
54798 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
54799 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
54800 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
54801 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
54802 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
54803 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
54804 | #define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
54805 | //BIFPLR0_1_PCIE_ESM_CAP_7 |
54806 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
54807 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
54808 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
54809 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
54810 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
54811 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
54812 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
54813 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
54814 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
54815 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
54816 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
54817 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
54818 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
54819 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
54820 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
54821 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
54822 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
54823 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
54824 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
54825 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
54826 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
54827 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
54828 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
54829 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
54830 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
54831 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
54832 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
54833 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
54834 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
54835 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
54836 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
54837 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
54838 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
54839 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
54840 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
54841 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
54842 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
54843 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
54844 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
54845 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
54846 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
54847 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
54848 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
54849 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
54850 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
54851 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
54852 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
54853 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
54854 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
54855 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
54856 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
54857 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
54858 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
54859 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
54860 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
54861 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
54862 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
54863 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
54864 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
54865 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
54866 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
54867 | #define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
54868 | |
54869 | |
54870 | // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
54871 | //BIFPLR1_1_VENDOR_ID |
54872 | #define BIFPLR1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
54873 | #define BIFPLR1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
54874 | //BIFPLR1_1_DEVICE_ID |
54875 | #define BIFPLR1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
54876 | #define BIFPLR1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
54877 | //BIFPLR1_1_COMMAND |
54878 | #define BIFPLR1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
54879 | #define BIFPLR1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
54880 | #define BIFPLR1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
54881 | #define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
54882 | #define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
54883 | #define BIFPLR1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
54884 | #define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
54885 | #define BIFPLR1_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
54886 | #define BIFPLR1_1_COMMAND__SERR_EN__SHIFT 0x8 |
54887 | #define BIFPLR1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
54888 | #define BIFPLR1_1_COMMAND__INT_DIS__SHIFT 0xa |
54889 | #define BIFPLR1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
54890 | #define BIFPLR1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
54891 | #define BIFPLR1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
54892 | #define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
54893 | #define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
54894 | #define BIFPLR1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
54895 | #define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
54896 | #define BIFPLR1_1_COMMAND__AD_STEPPING_MASK 0x0080L |
54897 | #define BIFPLR1_1_COMMAND__SERR_EN_MASK 0x0100L |
54898 | #define BIFPLR1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
54899 | #define BIFPLR1_1_COMMAND__INT_DIS_MASK 0x0400L |
54900 | //BIFPLR1_1_STATUS |
54901 | #define BIFPLR1_1_STATUS__INT_STATUS__SHIFT 0x3 |
54902 | #define BIFPLR1_1_STATUS__CAP_LIST__SHIFT 0x4 |
54903 | #define BIFPLR1_1_STATUS__PCI_66_EN__SHIFT 0x5 |
54904 | #define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
54905 | #define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
54906 | #define BIFPLR1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
54907 | #define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
54908 | #define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
54909 | #define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
54910 | #define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
54911 | #define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
54912 | #define BIFPLR1_1_STATUS__INT_STATUS_MASK 0x0008L |
54913 | #define BIFPLR1_1_STATUS__CAP_LIST_MASK 0x0010L |
54914 | #define BIFPLR1_1_STATUS__PCI_66_EN_MASK 0x0020L |
54915 | #define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
54916 | #define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
54917 | #define BIFPLR1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
54918 | #define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
54919 | #define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
54920 | #define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
54921 | #define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
54922 | #define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
54923 | //BIFPLR1_1_REVISION_ID |
54924 | #define BIFPLR1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
54925 | #define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
54926 | #define BIFPLR1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
54927 | #define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
54928 | //BIFPLR1_1_PROG_INTERFACE |
54929 | #define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
54930 | #define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
54931 | //BIFPLR1_1_SUB_CLASS |
54932 | #define BIFPLR1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
54933 | #define BIFPLR1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
54934 | //BIFPLR1_1_BASE_CLASS |
54935 | #define BIFPLR1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
54936 | #define BIFPLR1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
54937 | //BIFPLR1_1_CACHE_LINE |
54938 | #define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
54939 | #define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
54940 | //BIFPLR1_1_LATENCY |
54941 | #define BIFPLR1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
54942 | #define BIFPLR1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
54943 | //BIFPLR1_1_HEADER |
54944 | #define BIFPLR1_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
54945 | #define BIFPLR1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
54946 | #define BIFPLR1_1_HEADER__HEADER_TYPE_MASK 0x7FL |
54947 | #define BIFPLR1_1_HEADER__DEVICE_TYPE_MASK 0x80L |
54948 | //BIFPLR1_1_BIST |
54949 | #define BIFPLR1_1_BIST__BIST_COMP__SHIFT 0x0 |
54950 | #define BIFPLR1_1_BIST__BIST_STRT__SHIFT 0x6 |
54951 | #define BIFPLR1_1_BIST__BIST_CAP__SHIFT 0x7 |
54952 | #define BIFPLR1_1_BIST__BIST_COMP_MASK 0x0FL |
54953 | #define BIFPLR1_1_BIST__BIST_STRT_MASK 0x40L |
54954 | #define BIFPLR1_1_BIST__BIST_CAP_MASK 0x80L |
54955 | //BIFPLR1_1_SUB_BUS_NUMBER_LATENCY |
54956 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
54957 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
54958 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
54959 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
54960 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
54961 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
54962 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
54963 | #define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
54964 | //BIFPLR1_1_IO_BASE_LIMIT |
54965 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
54966 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
54967 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
54968 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
54969 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
54970 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
54971 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
54972 | #define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
54973 | //BIFPLR1_1_SECONDARY_STATUS |
54974 | #define BIFPLR1_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
54975 | #define BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
54976 | #define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
54977 | #define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
54978 | #define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
54979 | #define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
54980 | #define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
54981 | #define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
54982 | #define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
54983 | #define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
54984 | #define BIFPLR1_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
54985 | #define BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
54986 | #define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
54987 | #define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
54988 | #define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
54989 | #define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
54990 | #define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
54991 | #define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
54992 | #define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
54993 | #define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
54994 | //BIFPLR1_1_MEM_BASE_LIMIT |
54995 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
54996 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
54997 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
54998 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
54999 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
55000 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
55001 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
55002 | #define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
55003 | //BIFPLR1_1_PREF_BASE_LIMIT |
55004 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
55005 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
55006 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
55007 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
55008 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
55009 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
55010 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
55011 | #define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
55012 | //BIFPLR1_1_PREF_BASE_UPPER |
55013 | #define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
55014 | #define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
55015 | //BIFPLR1_1_PREF_LIMIT_UPPER |
55016 | #define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
55017 | #define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
55018 | //BIFPLR1_1_IO_BASE_LIMIT_HI |
55019 | #define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
55020 | #define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
55021 | #define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
55022 | #define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
55023 | //BIFPLR1_1_CAP_PTR |
55024 | #define BIFPLR1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
55025 | #define BIFPLR1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
55026 | //BIFPLR1_1_INTERRUPT_LINE |
55027 | #define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
55028 | #define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
55029 | //BIFPLR1_1_INTERRUPT_PIN |
55030 | #define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
55031 | #define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
55032 | //BIFPLR1_1_IRQ_BRIDGE_CNTL |
55033 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
55034 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
55035 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
55036 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
55037 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
55038 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
55039 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
55040 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
55041 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
55042 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
55043 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
55044 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
55045 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
55046 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
55047 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
55048 | #define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
55049 | //BIFPLR1_1_EXT_BRIDGE_CNTL |
55050 | #define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
55051 | #define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
55052 | //BIFPLR1_1_PMI_CAP_LIST |
55053 | #define BIFPLR1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
55054 | #define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
55055 | #define BIFPLR1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
55056 | #define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
55057 | //BIFPLR1_1_PMI_CAP |
55058 | #define BIFPLR1_1_PMI_CAP__VERSION__SHIFT 0x0 |
55059 | #define BIFPLR1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
55060 | #define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
55061 | #define BIFPLR1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
55062 | #define BIFPLR1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
55063 | #define BIFPLR1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
55064 | #define BIFPLR1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
55065 | #define BIFPLR1_1_PMI_CAP__VERSION_MASK 0x0007L |
55066 | #define BIFPLR1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
55067 | #define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
55068 | #define BIFPLR1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
55069 | #define BIFPLR1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
55070 | #define BIFPLR1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
55071 | #define BIFPLR1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
55072 | //BIFPLR1_1_PMI_STATUS_CNTL |
55073 | #define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
55074 | #define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
55075 | #define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
55076 | #define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
55077 | #define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
55078 | #define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
55079 | #define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
55080 | #define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
55081 | #define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
55082 | #define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
55083 | #define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
55084 | #define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
55085 | #define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
55086 | #define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
55087 | #define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
55088 | #define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
55089 | #define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
55090 | #define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
55091 | //BIFPLR1_1_PCIE_CAP_LIST |
55092 | #define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
55093 | #define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
55094 | #define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
55095 | #define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
55096 | //BIFPLR1_1_PCIE_CAP |
55097 | #define BIFPLR1_1_PCIE_CAP__VERSION__SHIFT 0x0 |
55098 | #define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
55099 | #define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
55100 | #define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
55101 | #define BIFPLR1_1_PCIE_CAP__VERSION_MASK 0x000FL |
55102 | #define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
55103 | #define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
55104 | #define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
55105 | //BIFPLR1_1_DEVICE_CAP |
55106 | #define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
55107 | #define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
55108 | #define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
55109 | #define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
55110 | #define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
55111 | #define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
55112 | #define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
55113 | #define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
55114 | #define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
55115 | #define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
55116 | #define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
55117 | #define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
55118 | #define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
55119 | #define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
55120 | #define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
55121 | #define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
55122 | #define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
55123 | #define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
55124 | //BIFPLR1_1_DEVICE_CNTL |
55125 | #define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
55126 | #define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
55127 | #define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
55128 | #define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
55129 | #define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
55130 | #define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
55131 | #define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
55132 | #define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
55133 | #define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
55134 | #define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
55135 | #define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
55136 | #define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
55137 | #define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
55138 | #define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
55139 | #define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
55140 | #define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
55141 | #define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
55142 | #define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
55143 | #define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
55144 | #define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
55145 | #define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
55146 | #define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
55147 | #define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
55148 | #define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
55149 | //BIFPLR1_1_DEVICE_STATUS |
55150 | #define BIFPLR1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
55151 | #define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
55152 | #define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
55153 | #define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
55154 | #define BIFPLR1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
55155 | #define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
55156 | #define BIFPLR1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
55157 | #define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
55158 | #define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
55159 | #define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
55160 | #define BIFPLR1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
55161 | #define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
55162 | //BIFPLR1_1_LINK_CAP |
55163 | #define BIFPLR1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
55164 | #define BIFPLR1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
55165 | #define BIFPLR1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
55166 | #define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
55167 | #define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
55168 | #define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
55169 | #define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
55170 | #define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
55171 | #define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
55172 | #define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
55173 | #define BIFPLR1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
55174 | #define BIFPLR1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
55175 | #define BIFPLR1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
55176 | #define BIFPLR1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
55177 | #define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
55178 | #define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
55179 | #define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
55180 | #define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
55181 | #define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
55182 | #define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
55183 | #define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
55184 | #define BIFPLR1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
55185 | //BIFPLR1_1_LINK_CNTL |
55186 | #define BIFPLR1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
55187 | #define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
55188 | #define BIFPLR1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
55189 | #define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
55190 | #define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
55191 | #define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
55192 | #define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
55193 | #define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
55194 | #define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
55195 | #define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
55196 | #define BIFPLR1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
55197 | #define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
55198 | #define BIFPLR1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
55199 | #define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
55200 | #define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
55201 | #define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
55202 | #define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
55203 | #define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
55204 | #define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
55205 | #define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
55206 | //BIFPLR1_1_LINK_STATUS |
55207 | #define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
55208 | #define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
55209 | #define BIFPLR1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
55210 | #define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
55211 | #define BIFPLR1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
55212 | #define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
55213 | #define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
55214 | #define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
55215 | #define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
55216 | #define BIFPLR1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
55217 | #define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
55218 | #define BIFPLR1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
55219 | #define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
55220 | #define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
55221 | //BIFPLR1_1_SLOT_CAP |
55222 | #define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
55223 | #define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
55224 | #define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
55225 | #define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
55226 | #define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
55227 | #define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
55228 | #define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
55229 | #define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
55230 | #define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
55231 | #define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
55232 | #define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
55233 | #define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
55234 | #define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
55235 | #define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
55236 | #define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
55237 | #define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
55238 | #define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
55239 | #define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
55240 | #define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
55241 | #define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
55242 | #define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
55243 | #define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
55244 | #define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
55245 | #define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
55246 | //BIFPLR1_1_SLOT_CNTL |
55247 | #define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
55248 | #define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
55249 | #define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
55250 | #define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
55251 | #define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
55252 | #define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
55253 | #define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
55254 | #define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
55255 | #define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
55256 | #define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
55257 | #define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
55258 | #define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
55259 | #define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
55260 | #define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
55261 | #define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
55262 | #define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
55263 | #define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
55264 | #define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
55265 | #define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
55266 | #define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
55267 | #define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
55268 | #define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
55269 | #define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
55270 | #define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
55271 | //BIFPLR1_1_SLOT_STATUS |
55272 | #define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
55273 | #define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
55274 | #define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
55275 | #define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
55276 | #define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
55277 | #define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
55278 | #define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
55279 | #define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
55280 | #define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
55281 | #define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
55282 | #define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
55283 | #define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
55284 | #define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
55285 | #define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
55286 | #define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
55287 | #define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
55288 | #define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
55289 | #define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
55290 | //BIFPLR1_1_ROOT_CNTL |
55291 | #define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
55292 | #define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
55293 | #define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
55294 | #define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
55295 | #define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
55296 | #define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
55297 | #define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
55298 | #define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
55299 | #define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
55300 | #define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
55301 | //BIFPLR1_1_ROOT_CAP |
55302 | #define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
55303 | #define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
55304 | //BIFPLR1_1_ROOT_STATUS |
55305 | #define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
55306 | #define BIFPLR1_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
55307 | #define BIFPLR1_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
55308 | #define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
55309 | #define BIFPLR1_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
55310 | #define BIFPLR1_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
55311 | //BIFPLR1_1_DEVICE_CAP2 |
55312 | #define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
55313 | #define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
55314 | #define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
55315 | #define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
55316 | #define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
55317 | #define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
55318 | #define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
55319 | #define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
55320 | #define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
55321 | #define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
55322 | #define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
55323 | #define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
55324 | #define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
55325 | #define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
55326 | #define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
55327 | #define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
55328 | #define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
55329 | #define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
55330 | #define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
55331 | #define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
55332 | #define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
55333 | #define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
55334 | #define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
55335 | #define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
55336 | #define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
55337 | #define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
55338 | #define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
55339 | #define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
55340 | //BIFPLR1_1_DEVICE_CNTL2 |
55341 | #define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
55342 | #define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
55343 | #define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
55344 | #define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
55345 | #define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
55346 | #define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
55347 | #define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
55348 | #define BIFPLR1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
55349 | #define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
55350 | #define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
55351 | #define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
55352 | #define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
55353 | #define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
55354 | #define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
55355 | #define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
55356 | #define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
55357 | #define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
55358 | #define BIFPLR1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
55359 | #define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
55360 | #define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
55361 | //BIFPLR1_1_DEVICE_STATUS2 |
55362 | #define BIFPLR1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
55363 | #define BIFPLR1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
55364 | //BIFPLR1_1_LINK_CAP2 |
55365 | #define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
55366 | #define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
55367 | #define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
55368 | #define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
55369 | #define BIFPLR1_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
55370 | #define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
55371 | #define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
55372 | #define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
55373 | #define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
55374 | #define BIFPLR1_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
55375 | //BIFPLR1_1_LINK_CNTL2 |
55376 | #define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
55377 | #define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
55378 | #define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
55379 | #define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
55380 | #define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
55381 | #define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
55382 | #define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
55383 | #define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
55384 | #define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
55385 | #define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
55386 | #define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
55387 | #define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
55388 | #define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
55389 | #define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
55390 | #define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
55391 | #define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
55392 | //BIFPLR1_1_LINK_STATUS2 |
55393 | #define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
55394 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
55395 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
55396 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
55397 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
55398 | #define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
55399 | #define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
55400 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
55401 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
55402 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
55403 | #define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
55404 | #define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
55405 | //BIFPLR1_1_SLOT_CAP2 |
55406 | #define BIFPLR1_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
55407 | #define BIFPLR1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
55408 | //BIFPLR1_1_SLOT_CNTL2 |
55409 | #define BIFPLR1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
55410 | #define BIFPLR1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
55411 | //BIFPLR1_1_SLOT_STATUS2 |
55412 | #define BIFPLR1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
55413 | #define BIFPLR1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
55414 | //BIFPLR1_1_MSI_CAP_LIST |
55415 | #define BIFPLR1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
55416 | #define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
55417 | #define BIFPLR1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
55418 | #define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
55419 | //BIFPLR1_1_MSI_MSG_CNTL |
55420 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
55421 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
55422 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
55423 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
55424 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
55425 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
55426 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
55427 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
55428 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
55429 | #define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
55430 | //BIFPLR1_1_MSI_MSG_ADDR_LO |
55431 | #define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
55432 | #define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
55433 | //BIFPLR1_1_MSI_MSG_ADDR_HI |
55434 | #define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
55435 | #define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
55436 | //BIFPLR1_1_MSI_MSG_DATA |
55437 | #define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
55438 | #define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
55439 | //BIFPLR1_1_MSI_MSG_DATA_64 |
55440 | #define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
55441 | #define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
55442 | //BIFPLR1_1_SSID_CAP_LIST |
55443 | #define BIFPLR1_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
55444 | #define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
55445 | #define BIFPLR1_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
55446 | #define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
55447 | //BIFPLR1_1_SSID_CAP |
55448 | #define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
55449 | #define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
55450 | #define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
55451 | #define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
55452 | //BIFPLR1_1_MSI_MAP_CAP_LIST |
55453 | #define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
55454 | #define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
55455 | #define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
55456 | #define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
55457 | //BIFPLR1_1_MSI_MAP_CAP |
55458 | #define BIFPLR1_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
55459 | #define BIFPLR1_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
55460 | #define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
55461 | #define BIFPLR1_1_MSI_MAP_CAP__EN_MASK 0x0001L |
55462 | #define BIFPLR1_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
55463 | #define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
55464 | //BIFPLR1_1_MSI_MAP_ADDR_LO |
55465 | #define BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
55466 | #define BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
55467 | //BIFPLR1_1_MSI_MAP_ADDR_HI |
55468 | #define BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
55469 | #define BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
55470 | //BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
55471 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
55472 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
55473 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
55474 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
55475 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
55476 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
55477 | //BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR |
55478 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
55479 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
55480 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
55481 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
55482 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
55483 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
55484 | //BIFPLR1_1_PCIE_VENDOR_SPECIFIC1 |
55485 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
55486 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
55487 | //BIFPLR1_1_PCIE_VENDOR_SPECIFIC2 |
55488 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
55489 | #define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
55490 | //BIFPLR1_1_PCIE_VC_ENH_CAP_LIST |
55491 | #define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
55492 | #define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
55493 | #define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
55494 | #define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
55495 | #define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
55496 | #define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
55497 | //BIFPLR1_1_PCIE_PORT_VC_CAP_REG1 |
55498 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
55499 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
55500 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
55501 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
55502 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
55503 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
55504 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
55505 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
55506 | //BIFPLR1_1_PCIE_PORT_VC_CAP_REG2 |
55507 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
55508 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
55509 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
55510 | #define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
55511 | //BIFPLR1_1_PCIE_PORT_VC_CNTL |
55512 | #define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
55513 | #define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
55514 | #define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
55515 | #define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
55516 | //BIFPLR1_1_PCIE_PORT_VC_STATUS |
55517 | #define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
55518 | #define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
55519 | //BIFPLR1_1_PCIE_VC0_RESOURCE_CAP |
55520 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
55521 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
55522 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
55523 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
55524 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
55525 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
55526 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
55527 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
55528 | //BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL |
55529 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
55530 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
55531 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
55532 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
55533 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
55534 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
55535 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
55536 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
55537 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
55538 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
55539 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
55540 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
55541 | //BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS |
55542 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
55543 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
55544 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
55545 | #define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
55546 | //BIFPLR1_1_PCIE_VC1_RESOURCE_CAP |
55547 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
55548 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
55549 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
55550 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
55551 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
55552 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
55553 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
55554 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
55555 | //BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL |
55556 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
55557 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
55558 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
55559 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
55560 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
55561 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
55562 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
55563 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
55564 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
55565 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
55566 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
55567 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
55568 | //BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS |
55569 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
55570 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
55571 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
55572 | #define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
55573 | //BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
55574 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
55575 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
55576 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
55577 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
55578 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
55579 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
55580 | //BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1 |
55581 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
55582 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
55583 | //BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2 |
55584 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
55585 | #define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
55586 | //BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
55587 | #define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
55588 | #define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
55589 | #define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
55590 | #define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
55591 | #define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
55592 | #define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
55593 | //BIFPLR1_1_PCIE_UNCORR_ERR_STATUS |
55594 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
55595 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
55596 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
55597 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
55598 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
55599 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
55600 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
55601 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
55602 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
55603 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
55604 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
55605 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
55606 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
55607 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
55608 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
55609 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
55610 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
55611 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
55612 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
55613 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
55614 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
55615 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
55616 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
55617 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
55618 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
55619 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
55620 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
55621 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
55622 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
55623 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
55624 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
55625 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
55626 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
55627 | #define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
55628 | //BIFPLR1_1_PCIE_UNCORR_ERR_MASK |
55629 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
55630 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
55631 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
55632 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
55633 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
55634 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
55635 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
55636 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
55637 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
55638 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
55639 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
55640 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
55641 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
55642 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
55643 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
55644 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
55645 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
55646 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
55647 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
55648 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
55649 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
55650 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
55651 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
55652 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
55653 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
55654 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
55655 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
55656 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
55657 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
55658 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
55659 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
55660 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
55661 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
55662 | #define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
55663 | //BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY |
55664 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
55665 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
55666 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
55667 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
55668 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
55669 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
55670 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
55671 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
55672 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
55673 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
55674 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
55675 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
55676 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
55677 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
55678 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
55679 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
55680 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
55681 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
55682 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
55683 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
55684 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
55685 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
55686 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
55687 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
55688 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
55689 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
55690 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
55691 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
55692 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
55693 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
55694 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
55695 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
55696 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
55697 | #define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
55698 | //BIFPLR1_1_PCIE_CORR_ERR_STATUS |
55699 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
55700 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
55701 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
55702 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
55703 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
55704 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
55705 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
55706 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
55707 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
55708 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
55709 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
55710 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
55711 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
55712 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
55713 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
55714 | #define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
55715 | //BIFPLR1_1_PCIE_CORR_ERR_MASK |
55716 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
55717 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
55718 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
55719 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
55720 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
55721 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
55722 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
55723 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
55724 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
55725 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
55726 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
55727 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
55728 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
55729 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
55730 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
55731 | #define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
55732 | //BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL |
55733 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
55734 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
55735 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
55736 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
55737 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
55738 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
55739 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
55740 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
55741 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
55742 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
55743 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
55744 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
55745 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
55746 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
55747 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
55748 | #define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
55749 | //BIFPLR1_1_PCIE_HDR_LOG0 |
55750 | #define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
55751 | #define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
55752 | //BIFPLR1_1_PCIE_HDR_LOG1 |
55753 | #define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
55754 | #define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
55755 | //BIFPLR1_1_PCIE_HDR_LOG2 |
55756 | #define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
55757 | #define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
55758 | //BIFPLR1_1_PCIE_HDR_LOG3 |
55759 | #define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
55760 | #define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
55761 | //BIFPLR1_1_PCIE_ROOT_ERR_CMD |
55762 | #define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
55763 | #define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
55764 | #define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
55765 | #define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
55766 | #define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
55767 | #define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
55768 | //BIFPLR1_1_PCIE_ROOT_ERR_STATUS |
55769 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
55770 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
55771 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
55772 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
55773 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
55774 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
55775 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
55776 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
55777 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
55778 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
55779 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
55780 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
55781 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
55782 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
55783 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
55784 | #define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
55785 | //BIFPLR1_1_PCIE_ERR_SRC_ID |
55786 | #define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
55787 | #define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
55788 | #define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
55789 | #define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
55790 | //BIFPLR1_1_PCIE_TLP_PREFIX_LOG0 |
55791 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
55792 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
55793 | //BIFPLR1_1_PCIE_TLP_PREFIX_LOG1 |
55794 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
55795 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
55796 | //BIFPLR1_1_PCIE_TLP_PREFIX_LOG2 |
55797 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
55798 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
55799 | //BIFPLR1_1_PCIE_TLP_PREFIX_LOG3 |
55800 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
55801 | #define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
55802 | //BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST |
55803 | #define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
55804 | #define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
55805 | #define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
55806 | #define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
55807 | #define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
55808 | #define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
55809 | //BIFPLR1_1_PCIE_LINK_CNTL3 |
55810 | #define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
55811 | #define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
55812 | #define BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
55813 | #define BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
55814 | #define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
55815 | #define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
55816 | #define BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
55817 | #define BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
55818 | //BIFPLR1_1_PCIE_LANE_ERROR_STATUS |
55819 | #define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
55820 | #define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
55821 | #define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
55822 | #define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
55823 | //BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL |
55824 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55825 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55826 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55827 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55828 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55829 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55830 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55831 | #define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55832 | //BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL |
55833 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55834 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55835 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55836 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55837 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55838 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55839 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55840 | #define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55841 | //BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL |
55842 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55843 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55844 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55845 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55846 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55847 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55848 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55849 | #define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55850 | //BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL |
55851 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55852 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55853 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55854 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55855 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55856 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55857 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55858 | #define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55859 | //BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL |
55860 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55861 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55862 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55863 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55864 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55865 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55866 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55867 | #define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55868 | //BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL |
55869 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55870 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55871 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55872 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55873 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55874 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55875 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55876 | #define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55877 | //BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL |
55878 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55879 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55880 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55881 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55882 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55883 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55884 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55885 | #define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55886 | //BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL |
55887 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55888 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55889 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55890 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55891 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55892 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55893 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55894 | #define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55895 | //BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL |
55896 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55897 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55898 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55899 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55900 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55901 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55902 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55903 | #define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55904 | //BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL |
55905 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55906 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55907 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55908 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55909 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55910 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55911 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55912 | #define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55913 | //BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL |
55914 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55915 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55916 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55917 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55918 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55919 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55920 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55921 | #define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55922 | //BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL |
55923 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55924 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55925 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55926 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55927 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55928 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55929 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55930 | #define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55931 | //BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL |
55932 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55933 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55934 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55935 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55936 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55937 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55938 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55939 | #define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55940 | //BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL |
55941 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55942 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55943 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55944 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55945 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55946 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55947 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55948 | #define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55949 | //BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL |
55950 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55951 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55952 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55953 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55954 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55955 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55956 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55957 | #define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55958 | //BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL |
55959 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
55960 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
55961 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
55962 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
55963 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
55964 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
55965 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
55966 | #define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
55967 | //BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST |
55968 | #define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
55969 | #define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
55970 | #define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
55971 | #define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
55972 | #define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
55973 | #define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
55974 | //BIFPLR1_1_PCIE_ACS_CAP |
55975 | #define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
55976 | #define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
55977 | #define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
55978 | #define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
55979 | #define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
55980 | #define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
55981 | #define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
55982 | #define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
55983 | #define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
55984 | #define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
55985 | #define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
55986 | #define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
55987 | #define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
55988 | #define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
55989 | #define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
55990 | #define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
55991 | //BIFPLR1_1_PCIE_ACS_CNTL |
55992 | #define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
55993 | #define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
55994 | #define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
55995 | #define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
55996 | #define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
55997 | #define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
55998 | #define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
55999 | #define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
56000 | #define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
56001 | #define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
56002 | #define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
56003 | #define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
56004 | #define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
56005 | #define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
56006 | //BIFPLR1_1_PCIE_MC_ENH_CAP_LIST |
56007 | #define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
56008 | #define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
56009 | #define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
56010 | #define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
56011 | #define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
56012 | #define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
56013 | //BIFPLR1_1_PCIE_MC_CAP |
56014 | #define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
56015 | #define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
56016 | #define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
56017 | #define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
56018 | //BIFPLR1_1_PCIE_MC_CNTL |
56019 | #define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
56020 | #define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
56021 | #define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
56022 | #define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
56023 | //BIFPLR1_1_PCIE_MC_ADDR0 |
56024 | #define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
56025 | #define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
56026 | #define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
56027 | #define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
56028 | //BIFPLR1_1_PCIE_MC_ADDR1 |
56029 | #define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
56030 | #define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
56031 | //BIFPLR1_1_PCIE_MC_RCV0 |
56032 | #define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
56033 | #define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
56034 | //BIFPLR1_1_PCIE_MC_RCV1 |
56035 | #define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
56036 | #define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
56037 | //BIFPLR1_1_PCIE_MC_BLOCK_ALL0 |
56038 | #define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
56039 | #define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
56040 | //BIFPLR1_1_PCIE_MC_BLOCK_ALL1 |
56041 | #define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
56042 | #define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
56043 | //BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
56044 | #define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
56045 | #define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
56046 | //BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
56047 | #define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
56048 | #define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
56049 | //BIFPLR1_1_PCIE_MC_OVERLAY_BAR0 |
56050 | #define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
56051 | #define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
56052 | #define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
56053 | #define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
56054 | //BIFPLR1_1_PCIE_MC_OVERLAY_BAR1 |
56055 | #define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
56056 | #define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
56057 | //BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST |
56058 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
56059 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
56060 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
56061 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
56062 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
56063 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
56064 | //BIFPLR1_1_PCIE_L1_PM_SUB_CAP |
56065 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
56066 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
56067 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
56068 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
56069 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
56070 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
56071 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
56072 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
56073 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
56074 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
56075 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
56076 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
56077 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
56078 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
56079 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
56080 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
56081 | //BIFPLR1_1_PCIE_L1_PM_SUB_CNTL |
56082 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
56083 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
56084 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
56085 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
56086 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
56087 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
56088 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
56089 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
56090 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
56091 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
56092 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
56093 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
56094 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
56095 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
56096 | //BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2 |
56097 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
56098 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
56099 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
56100 | #define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
56101 | //BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST |
56102 | #define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
56103 | #define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
56104 | #define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
56105 | #define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
56106 | #define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
56107 | #define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
56108 | //BIFPLR1_1_PCIE_DPC_CAP_LIST |
56109 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
56110 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
56111 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
56112 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
56113 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
56114 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
56115 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
56116 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
56117 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
56118 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
56119 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
56120 | #define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
56121 | //BIFPLR1_1_PCIE_DPC_CNTL |
56122 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
56123 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
56124 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
56125 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
56126 | #define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
56127 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
56128 | #define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
56129 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
56130 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
56131 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
56132 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
56133 | #define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
56134 | #define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
56135 | #define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
56136 | //BIFPLR1_1_PCIE_DPC_STATUS |
56137 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
56138 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
56139 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
56140 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
56141 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
56142 | #define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
56143 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
56144 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
56145 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
56146 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
56147 | #define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
56148 | #define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
56149 | //BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID |
56150 | #define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
56151 | #define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
56152 | //BIFPLR1_1_PCIE_RP_PIO_STATUS |
56153 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
56154 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
56155 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
56156 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
56157 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
56158 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
56159 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
56160 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
56161 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
56162 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
56163 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
56164 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
56165 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
56166 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
56167 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
56168 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
56169 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
56170 | #define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
56171 | //BIFPLR1_1_PCIE_RP_PIO_MASK |
56172 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
56173 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
56174 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
56175 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
56176 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
56177 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
56178 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
56179 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
56180 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
56181 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
56182 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
56183 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
56184 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
56185 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
56186 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
56187 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
56188 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
56189 | #define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
56190 | //BIFPLR1_1_PCIE_RP_PIO_SEVERITY |
56191 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
56192 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
56193 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
56194 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
56195 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
56196 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
56197 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
56198 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
56199 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
56200 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
56201 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
56202 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
56203 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
56204 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
56205 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
56206 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
56207 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
56208 | #define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
56209 | //BIFPLR1_1_PCIE_RP_PIO_SYSERROR |
56210 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
56211 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
56212 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
56213 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
56214 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
56215 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
56216 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
56217 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
56218 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
56219 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
56220 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
56221 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
56222 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
56223 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
56224 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
56225 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
56226 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
56227 | #define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
56228 | //BIFPLR1_1_PCIE_RP_PIO_EXCEPTION |
56229 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
56230 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
56231 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
56232 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
56233 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
56234 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
56235 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
56236 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
56237 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
56238 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
56239 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
56240 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
56241 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
56242 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
56243 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
56244 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
56245 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
56246 | #define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
56247 | //BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0 |
56248 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
56249 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
56250 | //BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1 |
56251 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
56252 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
56253 | //BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2 |
56254 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
56255 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
56256 | //BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3 |
56257 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
56258 | #define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
56259 | //BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG |
56260 | #define BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
56261 | #define BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
56262 | //BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0 |
56263 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
56264 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
56265 | //BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1 |
56266 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
56267 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
56268 | //BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2 |
56269 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
56270 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
56271 | //BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3 |
56272 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
56273 | #define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
56274 | //BIFPLR1_1_PCIE_ESM_CAP_LIST |
56275 | #define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
56276 | #define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
56277 | #define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
56278 | #define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
56279 | #define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
56280 | #define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
56281 | //BIFPLR1_1_PCIE_ESM_HEADER_1 |
56282 | #define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
56283 | #define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
56284 | #define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
56285 | #define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
56286 | #define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
56287 | #define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
56288 | //BIFPLR1_1_PCIE_ESM_HEADER_2 |
56289 | #define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
56290 | #define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
56291 | //BIFPLR1_1_PCIE_ESM_STATUS |
56292 | #define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
56293 | #define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
56294 | #define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
56295 | #define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
56296 | //BIFPLR1_1_PCIE_ESM_CTRL |
56297 | #define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
56298 | #define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
56299 | #define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
56300 | #define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
56301 | #define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
56302 | #define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
56303 | //BIFPLR1_1_PCIE_ESM_CAP_1 |
56304 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
56305 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
56306 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
56307 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
56308 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
56309 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
56310 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
56311 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
56312 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
56313 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
56314 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
56315 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
56316 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
56317 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
56318 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
56319 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
56320 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
56321 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
56322 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
56323 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
56324 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
56325 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
56326 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
56327 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
56328 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
56329 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
56330 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
56331 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
56332 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
56333 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
56334 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
56335 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
56336 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
56337 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
56338 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
56339 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
56340 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
56341 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
56342 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
56343 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
56344 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
56345 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
56346 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
56347 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
56348 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
56349 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
56350 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
56351 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
56352 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
56353 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
56354 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
56355 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
56356 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
56357 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
56358 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
56359 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
56360 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
56361 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
56362 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
56363 | #define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
56364 | //BIFPLR1_1_PCIE_ESM_CAP_2 |
56365 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
56366 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
56367 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
56368 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
56369 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
56370 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
56371 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
56372 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
56373 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
56374 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
56375 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
56376 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
56377 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
56378 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
56379 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
56380 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
56381 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
56382 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
56383 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
56384 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
56385 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
56386 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
56387 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
56388 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
56389 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
56390 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
56391 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
56392 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
56393 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
56394 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
56395 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
56396 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
56397 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
56398 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
56399 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
56400 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
56401 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
56402 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
56403 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
56404 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
56405 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
56406 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
56407 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
56408 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
56409 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
56410 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
56411 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
56412 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
56413 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
56414 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
56415 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
56416 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
56417 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
56418 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
56419 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
56420 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
56421 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
56422 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
56423 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
56424 | #define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
56425 | //BIFPLR1_1_PCIE_ESM_CAP_3 |
56426 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
56427 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
56428 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
56429 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
56430 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
56431 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
56432 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
56433 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
56434 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
56435 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
56436 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
56437 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
56438 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
56439 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
56440 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
56441 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
56442 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
56443 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
56444 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
56445 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
56446 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
56447 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
56448 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
56449 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
56450 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
56451 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
56452 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
56453 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
56454 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
56455 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
56456 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
56457 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
56458 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
56459 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
56460 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
56461 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
56462 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
56463 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
56464 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
56465 | #define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
56466 | //BIFPLR1_1_PCIE_ESM_CAP_4 |
56467 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
56468 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
56469 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
56470 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
56471 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
56472 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
56473 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
56474 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
56475 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
56476 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
56477 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
56478 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
56479 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
56480 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
56481 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
56482 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
56483 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
56484 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
56485 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
56486 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
56487 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
56488 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
56489 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
56490 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
56491 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
56492 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
56493 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
56494 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
56495 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
56496 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
56497 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
56498 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
56499 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
56500 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
56501 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
56502 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
56503 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
56504 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
56505 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
56506 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
56507 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
56508 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
56509 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
56510 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
56511 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
56512 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
56513 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
56514 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
56515 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
56516 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
56517 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
56518 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
56519 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
56520 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
56521 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
56522 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
56523 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
56524 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
56525 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
56526 | #define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
56527 | //BIFPLR1_1_PCIE_ESM_CAP_5 |
56528 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
56529 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
56530 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
56531 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
56532 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
56533 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
56534 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
56535 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
56536 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
56537 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
56538 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
56539 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
56540 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
56541 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
56542 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
56543 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
56544 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
56545 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
56546 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
56547 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
56548 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
56549 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
56550 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
56551 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
56552 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
56553 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
56554 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
56555 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
56556 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
56557 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
56558 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
56559 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
56560 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
56561 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
56562 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
56563 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
56564 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
56565 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
56566 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
56567 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
56568 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
56569 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
56570 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
56571 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
56572 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
56573 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
56574 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
56575 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
56576 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
56577 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
56578 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
56579 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
56580 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
56581 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
56582 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
56583 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
56584 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
56585 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
56586 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
56587 | #define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
56588 | //BIFPLR1_1_PCIE_ESM_CAP_6 |
56589 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
56590 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
56591 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
56592 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
56593 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
56594 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
56595 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
56596 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
56597 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
56598 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
56599 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
56600 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
56601 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
56602 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
56603 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
56604 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
56605 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
56606 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
56607 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
56608 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
56609 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
56610 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
56611 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
56612 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
56613 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
56614 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
56615 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
56616 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
56617 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
56618 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
56619 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
56620 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
56621 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
56622 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
56623 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
56624 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
56625 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
56626 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
56627 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
56628 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
56629 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
56630 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
56631 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
56632 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
56633 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
56634 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
56635 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
56636 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
56637 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
56638 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
56639 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
56640 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
56641 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
56642 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
56643 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
56644 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
56645 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
56646 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
56647 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
56648 | #define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
56649 | //BIFPLR1_1_PCIE_ESM_CAP_7 |
56650 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
56651 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
56652 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
56653 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
56654 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
56655 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
56656 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
56657 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
56658 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
56659 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
56660 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
56661 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
56662 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
56663 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
56664 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
56665 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
56666 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
56667 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
56668 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
56669 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
56670 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
56671 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
56672 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
56673 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
56674 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
56675 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
56676 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
56677 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
56678 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
56679 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
56680 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
56681 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
56682 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
56683 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
56684 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
56685 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
56686 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
56687 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
56688 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
56689 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
56690 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
56691 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
56692 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
56693 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
56694 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
56695 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
56696 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
56697 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
56698 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
56699 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
56700 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
56701 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
56702 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
56703 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
56704 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
56705 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
56706 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
56707 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
56708 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
56709 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
56710 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
56711 | #define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
56712 | |
56713 | |
56714 | // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
56715 | //BIFPLR2_1_VENDOR_ID |
56716 | #define BIFPLR2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
56717 | #define BIFPLR2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
56718 | //BIFPLR2_1_DEVICE_ID |
56719 | #define BIFPLR2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
56720 | #define BIFPLR2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
56721 | //BIFPLR2_1_COMMAND |
56722 | #define BIFPLR2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
56723 | #define BIFPLR2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
56724 | #define BIFPLR2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
56725 | #define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
56726 | #define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
56727 | #define BIFPLR2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
56728 | #define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
56729 | #define BIFPLR2_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
56730 | #define BIFPLR2_1_COMMAND__SERR_EN__SHIFT 0x8 |
56731 | #define BIFPLR2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
56732 | #define BIFPLR2_1_COMMAND__INT_DIS__SHIFT 0xa |
56733 | #define BIFPLR2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
56734 | #define BIFPLR2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
56735 | #define BIFPLR2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
56736 | #define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
56737 | #define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
56738 | #define BIFPLR2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
56739 | #define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
56740 | #define BIFPLR2_1_COMMAND__AD_STEPPING_MASK 0x0080L |
56741 | #define BIFPLR2_1_COMMAND__SERR_EN_MASK 0x0100L |
56742 | #define BIFPLR2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
56743 | #define BIFPLR2_1_COMMAND__INT_DIS_MASK 0x0400L |
56744 | //BIFPLR2_1_STATUS |
56745 | #define BIFPLR2_1_STATUS__INT_STATUS__SHIFT 0x3 |
56746 | #define BIFPLR2_1_STATUS__CAP_LIST__SHIFT 0x4 |
56747 | #define BIFPLR2_1_STATUS__PCI_66_EN__SHIFT 0x5 |
56748 | #define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
56749 | #define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
56750 | #define BIFPLR2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
56751 | #define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
56752 | #define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
56753 | #define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
56754 | #define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
56755 | #define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
56756 | #define BIFPLR2_1_STATUS__INT_STATUS_MASK 0x0008L |
56757 | #define BIFPLR2_1_STATUS__CAP_LIST_MASK 0x0010L |
56758 | #define BIFPLR2_1_STATUS__PCI_66_EN_MASK 0x0020L |
56759 | #define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
56760 | #define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
56761 | #define BIFPLR2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
56762 | #define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
56763 | #define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
56764 | #define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
56765 | #define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
56766 | #define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
56767 | //BIFPLR2_1_REVISION_ID |
56768 | #define BIFPLR2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
56769 | #define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
56770 | #define BIFPLR2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
56771 | #define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
56772 | //BIFPLR2_1_PROG_INTERFACE |
56773 | #define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
56774 | #define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
56775 | //BIFPLR2_1_SUB_CLASS |
56776 | #define BIFPLR2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
56777 | #define BIFPLR2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
56778 | //BIFPLR2_1_BASE_CLASS |
56779 | #define BIFPLR2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
56780 | #define BIFPLR2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
56781 | //BIFPLR2_1_CACHE_LINE |
56782 | #define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
56783 | #define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
56784 | //BIFPLR2_1_LATENCY |
56785 | #define BIFPLR2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
56786 | #define BIFPLR2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
56787 | //BIFPLR2_1_HEADER |
56788 | #define BIFPLR2_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
56789 | #define BIFPLR2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
56790 | #define BIFPLR2_1_HEADER__HEADER_TYPE_MASK 0x7FL |
56791 | #define BIFPLR2_1_HEADER__DEVICE_TYPE_MASK 0x80L |
56792 | //BIFPLR2_1_BIST |
56793 | #define BIFPLR2_1_BIST__BIST_COMP__SHIFT 0x0 |
56794 | #define BIFPLR2_1_BIST__BIST_STRT__SHIFT 0x6 |
56795 | #define BIFPLR2_1_BIST__BIST_CAP__SHIFT 0x7 |
56796 | #define BIFPLR2_1_BIST__BIST_COMP_MASK 0x0FL |
56797 | #define BIFPLR2_1_BIST__BIST_STRT_MASK 0x40L |
56798 | #define BIFPLR2_1_BIST__BIST_CAP_MASK 0x80L |
56799 | //BIFPLR2_1_SUB_BUS_NUMBER_LATENCY |
56800 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
56801 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
56802 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
56803 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
56804 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
56805 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
56806 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
56807 | #define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
56808 | //BIFPLR2_1_IO_BASE_LIMIT |
56809 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
56810 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
56811 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
56812 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
56813 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
56814 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
56815 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
56816 | #define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
56817 | //BIFPLR2_1_SECONDARY_STATUS |
56818 | #define BIFPLR2_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
56819 | #define BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
56820 | #define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
56821 | #define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
56822 | #define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
56823 | #define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
56824 | #define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
56825 | #define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
56826 | #define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
56827 | #define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
56828 | #define BIFPLR2_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
56829 | #define BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
56830 | #define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
56831 | #define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
56832 | #define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
56833 | #define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
56834 | #define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
56835 | #define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
56836 | #define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
56837 | #define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
56838 | //BIFPLR2_1_MEM_BASE_LIMIT |
56839 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
56840 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
56841 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
56842 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
56843 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
56844 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
56845 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
56846 | #define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
56847 | //BIFPLR2_1_PREF_BASE_LIMIT |
56848 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
56849 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
56850 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
56851 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
56852 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
56853 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
56854 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
56855 | #define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
56856 | //BIFPLR2_1_PREF_BASE_UPPER |
56857 | #define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
56858 | #define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
56859 | //BIFPLR2_1_PREF_LIMIT_UPPER |
56860 | #define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
56861 | #define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
56862 | //BIFPLR2_1_IO_BASE_LIMIT_HI |
56863 | #define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
56864 | #define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
56865 | #define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
56866 | #define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
56867 | //BIFPLR2_1_CAP_PTR |
56868 | #define BIFPLR2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
56869 | #define BIFPLR2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
56870 | //BIFPLR2_1_INTERRUPT_LINE |
56871 | #define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
56872 | #define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
56873 | //BIFPLR2_1_INTERRUPT_PIN |
56874 | #define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
56875 | #define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
56876 | //BIFPLR2_1_IRQ_BRIDGE_CNTL |
56877 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
56878 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
56879 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
56880 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
56881 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
56882 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
56883 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
56884 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
56885 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
56886 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
56887 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
56888 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
56889 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
56890 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
56891 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
56892 | #define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
56893 | //BIFPLR2_1_EXT_BRIDGE_CNTL |
56894 | #define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
56895 | #define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
56896 | //BIFPLR2_1_PMI_CAP_LIST |
56897 | #define BIFPLR2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
56898 | #define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
56899 | #define BIFPLR2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
56900 | #define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
56901 | //BIFPLR2_1_PMI_CAP |
56902 | #define BIFPLR2_1_PMI_CAP__VERSION__SHIFT 0x0 |
56903 | #define BIFPLR2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
56904 | #define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
56905 | #define BIFPLR2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
56906 | #define BIFPLR2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
56907 | #define BIFPLR2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
56908 | #define BIFPLR2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
56909 | #define BIFPLR2_1_PMI_CAP__VERSION_MASK 0x0007L |
56910 | #define BIFPLR2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
56911 | #define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
56912 | #define BIFPLR2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
56913 | #define BIFPLR2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
56914 | #define BIFPLR2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
56915 | #define BIFPLR2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
56916 | //BIFPLR2_1_PMI_STATUS_CNTL |
56917 | #define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
56918 | #define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
56919 | #define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
56920 | #define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
56921 | #define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
56922 | #define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
56923 | #define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
56924 | #define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
56925 | #define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
56926 | #define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
56927 | #define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
56928 | #define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
56929 | #define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
56930 | #define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
56931 | #define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
56932 | #define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
56933 | #define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
56934 | #define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
56935 | //BIFPLR2_1_PCIE_CAP_LIST |
56936 | #define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
56937 | #define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
56938 | #define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
56939 | #define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
56940 | //BIFPLR2_1_PCIE_CAP |
56941 | #define BIFPLR2_1_PCIE_CAP__VERSION__SHIFT 0x0 |
56942 | #define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
56943 | #define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
56944 | #define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
56945 | #define BIFPLR2_1_PCIE_CAP__VERSION_MASK 0x000FL |
56946 | #define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
56947 | #define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
56948 | #define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
56949 | //BIFPLR2_1_DEVICE_CAP |
56950 | #define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
56951 | #define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
56952 | #define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
56953 | #define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
56954 | #define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
56955 | #define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
56956 | #define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
56957 | #define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
56958 | #define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
56959 | #define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
56960 | #define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
56961 | #define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
56962 | #define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
56963 | #define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
56964 | #define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
56965 | #define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
56966 | #define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
56967 | #define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
56968 | //BIFPLR2_1_DEVICE_CNTL |
56969 | #define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
56970 | #define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
56971 | #define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
56972 | #define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
56973 | #define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
56974 | #define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
56975 | #define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
56976 | #define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
56977 | #define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
56978 | #define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
56979 | #define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
56980 | #define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
56981 | #define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
56982 | #define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
56983 | #define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
56984 | #define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
56985 | #define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
56986 | #define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
56987 | #define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
56988 | #define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
56989 | #define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
56990 | #define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
56991 | #define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
56992 | #define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
56993 | //BIFPLR2_1_DEVICE_STATUS |
56994 | #define BIFPLR2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
56995 | #define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
56996 | #define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
56997 | #define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
56998 | #define BIFPLR2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
56999 | #define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
57000 | #define BIFPLR2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
57001 | #define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
57002 | #define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
57003 | #define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
57004 | #define BIFPLR2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
57005 | #define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
57006 | //BIFPLR2_1_LINK_CAP |
57007 | #define BIFPLR2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
57008 | #define BIFPLR2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
57009 | #define BIFPLR2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
57010 | #define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
57011 | #define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
57012 | #define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
57013 | #define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
57014 | #define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
57015 | #define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
57016 | #define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
57017 | #define BIFPLR2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
57018 | #define BIFPLR2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
57019 | #define BIFPLR2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
57020 | #define BIFPLR2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
57021 | #define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
57022 | #define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
57023 | #define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
57024 | #define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
57025 | #define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
57026 | #define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
57027 | #define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
57028 | #define BIFPLR2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
57029 | //BIFPLR2_1_LINK_CNTL |
57030 | #define BIFPLR2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
57031 | #define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
57032 | #define BIFPLR2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
57033 | #define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
57034 | #define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
57035 | #define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
57036 | #define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
57037 | #define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
57038 | #define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
57039 | #define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
57040 | #define BIFPLR2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
57041 | #define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
57042 | #define BIFPLR2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
57043 | #define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
57044 | #define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
57045 | #define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
57046 | #define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
57047 | #define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
57048 | #define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
57049 | #define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
57050 | //BIFPLR2_1_LINK_STATUS |
57051 | #define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
57052 | #define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
57053 | #define BIFPLR2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
57054 | #define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
57055 | #define BIFPLR2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
57056 | #define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
57057 | #define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
57058 | #define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
57059 | #define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
57060 | #define BIFPLR2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
57061 | #define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
57062 | #define BIFPLR2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
57063 | #define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
57064 | #define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
57065 | //BIFPLR2_1_SLOT_CAP |
57066 | #define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
57067 | #define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
57068 | #define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
57069 | #define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
57070 | #define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
57071 | #define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
57072 | #define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
57073 | #define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
57074 | #define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
57075 | #define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
57076 | #define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
57077 | #define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
57078 | #define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
57079 | #define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
57080 | #define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
57081 | #define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
57082 | #define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
57083 | #define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
57084 | #define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
57085 | #define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
57086 | #define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
57087 | #define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
57088 | #define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
57089 | #define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
57090 | //BIFPLR2_1_SLOT_CNTL |
57091 | #define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
57092 | #define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
57093 | #define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
57094 | #define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
57095 | #define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
57096 | #define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
57097 | #define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
57098 | #define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
57099 | #define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
57100 | #define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
57101 | #define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
57102 | #define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
57103 | #define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
57104 | #define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
57105 | #define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
57106 | #define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
57107 | #define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
57108 | #define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
57109 | #define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
57110 | #define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
57111 | #define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
57112 | #define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
57113 | #define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
57114 | #define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
57115 | //BIFPLR2_1_SLOT_STATUS |
57116 | #define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
57117 | #define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
57118 | #define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
57119 | #define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
57120 | #define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
57121 | #define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
57122 | #define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
57123 | #define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
57124 | #define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
57125 | #define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
57126 | #define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
57127 | #define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
57128 | #define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
57129 | #define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
57130 | #define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
57131 | #define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
57132 | #define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
57133 | #define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
57134 | //BIFPLR2_1_ROOT_CNTL |
57135 | #define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
57136 | #define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
57137 | #define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
57138 | #define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
57139 | #define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
57140 | #define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
57141 | #define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
57142 | #define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
57143 | #define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
57144 | #define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
57145 | //BIFPLR2_1_ROOT_CAP |
57146 | #define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
57147 | #define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
57148 | //BIFPLR2_1_ROOT_STATUS |
57149 | #define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
57150 | #define BIFPLR2_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
57151 | #define BIFPLR2_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
57152 | #define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
57153 | #define BIFPLR2_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
57154 | #define BIFPLR2_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
57155 | //BIFPLR2_1_DEVICE_CAP2 |
57156 | #define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
57157 | #define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
57158 | #define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
57159 | #define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
57160 | #define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
57161 | #define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
57162 | #define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
57163 | #define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
57164 | #define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
57165 | #define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
57166 | #define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
57167 | #define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
57168 | #define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
57169 | #define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
57170 | #define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
57171 | #define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
57172 | #define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
57173 | #define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
57174 | #define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
57175 | #define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
57176 | #define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
57177 | #define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
57178 | #define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
57179 | #define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
57180 | #define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
57181 | #define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
57182 | #define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
57183 | #define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
57184 | //BIFPLR2_1_DEVICE_CNTL2 |
57185 | #define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
57186 | #define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
57187 | #define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
57188 | #define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
57189 | #define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
57190 | #define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
57191 | #define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
57192 | #define BIFPLR2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
57193 | #define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
57194 | #define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
57195 | #define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
57196 | #define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
57197 | #define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
57198 | #define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
57199 | #define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
57200 | #define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
57201 | #define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
57202 | #define BIFPLR2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
57203 | #define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
57204 | #define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
57205 | //BIFPLR2_1_DEVICE_STATUS2 |
57206 | #define BIFPLR2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
57207 | #define BIFPLR2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
57208 | //BIFPLR2_1_LINK_CAP2 |
57209 | #define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
57210 | #define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
57211 | #define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
57212 | #define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
57213 | #define BIFPLR2_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
57214 | #define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
57215 | #define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
57216 | #define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
57217 | #define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
57218 | #define BIFPLR2_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
57219 | //BIFPLR2_1_LINK_CNTL2 |
57220 | #define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
57221 | #define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
57222 | #define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
57223 | #define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
57224 | #define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
57225 | #define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
57226 | #define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
57227 | #define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
57228 | #define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
57229 | #define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
57230 | #define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
57231 | #define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
57232 | #define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
57233 | #define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
57234 | #define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
57235 | #define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
57236 | //BIFPLR2_1_LINK_STATUS2 |
57237 | #define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
57238 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
57239 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
57240 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
57241 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
57242 | #define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
57243 | #define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
57244 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
57245 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
57246 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
57247 | #define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
57248 | #define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
57249 | //BIFPLR2_1_SLOT_CAP2 |
57250 | #define BIFPLR2_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
57251 | #define BIFPLR2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
57252 | //BIFPLR2_1_SLOT_CNTL2 |
57253 | #define BIFPLR2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
57254 | #define BIFPLR2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
57255 | //BIFPLR2_1_SLOT_STATUS2 |
57256 | #define BIFPLR2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
57257 | #define BIFPLR2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
57258 | //BIFPLR2_1_MSI_CAP_LIST |
57259 | #define BIFPLR2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
57260 | #define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
57261 | #define BIFPLR2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
57262 | #define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
57263 | //BIFPLR2_1_MSI_MSG_CNTL |
57264 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
57265 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
57266 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
57267 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
57268 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
57269 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
57270 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
57271 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
57272 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
57273 | #define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
57274 | //BIFPLR2_1_MSI_MSG_ADDR_LO |
57275 | #define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
57276 | #define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
57277 | //BIFPLR2_1_MSI_MSG_ADDR_HI |
57278 | #define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
57279 | #define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
57280 | //BIFPLR2_1_MSI_MSG_DATA |
57281 | #define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
57282 | #define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
57283 | //BIFPLR2_1_MSI_MSG_DATA_64 |
57284 | #define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
57285 | #define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
57286 | //BIFPLR2_1_SSID_CAP_LIST |
57287 | #define BIFPLR2_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
57288 | #define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
57289 | #define BIFPLR2_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
57290 | #define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
57291 | //BIFPLR2_1_SSID_CAP |
57292 | #define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
57293 | #define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
57294 | #define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
57295 | #define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
57296 | //BIFPLR2_1_MSI_MAP_CAP_LIST |
57297 | #define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
57298 | #define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
57299 | #define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
57300 | #define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
57301 | //BIFPLR2_1_MSI_MAP_CAP |
57302 | #define BIFPLR2_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
57303 | #define BIFPLR2_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
57304 | #define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
57305 | #define BIFPLR2_1_MSI_MAP_CAP__EN_MASK 0x0001L |
57306 | #define BIFPLR2_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
57307 | #define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
57308 | //BIFPLR2_1_MSI_MAP_ADDR_LO |
57309 | #define BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
57310 | #define BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
57311 | //BIFPLR2_1_MSI_MAP_ADDR_HI |
57312 | #define BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
57313 | #define BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
57314 | //BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
57315 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57316 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57317 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57318 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57319 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57320 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57321 | //BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR |
57322 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
57323 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
57324 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
57325 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
57326 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
57327 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
57328 | //BIFPLR2_1_PCIE_VENDOR_SPECIFIC1 |
57329 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
57330 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
57331 | //BIFPLR2_1_PCIE_VENDOR_SPECIFIC2 |
57332 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
57333 | #define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
57334 | //BIFPLR2_1_PCIE_VC_ENH_CAP_LIST |
57335 | #define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57336 | #define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57337 | #define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57338 | #define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57339 | #define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57340 | #define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57341 | //BIFPLR2_1_PCIE_PORT_VC_CAP_REG1 |
57342 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
57343 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
57344 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
57345 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
57346 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
57347 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
57348 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
57349 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
57350 | //BIFPLR2_1_PCIE_PORT_VC_CAP_REG2 |
57351 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
57352 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
57353 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
57354 | #define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
57355 | //BIFPLR2_1_PCIE_PORT_VC_CNTL |
57356 | #define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
57357 | #define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
57358 | #define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
57359 | #define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
57360 | //BIFPLR2_1_PCIE_PORT_VC_STATUS |
57361 | #define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
57362 | #define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
57363 | //BIFPLR2_1_PCIE_VC0_RESOURCE_CAP |
57364 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
57365 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
57366 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
57367 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
57368 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
57369 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
57370 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
57371 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
57372 | //BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL |
57373 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
57374 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
57375 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
57376 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
57377 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
57378 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
57379 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
57380 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
57381 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
57382 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
57383 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
57384 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
57385 | //BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS |
57386 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
57387 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
57388 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
57389 | #define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
57390 | //BIFPLR2_1_PCIE_VC1_RESOURCE_CAP |
57391 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
57392 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
57393 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
57394 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
57395 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
57396 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
57397 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
57398 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
57399 | //BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL |
57400 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
57401 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
57402 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
57403 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
57404 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
57405 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
57406 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
57407 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
57408 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
57409 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
57410 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
57411 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
57412 | //BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS |
57413 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
57414 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
57415 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
57416 | #define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
57417 | //BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
57418 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57419 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57420 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57421 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57422 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57423 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57424 | //BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1 |
57425 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
57426 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
57427 | //BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2 |
57428 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
57429 | #define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
57430 | //BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
57431 | #define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57432 | #define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57433 | #define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57434 | #define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57435 | #define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57436 | #define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57437 | //BIFPLR2_1_PCIE_UNCORR_ERR_STATUS |
57438 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
57439 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
57440 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
57441 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
57442 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
57443 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
57444 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
57445 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
57446 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
57447 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
57448 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
57449 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
57450 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
57451 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
57452 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
57453 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
57454 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
57455 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
57456 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
57457 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
57458 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
57459 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
57460 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
57461 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
57462 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
57463 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
57464 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
57465 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
57466 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
57467 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
57468 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
57469 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
57470 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
57471 | #define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
57472 | //BIFPLR2_1_PCIE_UNCORR_ERR_MASK |
57473 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
57474 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
57475 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
57476 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
57477 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
57478 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
57479 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
57480 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
57481 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
57482 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
57483 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
57484 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
57485 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
57486 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
57487 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
57488 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
57489 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
57490 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
57491 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
57492 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
57493 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
57494 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
57495 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
57496 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
57497 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
57498 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
57499 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
57500 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
57501 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
57502 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
57503 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
57504 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
57505 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
57506 | #define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
57507 | //BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY |
57508 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
57509 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
57510 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
57511 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
57512 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
57513 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
57514 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
57515 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
57516 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
57517 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
57518 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
57519 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
57520 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
57521 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
57522 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
57523 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
57524 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
57525 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
57526 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
57527 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
57528 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
57529 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
57530 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
57531 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
57532 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
57533 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
57534 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
57535 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
57536 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
57537 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
57538 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
57539 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
57540 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
57541 | #define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
57542 | //BIFPLR2_1_PCIE_CORR_ERR_STATUS |
57543 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
57544 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
57545 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
57546 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
57547 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
57548 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
57549 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
57550 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
57551 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
57552 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
57553 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
57554 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
57555 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
57556 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
57557 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
57558 | #define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
57559 | //BIFPLR2_1_PCIE_CORR_ERR_MASK |
57560 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
57561 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
57562 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
57563 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
57564 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
57565 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
57566 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
57567 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
57568 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
57569 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
57570 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
57571 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
57572 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
57573 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
57574 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
57575 | #define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
57576 | //BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL |
57577 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
57578 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
57579 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
57580 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
57581 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
57582 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
57583 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
57584 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
57585 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
57586 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
57587 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
57588 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
57589 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
57590 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
57591 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
57592 | #define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
57593 | //BIFPLR2_1_PCIE_HDR_LOG0 |
57594 | #define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
57595 | #define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
57596 | //BIFPLR2_1_PCIE_HDR_LOG1 |
57597 | #define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
57598 | #define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
57599 | //BIFPLR2_1_PCIE_HDR_LOG2 |
57600 | #define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
57601 | #define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
57602 | //BIFPLR2_1_PCIE_HDR_LOG3 |
57603 | #define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
57604 | #define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
57605 | //BIFPLR2_1_PCIE_ROOT_ERR_CMD |
57606 | #define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
57607 | #define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
57608 | #define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
57609 | #define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
57610 | #define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
57611 | #define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
57612 | //BIFPLR2_1_PCIE_ROOT_ERR_STATUS |
57613 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
57614 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
57615 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
57616 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
57617 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
57618 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
57619 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
57620 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
57621 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
57622 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
57623 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
57624 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
57625 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
57626 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
57627 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
57628 | #define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
57629 | //BIFPLR2_1_PCIE_ERR_SRC_ID |
57630 | #define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
57631 | #define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
57632 | #define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
57633 | #define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
57634 | //BIFPLR2_1_PCIE_TLP_PREFIX_LOG0 |
57635 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
57636 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
57637 | //BIFPLR2_1_PCIE_TLP_PREFIX_LOG1 |
57638 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
57639 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
57640 | //BIFPLR2_1_PCIE_TLP_PREFIX_LOG2 |
57641 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
57642 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
57643 | //BIFPLR2_1_PCIE_TLP_PREFIX_LOG3 |
57644 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
57645 | #define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
57646 | //BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST |
57647 | #define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57648 | #define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57649 | #define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57650 | #define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57651 | #define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57652 | #define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57653 | //BIFPLR2_1_PCIE_LINK_CNTL3 |
57654 | #define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
57655 | #define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
57656 | #define BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
57657 | #define BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
57658 | #define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
57659 | #define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
57660 | #define BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
57661 | #define BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
57662 | //BIFPLR2_1_PCIE_LANE_ERROR_STATUS |
57663 | #define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
57664 | #define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
57665 | #define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
57666 | #define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
57667 | //BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL |
57668 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57669 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57670 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57671 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57672 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57673 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57674 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57675 | #define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57676 | //BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL |
57677 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57678 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57679 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57680 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57681 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57682 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57683 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57684 | #define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57685 | //BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL |
57686 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57687 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57688 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57689 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57690 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57691 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57692 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57693 | #define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57694 | //BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL |
57695 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57696 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57697 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57698 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57699 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57700 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57701 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57702 | #define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57703 | //BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL |
57704 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57705 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57706 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57707 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57708 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57709 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57710 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57711 | #define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57712 | //BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL |
57713 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57714 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57715 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57716 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57717 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57718 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57719 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57720 | #define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57721 | //BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL |
57722 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57723 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57724 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57725 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57726 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57727 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57728 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57729 | #define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57730 | //BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL |
57731 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57732 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57733 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57734 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57735 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57736 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57737 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57738 | #define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57739 | //BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL |
57740 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57741 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57742 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57743 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57744 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57745 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57746 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57747 | #define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57748 | //BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL |
57749 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57750 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57751 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57752 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57753 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57754 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57755 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57756 | #define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57757 | //BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL |
57758 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57759 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57760 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57761 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57762 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57763 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57764 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57765 | #define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57766 | //BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL |
57767 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57768 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57769 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57770 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57771 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57772 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57773 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57774 | #define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57775 | //BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL |
57776 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57777 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57778 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57779 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57780 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57781 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57782 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57783 | #define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57784 | //BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL |
57785 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57786 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57787 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57788 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57789 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57790 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57791 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57792 | #define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57793 | //BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL |
57794 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57795 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57796 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57797 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57798 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57799 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57800 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57801 | #define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57802 | //BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL |
57803 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
57804 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
57805 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
57806 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
57807 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
57808 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
57809 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
57810 | #define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
57811 | //BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST |
57812 | #define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57813 | #define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57814 | #define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57815 | #define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57816 | #define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57817 | #define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57818 | //BIFPLR2_1_PCIE_ACS_CAP |
57819 | #define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
57820 | #define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
57821 | #define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
57822 | #define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
57823 | #define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
57824 | #define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
57825 | #define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
57826 | #define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
57827 | #define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
57828 | #define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
57829 | #define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
57830 | #define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
57831 | #define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
57832 | #define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
57833 | #define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
57834 | #define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
57835 | //BIFPLR2_1_PCIE_ACS_CNTL |
57836 | #define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
57837 | #define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
57838 | #define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
57839 | #define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
57840 | #define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
57841 | #define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
57842 | #define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
57843 | #define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
57844 | #define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
57845 | #define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
57846 | #define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
57847 | #define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
57848 | #define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
57849 | #define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
57850 | //BIFPLR2_1_PCIE_MC_ENH_CAP_LIST |
57851 | #define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57852 | #define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57853 | #define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57854 | #define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57855 | #define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57856 | #define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57857 | //BIFPLR2_1_PCIE_MC_CAP |
57858 | #define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
57859 | #define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
57860 | #define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
57861 | #define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
57862 | //BIFPLR2_1_PCIE_MC_CNTL |
57863 | #define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
57864 | #define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
57865 | #define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
57866 | #define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
57867 | //BIFPLR2_1_PCIE_MC_ADDR0 |
57868 | #define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
57869 | #define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
57870 | #define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
57871 | #define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
57872 | //BIFPLR2_1_PCIE_MC_ADDR1 |
57873 | #define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
57874 | #define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
57875 | //BIFPLR2_1_PCIE_MC_RCV0 |
57876 | #define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
57877 | #define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
57878 | //BIFPLR2_1_PCIE_MC_RCV1 |
57879 | #define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
57880 | #define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
57881 | //BIFPLR2_1_PCIE_MC_BLOCK_ALL0 |
57882 | #define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
57883 | #define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
57884 | //BIFPLR2_1_PCIE_MC_BLOCK_ALL1 |
57885 | #define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
57886 | #define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
57887 | //BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
57888 | #define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
57889 | #define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
57890 | //BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
57891 | #define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
57892 | #define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
57893 | //BIFPLR2_1_PCIE_MC_OVERLAY_BAR0 |
57894 | #define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
57895 | #define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
57896 | #define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
57897 | #define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
57898 | //BIFPLR2_1_PCIE_MC_OVERLAY_BAR1 |
57899 | #define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
57900 | #define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
57901 | //BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST |
57902 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
57903 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
57904 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57905 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57906 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57907 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57908 | //BIFPLR2_1_PCIE_L1_PM_SUB_CAP |
57909 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
57910 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
57911 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
57912 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
57913 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
57914 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
57915 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
57916 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
57917 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
57918 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
57919 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
57920 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
57921 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
57922 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
57923 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
57924 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
57925 | //BIFPLR2_1_PCIE_L1_PM_SUB_CNTL |
57926 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
57927 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
57928 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
57929 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
57930 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
57931 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
57932 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
57933 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
57934 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
57935 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
57936 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
57937 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
57938 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
57939 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
57940 | //BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2 |
57941 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
57942 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
57943 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
57944 | #define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
57945 | //BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST |
57946 | #define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
57947 | #define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
57948 | #define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
57949 | #define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
57950 | #define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
57951 | #define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
57952 | //BIFPLR2_1_PCIE_DPC_CAP_LIST |
57953 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
57954 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
57955 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
57956 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
57957 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
57958 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
57959 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
57960 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
57961 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
57962 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
57963 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
57964 | #define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
57965 | //BIFPLR2_1_PCIE_DPC_CNTL |
57966 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
57967 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
57968 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
57969 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
57970 | #define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
57971 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
57972 | #define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
57973 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
57974 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
57975 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
57976 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
57977 | #define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
57978 | #define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
57979 | #define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
57980 | //BIFPLR2_1_PCIE_DPC_STATUS |
57981 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
57982 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
57983 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
57984 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
57985 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
57986 | #define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
57987 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
57988 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
57989 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
57990 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
57991 | #define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
57992 | #define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
57993 | //BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID |
57994 | #define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
57995 | #define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
57996 | //BIFPLR2_1_PCIE_RP_PIO_STATUS |
57997 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
57998 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
57999 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
58000 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
58001 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
58002 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
58003 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
58004 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
58005 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
58006 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
58007 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
58008 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
58009 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
58010 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
58011 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
58012 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
58013 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
58014 | #define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
58015 | //BIFPLR2_1_PCIE_RP_PIO_MASK |
58016 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
58017 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
58018 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
58019 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
58020 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
58021 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
58022 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
58023 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
58024 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
58025 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
58026 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
58027 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
58028 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
58029 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
58030 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
58031 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
58032 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
58033 | #define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
58034 | //BIFPLR2_1_PCIE_RP_PIO_SEVERITY |
58035 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
58036 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
58037 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
58038 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
58039 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
58040 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
58041 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
58042 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
58043 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
58044 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
58045 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
58046 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
58047 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
58048 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
58049 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
58050 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
58051 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
58052 | #define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
58053 | //BIFPLR2_1_PCIE_RP_PIO_SYSERROR |
58054 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
58055 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
58056 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
58057 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
58058 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
58059 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
58060 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
58061 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
58062 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
58063 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
58064 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
58065 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
58066 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
58067 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
58068 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
58069 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
58070 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
58071 | #define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
58072 | //BIFPLR2_1_PCIE_RP_PIO_EXCEPTION |
58073 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
58074 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
58075 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
58076 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
58077 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
58078 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
58079 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
58080 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
58081 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
58082 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
58083 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
58084 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
58085 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
58086 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
58087 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
58088 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
58089 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
58090 | #define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
58091 | //BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0 |
58092 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
58093 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
58094 | //BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1 |
58095 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
58096 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
58097 | //BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2 |
58098 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
58099 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
58100 | //BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3 |
58101 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
58102 | #define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
58103 | //BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG |
58104 | #define BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
58105 | #define BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
58106 | //BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0 |
58107 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
58108 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
58109 | //BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1 |
58110 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
58111 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
58112 | //BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2 |
58113 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
58114 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
58115 | //BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3 |
58116 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
58117 | #define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
58118 | //BIFPLR2_1_PCIE_ESM_CAP_LIST |
58119 | #define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
58120 | #define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
58121 | #define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
58122 | #define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
58123 | #define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
58124 | #define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
58125 | //BIFPLR2_1_PCIE_ESM_HEADER_1 |
58126 | #define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
58127 | #define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
58128 | #define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
58129 | #define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
58130 | #define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
58131 | #define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
58132 | //BIFPLR2_1_PCIE_ESM_HEADER_2 |
58133 | #define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
58134 | #define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
58135 | //BIFPLR2_1_PCIE_ESM_STATUS |
58136 | #define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
58137 | #define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
58138 | #define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
58139 | #define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
58140 | //BIFPLR2_1_PCIE_ESM_CTRL |
58141 | #define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
58142 | #define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
58143 | #define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
58144 | #define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
58145 | #define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
58146 | #define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
58147 | //BIFPLR2_1_PCIE_ESM_CAP_1 |
58148 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
58149 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
58150 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
58151 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
58152 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
58153 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
58154 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
58155 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
58156 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
58157 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
58158 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
58159 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
58160 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
58161 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
58162 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
58163 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
58164 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
58165 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
58166 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
58167 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
58168 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
58169 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
58170 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
58171 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
58172 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
58173 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
58174 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
58175 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
58176 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
58177 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
58178 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
58179 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
58180 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
58181 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
58182 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
58183 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
58184 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
58185 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
58186 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
58187 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
58188 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
58189 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
58190 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
58191 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
58192 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
58193 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
58194 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
58195 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
58196 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
58197 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
58198 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
58199 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
58200 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
58201 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
58202 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
58203 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
58204 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
58205 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
58206 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
58207 | #define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
58208 | //BIFPLR2_1_PCIE_ESM_CAP_2 |
58209 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
58210 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
58211 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
58212 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
58213 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
58214 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
58215 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
58216 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
58217 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
58218 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
58219 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
58220 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
58221 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
58222 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
58223 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
58224 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
58225 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
58226 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
58227 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
58228 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
58229 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
58230 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
58231 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
58232 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
58233 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
58234 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
58235 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
58236 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
58237 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
58238 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
58239 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
58240 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
58241 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
58242 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
58243 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
58244 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
58245 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
58246 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
58247 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
58248 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
58249 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
58250 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
58251 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
58252 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
58253 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
58254 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
58255 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
58256 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
58257 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
58258 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
58259 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
58260 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
58261 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
58262 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
58263 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
58264 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
58265 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
58266 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
58267 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
58268 | #define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
58269 | //BIFPLR2_1_PCIE_ESM_CAP_3 |
58270 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
58271 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
58272 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
58273 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
58274 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
58275 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
58276 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
58277 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
58278 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
58279 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
58280 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
58281 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
58282 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
58283 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
58284 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
58285 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
58286 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
58287 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
58288 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
58289 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
58290 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
58291 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
58292 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
58293 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
58294 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
58295 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
58296 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
58297 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
58298 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
58299 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
58300 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
58301 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
58302 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
58303 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
58304 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
58305 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
58306 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
58307 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
58308 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
58309 | #define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
58310 | //BIFPLR2_1_PCIE_ESM_CAP_4 |
58311 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
58312 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
58313 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
58314 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
58315 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
58316 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
58317 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
58318 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
58319 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
58320 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
58321 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
58322 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
58323 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
58324 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
58325 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
58326 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
58327 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
58328 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
58329 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
58330 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
58331 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
58332 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
58333 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
58334 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
58335 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
58336 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
58337 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
58338 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
58339 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
58340 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
58341 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
58342 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
58343 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
58344 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
58345 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
58346 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
58347 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
58348 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
58349 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
58350 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
58351 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
58352 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
58353 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
58354 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
58355 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
58356 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
58357 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
58358 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
58359 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
58360 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
58361 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
58362 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
58363 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
58364 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
58365 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
58366 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
58367 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
58368 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
58369 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
58370 | #define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
58371 | //BIFPLR2_1_PCIE_ESM_CAP_5 |
58372 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
58373 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
58374 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
58375 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
58376 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
58377 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
58378 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
58379 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
58380 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
58381 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
58382 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
58383 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
58384 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
58385 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
58386 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
58387 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
58388 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
58389 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
58390 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
58391 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
58392 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
58393 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
58394 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
58395 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
58396 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
58397 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
58398 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
58399 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
58400 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
58401 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
58402 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
58403 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
58404 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
58405 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
58406 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
58407 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
58408 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
58409 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
58410 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
58411 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
58412 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
58413 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
58414 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
58415 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
58416 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
58417 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
58418 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
58419 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
58420 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
58421 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
58422 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
58423 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
58424 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
58425 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
58426 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
58427 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
58428 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
58429 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
58430 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
58431 | #define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
58432 | //BIFPLR2_1_PCIE_ESM_CAP_6 |
58433 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
58434 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
58435 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
58436 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
58437 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
58438 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
58439 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
58440 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
58441 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
58442 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
58443 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
58444 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
58445 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
58446 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
58447 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
58448 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
58449 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
58450 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
58451 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
58452 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
58453 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
58454 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
58455 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
58456 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
58457 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
58458 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
58459 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
58460 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
58461 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
58462 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
58463 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
58464 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
58465 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
58466 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
58467 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
58468 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
58469 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
58470 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
58471 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
58472 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
58473 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
58474 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
58475 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
58476 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
58477 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
58478 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
58479 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
58480 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
58481 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
58482 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
58483 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
58484 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
58485 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
58486 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
58487 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
58488 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
58489 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
58490 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
58491 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
58492 | #define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
58493 | //BIFPLR2_1_PCIE_ESM_CAP_7 |
58494 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
58495 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
58496 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
58497 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
58498 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
58499 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
58500 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
58501 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
58502 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
58503 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
58504 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
58505 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
58506 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
58507 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
58508 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
58509 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
58510 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
58511 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
58512 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
58513 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
58514 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
58515 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
58516 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
58517 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
58518 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
58519 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
58520 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
58521 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
58522 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
58523 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
58524 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
58525 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
58526 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
58527 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
58528 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
58529 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
58530 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
58531 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
58532 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
58533 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
58534 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
58535 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
58536 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
58537 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
58538 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
58539 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
58540 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
58541 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
58542 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
58543 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
58544 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
58545 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
58546 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
58547 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
58548 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
58549 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
58550 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
58551 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
58552 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
58553 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
58554 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
58555 | #define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
58556 | |
58557 | |
58558 | // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
58559 | //BIFPLR3_1_VENDOR_ID |
58560 | #define BIFPLR3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
58561 | #define BIFPLR3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
58562 | //BIFPLR3_1_DEVICE_ID |
58563 | #define BIFPLR3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
58564 | #define BIFPLR3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
58565 | //BIFPLR3_1_COMMAND |
58566 | #define BIFPLR3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
58567 | #define BIFPLR3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
58568 | #define BIFPLR3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
58569 | #define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
58570 | #define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
58571 | #define BIFPLR3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
58572 | #define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
58573 | #define BIFPLR3_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
58574 | #define BIFPLR3_1_COMMAND__SERR_EN__SHIFT 0x8 |
58575 | #define BIFPLR3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
58576 | #define BIFPLR3_1_COMMAND__INT_DIS__SHIFT 0xa |
58577 | #define BIFPLR3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
58578 | #define BIFPLR3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
58579 | #define BIFPLR3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
58580 | #define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
58581 | #define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
58582 | #define BIFPLR3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
58583 | #define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
58584 | #define BIFPLR3_1_COMMAND__AD_STEPPING_MASK 0x0080L |
58585 | #define BIFPLR3_1_COMMAND__SERR_EN_MASK 0x0100L |
58586 | #define BIFPLR3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
58587 | #define BIFPLR3_1_COMMAND__INT_DIS_MASK 0x0400L |
58588 | //BIFPLR3_1_STATUS |
58589 | #define BIFPLR3_1_STATUS__INT_STATUS__SHIFT 0x3 |
58590 | #define BIFPLR3_1_STATUS__CAP_LIST__SHIFT 0x4 |
58591 | #define BIFPLR3_1_STATUS__PCI_66_EN__SHIFT 0x5 |
58592 | #define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
58593 | #define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
58594 | #define BIFPLR3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
58595 | #define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
58596 | #define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
58597 | #define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
58598 | #define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
58599 | #define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
58600 | #define BIFPLR3_1_STATUS__INT_STATUS_MASK 0x0008L |
58601 | #define BIFPLR3_1_STATUS__CAP_LIST_MASK 0x0010L |
58602 | #define BIFPLR3_1_STATUS__PCI_66_EN_MASK 0x0020L |
58603 | #define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
58604 | #define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
58605 | #define BIFPLR3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
58606 | #define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
58607 | #define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
58608 | #define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
58609 | #define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
58610 | #define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
58611 | //BIFPLR3_1_REVISION_ID |
58612 | #define BIFPLR3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
58613 | #define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
58614 | #define BIFPLR3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
58615 | #define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
58616 | //BIFPLR3_1_PROG_INTERFACE |
58617 | #define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
58618 | #define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
58619 | //BIFPLR3_1_SUB_CLASS |
58620 | #define BIFPLR3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
58621 | #define BIFPLR3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
58622 | //BIFPLR3_1_BASE_CLASS |
58623 | #define BIFPLR3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
58624 | #define BIFPLR3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
58625 | //BIFPLR3_1_CACHE_LINE |
58626 | #define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
58627 | #define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
58628 | //BIFPLR3_1_LATENCY |
58629 | #define BIFPLR3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
58630 | #define BIFPLR3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
58631 | //BIFPLR3_1_HEADER |
58632 | #define BIFPLR3_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
58633 | #define BIFPLR3_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
58634 | #define BIFPLR3_1_HEADER__HEADER_TYPE_MASK 0x7FL |
58635 | #define BIFPLR3_1_HEADER__DEVICE_TYPE_MASK 0x80L |
58636 | //BIFPLR3_1_BIST |
58637 | #define BIFPLR3_1_BIST__BIST_COMP__SHIFT 0x0 |
58638 | #define BIFPLR3_1_BIST__BIST_STRT__SHIFT 0x6 |
58639 | #define BIFPLR3_1_BIST__BIST_CAP__SHIFT 0x7 |
58640 | #define BIFPLR3_1_BIST__BIST_COMP_MASK 0x0FL |
58641 | #define BIFPLR3_1_BIST__BIST_STRT_MASK 0x40L |
58642 | #define BIFPLR3_1_BIST__BIST_CAP_MASK 0x80L |
58643 | //BIFPLR3_1_SUB_BUS_NUMBER_LATENCY |
58644 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
58645 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
58646 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
58647 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
58648 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
58649 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
58650 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
58651 | #define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
58652 | //BIFPLR3_1_IO_BASE_LIMIT |
58653 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
58654 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
58655 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
58656 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
58657 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
58658 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
58659 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
58660 | #define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
58661 | //BIFPLR3_1_SECONDARY_STATUS |
58662 | #define BIFPLR3_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
58663 | #define BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
58664 | #define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
58665 | #define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
58666 | #define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
58667 | #define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
58668 | #define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
58669 | #define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
58670 | #define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
58671 | #define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
58672 | #define BIFPLR3_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
58673 | #define BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
58674 | #define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
58675 | #define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
58676 | #define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
58677 | #define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
58678 | #define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
58679 | #define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
58680 | #define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
58681 | #define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
58682 | //BIFPLR3_1_MEM_BASE_LIMIT |
58683 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
58684 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
58685 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
58686 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
58687 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
58688 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
58689 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
58690 | #define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
58691 | //BIFPLR3_1_PREF_BASE_LIMIT |
58692 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
58693 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
58694 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
58695 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
58696 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
58697 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
58698 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
58699 | #define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
58700 | //BIFPLR3_1_PREF_BASE_UPPER |
58701 | #define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
58702 | #define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
58703 | //BIFPLR3_1_PREF_LIMIT_UPPER |
58704 | #define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
58705 | #define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
58706 | //BIFPLR3_1_IO_BASE_LIMIT_HI |
58707 | #define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
58708 | #define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
58709 | #define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
58710 | #define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
58711 | //BIFPLR3_1_CAP_PTR |
58712 | #define BIFPLR3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
58713 | #define BIFPLR3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
58714 | //BIFPLR3_1_INTERRUPT_LINE |
58715 | #define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
58716 | #define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
58717 | //BIFPLR3_1_INTERRUPT_PIN |
58718 | #define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
58719 | #define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
58720 | //BIFPLR3_1_IRQ_BRIDGE_CNTL |
58721 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
58722 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
58723 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
58724 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
58725 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
58726 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
58727 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
58728 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
58729 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
58730 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
58731 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
58732 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
58733 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
58734 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
58735 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
58736 | #define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
58737 | //BIFPLR3_1_EXT_BRIDGE_CNTL |
58738 | #define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
58739 | #define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
58740 | //BIFPLR3_1_PMI_CAP_LIST |
58741 | #define BIFPLR3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
58742 | #define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
58743 | #define BIFPLR3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
58744 | #define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
58745 | //BIFPLR3_1_PMI_CAP |
58746 | #define BIFPLR3_1_PMI_CAP__VERSION__SHIFT 0x0 |
58747 | #define BIFPLR3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
58748 | #define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
58749 | #define BIFPLR3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
58750 | #define BIFPLR3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
58751 | #define BIFPLR3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
58752 | #define BIFPLR3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
58753 | #define BIFPLR3_1_PMI_CAP__VERSION_MASK 0x0007L |
58754 | #define BIFPLR3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
58755 | #define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
58756 | #define BIFPLR3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
58757 | #define BIFPLR3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
58758 | #define BIFPLR3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
58759 | #define BIFPLR3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
58760 | //BIFPLR3_1_PMI_STATUS_CNTL |
58761 | #define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
58762 | #define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
58763 | #define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
58764 | #define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
58765 | #define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
58766 | #define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
58767 | #define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
58768 | #define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
58769 | #define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
58770 | #define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
58771 | #define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
58772 | #define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
58773 | #define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
58774 | #define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
58775 | #define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
58776 | #define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
58777 | #define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
58778 | #define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
58779 | //BIFPLR3_1_PCIE_CAP_LIST |
58780 | #define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
58781 | #define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
58782 | #define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
58783 | #define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
58784 | //BIFPLR3_1_PCIE_CAP |
58785 | #define BIFPLR3_1_PCIE_CAP__VERSION__SHIFT 0x0 |
58786 | #define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
58787 | #define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
58788 | #define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
58789 | #define BIFPLR3_1_PCIE_CAP__VERSION_MASK 0x000FL |
58790 | #define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
58791 | #define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
58792 | #define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
58793 | //BIFPLR3_1_DEVICE_CAP |
58794 | #define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
58795 | #define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
58796 | #define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
58797 | #define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
58798 | #define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
58799 | #define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
58800 | #define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
58801 | #define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
58802 | #define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
58803 | #define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
58804 | #define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
58805 | #define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
58806 | #define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
58807 | #define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
58808 | #define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
58809 | #define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
58810 | #define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
58811 | #define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
58812 | //BIFPLR3_1_DEVICE_CNTL |
58813 | #define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
58814 | #define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
58815 | #define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
58816 | #define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
58817 | #define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
58818 | #define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
58819 | #define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
58820 | #define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
58821 | #define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
58822 | #define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
58823 | #define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
58824 | #define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
58825 | #define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
58826 | #define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
58827 | #define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
58828 | #define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
58829 | #define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
58830 | #define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
58831 | #define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
58832 | #define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
58833 | #define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
58834 | #define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
58835 | #define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
58836 | #define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
58837 | //BIFPLR3_1_DEVICE_STATUS |
58838 | #define BIFPLR3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
58839 | #define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
58840 | #define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
58841 | #define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
58842 | #define BIFPLR3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
58843 | #define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
58844 | #define BIFPLR3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
58845 | #define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
58846 | #define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
58847 | #define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
58848 | #define BIFPLR3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
58849 | #define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
58850 | //BIFPLR3_1_LINK_CAP |
58851 | #define BIFPLR3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
58852 | #define BIFPLR3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
58853 | #define BIFPLR3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
58854 | #define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
58855 | #define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
58856 | #define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
58857 | #define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
58858 | #define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
58859 | #define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
58860 | #define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
58861 | #define BIFPLR3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
58862 | #define BIFPLR3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
58863 | #define BIFPLR3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
58864 | #define BIFPLR3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
58865 | #define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
58866 | #define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
58867 | #define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
58868 | #define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
58869 | #define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
58870 | #define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
58871 | #define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
58872 | #define BIFPLR3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
58873 | //BIFPLR3_1_LINK_CNTL |
58874 | #define BIFPLR3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
58875 | #define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
58876 | #define BIFPLR3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
58877 | #define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
58878 | #define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
58879 | #define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
58880 | #define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
58881 | #define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
58882 | #define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
58883 | #define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
58884 | #define BIFPLR3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
58885 | #define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
58886 | #define BIFPLR3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
58887 | #define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
58888 | #define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
58889 | #define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
58890 | #define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
58891 | #define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
58892 | #define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
58893 | #define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
58894 | //BIFPLR3_1_LINK_STATUS |
58895 | #define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
58896 | #define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
58897 | #define BIFPLR3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
58898 | #define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
58899 | #define BIFPLR3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
58900 | #define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
58901 | #define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
58902 | #define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
58903 | #define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
58904 | #define BIFPLR3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
58905 | #define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
58906 | #define BIFPLR3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
58907 | #define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
58908 | #define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
58909 | //BIFPLR3_1_SLOT_CAP |
58910 | #define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
58911 | #define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
58912 | #define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
58913 | #define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
58914 | #define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
58915 | #define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
58916 | #define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
58917 | #define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
58918 | #define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
58919 | #define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
58920 | #define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
58921 | #define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
58922 | #define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
58923 | #define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
58924 | #define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
58925 | #define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
58926 | #define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
58927 | #define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
58928 | #define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
58929 | #define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
58930 | #define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
58931 | #define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
58932 | #define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
58933 | #define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
58934 | //BIFPLR3_1_SLOT_CNTL |
58935 | #define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
58936 | #define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
58937 | #define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
58938 | #define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
58939 | #define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
58940 | #define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
58941 | #define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
58942 | #define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
58943 | #define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
58944 | #define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
58945 | #define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
58946 | #define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
58947 | #define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
58948 | #define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
58949 | #define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
58950 | #define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
58951 | #define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
58952 | #define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
58953 | #define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
58954 | #define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
58955 | #define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
58956 | #define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
58957 | #define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
58958 | #define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
58959 | //BIFPLR3_1_SLOT_STATUS |
58960 | #define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
58961 | #define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
58962 | #define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
58963 | #define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
58964 | #define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
58965 | #define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
58966 | #define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
58967 | #define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
58968 | #define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
58969 | #define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
58970 | #define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
58971 | #define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
58972 | #define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
58973 | #define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
58974 | #define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
58975 | #define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
58976 | #define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
58977 | #define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
58978 | //BIFPLR3_1_ROOT_CNTL |
58979 | #define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
58980 | #define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
58981 | #define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
58982 | #define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
58983 | #define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
58984 | #define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
58985 | #define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
58986 | #define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
58987 | #define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
58988 | #define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
58989 | //BIFPLR3_1_ROOT_CAP |
58990 | #define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
58991 | #define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
58992 | //BIFPLR3_1_ROOT_STATUS |
58993 | #define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
58994 | #define BIFPLR3_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
58995 | #define BIFPLR3_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
58996 | #define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
58997 | #define BIFPLR3_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
58998 | #define BIFPLR3_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
58999 | //BIFPLR3_1_DEVICE_CAP2 |
59000 | #define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
59001 | #define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
59002 | #define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
59003 | #define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
59004 | #define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
59005 | #define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
59006 | #define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
59007 | #define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
59008 | #define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
59009 | #define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
59010 | #define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
59011 | #define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
59012 | #define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
59013 | #define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
59014 | #define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
59015 | #define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
59016 | #define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
59017 | #define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
59018 | #define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
59019 | #define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
59020 | #define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
59021 | #define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
59022 | #define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
59023 | #define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
59024 | #define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
59025 | #define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
59026 | #define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
59027 | #define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
59028 | //BIFPLR3_1_DEVICE_CNTL2 |
59029 | #define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
59030 | #define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
59031 | #define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
59032 | #define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
59033 | #define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
59034 | #define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
59035 | #define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
59036 | #define BIFPLR3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
59037 | #define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
59038 | #define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
59039 | #define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
59040 | #define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
59041 | #define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
59042 | #define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
59043 | #define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
59044 | #define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
59045 | #define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
59046 | #define BIFPLR3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
59047 | #define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
59048 | #define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
59049 | //BIFPLR3_1_DEVICE_STATUS2 |
59050 | #define BIFPLR3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
59051 | #define BIFPLR3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
59052 | //BIFPLR3_1_LINK_CAP2 |
59053 | #define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
59054 | #define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
59055 | #define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
59056 | #define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
59057 | #define BIFPLR3_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
59058 | #define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
59059 | #define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
59060 | #define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
59061 | #define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
59062 | #define BIFPLR3_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
59063 | //BIFPLR3_1_LINK_CNTL2 |
59064 | #define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
59065 | #define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
59066 | #define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
59067 | #define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
59068 | #define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
59069 | #define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
59070 | #define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
59071 | #define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
59072 | #define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
59073 | #define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
59074 | #define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
59075 | #define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
59076 | #define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
59077 | #define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
59078 | #define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
59079 | #define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
59080 | //BIFPLR3_1_LINK_STATUS2 |
59081 | #define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
59082 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
59083 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
59084 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
59085 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
59086 | #define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
59087 | #define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
59088 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
59089 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
59090 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
59091 | #define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
59092 | #define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
59093 | //BIFPLR3_1_SLOT_CAP2 |
59094 | #define BIFPLR3_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
59095 | #define BIFPLR3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
59096 | //BIFPLR3_1_SLOT_CNTL2 |
59097 | #define BIFPLR3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
59098 | #define BIFPLR3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
59099 | //BIFPLR3_1_SLOT_STATUS2 |
59100 | #define BIFPLR3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
59101 | #define BIFPLR3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
59102 | //BIFPLR3_1_MSI_CAP_LIST |
59103 | #define BIFPLR3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
59104 | #define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
59105 | #define BIFPLR3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
59106 | #define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
59107 | //BIFPLR3_1_MSI_MSG_CNTL |
59108 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
59109 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
59110 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
59111 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
59112 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
59113 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
59114 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
59115 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
59116 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
59117 | #define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
59118 | //BIFPLR3_1_MSI_MSG_ADDR_LO |
59119 | #define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
59120 | #define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
59121 | //BIFPLR3_1_MSI_MSG_ADDR_HI |
59122 | #define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
59123 | #define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
59124 | //BIFPLR3_1_MSI_MSG_DATA |
59125 | #define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
59126 | #define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
59127 | //BIFPLR3_1_MSI_MSG_DATA_64 |
59128 | #define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
59129 | #define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
59130 | //BIFPLR3_1_SSID_CAP_LIST |
59131 | #define BIFPLR3_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
59132 | #define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
59133 | #define BIFPLR3_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
59134 | #define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
59135 | //BIFPLR3_1_SSID_CAP |
59136 | #define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
59137 | #define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
59138 | #define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
59139 | #define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
59140 | //BIFPLR3_1_MSI_MAP_CAP_LIST |
59141 | #define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
59142 | #define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
59143 | #define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
59144 | #define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
59145 | //BIFPLR3_1_MSI_MAP_CAP |
59146 | #define BIFPLR3_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
59147 | #define BIFPLR3_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
59148 | #define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
59149 | #define BIFPLR3_1_MSI_MAP_CAP__EN_MASK 0x0001L |
59150 | #define BIFPLR3_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
59151 | #define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
59152 | //BIFPLR3_1_MSI_MAP_ADDR_LO |
59153 | #define BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
59154 | #define BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
59155 | //BIFPLR3_1_MSI_MAP_ADDR_HI |
59156 | #define BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
59157 | #define BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
59158 | //BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
59159 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59160 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59161 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59162 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59163 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59164 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59165 | //BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR |
59166 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
59167 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
59168 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
59169 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
59170 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
59171 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
59172 | //BIFPLR3_1_PCIE_VENDOR_SPECIFIC1 |
59173 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
59174 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
59175 | //BIFPLR3_1_PCIE_VENDOR_SPECIFIC2 |
59176 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
59177 | #define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
59178 | //BIFPLR3_1_PCIE_VC_ENH_CAP_LIST |
59179 | #define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59180 | #define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59181 | #define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59182 | #define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59183 | #define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59184 | #define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59185 | //BIFPLR3_1_PCIE_PORT_VC_CAP_REG1 |
59186 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
59187 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
59188 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
59189 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
59190 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
59191 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
59192 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
59193 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
59194 | //BIFPLR3_1_PCIE_PORT_VC_CAP_REG2 |
59195 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
59196 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
59197 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
59198 | #define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
59199 | //BIFPLR3_1_PCIE_PORT_VC_CNTL |
59200 | #define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
59201 | #define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
59202 | #define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
59203 | #define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
59204 | //BIFPLR3_1_PCIE_PORT_VC_STATUS |
59205 | #define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
59206 | #define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
59207 | //BIFPLR3_1_PCIE_VC0_RESOURCE_CAP |
59208 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
59209 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
59210 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
59211 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
59212 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
59213 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
59214 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
59215 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
59216 | //BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL |
59217 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
59218 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
59219 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
59220 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
59221 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
59222 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
59223 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
59224 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
59225 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
59226 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
59227 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
59228 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
59229 | //BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS |
59230 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
59231 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
59232 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
59233 | #define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
59234 | //BIFPLR3_1_PCIE_VC1_RESOURCE_CAP |
59235 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
59236 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
59237 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
59238 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
59239 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
59240 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
59241 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
59242 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
59243 | //BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL |
59244 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
59245 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
59246 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
59247 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
59248 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
59249 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
59250 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
59251 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
59252 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
59253 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
59254 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
59255 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
59256 | //BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS |
59257 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
59258 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
59259 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
59260 | #define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
59261 | //BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
59262 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59263 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59264 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59265 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59266 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59267 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59268 | //BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1 |
59269 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
59270 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
59271 | //BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2 |
59272 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
59273 | #define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
59274 | //BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
59275 | #define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59276 | #define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59277 | #define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59278 | #define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59279 | #define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59280 | #define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59281 | //BIFPLR3_1_PCIE_UNCORR_ERR_STATUS |
59282 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
59283 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
59284 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
59285 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
59286 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
59287 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
59288 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
59289 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
59290 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
59291 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
59292 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
59293 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
59294 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
59295 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
59296 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
59297 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
59298 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
59299 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
59300 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
59301 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
59302 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
59303 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
59304 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
59305 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
59306 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
59307 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
59308 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
59309 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
59310 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
59311 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
59312 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
59313 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
59314 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
59315 | #define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
59316 | //BIFPLR3_1_PCIE_UNCORR_ERR_MASK |
59317 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
59318 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
59319 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
59320 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
59321 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
59322 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
59323 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
59324 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
59325 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
59326 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
59327 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
59328 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
59329 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
59330 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
59331 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
59332 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
59333 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
59334 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
59335 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
59336 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
59337 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
59338 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
59339 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
59340 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
59341 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
59342 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
59343 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
59344 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
59345 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
59346 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
59347 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
59348 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
59349 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
59350 | #define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
59351 | //BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY |
59352 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
59353 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
59354 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
59355 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
59356 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
59357 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
59358 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
59359 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
59360 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
59361 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
59362 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
59363 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
59364 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
59365 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
59366 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
59367 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
59368 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
59369 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
59370 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
59371 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
59372 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
59373 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
59374 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
59375 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
59376 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
59377 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
59378 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
59379 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
59380 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
59381 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
59382 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
59383 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
59384 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
59385 | #define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
59386 | //BIFPLR3_1_PCIE_CORR_ERR_STATUS |
59387 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
59388 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
59389 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
59390 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
59391 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
59392 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
59393 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
59394 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
59395 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
59396 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
59397 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
59398 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
59399 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
59400 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
59401 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
59402 | #define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
59403 | //BIFPLR3_1_PCIE_CORR_ERR_MASK |
59404 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
59405 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
59406 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
59407 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
59408 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
59409 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
59410 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
59411 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
59412 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
59413 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
59414 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
59415 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
59416 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
59417 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
59418 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
59419 | #define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
59420 | //BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL |
59421 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
59422 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
59423 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
59424 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
59425 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
59426 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
59427 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
59428 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
59429 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
59430 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
59431 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
59432 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
59433 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
59434 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
59435 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
59436 | #define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
59437 | //BIFPLR3_1_PCIE_HDR_LOG0 |
59438 | #define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
59439 | #define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
59440 | //BIFPLR3_1_PCIE_HDR_LOG1 |
59441 | #define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
59442 | #define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
59443 | //BIFPLR3_1_PCIE_HDR_LOG2 |
59444 | #define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
59445 | #define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
59446 | //BIFPLR3_1_PCIE_HDR_LOG3 |
59447 | #define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
59448 | #define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
59449 | //BIFPLR3_1_PCIE_ROOT_ERR_CMD |
59450 | #define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
59451 | #define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
59452 | #define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
59453 | #define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
59454 | #define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
59455 | #define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
59456 | //BIFPLR3_1_PCIE_ROOT_ERR_STATUS |
59457 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
59458 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
59459 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
59460 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
59461 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
59462 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
59463 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
59464 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
59465 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
59466 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
59467 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
59468 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
59469 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
59470 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
59471 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
59472 | #define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
59473 | //BIFPLR3_1_PCIE_ERR_SRC_ID |
59474 | #define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
59475 | #define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
59476 | #define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
59477 | #define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
59478 | //BIFPLR3_1_PCIE_TLP_PREFIX_LOG0 |
59479 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
59480 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
59481 | //BIFPLR3_1_PCIE_TLP_PREFIX_LOG1 |
59482 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
59483 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
59484 | //BIFPLR3_1_PCIE_TLP_PREFIX_LOG2 |
59485 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
59486 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
59487 | //BIFPLR3_1_PCIE_TLP_PREFIX_LOG3 |
59488 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
59489 | #define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
59490 | //BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST |
59491 | #define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59492 | #define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59493 | #define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59494 | #define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59495 | #define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59496 | #define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59497 | //BIFPLR3_1_PCIE_LINK_CNTL3 |
59498 | #define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
59499 | #define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
59500 | #define BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
59501 | #define BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
59502 | #define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
59503 | #define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
59504 | #define BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
59505 | #define BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
59506 | //BIFPLR3_1_PCIE_LANE_ERROR_STATUS |
59507 | #define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
59508 | #define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
59509 | #define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
59510 | #define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
59511 | //BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL |
59512 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59513 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59514 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59515 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59516 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59517 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59518 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59519 | #define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59520 | //BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL |
59521 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59522 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59523 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59524 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59525 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59526 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59527 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59528 | #define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59529 | //BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL |
59530 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59531 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59532 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59533 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59534 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59535 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59536 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59537 | #define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59538 | //BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL |
59539 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59540 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59541 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59542 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59543 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59544 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59545 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59546 | #define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59547 | //BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL |
59548 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59549 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59550 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59551 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59552 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59553 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59554 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59555 | #define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59556 | //BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL |
59557 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59558 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59559 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59560 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59561 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59562 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59563 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59564 | #define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59565 | //BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL |
59566 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59567 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59568 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59569 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59570 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59571 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59572 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59573 | #define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59574 | //BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL |
59575 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59576 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59577 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59578 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59579 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59580 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59581 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59582 | #define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59583 | //BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL |
59584 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59585 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59586 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59587 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59588 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59589 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59590 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59591 | #define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59592 | //BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL |
59593 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59594 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59595 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59596 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59597 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59598 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59599 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59600 | #define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59601 | //BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL |
59602 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59603 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59604 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59605 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59606 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59607 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59608 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59609 | #define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59610 | //BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL |
59611 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59612 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59613 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59614 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59615 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59616 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59617 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59618 | #define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59619 | //BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL |
59620 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59621 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59622 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59623 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59624 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59625 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59626 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59627 | #define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59628 | //BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL |
59629 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59630 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59631 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59632 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59633 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59634 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59635 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59636 | #define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59637 | //BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL |
59638 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59639 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59640 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59641 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59642 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59643 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59644 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59645 | #define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59646 | //BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL |
59647 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
59648 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
59649 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
59650 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
59651 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
59652 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
59653 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
59654 | #define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
59655 | //BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST |
59656 | #define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59657 | #define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59658 | #define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59659 | #define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59660 | #define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59661 | #define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59662 | //BIFPLR3_1_PCIE_ACS_CAP |
59663 | #define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
59664 | #define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
59665 | #define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
59666 | #define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
59667 | #define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
59668 | #define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
59669 | #define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
59670 | #define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
59671 | #define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
59672 | #define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
59673 | #define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
59674 | #define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
59675 | #define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
59676 | #define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
59677 | #define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
59678 | #define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
59679 | //BIFPLR3_1_PCIE_ACS_CNTL |
59680 | #define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
59681 | #define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
59682 | #define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
59683 | #define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
59684 | #define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
59685 | #define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
59686 | #define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
59687 | #define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
59688 | #define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
59689 | #define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
59690 | #define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
59691 | #define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
59692 | #define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
59693 | #define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
59694 | //BIFPLR3_1_PCIE_MC_ENH_CAP_LIST |
59695 | #define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59696 | #define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59697 | #define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59698 | #define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59699 | #define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59700 | #define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59701 | //BIFPLR3_1_PCIE_MC_CAP |
59702 | #define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
59703 | #define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
59704 | #define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
59705 | #define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
59706 | //BIFPLR3_1_PCIE_MC_CNTL |
59707 | #define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
59708 | #define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
59709 | #define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
59710 | #define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
59711 | //BIFPLR3_1_PCIE_MC_ADDR0 |
59712 | #define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
59713 | #define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
59714 | #define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
59715 | #define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
59716 | //BIFPLR3_1_PCIE_MC_ADDR1 |
59717 | #define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
59718 | #define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
59719 | //BIFPLR3_1_PCIE_MC_RCV0 |
59720 | #define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
59721 | #define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
59722 | //BIFPLR3_1_PCIE_MC_RCV1 |
59723 | #define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
59724 | #define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
59725 | //BIFPLR3_1_PCIE_MC_BLOCK_ALL0 |
59726 | #define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
59727 | #define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
59728 | //BIFPLR3_1_PCIE_MC_BLOCK_ALL1 |
59729 | #define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
59730 | #define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
59731 | //BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
59732 | #define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
59733 | #define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
59734 | //BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
59735 | #define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
59736 | #define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
59737 | //BIFPLR3_1_PCIE_MC_OVERLAY_BAR0 |
59738 | #define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
59739 | #define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
59740 | #define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
59741 | #define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
59742 | //BIFPLR3_1_PCIE_MC_OVERLAY_BAR1 |
59743 | #define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
59744 | #define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
59745 | //BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST |
59746 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
59747 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
59748 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59749 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59750 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59751 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59752 | //BIFPLR3_1_PCIE_L1_PM_SUB_CAP |
59753 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
59754 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
59755 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
59756 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
59757 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
59758 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
59759 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
59760 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
59761 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
59762 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
59763 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
59764 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
59765 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
59766 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
59767 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
59768 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
59769 | //BIFPLR3_1_PCIE_L1_PM_SUB_CNTL |
59770 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
59771 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
59772 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
59773 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
59774 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
59775 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
59776 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
59777 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
59778 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
59779 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
59780 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
59781 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
59782 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
59783 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
59784 | //BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2 |
59785 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
59786 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
59787 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
59788 | #define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
59789 | //BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST |
59790 | #define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
59791 | #define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
59792 | #define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59793 | #define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59794 | #define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59795 | #define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59796 | //BIFPLR3_1_PCIE_DPC_CAP_LIST |
59797 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
59798 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
59799 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
59800 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
59801 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
59802 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
59803 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
59804 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
59805 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
59806 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
59807 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
59808 | #define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
59809 | //BIFPLR3_1_PCIE_DPC_CNTL |
59810 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
59811 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
59812 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
59813 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
59814 | #define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
59815 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
59816 | #define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
59817 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
59818 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
59819 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
59820 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
59821 | #define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
59822 | #define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
59823 | #define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
59824 | //BIFPLR3_1_PCIE_DPC_STATUS |
59825 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
59826 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
59827 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
59828 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
59829 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
59830 | #define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
59831 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
59832 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
59833 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
59834 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
59835 | #define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
59836 | #define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
59837 | //BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID |
59838 | #define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
59839 | #define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
59840 | //BIFPLR3_1_PCIE_RP_PIO_STATUS |
59841 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
59842 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
59843 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
59844 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
59845 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
59846 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
59847 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
59848 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
59849 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
59850 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
59851 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
59852 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
59853 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
59854 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
59855 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
59856 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
59857 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
59858 | #define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
59859 | //BIFPLR3_1_PCIE_RP_PIO_MASK |
59860 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
59861 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
59862 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
59863 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
59864 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
59865 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
59866 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
59867 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
59868 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
59869 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
59870 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
59871 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
59872 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
59873 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
59874 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
59875 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
59876 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
59877 | #define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
59878 | //BIFPLR3_1_PCIE_RP_PIO_SEVERITY |
59879 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
59880 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
59881 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
59882 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
59883 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
59884 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
59885 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
59886 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
59887 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
59888 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
59889 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
59890 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
59891 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
59892 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
59893 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
59894 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
59895 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
59896 | #define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
59897 | //BIFPLR3_1_PCIE_RP_PIO_SYSERROR |
59898 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
59899 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
59900 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
59901 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
59902 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
59903 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
59904 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
59905 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
59906 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
59907 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
59908 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
59909 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
59910 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
59911 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
59912 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
59913 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
59914 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
59915 | #define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
59916 | //BIFPLR3_1_PCIE_RP_PIO_EXCEPTION |
59917 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
59918 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
59919 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
59920 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
59921 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
59922 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
59923 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
59924 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
59925 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
59926 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
59927 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
59928 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
59929 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
59930 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
59931 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
59932 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
59933 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
59934 | #define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
59935 | //BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0 |
59936 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
59937 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
59938 | //BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1 |
59939 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
59940 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
59941 | //BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2 |
59942 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
59943 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
59944 | //BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3 |
59945 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
59946 | #define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
59947 | //BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG |
59948 | #define BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
59949 | #define BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
59950 | //BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0 |
59951 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
59952 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
59953 | //BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1 |
59954 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
59955 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
59956 | //BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2 |
59957 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
59958 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
59959 | //BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3 |
59960 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
59961 | #define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
59962 | //BIFPLR3_1_PCIE_ESM_CAP_LIST |
59963 | #define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
59964 | #define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
59965 | #define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
59966 | #define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
59967 | #define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
59968 | #define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
59969 | //BIFPLR3_1_PCIE_ESM_HEADER_1 |
59970 | #define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
59971 | #define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
59972 | #define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
59973 | #define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
59974 | #define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
59975 | #define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
59976 | //BIFPLR3_1_PCIE_ESM_HEADER_2 |
59977 | #define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
59978 | #define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
59979 | //BIFPLR3_1_PCIE_ESM_STATUS |
59980 | #define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
59981 | #define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
59982 | #define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
59983 | #define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
59984 | //BIFPLR3_1_PCIE_ESM_CTRL |
59985 | #define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
59986 | #define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
59987 | #define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
59988 | #define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
59989 | #define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
59990 | #define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
59991 | //BIFPLR3_1_PCIE_ESM_CAP_1 |
59992 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
59993 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
59994 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
59995 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
59996 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
59997 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
59998 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
59999 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
60000 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
60001 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
60002 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
60003 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
60004 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
60005 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
60006 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
60007 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
60008 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
60009 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
60010 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
60011 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
60012 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
60013 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
60014 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
60015 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
60016 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
60017 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
60018 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
60019 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
60020 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
60021 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
60022 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
60023 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
60024 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
60025 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
60026 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
60027 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
60028 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
60029 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
60030 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
60031 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
60032 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
60033 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
60034 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
60035 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
60036 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
60037 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
60038 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
60039 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
60040 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
60041 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
60042 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
60043 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
60044 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
60045 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
60046 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
60047 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
60048 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
60049 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
60050 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
60051 | #define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
60052 | //BIFPLR3_1_PCIE_ESM_CAP_2 |
60053 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
60054 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
60055 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
60056 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
60057 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
60058 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
60059 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
60060 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
60061 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
60062 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
60063 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
60064 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
60065 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
60066 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
60067 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
60068 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
60069 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
60070 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
60071 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
60072 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
60073 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
60074 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
60075 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
60076 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
60077 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
60078 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
60079 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
60080 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
60081 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
60082 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
60083 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
60084 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
60085 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
60086 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
60087 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
60088 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
60089 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
60090 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
60091 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
60092 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
60093 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
60094 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
60095 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
60096 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
60097 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
60098 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
60099 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
60100 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
60101 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
60102 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
60103 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
60104 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
60105 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
60106 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
60107 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
60108 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
60109 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
60110 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
60111 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
60112 | #define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
60113 | //BIFPLR3_1_PCIE_ESM_CAP_3 |
60114 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
60115 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
60116 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
60117 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
60118 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
60119 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
60120 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
60121 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
60122 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
60123 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
60124 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
60125 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
60126 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
60127 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
60128 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
60129 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
60130 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
60131 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
60132 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
60133 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
60134 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
60135 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
60136 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
60137 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
60138 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
60139 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
60140 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
60141 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
60142 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
60143 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
60144 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
60145 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
60146 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
60147 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
60148 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
60149 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
60150 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
60151 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
60152 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
60153 | #define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
60154 | //BIFPLR3_1_PCIE_ESM_CAP_4 |
60155 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
60156 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
60157 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
60158 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
60159 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
60160 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
60161 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
60162 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
60163 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
60164 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
60165 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
60166 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
60167 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
60168 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
60169 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
60170 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
60171 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
60172 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
60173 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
60174 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
60175 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
60176 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
60177 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
60178 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
60179 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
60180 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
60181 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
60182 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
60183 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
60184 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
60185 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
60186 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
60187 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
60188 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
60189 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
60190 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
60191 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
60192 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
60193 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
60194 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
60195 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
60196 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
60197 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
60198 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
60199 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
60200 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
60201 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
60202 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
60203 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
60204 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
60205 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
60206 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
60207 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
60208 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
60209 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
60210 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
60211 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
60212 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
60213 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
60214 | #define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
60215 | //BIFPLR3_1_PCIE_ESM_CAP_5 |
60216 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
60217 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
60218 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
60219 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
60220 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
60221 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
60222 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
60223 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
60224 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
60225 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
60226 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
60227 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
60228 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
60229 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
60230 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
60231 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
60232 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
60233 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
60234 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
60235 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
60236 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
60237 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
60238 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
60239 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
60240 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
60241 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
60242 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
60243 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
60244 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
60245 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
60246 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
60247 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
60248 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
60249 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
60250 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
60251 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
60252 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
60253 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
60254 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
60255 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
60256 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
60257 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
60258 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
60259 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
60260 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
60261 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
60262 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
60263 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
60264 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
60265 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
60266 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
60267 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
60268 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
60269 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
60270 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
60271 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
60272 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
60273 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
60274 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
60275 | #define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
60276 | //BIFPLR3_1_PCIE_ESM_CAP_6 |
60277 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
60278 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
60279 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
60280 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
60281 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
60282 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
60283 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
60284 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
60285 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
60286 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
60287 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
60288 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
60289 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
60290 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
60291 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
60292 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
60293 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
60294 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
60295 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
60296 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
60297 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
60298 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
60299 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
60300 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
60301 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
60302 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
60303 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
60304 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
60305 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
60306 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
60307 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
60308 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
60309 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
60310 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
60311 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
60312 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
60313 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
60314 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
60315 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
60316 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
60317 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
60318 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
60319 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
60320 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
60321 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
60322 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
60323 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
60324 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
60325 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
60326 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
60327 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
60328 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
60329 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
60330 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
60331 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
60332 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
60333 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
60334 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
60335 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
60336 | #define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
60337 | //BIFPLR3_1_PCIE_ESM_CAP_7 |
60338 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
60339 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
60340 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
60341 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
60342 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
60343 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
60344 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
60345 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
60346 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
60347 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
60348 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
60349 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
60350 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
60351 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
60352 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
60353 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
60354 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
60355 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
60356 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
60357 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
60358 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
60359 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
60360 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
60361 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
60362 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
60363 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
60364 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
60365 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
60366 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
60367 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
60368 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
60369 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
60370 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
60371 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
60372 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
60373 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
60374 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
60375 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
60376 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
60377 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
60378 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
60379 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
60380 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
60381 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
60382 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
60383 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
60384 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
60385 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
60386 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
60387 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
60388 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
60389 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
60390 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
60391 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
60392 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
60393 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
60394 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
60395 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
60396 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
60397 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
60398 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
60399 | #define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
60400 | |
60401 | |
60402 | // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
60403 | //BIFPLR4_1_VENDOR_ID |
60404 | #define BIFPLR4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
60405 | #define BIFPLR4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
60406 | //BIFPLR4_1_DEVICE_ID |
60407 | #define BIFPLR4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
60408 | #define BIFPLR4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
60409 | //BIFPLR4_1_COMMAND |
60410 | #define BIFPLR4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
60411 | #define BIFPLR4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
60412 | #define BIFPLR4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
60413 | #define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
60414 | #define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
60415 | #define BIFPLR4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
60416 | #define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
60417 | #define BIFPLR4_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
60418 | #define BIFPLR4_1_COMMAND__SERR_EN__SHIFT 0x8 |
60419 | #define BIFPLR4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
60420 | #define BIFPLR4_1_COMMAND__INT_DIS__SHIFT 0xa |
60421 | #define BIFPLR4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
60422 | #define BIFPLR4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
60423 | #define BIFPLR4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
60424 | #define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
60425 | #define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
60426 | #define BIFPLR4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
60427 | #define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
60428 | #define BIFPLR4_1_COMMAND__AD_STEPPING_MASK 0x0080L |
60429 | #define BIFPLR4_1_COMMAND__SERR_EN_MASK 0x0100L |
60430 | #define BIFPLR4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
60431 | #define BIFPLR4_1_COMMAND__INT_DIS_MASK 0x0400L |
60432 | //BIFPLR4_1_STATUS |
60433 | #define BIFPLR4_1_STATUS__INT_STATUS__SHIFT 0x3 |
60434 | #define BIFPLR4_1_STATUS__CAP_LIST__SHIFT 0x4 |
60435 | #define BIFPLR4_1_STATUS__PCI_66_EN__SHIFT 0x5 |
60436 | #define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
60437 | #define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
60438 | #define BIFPLR4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
60439 | #define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
60440 | #define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
60441 | #define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
60442 | #define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
60443 | #define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
60444 | #define BIFPLR4_1_STATUS__INT_STATUS_MASK 0x0008L |
60445 | #define BIFPLR4_1_STATUS__CAP_LIST_MASK 0x0010L |
60446 | #define BIFPLR4_1_STATUS__PCI_66_EN_MASK 0x0020L |
60447 | #define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
60448 | #define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
60449 | #define BIFPLR4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
60450 | #define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
60451 | #define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
60452 | #define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
60453 | #define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
60454 | #define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
60455 | //BIFPLR4_1_REVISION_ID |
60456 | #define BIFPLR4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
60457 | #define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
60458 | #define BIFPLR4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
60459 | #define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
60460 | //BIFPLR4_1_PROG_INTERFACE |
60461 | #define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
60462 | #define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
60463 | //BIFPLR4_1_SUB_CLASS |
60464 | #define BIFPLR4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
60465 | #define BIFPLR4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
60466 | //BIFPLR4_1_BASE_CLASS |
60467 | #define BIFPLR4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
60468 | #define BIFPLR4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
60469 | //BIFPLR4_1_CACHE_LINE |
60470 | #define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
60471 | #define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
60472 | //BIFPLR4_1_LATENCY |
60473 | #define BIFPLR4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
60474 | #define BIFPLR4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
60475 | //BIFPLR4_1_HEADER |
60476 | #define BIFPLR4_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
60477 | #define BIFPLR4_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
60478 | #define BIFPLR4_1_HEADER__HEADER_TYPE_MASK 0x7FL |
60479 | #define BIFPLR4_1_HEADER__DEVICE_TYPE_MASK 0x80L |
60480 | //BIFPLR4_1_BIST |
60481 | #define BIFPLR4_1_BIST__BIST_COMP__SHIFT 0x0 |
60482 | #define BIFPLR4_1_BIST__BIST_STRT__SHIFT 0x6 |
60483 | #define BIFPLR4_1_BIST__BIST_CAP__SHIFT 0x7 |
60484 | #define BIFPLR4_1_BIST__BIST_COMP_MASK 0x0FL |
60485 | #define BIFPLR4_1_BIST__BIST_STRT_MASK 0x40L |
60486 | #define BIFPLR4_1_BIST__BIST_CAP_MASK 0x80L |
60487 | //BIFPLR4_1_SUB_BUS_NUMBER_LATENCY |
60488 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
60489 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
60490 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
60491 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
60492 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
60493 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
60494 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
60495 | #define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
60496 | //BIFPLR4_1_IO_BASE_LIMIT |
60497 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
60498 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
60499 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
60500 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
60501 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
60502 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
60503 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
60504 | #define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
60505 | //BIFPLR4_1_SECONDARY_STATUS |
60506 | #define BIFPLR4_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
60507 | #define BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
60508 | #define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
60509 | #define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
60510 | #define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
60511 | #define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
60512 | #define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
60513 | #define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
60514 | #define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
60515 | #define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
60516 | #define BIFPLR4_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
60517 | #define BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
60518 | #define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
60519 | #define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
60520 | #define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
60521 | #define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
60522 | #define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
60523 | #define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
60524 | #define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
60525 | #define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
60526 | //BIFPLR4_1_MEM_BASE_LIMIT |
60527 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
60528 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
60529 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
60530 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
60531 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
60532 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
60533 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
60534 | #define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
60535 | //BIFPLR4_1_PREF_BASE_LIMIT |
60536 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
60537 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
60538 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
60539 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
60540 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
60541 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
60542 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
60543 | #define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
60544 | //BIFPLR4_1_PREF_BASE_UPPER |
60545 | #define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
60546 | #define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
60547 | //BIFPLR4_1_PREF_LIMIT_UPPER |
60548 | #define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
60549 | #define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
60550 | //BIFPLR4_1_IO_BASE_LIMIT_HI |
60551 | #define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
60552 | #define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
60553 | #define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
60554 | #define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
60555 | //BIFPLR4_1_CAP_PTR |
60556 | #define BIFPLR4_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
60557 | #define BIFPLR4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
60558 | //BIFPLR4_1_INTERRUPT_LINE |
60559 | #define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
60560 | #define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
60561 | //BIFPLR4_1_INTERRUPT_PIN |
60562 | #define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
60563 | #define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
60564 | //BIFPLR4_1_IRQ_BRIDGE_CNTL |
60565 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
60566 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
60567 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
60568 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
60569 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
60570 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
60571 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
60572 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
60573 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
60574 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
60575 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
60576 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
60577 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
60578 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
60579 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
60580 | #define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
60581 | //BIFPLR4_1_EXT_BRIDGE_CNTL |
60582 | #define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
60583 | #define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
60584 | //BIFPLR4_1_PMI_CAP_LIST |
60585 | #define BIFPLR4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
60586 | #define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
60587 | #define BIFPLR4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
60588 | #define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
60589 | //BIFPLR4_1_PMI_CAP |
60590 | #define BIFPLR4_1_PMI_CAP__VERSION__SHIFT 0x0 |
60591 | #define BIFPLR4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
60592 | #define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
60593 | #define BIFPLR4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
60594 | #define BIFPLR4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
60595 | #define BIFPLR4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
60596 | #define BIFPLR4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
60597 | #define BIFPLR4_1_PMI_CAP__VERSION_MASK 0x0007L |
60598 | #define BIFPLR4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
60599 | #define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
60600 | #define BIFPLR4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
60601 | #define BIFPLR4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
60602 | #define BIFPLR4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
60603 | #define BIFPLR4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
60604 | //BIFPLR4_1_PMI_STATUS_CNTL |
60605 | #define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
60606 | #define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
60607 | #define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
60608 | #define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
60609 | #define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
60610 | #define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
60611 | #define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
60612 | #define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
60613 | #define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
60614 | #define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
60615 | #define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
60616 | #define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
60617 | #define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
60618 | #define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
60619 | #define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
60620 | #define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
60621 | #define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
60622 | #define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
60623 | //BIFPLR4_1_PCIE_CAP_LIST |
60624 | #define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
60625 | #define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
60626 | #define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
60627 | #define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
60628 | //BIFPLR4_1_PCIE_CAP |
60629 | #define BIFPLR4_1_PCIE_CAP__VERSION__SHIFT 0x0 |
60630 | #define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
60631 | #define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
60632 | #define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
60633 | #define BIFPLR4_1_PCIE_CAP__VERSION_MASK 0x000FL |
60634 | #define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
60635 | #define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
60636 | #define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
60637 | //BIFPLR4_1_DEVICE_CAP |
60638 | #define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
60639 | #define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
60640 | #define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
60641 | #define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
60642 | #define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
60643 | #define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
60644 | #define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
60645 | #define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
60646 | #define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
60647 | #define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
60648 | #define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
60649 | #define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
60650 | #define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
60651 | #define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
60652 | #define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
60653 | #define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
60654 | #define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
60655 | #define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
60656 | //BIFPLR4_1_DEVICE_CNTL |
60657 | #define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
60658 | #define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
60659 | #define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
60660 | #define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
60661 | #define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
60662 | #define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
60663 | #define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
60664 | #define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
60665 | #define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
60666 | #define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
60667 | #define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
60668 | #define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
60669 | #define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
60670 | #define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
60671 | #define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
60672 | #define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
60673 | #define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
60674 | #define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
60675 | #define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
60676 | #define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
60677 | #define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
60678 | #define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
60679 | #define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
60680 | #define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
60681 | //BIFPLR4_1_DEVICE_STATUS |
60682 | #define BIFPLR4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
60683 | #define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
60684 | #define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
60685 | #define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
60686 | #define BIFPLR4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
60687 | #define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
60688 | #define BIFPLR4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
60689 | #define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
60690 | #define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
60691 | #define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
60692 | #define BIFPLR4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
60693 | #define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
60694 | //BIFPLR4_1_LINK_CAP |
60695 | #define BIFPLR4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
60696 | #define BIFPLR4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
60697 | #define BIFPLR4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
60698 | #define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
60699 | #define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
60700 | #define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
60701 | #define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
60702 | #define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
60703 | #define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
60704 | #define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
60705 | #define BIFPLR4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
60706 | #define BIFPLR4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
60707 | #define BIFPLR4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
60708 | #define BIFPLR4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
60709 | #define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
60710 | #define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
60711 | #define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
60712 | #define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
60713 | #define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
60714 | #define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
60715 | #define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
60716 | #define BIFPLR4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
60717 | //BIFPLR4_1_LINK_CNTL |
60718 | #define BIFPLR4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
60719 | #define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
60720 | #define BIFPLR4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
60721 | #define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
60722 | #define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
60723 | #define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
60724 | #define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
60725 | #define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
60726 | #define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
60727 | #define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
60728 | #define BIFPLR4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
60729 | #define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
60730 | #define BIFPLR4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
60731 | #define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
60732 | #define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
60733 | #define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
60734 | #define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
60735 | #define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
60736 | #define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
60737 | #define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
60738 | //BIFPLR4_1_LINK_STATUS |
60739 | #define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
60740 | #define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
60741 | #define BIFPLR4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
60742 | #define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
60743 | #define BIFPLR4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
60744 | #define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
60745 | #define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
60746 | #define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
60747 | #define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
60748 | #define BIFPLR4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
60749 | #define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
60750 | #define BIFPLR4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
60751 | #define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
60752 | #define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
60753 | //BIFPLR4_1_SLOT_CAP |
60754 | #define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
60755 | #define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
60756 | #define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
60757 | #define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
60758 | #define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
60759 | #define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
60760 | #define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
60761 | #define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
60762 | #define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
60763 | #define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
60764 | #define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
60765 | #define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
60766 | #define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
60767 | #define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
60768 | #define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
60769 | #define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
60770 | #define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
60771 | #define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
60772 | #define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
60773 | #define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
60774 | #define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
60775 | #define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
60776 | #define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
60777 | #define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
60778 | //BIFPLR4_1_SLOT_CNTL |
60779 | #define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
60780 | #define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
60781 | #define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
60782 | #define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
60783 | #define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
60784 | #define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
60785 | #define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
60786 | #define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
60787 | #define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
60788 | #define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
60789 | #define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
60790 | #define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
60791 | #define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
60792 | #define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
60793 | #define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
60794 | #define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
60795 | #define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
60796 | #define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
60797 | #define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
60798 | #define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
60799 | #define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
60800 | #define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
60801 | #define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
60802 | #define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
60803 | //BIFPLR4_1_SLOT_STATUS |
60804 | #define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
60805 | #define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
60806 | #define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
60807 | #define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
60808 | #define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
60809 | #define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
60810 | #define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
60811 | #define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
60812 | #define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
60813 | #define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
60814 | #define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
60815 | #define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
60816 | #define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
60817 | #define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
60818 | #define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
60819 | #define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
60820 | #define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
60821 | #define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
60822 | //BIFPLR4_1_ROOT_CNTL |
60823 | #define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
60824 | #define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
60825 | #define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
60826 | #define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
60827 | #define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
60828 | #define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
60829 | #define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
60830 | #define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
60831 | #define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
60832 | #define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
60833 | //BIFPLR4_1_ROOT_CAP |
60834 | #define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
60835 | #define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
60836 | //BIFPLR4_1_ROOT_STATUS |
60837 | #define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
60838 | #define BIFPLR4_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
60839 | #define BIFPLR4_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
60840 | #define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
60841 | #define BIFPLR4_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
60842 | #define BIFPLR4_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
60843 | //BIFPLR4_1_DEVICE_CAP2 |
60844 | #define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
60845 | #define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
60846 | #define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
60847 | #define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
60848 | #define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
60849 | #define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
60850 | #define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
60851 | #define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
60852 | #define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
60853 | #define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
60854 | #define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
60855 | #define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
60856 | #define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
60857 | #define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
60858 | #define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
60859 | #define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
60860 | #define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
60861 | #define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
60862 | #define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
60863 | #define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
60864 | #define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
60865 | #define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
60866 | #define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
60867 | #define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
60868 | #define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
60869 | #define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
60870 | #define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
60871 | #define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
60872 | //BIFPLR4_1_DEVICE_CNTL2 |
60873 | #define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
60874 | #define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
60875 | #define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
60876 | #define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
60877 | #define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
60878 | #define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
60879 | #define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
60880 | #define BIFPLR4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
60881 | #define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
60882 | #define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
60883 | #define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
60884 | #define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
60885 | #define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
60886 | #define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
60887 | #define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
60888 | #define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
60889 | #define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
60890 | #define BIFPLR4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
60891 | #define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
60892 | #define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
60893 | //BIFPLR4_1_DEVICE_STATUS2 |
60894 | #define BIFPLR4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
60895 | #define BIFPLR4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
60896 | //BIFPLR4_1_LINK_CAP2 |
60897 | #define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
60898 | #define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
60899 | #define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
60900 | #define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
60901 | #define BIFPLR4_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
60902 | #define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
60903 | #define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
60904 | #define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
60905 | #define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
60906 | #define BIFPLR4_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
60907 | //BIFPLR4_1_LINK_CNTL2 |
60908 | #define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
60909 | #define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
60910 | #define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
60911 | #define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
60912 | #define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
60913 | #define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
60914 | #define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
60915 | #define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
60916 | #define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
60917 | #define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
60918 | #define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
60919 | #define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
60920 | #define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
60921 | #define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
60922 | #define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
60923 | #define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
60924 | //BIFPLR4_1_LINK_STATUS2 |
60925 | #define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
60926 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
60927 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
60928 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
60929 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
60930 | #define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
60931 | #define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
60932 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
60933 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
60934 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
60935 | #define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
60936 | #define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
60937 | //BIFPLR4_1_SLOT_CAP2 |
60938 | #define BIFPLR4_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
60939 | #define BIFPLR4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
60940 | //BIFPLR4_1_SLOT_CNTL2 |
60941 | #define BIFPLR4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
60942 | #define BIFPLR4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
60943 | //BIFPLR4_1_SLOT_STATUS2 |
60944 | #define BIFPLR4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
60945 | #define BIFPLR4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
60946 | //BIFPLR4_1_MSI_CAP_LIST |
60947 | #define BIFPLR4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
60948 | #define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
60949 | #define BIFPLR4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
60950 | #define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
60951 | //BIFPLR4_1_MSI_MSG_CNTL |
60952 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
60953 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
60954 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
60955 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
60956 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
60957 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
60958 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
60959 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
60960 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
60961 | #define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
60962 | //BIFPLR4_1_MSI_MSG_ADDR_LO |
60963 | #define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
60964 | #define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
60965 | //BIFPLR4_1_MSI_MSG_ADDR_HI |
60966 | #define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
60967 | #define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
60968 | //BIFPLR4_1_MSI_MSG_DATA |
60969 | #define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
60970 | #define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
60971 | //BIFPLR4_1_MSI_MSG_DATA_64 |
60972 | #define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
60973 | #define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
60974 | //BIFPLR4_1_SSID_CAP_LIST |
60975 | #define BIFPLR4_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
60976 | #define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
60977 | #define BIFPLR4_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
60978 | #define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
60979 | //BIFPLR4_1_SSID_CAP |
60980 | #define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
60981 | #define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
60982 | #define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
60983 | #define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
60984 | //BIFPLR4_1_MSI_MAP_CAP_LIST |
60985 | #define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
60986 | #define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
60987 | #define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
60988 | #define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
60989 | //BIFPLR4_1_MSI_MAP_CAP |
60990 | #define BIFPLR4_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
60991 | #define BIFPLR4_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
60992 | #define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
60993 | #define BIFPLR4_1_MSI_MAP_CAP__EN_MASK 0x0001L |
60994 | #define BIFPLR4_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
60995 | #define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
60996 | //BIFPLR4_1_MSI_MAP_ADDR_LO |
60997 | #define BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
60998 | #define BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
60999 | //BIFPLR4_1_MSI_MAP_ADDR_HI |
61000 | #define BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
61001 | #define BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
61002 | //BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
61003 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61004 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61005 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61006 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61007 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61008 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61009 | //BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR |
61010 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
61011 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
61012 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
61013 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
61014 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
61015 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
61016 | //BIFPLR4_1_PCIE_VENDOR_SPECIFIC1 |
61017 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
61018 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
61019 | //BIFPLR4_1_PCIE_VENDOR_SPECIFIC2 |
61020 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
61021 | #define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
61022 | //BIFPLR4_1_PCIE_VC_ENH_CAP_LIST |
61023 | #define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61024 | #define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61025 | #define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61026 | #define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61027 | #define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61028 | #define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61029 | //BIFPLR4_1_PCIE_PORT_VC_CAP_REG1 |
61030 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
61031 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
61032 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
61033 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
61034 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
61035 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
61036 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
61037 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
61038 | //BIFPLR4_1_PCIE_PORT_VC_CAP_REG2 |
61039 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
61040 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
61041 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
61042 | #define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
61043 | //BIFPLR4_1_PCIE_PORT_VC_CNTL |
61044 | #define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
61045 | #define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
61046 | #define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
61047 | #define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
61048 | //BIFPLR4_1_PCIE_PORT_VC_STATUS |
61049 | #define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
61050 | #define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
61051 | //BIFPLR4_1_PCIE_VC0_RESOURCE_CAP |
61052 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
61053 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
61054 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
61055 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
61056 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
61057 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
61058 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
61059 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
61060 | //BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL |
61061 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
61062 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
61063 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
61064 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
61065 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
61066 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
61067 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
61068 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
61069 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
61070 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
61071 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
61072 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
61073 | //BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS |
61074 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
61075 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
61076 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
61077 | #define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
61078 | //BIFPLR4_1_PCIE_VC1_RESOURCE_CAP |
61079 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
61080 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
61081 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
61082 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
61083 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
61084 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
61085 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
61086 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
61087 | //BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL |
61088 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
61089 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
61090 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
61091 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
61092 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
61093 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
61094 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
61095 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
61096 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
61097 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
61098 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
61099 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
61100 | //BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS |
61101 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
61102 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
61103 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
61104 | #define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
61105 | //BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
61106 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61107 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61108 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61109 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61110 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61111 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61112 | //BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1 |
61113 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
61114 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
61115 | //BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2 |
61116 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
61117 | #define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
61118 | //BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
61119 | #define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61120 | #define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61121 | #define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61122 | #define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61123 | #define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61124 | #define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61125 | //BIFPLR4_1_PCIE_UNCORR_ERR_STATUS |
61126 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
61127 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
61128 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
61129 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
61130 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
61131 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
61132 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
61133 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
61134 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
61135 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
61136 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
61137 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
61138 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
61139 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
61140 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
61141 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
61142 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
61143 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
61144 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
61145 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
61146 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
61147 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
61148 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
61149 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
61150 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
61151 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
61152 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
61153 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
61154 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
61155 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
61156 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
61157 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
61158 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
61159 | #define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
61160 | //BIFPLR4_1_PCIE_UNCORR_ERR_MASK |
61161 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
61162 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
61163 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
61164 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
61165 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
61166 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
61167 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
61168 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
61169 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
61170 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
61171 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
61172 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
61173 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
61174 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
61175 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
61176 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
61177 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
61178 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
61179 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
61180 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
61181 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
61182 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
61183 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
61184 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
61185 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
61186 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
61187 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
61188 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
61189 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
61190 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
61191 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
61192 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
61193 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
61194 | #define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
61195 | //BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY |
61196 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
61197 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
61198 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
61199 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
61200 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
61201 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
61202 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
61203 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
61204 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
61205 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
61206 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
61207 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
61208 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
61209 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
61210 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
61211 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
61212 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
61213 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
61214 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
61215 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
61216 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
61217 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
61218 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
61219 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
61220 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
61221 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
61222 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
61223 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
61224 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
61225 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
61226 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
61227 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
61228 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
61229 | #define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
61230 | //BIFPLR4_1_PCIE_CORR_ERR_STATUS |
61231 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
61232 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
61233 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
61234 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
61235 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
61236 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
61237 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
61238 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
61239 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
61240 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
61241 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
61242 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
61243 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
61244 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
61245 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
61246 | #define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
61247 | //BIFPLR4_1_PCIE_CORR_ERR_MASK |
61248 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
61249 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
61250 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
61251 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
61252 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
61253 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
61254 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
61255 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
61256 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
61257 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
61258 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
61259 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
61260 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
61261 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
61262 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
61263 | #define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
61264 | //BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL |
61265 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
61266 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
61267 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
61268 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
61269 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
61270 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
61271 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
61272 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
61273 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
61274 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
61275 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
61276 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
61277 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
61278 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
61279 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
61280 | #define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
61281 | //BIFPLR4_1_PCIE_HDR_LOG0 |
61282 | #define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
61283 | #define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
61284 | //BIFPLR4_1_PCIE_HDR_LOG1 |
61285 | #define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
61286 | #define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
61287 | //BIFPLR4_1_PCIE_HDR_LOG2 |
61288 | #define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
61289 | #define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
61290 | //BIFPLR4_1_PCIE_HDR_LOG3 |
61291 | #define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
61292 | #define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
61293 | //BIFPLR4_1_PCIE_ROOT_ERR_CMD |
61294 | #define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
61295 | #define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
61296 | #define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
61297 | #define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
61298 | #define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
61299 | #define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
61300 | //BIFPLR4_1_PCIE_ROOT_ERR_STATUS |
61301 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
61302 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
61303 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
61304 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
61305 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
61306 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
61307 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
61308 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
61309 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
61310 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
61311 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
61312 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
61313 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
61314 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
61315 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
61316 | #define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
61317 | //BIFPLR4_1_PCIE_ERR_SRC_ID |
61318 | #define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
61319 | #define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
61320 | #define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
61321 | #define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
61322 | //BIFPLR4_1_PCIE_TLP_PREFIX_LOG0 |
61323 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
61324 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
61325 | //BIFPLR4_1_PCIE_TLP_PREFIX_LOG1 |
61326 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
61327 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
61328 | //BIFPLR4_1_PCIE_TLP_PREFIX_LOG2 |
61329 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
61330 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
61331 | //BIFPLR4_1_PCIE_TLP_PREFIX_LOG3 |
61332 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
61333 | #define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
61334 | //BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST |
61335 | #define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61336 | #define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61337 | #define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61338 | #define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61339 | #define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61340 | #define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61341 | //BIFPLR4_1_PCIE_LINK_CNTL3 |
61342 | #define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
61343 | #define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
61344 | #define BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
61345 | #define BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
61346 | #define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
61347 | #define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
61348 | #define BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
61349 | #define BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
61350 | //BIFPLR4_1_PCIE_LANE_ERROR_STATUS |
61351 | #define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
61352 | #define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
61353 | #define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
61354 | #define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
61355 | //BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL |
61356 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61357 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61358 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61359 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61360 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61361 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61362 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61363 | #define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61364 | //BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL |
61365 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61366 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61367 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61368 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61369 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61370 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61371 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61372 | #define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61373 | //BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL |
61374 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61375 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61376 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61377 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61378 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61379 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61380 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61381 | #define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61382 | //BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL |
61383 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61384 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61385 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61386 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61387 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61388 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61389 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61390 | #define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61391 | //BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL |
61392 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61393 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61394 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61395 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61396 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61397 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61398 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61399 | #define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61400 | //BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL |
61401 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61402 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61403 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61404 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61405 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61406 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61407 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61408 | #define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61409 | //BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL |
61410 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61411 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61412 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61413 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61414 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61415 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61416 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61417 | #define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61418 | //BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL |
61419 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61420 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61421 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61422 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61423 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61424 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61425 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61426 | #define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61427 | //BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL |
61428 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61429 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61430 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61431 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61432 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61433 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61434 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61435 | #define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61436 | //BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL |
61437 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61438 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61439 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61440 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61441 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61442 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61443 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61444 | #define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61445 | //BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL |
61446 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61447 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61448 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61449 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61450 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61451 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61452 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61453 | #define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61454 | //BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL |
61455 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61456 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61457 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61458 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61459 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61460 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61461 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61462 | #define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61463 | //BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL |
61464 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61465 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61466 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61467 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61468 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61469 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61470 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61471 | #define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61472 | //BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL |
61473 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61474 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61475 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61476 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61477 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61478 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61479 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61480 | #define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61481 | //BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL |
61482 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61483 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61484 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61485 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61486 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61487 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61488 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61489 | #define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61490 | //BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL |
61491 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
61492 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
61493 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
61494 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
61495 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
61496 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
61497 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
61498 | #define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
61499 | //BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST |
61500 | #define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61501 | #define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61502 | #define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61503 | #define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61504 | #define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61505 | #define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61506 | //BIFPLR4_1_PCIE_ACS_CAP |
61507 | #define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
61508 | #define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
61509 | #define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
61510 | #define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
61511 | #define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
61512 | #define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
61513 | #define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
61514 | #define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
61515 | #define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
61516 | #define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
61517 | #define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
61518 | #define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
61519 | #define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
61520 | #define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
61521 | #define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
61522 | #define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
61523 | //BIFPLR4_1_PCIE_ACS_CNTL |
61524 | #define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
61525 | #define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
61526 | #define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
61527 | #define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
61528 | #define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
61529 | #define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
61530 | #define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
61531 | #define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
61532 | #define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
61533 | #define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
61534 | #define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
61535 | #define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
61536 | #define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
61537 | #define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
61538 | //BIFPLR4_1_PCIE_MC_ENH_CAP_LIST |
61539 | #define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61540 | #define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61541 | #define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61542 | #define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61543 | #define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61544 | #define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61545 | //BIFPLR4_1_PCIE_MC_CAP |
61546 | #define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
61547 | #define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
61548 | #define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
61549 | #define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
61550 | //BIFPLR4_1_PCIE_MC_CNTL |
61551 | #define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
61552 | #define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
61553 | #define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
61554 | #define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
61555 | //BIFPLR4_1_PCIE_MC_ADDR0 |
61556 | #define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
61557 | #define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
61558 | #define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
61559 | #define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
61560 | //BIFPLR4_1_PCIE_MC_ADDR1 |
61561 | #define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
61562 | #define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
61563 | //BIFPLR4_1_PCIE_MC_RCV0 |
61564 | #define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
61565 | #define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
61566 | //BIFPLR4_1_PCIE_MC_RCV1 |
61567 | #define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
61568 | #define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
61569 | //BIFPLR4_1_PCIE_MC_BLOCK_ALL0 |
61570 | #define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
61571 | #define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
61572 | //BIFPLR4_1_PCIE_MC_BLOCK_ALL1 |
61573 | #define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
61574 | #define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
61575 | //BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
61576 | #define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
61577 | #define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
61578 | //BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
61579 | #define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
61580 | #define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
61581 | //BIFPLR4_1_PCIE_MC_OVERLAY_BAR0 |
61582 | #define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
61583 | #define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
61584 | #define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
61585 | #define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
61586 | //BIFPLR4_1_PCIE_MC_OVERLAY_BAR1 |
61587 | #define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
61588 | #define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
61589 | //BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST |
61590 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
61591 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
61592 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61593 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61594 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61595 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61596 | //BIFPLR4_1_PCIE_L1_PM_SUB_CAP |
61597 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
61598 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
61599 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
61600 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
61601 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
61602 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
61603 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
61604 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
61605 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
61606 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
61607 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
61608 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
61609 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
61610 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
61611 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
61612 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
61613 | //BIFPLR4_1_PCIE_L1_PM_SUB_CNTL |
61614 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
61615 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
61616 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
61617 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
61618 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
61619 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
61620 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
61621 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
61622 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
61623 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
61624 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
61625 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
61626 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
61627 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
61628 | //BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2 |
61629 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
61630 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
61631 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
61632 | #define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
61633 | //BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST |
61634 | #define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
61635 | #define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
61636 | #define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61637 | #define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61638 | #define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61639 | #define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61640 | //BIFPLR4_1_PCIE_DPC_CAP_LIST |
61641 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
61642 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
61643 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
61644 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
61645 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
61646 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
61647 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
61648 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
61649 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
61650 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
61651 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
61652 | #define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
61653 | //BIFPLR4_1_PCIE_DPC_CNTL |
61654 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
61655 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
61656 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
61657 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
61658 | #define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
61659 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
61660 | #define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
61661 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
61662 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
61663 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
61664 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
61665 | #define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
61666 | #define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
61667 | #define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
61668 | //BIFPLR4_1_PCIE_DPC_STATUS |
61669 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
61670 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
61671 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
61672 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
61673 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
61674 | #define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
61675 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
61676 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
61677 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
61678 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
61679 | #define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
61680 | #define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
61681 | //BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID |
61682 | #define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
61683 | #define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
61684 | //BIFPLR4_1_PCIE_RP_PIO_STATUS |
61685 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
61686 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
61687 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
61688 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
61689 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
61690 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
61691 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
61692 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
61693 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
61694 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
61695 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
61696 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
61697 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
61698 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
61699 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
61700 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
61701 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
61702 | #define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
61703 | //BIFPLR4_1_PCIE_RP_PIO_MASK |
61704 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
61705 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
61706 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
61707 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
61708 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
61709 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
61710 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
61711 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
61712 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
61713 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
61714 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
61715 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
61716 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
61717 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
61718 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
61719 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
61720 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
61721 | #define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
61722 | //BIFPLR4_1_PCIE_RP_PIO_SEVERITY |
61723 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
61724 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
61725 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
61726 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
61727 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
61728 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
61729 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
61730 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
61731 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
61732 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
61733 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
61734 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
61735 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
61736 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
61737 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
61738 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
61739 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
61740 | #define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
61741 | //BIFPLR4_1_PCIE_RP_PIO_SYSERROR |
61742 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
61743 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
61744 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
61745 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
61746 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
61747 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
61748 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
61749 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
61750 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
61751 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
61752 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
61753 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
61754 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
61755 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
61756 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
61757 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
61758 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
61759 | #define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
61760 | //BIFPLR4_1_PCIE_RP_PIO_EXCEPTION |
61761 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
61762 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
61763 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
61764 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
61765 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
61766 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
61767 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
61768 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
61769 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
61770 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
61771 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
61772 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
61773 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
61774 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
61775 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
61776 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
61777 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
61778 | #define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
61779 | //BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0 |
61780 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
61781 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
61782 | //BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1 |
61783 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
61784 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
61785 | //BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2 |
61786 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
61787 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
61788 | //BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3 |
61789 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
61790 | #define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
61791 | //BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG |
61792 | #define BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
61793 | #define BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
61794 | //BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0 |
61795 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
61796 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
61797 | //BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1 |
61798 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
61799 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
61800 | //BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2 |
61801 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
61802 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
61803 | //BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3 |
61804 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
61805 | #define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
61806 | //BIFPLR4_1_PCIE_ESM_CAP_LIST |
61807 | #define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
61808 | #define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
61809 | #define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
61810 | #define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
61811 | #define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
61812 | #define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
61813 | //BIFPLR4_1_PCIE_ESM_HEADER_1 |
61814 | #define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
61815 | #define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
61816 | #define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
61817 | #define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
61818 | #define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
61819 | #define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
61820 | //BIFPLR4_1_PCIE_ESM_HEADER_2 |
61821 | #define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
61822 | #define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
61823 | //BIFPLR4_1_PCIE_ESM_STATUS |
61824 | #define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
61825 | #define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
61826 | #define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
61827 | #define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
61828 | //BIFPLR4_1_PCIE_ESM_CTRL |
61829 | #define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
61830 | #define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
61831 | #define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
61832 | #define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
61833 | #define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
61834 | #define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
61835 | //BIFPLR4_1_PCIE_ESM_CAP_1 |
61836 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
61837 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
61838 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
61839 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
61840 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
61841 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
61842 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
61843 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
61844 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
61845 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
61846 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
61847 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
61848 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
61849 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
61850 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
61851 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
61852 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
61853 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
61854 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
61855 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
61856 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
61857 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
61858 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
61859 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
61860 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
61861 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
61862 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
61863 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
61864 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
61865 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
61866 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
61867 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
61868 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
61869 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
61870 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
61871 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
61872 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
61873 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
61874 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
61875 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
61876 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
61877 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
61878 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
61879 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
61880 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
61881 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
61882 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
61883 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
61884 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
61885 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
61886 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
61887 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
61888 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
61889 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
61890 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
61891 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
61892 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
61893 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
61894 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
61895 | #define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
61896 | //BIFPLR4_1_PCIE_ESM_CAP_2 |
61897 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
61898 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
61899 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
61900 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
61901 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
61902 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
61903 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
61904 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
61905 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
61906 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
61907 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
61908 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
61909 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
61910 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
61911 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
61912 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
61913 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
61914 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
61915 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
61916 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
61917 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
61918 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
61919 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
61920 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
61921 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
61922 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
61923 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
61924 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
61925 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
61926 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
61927 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
61928 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
61929 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
61930 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
61931 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
61932 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
61933 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
61934 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
61935 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
61936 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
61937 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
61938 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
61939 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
61940 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
61941 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
61942 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
61943 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
61944 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
61945 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
61946 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
61947 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
61948 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
61949 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
61950 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
61951 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
61952 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
61953 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
61954 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
61955 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
61956 | #define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
61957 | //BIFPLR4_1_PCIE_ESM_CAP_3 |
61958 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
61959 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
61960 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
61961 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
61962 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
61963 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
61964 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
61965 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
61966 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
61967 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
61968 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
61969 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
61970 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
61971 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
61972 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
61973 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
61974 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
61975 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
61976 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
61977 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
61978 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
61979 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
61980 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
61981 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
61982 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
61983 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
61984 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
61985 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
61986 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
61987 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
61988 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
61989 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
61990 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
61991 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
61992 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
61993 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
61994 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
61995 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
61996 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
61997 | #define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
61998 | //BIFPLR4_1_PCIE_ESM_CAP_4 |
61999 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
62000 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
62001 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
62002 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
62003 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
62004 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
62005 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
62006 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
62007 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
62008 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
62009 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
62010 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
62011 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
62012 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
62013 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
62014 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
62015 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
62016 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
62017 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
62018 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
62019 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
62020 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
62021 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
62022 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
62023 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
62024 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
62025 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
62026 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
62027 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
62028 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
62029 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
62030 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
62031 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
62032 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
62033 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
62034 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
62035 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
62036 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
62037 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
62038 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
62039 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
62040 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
62041 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
62042 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
62043 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
62044 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
62045 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
62046 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
62047 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
62048 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
62049 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
62050 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
62051 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
62052 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
62053 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
62054 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
62055 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
62056 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
62057 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
62058 | #define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
62059 | //BIFPLR4_1_PCIE_ESM_CAP_5 |
62060 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
62061 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
62062 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
62063 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
62064 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
62065 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
62066 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
62067 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
62068 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
62069 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
62070 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
62071 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
62072 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
62073 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
62074 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
62075 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
62076 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
62077 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
62078 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
62079 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
62080 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
62081 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
62082 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
62083 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
62084 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
62085 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
62086 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
62087 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
62088 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
62089 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
62090 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
62091 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
62092 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
62093 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
62094 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
62095 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
62096 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
62097 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
62098 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
62099 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
62100 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
62101 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
62102 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
62103 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
62104 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
62105 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
62106 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
62107 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
62108 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
62109 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
62110 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
62111 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
62112 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
62113 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
62114 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
62115 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
62116 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
62117 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
62118 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
62119 | #define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
62120 | //BIFPLR4_1_PCIE_ESM_CAP_6 |
62121 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
62122 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
62123 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
62124 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
62125 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
62126 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
62127 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
62128 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
62129 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
62130 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
62131 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
62132 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
62133 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
62134 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
62135 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
62136 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
62137 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
62138 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
62139 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
62140 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
62141 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
62142 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
62143 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
62144 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
62145 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
62146 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
62147 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
62148 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
62149 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
62150 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
62151 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
62152 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
62153 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
62154 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
62155 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
62156 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
62157 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
62158 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
62159 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
62160 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
62161 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
62162 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
62163 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
62164 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
62165 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
62166 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
62167 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
62168 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
62169 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
62170 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
62171 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
62172 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
62173 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
62174 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
62175 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
62176 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
62177 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
62178 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
62179 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
62180 | #define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
62181 | //BIFPLR4_1_PCIE_ESM_CAP_7 |
62182 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
62183 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
62184 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
62185 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
62186 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
62187 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
62188 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
62189 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
62190 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
62191 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
62192 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
62193 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
62194 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
62195 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
62196 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
62197 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
62198 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
62199 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
62200 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
62201 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
62202 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
62203 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
62204 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
62205 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
62206 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
62207 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
62208 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
62209 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
62210 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
62211 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
62212 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
62213 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
62214 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
62215 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
62216 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
62217 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
62218 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
62219 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
62220 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
62221 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
62222 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
62223 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
62224 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
62225 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
62226 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
62227 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
62228 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
62229 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
62230 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
62231 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
62232 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
62233 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
62234 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
62235 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
62236 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
62237 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
62238 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
62239 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
62240 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
62241 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
62242 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
62243 | #define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
62244 | |
62245 | |
62246 | // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
62247 | //BIFPLR5_1_VENDOR_ID |
62248 | #define BIFPLR5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
62249 | #define BIFPLR5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
62250 | //BIFPLR5_1_DEVICE_ID |
62251 | #define BIFPLR5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
62252 | #define BIFPLR5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
62253 | //BIFPLR5_1_COMMAND |
62254 | #define BIFPLR5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
62255 | #define BIFPLR5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
62256 | #define BIFPLR5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
62257 | #define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
62258 | #define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
62259 | #define BIFPLR5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
62260 | #define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
62261 | #define BIFPLR5_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
62262 | #define BIFPLR5_1_COMMAND__SERR_EN__SHIFT 0x8 |
62263 | #define BIFPLR5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
62264 | #define BIFPLR5_1_COMMAND__INT_DIS__SHIFT 0xa |
62265 | #define BIFPLR5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
62266 | #define BIFPLR5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
62267 | #define BIFPLR5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
62268 | #define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
62269 | #define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
62270 | #define BIFPLR5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
62271 | #define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
62272 | #define BIFPLR5_1_COMMAND__AD_STEPPING_MASK 0x0080L |
62273 | #define BIFPLR5_1_COMMAND__SERR_EN_MASK 0x0100L |
62274 | #define BIFPLR5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
62275 | #define BIFPLR5_1_COMMAND__INT_DIS_MASK 0x0400L |
62276 | //BIFPLR5_1_STATUS |
62277 | #define BIFPLR5_1_STATUS__INT_STATUS__SHIFT 0x3 |
62278 | #define BIFPLR5_1_STATUS__CAP_LIST__SHIFT 0x4 |
62279 | #define BIFPLR5_1_STATUS__PCI_66_EN__SHIFT 0x5 |
62280 | #define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
62281 | #define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
62282 | #define BIFPLR5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
62283 | #define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
62284 | #define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
62285 | #define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
62286 | #define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
62287 | #define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
62288 | #define BIFPLR5_1_STATUS__INT_STATUS_MASK 0x0008L |
62289 | #define BIFPLR5_1_STATUS__CAP_LIST_MASK 0x0010L |
62290 | #define BIFPLR5_1_STATUS__PCI_66_EN_MASK 0x0020L |
62291 | #define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
62292 | #define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
62293 | #define BIFPLR5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
62294 | #define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
62295 | #define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
62296 | #define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
62297 | #define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
62298 | #define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
62299 | //BIFPLR5_1_REVISION_ID |
62300 | #define BIFPLR5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
62301 | #define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
62302 | #define BIFPLR5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
62303 | #define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
62304 | //BIFPLR5_1_PROG_INTERFACE |
62305 | #define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
62306 | #define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
62307 | //BIFPLR5_1_SUB_CLASS |
62308 | #define BIFPLR5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
62309 | #define BIFPLR5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
62310 | //BIFPLR5_1_BASE_CLASS |
62311 | #define BIFPLR5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
62312 | #define BIFPLR5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
62313 | //BIFPLR5_1_CACHE_LINE |
62314 | #define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
62315 | #define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
62316 | //BIFPLR5_1_LATENCY |
62317 | #define BIFPLR5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
62318 | #define BIFPLR5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
62319 | //BIFPLR5_1_HEADER |
62320 | #define BIFPLR5_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
62321 | #define BIFPLR5_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
62322 | #define BIFPLR5_1_HEADER__HEADER_TYPE_MASK 0x7FL |
62323 | #define BIFPLR5_1_HEADER__DEVICE_TYPE_MASK 0x80L |
62324 | //BIFPLR5_1_BIST |
62325 | #define BIFPLR5_1_BIST__BIST_COMP__SHIFT 0x0 |
62326 | #define BIFPLR5_1_BIST__BIST_STRT__SHIFT 0x6 |
62327 | #define BIFPLR5_1_BIST__BIST_CAP__SHIFT 0x7 |
62328 | #define BIFPLR5_1_BIST__BIST_COMP_MASK 0x0FL |
62329 | #define BIFPLR5_1_BIST__BIST_STRT_MASK 0x40L |
62330 | #define BIFPLR5_1_BIST__BIST_CAP_MASK 0x80L |
62331 | //BIFPLR5_1_SUB_BUS_NUMBER_LATENCY |
62332 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
62333 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
62334 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
62335 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
62336 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
62337 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
62338 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
62339 | #define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
62340 | //BIFPLR5_1_IO_BASE_LIMIT |
62341 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
62342 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
62343 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
62344 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
62345 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
62346 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
62347 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
62348 | #define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
62349 | //BIFPLR5_1_SECONDARY_STATUS |
62350 | #define BIFPLR5_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
62351 | #define BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
62352 | #define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
62353 | #define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
62354 | #define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
62355 | #define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
62356 | #define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
62357 | #define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
62358 | #define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
62359 | #define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
62360 | #define BIFPLR5_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
62361 | #define BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
62362 | #define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
62363 | #define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
62364 | #define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
62365 | #define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
62366 | #define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
62367 | #define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
62368 | #define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
62369 | #define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
62370 | //BIFPLR5_1_MEM_BASE_LIMIT |
62371 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
62372 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
62373 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
62374 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
62375 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
62376 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
62377 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
62378 | #define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
62379 | //BIFPLR5_1_PREF_BASE_LIMIT |
62380 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
62381 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
62382 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
62383 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
62384 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
62385 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
62386 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
62387 | #define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
62388 | //BIFPLR5_1_PREF_BASE_UPPER |
62389 | #define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
62390 | #define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
62391 | //BIFPLR5_1_PREF_LIMIT_UPPER |
62392 | #define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
62393 | #define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
62394 | //BIFPLR5_1_IO_BASE_LIMIT_HI |
62395 | #define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
62396 | #define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
62397 | #define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
62398 | #define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
62399 | //BIFPLR5_1_CAP_PTR |
62400 | #define BIFPLR5_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
62401 | #define BIFPLR5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
62402 | //BIFPLR5_1_INTERRUPT_LINE |
62403 | #define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
62404 | #define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
62405 | //BIFPLR5_1_INTERRUPT_PIN |
62406 | #define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
62407 | #define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
62408 | //BIFPLR5_1_IRQ_BRIDGE_CNTL |
62409 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
62410 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
62411 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
62412 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
62413 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
62414 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
62415 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
62416 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
62417 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
62418 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
62419 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
62420 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
62421 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
62422 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
62423 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
62424 | #define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
62425 | //BIFPLR5_1_EXT_BRIDGE_CNTL |
62426 | #define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
62427 | #define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
62428 | //BIFPLR5_1_PMI_CAP_LIST |
62429 | #define BIFPLR5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
62430 | #define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
62431 | #define BIFPLR5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
62432 | #define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
62433 | //BIFPLR5_1_PMI_CAP |
62434 | #define BIFPLR5_1_PMI_CAP__VERSION__SHIFT 0x0 |
62435 | #define BIFPLR5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
62436 | #define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
62437 | #define BIFPLR5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
62438 | #define BIFPLR5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
62439 | #define BIFPLR5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
62440 | #define BIFPLR5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
62441 | #define BIFPLR5_1_PMI_CAP__VERSION_MASK 0x0007L |
62442 | #define BIFPLR5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
62443 | #define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
62444 | #define BIFPLR5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
62445 | #define BIFPLR5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
62446 | #define BIFPLR5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
62447 | #define BIFPLR5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
62448 | //BIFPLR5_1_PMI_STATUS_CNTL |
62449 | #define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
62450 | #define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
62451 | #define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
62452 | #define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
62453 | #define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
62454 | #define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
62455 | #define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
62456 | #define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
62457 | #define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
62458 | #define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
62459 | #define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
62460 | #define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
62461 | #define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
62462 | #define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
62463 | #define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
62464 | #define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
62465 | #define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
62466 | #define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
62467 | //BIFPLR5_1_PCIE_CAP_LIST |
62468 | #define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
62469 | #define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
62470 | #define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
62471 | #define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
62472 | //BIFPLR5_1_PCIE_CAP |
62473 | #define BIFPLR5_1_PCIE_CAP__VERSION__SHIFT 0x0 |
62474 | #define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
62475 | #define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
62476 | #define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
62477 | #define BIFPLR5_1_PCIE_CAP__VERSION_MASK 0x000FL |
62478 | #define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
62479 | #define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
62480 | #define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
62481 | //BIFPLR5_1_DEVICE_CAP |
62482 | #define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
62483 | #define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
62484 | #define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
62485 | #define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
62486 | #define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
62487 | #define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
62488 | #define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
62489 | #define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
62490 | #define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
62491 | #define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
62492 | #define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
62493 | #define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
62494 | #define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
62495 | #define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
62496 | #define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
62497 | #define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
62498 | #define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
62499 | #define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
62500 | //BIFPLR5_1_DEVICE_CNTL |
62501 | #define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
62502 | #define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
62503 | #define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
62504 | #define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
62505 | #define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
62506 | #define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
62507 | #define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
62508 | #define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
62509 | #define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
62510 | #define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
62511 | #define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
62512 | #define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
62513 | #define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
62514 | #define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
62515 | #define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
62516 | #define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
62517 | #define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
62518 | #define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
62519 | #define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
62520 | #define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
62521 | #define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
62522 | #define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
62523 | #define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
62524 | #define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
62525 | //BIFPLR5_1_DEVICE_STATUS |
62526 | #define BIFPLR5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
62527 | #define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
62528 | #define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
62529 | #define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
62530 | #define BIFPLR5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
62531 | #define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
62532 | #define BIFPLR5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
62533 | #define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
62534 | #define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
62535 | #define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
62536 | #define BIFPLR5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
62537 | #define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
62538 | //BIFPLR5_1_LINK_CAP |
62539 | #define BIFPLR5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
62540 | #define BIFPLR5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
62541 | #define BIFPLR5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
62542 | #define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
62543 | #define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
62544 | #define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
62545 | #define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
62546 | #define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
62547 | #define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
62548 | #define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
62549 | #define BIFPLR5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
62550 | #define BIFPLR5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
62551 | #define BIFPLR5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
62552 | #define BIFPLR5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
62553 | #define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
62554 | #define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
62555 | #define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
62556 | #define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
62557 | #define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
62558 | #define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
62559 | #define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
62560 | #define BIFPLR5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
62561 | //BIFPLR5_1_LINK_CNTL |
62562 | #define BIFPLR5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
62563 | #define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
62564 | #define BIFPLR5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
62565 | #define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
62566 | #define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
62567 | #define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
62568 | #define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
62569 | #define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
62570 | #define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
62571 | #define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
62572 | #define BIFPLR5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
62573 | #define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
62574 | #define BIFPLR5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
62575 | #define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
62576 | #define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
62577 | #define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
62578 | #define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
62579 | #define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
62580 | #define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
62581 | #define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
62582 | //BIFPLR5_1_LINK_STATUS |
62583 | #define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
62584 | #define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
62585 | #define BIFPLR5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
62586 | #define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
62587 | #define BIFPLR5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
62588 | #define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
62589 | #define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
62590 | #define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
62591 | #define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
62592 | #define BIFPLR5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
62593 | #define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
62594 | #define BIFPLR5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
62595 | #define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
62596 | #define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
62597 | //BIFPLR5_1_SLOT_CAP |
62598 | #define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
62599 | #define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
62600 | #define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
62601 | #define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
62602 | #define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
62603 | #define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
62604 | #define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
62605 | #define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
62606 | #define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
62607 | #define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
62608 | #define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
62609 | #define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
62610 | #define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
62611 | #define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
62612 | #define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
62613 | #define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
62614 | #define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
62615 | #define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
62616 | #define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
62617 | #define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
62618 | #define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
62619 | #define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
62620 | #define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
62621 | #define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
62622 | //BIFPLR5_1_SLOT_CNTL |
62623 | #define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
62624 | #define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
62625 | #define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
62626 | #define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
62627 | #define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
62628 | #define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
62629 | #define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
62630 | #define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
62631 | #define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
62632 | #define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
62633 | #define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
62634 | #define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
62635 | #define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
62636 | #define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
62637 | #define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
62638 | #define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
62639 | #define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
62640 | #define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
62641 | #define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
62642 | #define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
62643 | #define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
62644 | #define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
62645 | #define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
62646 | #define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
62647 | //BIFPLR5_1_SLOT_STATUS |
62648 | #define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
62649 | #define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
62650 | #define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
62651 | #define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
62652 | #define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
62653 | #define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
62654 | #define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
62655 | #define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
62656 | #define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
62657 | #define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
62658 | #define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
62659 | #define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
62660 | #define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
62661 | #define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
62662 | #define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
62663 | #define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
62664 | #define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
62665 | #define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
62666 | //BIFPLR5_1_ROOT_CNTL |
62667 | #define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
62668 | #define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
62669 | #define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
62670 | #define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
62671 | #define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
62672 | #define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
62673 | #define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
62674 | #define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
62675 | #define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
62676 | #define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
62677 | //BIFPLR5_1_ROOT_CAP |
62678 | #define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
62679 | #define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
62680 | //BIFPLR5_1_ROOT_STATUS |
62681 | #define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
62682 | #define BIFPLR5_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
62683 | #define BIFPLR5_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
62684 | #define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
62685 | #define BIFPLR5_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
62686 | #define BIFPLR5_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
62687 | //BIFPLR5_1_DEVICE_CAP2 |
62688 | #define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
62689 | #define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
62690 | #define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
62691 | #define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
62692 | #define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
62693 | #define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
62694 | #define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
62695 | #define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
62696 | #define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
62697 | #define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
62698 | #define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
62699 | #define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
62700 | #define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
62701 | #define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
62702 | #define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
62703 | #define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
62704 | #define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
62705 | #define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
62706 | #define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
62707 | #define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
62708 | #define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
62709 | #define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
62710 | #define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
62711 | #define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
62712 | #define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
62713 | #define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
62714 | #define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
62715 | #define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
62716 | //BIFPLR5_1_DEVICE_CNTL2 |
62717 | #define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
62718 | #define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
62719 | #define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
62720 | #define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
62721 | #define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
62722 | #define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
62723 | #define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
62724 | #define BIFPLR5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
62725 | #define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
62726 | #define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
62727 | #define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
62728 | #define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
62729 | #define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
62730 | #define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
62731 | #define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
62732 | #define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
62733 | #define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
62734 | #define BIFPLR5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
62735 | #define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
62736 | #define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
62737 | //BIFPLR5_1_DEVICE_STATUS2 |
62738 | #define BIFPLR5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
62739 | #define BIFPLR5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
62740 | //BIFPLR5_1_LINK_CAP2 |
62741 | #define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
62742 | #define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
62743 | #define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
62744 | #define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
62745 | #define BIFPLR5_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
62746 | #define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
62747 | #define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
62748 | #define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
62749 | #define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
62750 | #define BIFPLR5_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
62751 | //BIFPLR5_1_LINK_CNTL2 |
62752 | #define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
62753 | #define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
62754 | #define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
62755 | #define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
62756 | #define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
62757 | #define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
62758 | #define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
62759 | #define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
62760 | #define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
62761 | #define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
62762 | #define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
62763 | #define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
62764 | #define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
62765 | #define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
62766 | #define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
62767 | #define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
62768 | //BIFPLR5_1_LINK_STATUS2 |
62769 | #define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
62770 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
62771 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
62772 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
62773 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
62774 | #define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
62775 | #define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
62776 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
62777 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
62778 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
62779 | #define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
62780 | #define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
62781 | //BIFPLR5_1_SLOT_CAP2 |
62782 | #define BIFPLR5_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
62783 | #define BIFPLR5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
62784 | //BIFPLR5_1_SLOT_CNTL2 |
62785 | #define BIFPLR5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
62786 | #define BIFPLR5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
62787 | //BIFPLR5_1_SLOT_STATUS2 |
62788 | #define BIFPLR5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
62789 | #define BIFPLR5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
62790 | //BIFPLR5_1_MSI_CAP_LIST |
62791 | #define BIFPLR5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
62792 | #define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
62793 | #define BIFPLR5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
62794 | #define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
62795 | //BIFPLR5_1_MSI_MSG_CNTL |
62796 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
62797 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
62798 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
62799 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
62800 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
62801 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
62802 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
62803 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
62804 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
62805 | #define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
62806 | //BIFPLR5_1_MSI_MSG_ADDR_LO |
62807 | #define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
62808 | #define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
62809 | //BIFPLR5_1_MSI_MSG_ADDR_HI |
62810 | #define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
62811 | #define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
62812 | //BIFPLR5_1_MSI_MSG_DATA |
62813 | #define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
62814 | #define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
62815 | //BIFPLR5_1_MSI_MSG_DATA_64 |
62816 | #define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
62817 | #define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
62818 | //BIFPLR5_1_SSID_CAP_LIST |
62819 | #define BIFPLR5_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
62820 | #define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
62821 | #define BIFPLR5_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
62822 | #define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
62823 | //BIFPLR5_1_SSID_CAP |
62824 | #define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
62825 | #define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
62826 | #define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
62827 | #define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
62828 | //BIFPLR5_1_MSI_MAP_CAP_LIST |
62829 | #define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
62830 | #define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
62831 | #define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
62832 | #define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
62833 | //BIFPLR5_1_MSI_MAP_CAP |
62834 | #define BIFPLR5_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
62835 | #define BIFPLR5_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
62836 | #define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
62837 | #define BIFPLR5_1_MSI_MAP_CAP__EN_MASK 0x0001L |
62838 | #define BIFPLR5_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
62839 | #define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
62840 | //BIFPLR5_1_MSI_MAP_ADDR_LO |
62841 | #define BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
62842 | #define BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
62843 | //BIFPLR5_1_MSI_MAP_ADDR_HI |
62844 | #define BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
62845 | #define BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
62846 | //BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
62847 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
62848 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
62849 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
62850 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
62851 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
62852 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
62853 | //BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR |
62854 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
62855 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
62856 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
62857 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
62858 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
62859 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
62860 | //BIFPLR5_1_PCIE_VENDOR_SPECIFIC1 |
62861 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
62862 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
62863 | //BIFPLR5_1_PCIE_VENDOR_SPECIFIC2 |
62864 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
62865 | #define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
62866 | //BIFPLR5_1_PCIE_VC_ENH_CAP_LIST |
62867 | #define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
62868 | #define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
62869 | #define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
62870 | #define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
62871 | #define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
62872 | #define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
62873 | //BIFPLR5_1_PCIE_PORT_VC_CAP_REG1 |
62874 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
62875 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
62876 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
62877 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
62878 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
62879 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
62880 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
62881 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
62882 | //BIFPLR5_1_PCIE_PORT_VC_CAP_REG2 |
62883 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
62884 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
62885 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
62886 | #define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
62887 | //BIFPLR5_1_PCIE_PORT_VC_CNTL |
62888 | #define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
62889 | #define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
62890 | #define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
62891 | #define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
62892 | //BIFPLR5_1_PCIE_PORT_VC_STATUS |
62893 | #define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
62894 | #define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
62895 | //BIFPLR5_1_PCIE_VC0_RESOURCE_CAP |
62896 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
62897 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
62898 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
62899 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
62900 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
62901 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
62902 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
62903 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
62904 | //BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL |
62905 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
62906 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
62907 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
62908 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
62909 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
62910 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
62911 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
62912 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
62913 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
62914 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
62915 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
62916 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
62917 | //BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS |
62918 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
62919 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
62920 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
62921 | #define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
62922 | //BIFPLR5_1_PCIE_VC1_RESOURCE_CAP |
62923 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
62924 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
62925 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
62926 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
62927 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
62928 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
62929 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
62930 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
62931 | //BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL |
62932 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
62933 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
62934 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
62935 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
62936 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
62937 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
62938 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
62939 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
62940 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
62941 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
62942 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
62943 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
62944 | //BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS |
62945 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
62946 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
62947 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
62948 | #define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
62949 | //BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
62950 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
62951 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
62952 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
62953 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
62954 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
62955 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
62956 | //BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1 |
62957 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
62958 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
62959 | //BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2 |
62960 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
62961 | #define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
62962 | //BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
62963 | #define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
62964 | #define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
62965 | #define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
62966 | #define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
62967 | #define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
62968 | #define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
62969 | //BIFPLR5_1_PCIE_UNCORR_ERR_STATUS |
62970 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
62971 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
62972 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
62973 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
62974 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
62975 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
62976 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
62977 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
62978 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
62979 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
62980 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
62981 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
62982 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
62983 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
62984 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
62985 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
62986 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
62987 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
62988 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
62989 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
62990 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
62991 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
62992 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
62993 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
62994 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
62995 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
62996 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
62997 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
62998 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
62999 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
63000 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
63001 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
63002 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
63003 | #define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
63004 | //BIFPLR5_1_PCIE_UNCORR_ERR_MASK |
63005 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
63006 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
63007 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
63008 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
63009 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
63010 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
63011 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
63012 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
63013 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
63014 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
63015 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
63016 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
63017 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
63018 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
63019 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
63020 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
63021 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
63022 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
63023 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
63024 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
63025 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
63026 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
63027 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
63028 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
63029 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
63030 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
63031 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
63032 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
63033 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
63034 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
63035 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
63036 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
63037 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
63038 | #define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
63039 | //BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY |
63040 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
63041 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
63042 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
63043 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
63044 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
63045 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
63046 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
63047 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
63048 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
63049 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
63050 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
63051 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
63052 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
63053 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
63054 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
63055 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
63056 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
63057 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
63058 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
63059 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
63060 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
63061 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
63062 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
63063 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
63064 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
63065 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
63066 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
63067 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
63068 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
63069 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
63070 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
63071 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
63072 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
63073 | #define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
63074 | //BIFPLR5_1_PCIE_CORR_ERR_STATUS |
63075 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
63076 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
63077 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
63078 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
63079 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
63080 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
63081 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
63082 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
63083 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
63084 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
63085 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
63086 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
63087 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
63088 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
63089 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
63090 | #define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
63091 | //BIFPLR5_1_PCIE_CORR_ERR_MASK |
63092 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
63093 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
63094 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
63095 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
63096 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
63097 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
63098 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
63099 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
63100 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
63101 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
63102 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
63103 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
63104 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
63105 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
63106 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
63107 | #define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
63108 | //BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL |
63109 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
63110 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
63111 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
63112 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
63113 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
63114 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
63115 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
63116 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
63117 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
63118 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
63119 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
63120 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
63121 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
63122 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
63123 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
63124 | #define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
63125 | //BIFPLR5_1_PCIE_HDR_LOG0 |
63126 | #define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
63127 | #define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
63128 | //BIFPLR5_1_PCIE_HDR_LOG1 |
63129 | #define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
63130 | #define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
63131 | //BIFPLR5_1_PCIE_HDR_LOG2 |
63132 | #define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
63133 | #define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
63134 | //BIFPLR5_1_PCIE_HDR_LOG3 |
63135 | #define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
63136 | #define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
63137 | //BIFPLR5_1_PCIE_ROOT_ERR_CMD |
63138 | #define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
63139 | #define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
63140 | #define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
63141 | #define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
63142 | #define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
63143 | #define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
63144 | //BIFPLR5_1_PCIE_ROOT_ERR_STATUS |
63145 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
63146 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
63147 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
63148 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
63149 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
63150 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
63151 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
63152 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
63153 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
63154 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
63155 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
63156 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
63157 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
63158 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
63159 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
63160 | #define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
63161 | //BIFPLR5_1_PCIE_ERR_SRC_ID |
63162 | #define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
63163 | #define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
63164 | #define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
63165 | #define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
63166 | //BIFPLR5_1_PCIE_TLP_PREFIX_LOG0 |
63167 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
63168 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
63169 | //BIFPLR5_1_PCIE_TLP_PREFIX_LOG1 |
63170 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
63171 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
63172 | //BIFPLR5_1_PCIE_TLP_PREFIX_LOG2 |
63173 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
63174 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
63175 | //BIFPLR5_1_PCIE_TLP_PREFIX_LOG3 |
63176 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
63177 | #define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
63178 | //BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST |
63179 | #define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
63180 | #define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
63181 | #define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
63182 | #define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
63183 | #define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
63184 | #define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
63185 | //BIFPLR5_1_PCIE_LINK_CNTL3 |
63186 | #define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
63187 | #define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
63188 | #define BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
63189 | #define BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
63190 | #define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
63191 | #define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
63192 | #define BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
63193 | #define BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
63194 | //BIFPLR5_1_PCIE_LANE_ERROR_STATUS |
63195 | #define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
63196 | #define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
63197 | #define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
63198 | #define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
63199 | //BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL |
63200 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63201 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63202 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63203 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63204 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63205 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63206 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63207 | #define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63208 | //BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL |
63209 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63210 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63211 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63212 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63213 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63214 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63215 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63216 | #define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63217 | //BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL |
63218 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63219 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63220 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63221 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63222 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63223 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63224 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63225 | #define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63226 | //BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL |
63227 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63228 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63229 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63230 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63231 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63232 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63233 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63234 | #define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63235 | //BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL |
63236 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63237 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63238 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63239 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63240 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63241 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63242 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63243 | #define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63244 | //BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL |
63245 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63246 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63247 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63248 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63249 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63250 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63251 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63252 | #define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63253 | //BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL |
63254 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63255 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63256 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63257 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63258 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63259 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63260 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63261 | #define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63262 | //BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL |
63263 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63264 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63265 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63266 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63267 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63268 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63269 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63270 | #define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63271 | //BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL |
63272 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63273 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63274 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63275 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63276 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63277 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63278 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63279 | #define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63280 | //BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL |
63281 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63282 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63283 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63284 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63285 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63286 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63287 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63288 | #define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63289 | //BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL |
63290 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63291 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63292 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63293 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63294 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63295 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63296 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63297 | #define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63298 | //BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL |
63299 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63300 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63301 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63302 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63303 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63304 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63305 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63306 | #define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63307 | //BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL |
63308 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63309 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63310 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63311 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63312 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63313 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63314 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63315 | #define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63316 | //BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL |
63317 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63318 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63319 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63320 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63321 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63322 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63323 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63324 | #define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63325 | //BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL |
63326 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63327 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63328 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63329 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63330 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63331 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63332 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63333 | #define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63334 | //BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL |
63335 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
63336 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
63337 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
63338 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
63339 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
63340 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
63341 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
63342 | #define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
63343 | //BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST |
63344 | #define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
63345 | #define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
63346 | #define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
63347 | #define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
63348 | #define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
63349 | #define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
63350 | //BIFPLR5_1_PCIE_ACS_CAP |
63351 | #define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
63352 | #define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
63353 | #define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
63354 | #define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
63355 | #define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
63356 | #define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
63357 | #define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
63358 | #define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
63359 | #define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
63360 | #define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
63361 | #define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
63362 | #define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
63363 | #define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
63364 | #define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
63365 | #define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
63366 | #define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
63367 | //BIFPLR5_1_PCIE_ACS_CNTL |
63368 | #define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
63369 | #define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
63370 | #define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
63371 | #define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
63372 | #define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
63373 | #define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
63374 | #define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
63375 | #define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
63376 | #define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
63377 | #define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
63378 | #define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
63379 | #define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
63380 | #define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
63381 | #define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
63382 | //BIFPLR5_1_PCIE_MC_ENH_CAP_LIST |
63383 | #define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
63384 | #define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
63385 | #define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
63386 | #define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
63387 | #define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
63388 | #define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
63389 | //BIFPLR5_1_PCIE_MC_CAP |
63390 | #define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
63391 | #define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
63392 | #define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
63393 | #define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
63394 | //BIFPLR5_1_PCIE_MC_CNTL |
63395 | #define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
63396 | #define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
63397 | #define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
63398 | #define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
63399 | //BIFPLR5_1_PCIE_MC_ADDR0 |
63400 | #define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
63401 | #define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
63402 | #define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
63403 | #define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
63404 | //BIFPLR5_1_PCIE_MC_ADDR1 |
63405 | #define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
63406 | #define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
63407 | //BIFPLR5_1_PCIE_MC_RCV0 |
63408 | #define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
63409 | #define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
63410 | //BIFPLR5_1_PCIE_MC_RCV1 |
63411 | #define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
63412 | #define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
63413 | //BIFPLR5_1_PCIE_MC_BLOCK_ALL0 |
63414 | #define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
63415 | #define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
63416 | //BIFPLR5_1_PCIE_MC_BLOCK_ALL1 |
63417 | #define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
63418 | #define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
63419 | //BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
63420 | #define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
63421 | #define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
63422 | //BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
63423 | #define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
63424 | #define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
63425 | //BIFPLR5_1_PCIE_MC_OVERLAY_BAR0 |
63426 | #define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
63427 | #define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
63428 | #define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
63429 | #define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
63430 | //BIFPLR5_1_PCIE_MC_OVERLAY_BAR1 |
63431 | #define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
63432 | #define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
63433 | //BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST |
63434 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
63435 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
63436 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
63437 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
63438 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
63439 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
63440 | //BIFPLR5_1_PCIE_L1_PM_SUB_CAP |
63441 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
63442 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
63443 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
63444 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
63445 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
63446 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
63447 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
63448 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
63449 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
63450 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
63451 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
63452 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
63453 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
63454 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
63455 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
63456 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
63457 | //BIFPLR5_1_PCIE_L1_PM_SUB_CNTL |
63458 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
63459 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
63460 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
63461 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
63462 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
63463 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
63464 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
63465 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
63466 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
63467 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
63468 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
63469 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
63470 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
63471 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
63472 | //BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2 |
63473 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
63474 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
63475 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
63476 | #define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
63477 | //BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST |
63478 | #define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
63479 | #define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
63480 | #define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
63481 | #define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
63482 | #define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
63483 | #define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
63484 | //BIFPLR5_1_PCIE_DPC_CAP_LIST |
63485 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
63486 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
63487 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
63488 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
63489 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
63490 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
63491 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
63492 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
63493 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
63494 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
63495 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
63496 | #define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
63497 | //BIFPLR5_1_PCIE_DPC_CNTL |
63498 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
63499 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
63500 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
63501 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
63502 | #define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
63503 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
63504 | #define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
63505 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
63506 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
63507 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
63508 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
63509 | #define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
63510 | #define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
63511 | #define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
63512 | //BIFPLR5_1_PCIE_DPC_STATUS |
63513 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
63514 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
63515 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
63516 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
63517 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
63518 | #define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
63519 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
63520 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
63521 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
63522 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
63523 | #define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
63524 | #define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
63525 | //BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID |
63526 | #define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
63527 | #define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
63528 | //BIFPLR5_1_PCIE_RP_PIO_STATUS |
63529 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
63530 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
63531 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
63532 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
63533 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
63534 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
63535 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
63536 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
63537 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
63538 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
63539 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
63540 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
63541 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
63542 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
63543 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
63544 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
63545 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
63546 | #define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
63547 | //BIFPLR5_1_PCIE_RP_PIO_MASK |
63548 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
63549 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
63550 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
63551 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
63552 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
63553 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
63554 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
63555 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
63556 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
63557 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
63558 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
63559 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
63560 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
63561 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
63562 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
63563 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
63564 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
63565 | #define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
63566 | //BIFPLR5_1_PCIE_RP_PIO_SEVERITY |
63567 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
63568 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
63569 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
63570 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
63571 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
63572 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
63573 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
63574 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
63575 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
63576 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
63577 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
63578 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
63579 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
63580 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
63581 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
63582 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
63583 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
63584 | #define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
63585 | //BIFPLR5_1_PCIE_RP_PIO_SYSERROR |
63586 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
63587 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
63588 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
63589 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
63590 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
63591 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
63592 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
63593 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
63594 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
63595 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
63596 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
63597 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
63598 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
63599 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
63600 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
63601 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
63602 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
63603 | #define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
63604 | //BIFPLR5_1_PCIE_RP_PIO_EXCEPTION |
63605 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
63606 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
63607 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
63608 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
63609 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
63610 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
63611 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
63612 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
63613 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
63614 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
63615 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
63616 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
63617 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
63618 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
63619 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
63620 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
63621 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
63622 | #define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
63623 | //BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0 |
63624 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
63625 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
63626 | //BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1 |
63627 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
63628 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
63629 | //BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2 |
63630 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
63631 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
63632 | //BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3 |
63633 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
63634 | #define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
63635 | //BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG |
63636 | #define BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
63637 | #define BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
63638 | //BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0 |
63639 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
63640 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
63641 | //BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1 |
63642 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
63643 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
63644 | //BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2 |
63645 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
63646 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
63647 | //BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3 |
63648 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
63649 | #define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
63650 | //BIFPLR5_1_PCIE_ESM_CAP_LIST |
63651 | #define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
63652 | #define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
63653 | #define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
63654 | #define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
63655 | #define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
63656 | #define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
63657 | //BIFPLR5_1_PCIE_ESM_HEADER_1 |
63658 | #define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
63659 | #define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
63660 | #define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
63661 | #define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
63662 | #define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
63663 | #define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
63664 | //BIFPLR5_1_PCIE_ESM_HEADER_2 |
63665 | #define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
63666 | #define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
63667 | //BIFPLR5_1_PCIE_ESM_STATUS |
63668 | #define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
63669 | #define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
63670 | #define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
63671 | #define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
63672 | //BIFPLR5_1_PCIE_ESM_CTRL |
63673 | #define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
63674 | #define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
63675 | #define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
63676 | #define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
63677 | #define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
63678 | #define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
63679 | //BIFPLR5_1_PCIE_ESM_CAP_1 |
63680 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
63681 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
63682 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
63683 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
63684 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
63685 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
63686 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
63687 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
63688 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
63689 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
63690 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
63691 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
63692 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
63693 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
63694 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
63695 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
63696 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
63697 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
63698 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
63699 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
63700 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
63701 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
63702 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
63703 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
63704 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
63705 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
63706 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
63707 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
63708 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
63709 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
63710 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
63711 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
63712 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
63713 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
63714 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
63715 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
63716 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
63717 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
63718 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
63719 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
63720 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
63721 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
63722 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
63723 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
63724 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
63725 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
63726 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
63727 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
63728 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
63729 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
63730 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
63731 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
63732 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
63733 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
63734 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
63735 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
63736 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
63737 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
63738 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
63739 | #define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
63740 | //BIFPLR5_1_PCIE_ESM_CAP_2 |
63741 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
63742 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
63743 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
63744 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
63745 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
63746 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
63747 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
63748 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
63749 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
63750 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
63751 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
63752 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
63753 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
63754 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
63755 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
63756 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
63757 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
63758 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
63759 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
63760 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
63761 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
63762 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
63763 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
63764 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
63765 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
63766 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
63767 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
63768 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
63769 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
63770 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
63771 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
63772 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
63773 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
63774 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
63775 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
63776 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
63777 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
63778 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
63779 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
63780 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
63781 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
63782 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
63783 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
63784 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
63785 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
63786 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
63787 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
63788 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
63789 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
63790 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
63791 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
63792 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
63793 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
63794 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
63795 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
63796 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
63797 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
63798 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
63799 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
63800 | #define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
63801 | //BIFPLR5_1_PCIE_ESM_CAP_3 |
63802 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
63803 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
63804 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
63805 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
63806 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
63807 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
63808 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
63809 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
63810 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
63811 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
63812 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
63813 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
63814 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
63815 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
63816 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
63817 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
63818 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
63819 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
63820 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
63821 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
63822 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
63823 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
63824 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
63825 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
63826 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
63827 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
63828 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
63829 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
63830 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
63831 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
63832 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
63833 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
63834 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
63835 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
63836 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
63837 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
63838 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
63839 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
63840 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
63841 | #define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
63842 | //BIFPLR5_1_PCIE_ESM_CAP_4 |
63843 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
63844 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
63845 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
63846 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
63847 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
63848 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
63849 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
63850 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
63851 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
63852 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
63853 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
63854 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
63855 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
63856 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
63857 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
63858 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
63859 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
63860 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
63861 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
63862 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
63863 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
63864 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
63865 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
63866 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
63867 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
63868 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
63869 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
63870 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
63871 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
63872 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
63873 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
63874 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
63875 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
63876 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
63877 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
63878 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
63879 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
63880 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
63881 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
63882 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
63883 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
63884 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
63885 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
63886 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
63887 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
63888 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
63889 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
63890 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
63891 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
63892 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
63893 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
63894 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
63895 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
63896 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
63897 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
63898 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
63899 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
63900 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
63901 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
63902 | #define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
63903 | //BIFPLR5_1_PCIE_ESM_CAP_5 |
63904 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
63905 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
63906 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
63907 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
63908 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
63909 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
63910 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
63911 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
63912 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
63913 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
63914 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
63915 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
63916 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
63917 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
63918 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
63919 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
63920 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
63921 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
63922 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
63923 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
63924 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
63925 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
63926 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
63927 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
63928 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
63929 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
63930 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
63931 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
63932 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
63933 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
63934 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
63935 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
63936 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
63937 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
63938 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
63939 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
63940 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
63941 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
63942 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
63943 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
63944 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
63945 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
63946 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
63947 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
63948 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
63949 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
63950 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
63951 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
63952 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
63953 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
63954 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
63955 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
63956 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
63957 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
63958 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
63959 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
63960 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
63961 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
63962 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
63963 | #define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
63964 | //BIFPLR5_1_PCIE_ESM_CAP_6 |
63965 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
63966 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
63967 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
63968 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
63969 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
63970 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
63971 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
63972 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
63973 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
63974 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
63975 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
63976 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
63977 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
63978 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
63979 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
63980 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
63981 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
63982 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
63983 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
63984 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
63985 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
63986 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
63987 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
63988 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
63989 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
63990 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
63991 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
63992 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
63993 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
63994 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
63995 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
63996 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
63997 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
63998 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
63999 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
64000 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
64001 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
64002 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
64003 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
64004 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
64005 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
64006 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
64007 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
64008 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
64009 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
64010 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
64011 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
64012 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
64013 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
64014 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
64015 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
64016 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
64017 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
64018 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
64019 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
64020 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
64021 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
64022 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
64023 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
64024 | #define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
64025 | //BIFPLR5_1_PCIE_ESM_CAP_7 |
64026 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
64027 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
64028 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
64029 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
64030 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
64031 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
64032 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
64033 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
64034 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
64035 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
64036 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
64037 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
64038 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
64039 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
64040 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
64041 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
64042 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
64043 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
64044 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
64045 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
64046 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
64047 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
64048 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
64049 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
64050 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
64051 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
64052 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
64053 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
64054 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
64055 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
64056 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
64057 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
64058 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
64059 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
64060 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
64061 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
64062 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
64063 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
64064 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
64065 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
64066 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
64067 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
64068 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
64069 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
64070 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
64071 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
64072 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
64073 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
64074 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
64075 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
64076 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
64077 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
64078 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
64079 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
64080 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
64081 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
64082 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
64083 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
64084 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
64085 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
64086 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
64087 | #define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
64088 | |
64089 | |
64090 | // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
64091 | //BIFPLR6_1_VENDOR_ID |
64092 | #define BIFPLR6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
64093 | #define BIFPLR6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
64094 | //BIFPLR6_1_DEVICE_ID |
64095 | #define BIFPLR6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
64096 | #define BIFPLR6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
64097 | //BIFPLR6_1_COMMAND |
64098 | #define BIFPLR6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
64099 | #define BIFPLR6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
64100 | #define BIFPLR6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
64101 | #define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
64102 | #define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
64103 | #define BIFPLR6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
64104 | #define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
64105 | #define BIFPLR6_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
64106 | #define BIFPLR6_1_COMMAND__SERR_EN__SHIFT 0x8 |
64107 | #define BIFPLR6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
64108 | #define BIFPLR6_1_COMMAND__INT_DIS__SHIFT 0xa |
64109 | #define BIFPLR6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
64110 | #define BIFPLR6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
64111 | #define BIFPLR6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
64112 | #define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
64113 | #define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
64114 | #define BIFPLR6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
64115 | #define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
64116 | #define BIFPLR6_1_COMMAND__AD_STEPPING_MASK 0x0080L |
64117 | #define BIFPLR6_1_COMMAND__SERR_EN_MASK 0x0100L |
64118 | #define BIFPLR6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
64119 | #define BIFPLR6_1_COMMAND__INT_DIS_MASK 0x0400L |
64120 | //BIFPLR6_1_STATUS |
64121 | #define BIFPLR6_1_STATUS__INT_STATUS__SHIFT 0x3 |
64122 | #define BIFPLR6_1_STATUS__CAP_LIST__SHIFT 0x4 |
64123 | #define BIFPLR6_1_STATUS__PCI_66_EN__SHIFT 0x5 |
64124 | #define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
64125 | #define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
64126 | #define BIFPLR6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
64127 | #define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
64128 | #define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
64129 | #define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
64130 | #define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
64131 | #define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
64132 | #define BIFPLR6_1_STATUS__INT_STATUS_MASK 0x0008L |
64133 | #define BIFPLR6_1_STATUS__CAP_LIST_MASK 0x0010L |
64134 | #define BIFPLR6_1_STATUS__PCI_66_EN_MASK 0x0020L |
64135 | #define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
64136 | #define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
64137 | #define BIFPLR6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
64138 | #define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
64139 | #define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
64140 | #define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
64141 | #define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
64142 | #define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
64143 | //BIFPLR6_1_REVISION_ID |
64144 | #define BIFPLR6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
64145 | #define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
64146 | #define BIFPLR6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
64147 | #define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
64148 | //BIFPLR6_1_PROG_INTERFACE |
64149 | #define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
64150 | #define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
64151 | //BIFPLR6_1_SUB_CLASS |
64152 | #define BIFPLR6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
64153 | #define BIFPLR6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
64154 | //BIFPLR6_1_BASE_CLASS |
64155 | #define BIFPLR6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
64156 | #define BIFPLR6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
64157 | //BIFPLR6_1_CACHE_LINE |
64158 | #define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
64159 | #define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
64160 | //BIFPLR6_1_LATENCY |
64161 | #define BIFPLR6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
64162 | #define BIFPLR6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
64163 | //BIFPLR6_1_HEADER |
64164 | #define BIFPLR6_1_HEADER__HEADER_TYPE__SHIFT 0x0 |
64165 | #define BIFPLR6_1_HEADER__DEVICE_TYPE__SHIFT 0x7 |
64166 | #define BIFPLR6_1_HEADER__HEADER_TYPE_MASK 0x7FL |
64167 | #define BIFPLR6_1_HEADER__DEVICE_TYPE_MASK 0x80L |
64168 | //BIFPLR6_1_BIST |
64169 | #define BIFPLR6_1_BIST__BIST_COMP__SHIFT 0x0 |
64170 | #define BIFPLR6_1_BIST__BIST_STRT__SHIFT 0x6 |
64171 | #define BIFPLR6_1_BIST__BIST_CAP__SHIFT 0x7 |
64172 | #define BIFPLR6_1_BIST__BIST_COMP_MASK 0x0FL |
64173 | #define BIFPLR6_1_BIST__BIST_STRT_MASK 0x40L |
64174 | #define BIFPLR6_1_BIST__BIST_CAP_MASK 0x80L |
64175 | //BIFPLR6_1_SUB_BUS_NUMBER_LATENCY |
64176 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
64177 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
64178 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
64179 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
64180 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
64181 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
64182 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
64183 | #define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
64184 | //BIFPLR6_1_IO_BASE_LIMIT |
64185 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
64186 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
64187 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
64188 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
64189 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
64190 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
64191 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
64192 | #define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
64193 | //BIFPLR6_1_SECONDARY_STATUS |
64194 | #define BIFPLR6_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
64195 | #define BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
64196 | #define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
64197 | #define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
64198 | #define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
64199 | #define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
64200 | #define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
64201 | #define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
64202 | #define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
64203 | #define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
64204 | #define BIFPLR6_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
64205 | #define BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
64206 | #define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
64207 | #define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
64208 | #define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
64209 | #define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
64210 | #define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
64211 | #define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
64212 | #define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
64213 | #define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
64214 | //BIFPLR6_1_MEM_BASE_LIMIT |
64215 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
64216 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
64217 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
64218 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
64219 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
64220 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
64221 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
64222 | #define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
64223 | //BIFPLR6_1_PREF_BASE_LIMIT |
64224 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
64225 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
64226 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
64227 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
64228 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
64229 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
64230 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
64231 | #define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
64232 | //BIFPLR6_1_PREF_BASE_UPPER |
64233 | #define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
64234 | #define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
64235 | //BIFPLR6_1_PREF_LIMIT_UPPER |
64236 | #define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
64237 | #define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
64238 | //BIFPLR6_1_IO_BASE_LIMIT_HI |
64239 | #define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
64240 | #define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
64241 | #define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
64242 | #define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
64243 | //BIFPLR6_1_CAP_PTR |
64244 | #define BIFPLR6_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
64245 | #define BIFPLR6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
64246 | //BIFPLR6_1_INTERRUPT_LINE |
64247 | #define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
64248 | #define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
64249 | //BIFPLR6_1_INTERRUPT_PIN |
64250 | #define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
64251 | #define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
64252 | //BIFPLR6_1_IRQ_BRIDGE_CNTL |
64253 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
64254 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
64255 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
64256 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
64257 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
64258 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
64259 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
64260 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
64261 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
64262 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
64263 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
64264 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
64265 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
64266 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
64267 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
64268 | #define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
64269 | //BIFPLR6_1_EXT_BRIDGE_CNTL |
64270 | #define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
64271 | #define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
64272 | //BIFPLR6_1_PMI_CAP_LIST |
64273 | #define BIFPLR6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
64274 | #define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
64275 | #define BIFPLR6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
64276 | #define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
64277 | //BIFPLR6_1_PMI_CAP |
64278 | #define BIFPLR6_1_PMI_CAP__VERSION__SHIFT 0x0 |
64279 | #define BIFPLR6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
64280 | #define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
64281 | #define BIFPLR6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
64282 | #define BIFPLR6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
64283 | #define BIFPLR6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
64284 | #define BIFPLR6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
64285 | #define BIFPLR6_1_PMI_CAP__VERSION_MASK 0x0007L |
64286 | #define BIFPLR6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
64287 | #define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
64288 | #define BIFPLR6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
64289 | #define BIFPLR6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
64290 | #define BIFPLR6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
64291 | #define BIFPLR6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
64292 | //BIFPLR6_1_PMI_STATUS_CNTL |
64293 | #define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
64294 | #define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
64295 | #define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
64296 | #define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
64297 | #define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
64298 | #define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
64299 | #define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
64300 | #define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
64301 | #define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
64302 | #define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
64303 | #define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
64304 | #define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
64305 | #define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
64306 | #define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
64307 | #define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
64308 | #define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
64309 | #define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
64310 | #define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
64311 | //BIFPLR6_1_PCIE_CAP_LIST |
64312 | #define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
64313 | #define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
64314 | #define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
64315 | #define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
64316 | //BIFPLR6_1_PCIE_CAP |
64317 | #define BIFPLR6_1_PCIE_CAP__VERSION__SHIFT 0x0 |
64318 | #define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
64319 | #define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
64320 | #define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
64321 | #define BIFPLR6_1_PCIE_CAP__VERSION_MASK 0x000FL |
64322 | #define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
64323 | #define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
64324 | #define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
64325 | //BIFPLR6_1_DEVICE_CAP |
64326 | #define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
64327 | #define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
64328 | #define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
64329 | #define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
64330 | #define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
64331 | #define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
64332 | #define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
64333 | #define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
64334 | #define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
64335 | #define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
64336 | #define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
64337 | #define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
64338 | #define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
64339 | #define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
64340 | #define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
64341 | #define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
64342 | #define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
64343 | #define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
64344 | //BIFPLR6_1_DEVICE_CNTL |
64345 | #define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
64346 | #define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
64347 | #define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
64348 | #define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
64349 | #define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
64350 | #define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
64351 | #define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
64352 | #define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
64353 | #define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
64354 | #define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
64355 | #define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
64356 | #define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
64357 | #define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
64358 | #define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
64359 | #define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
64360 | #define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
64361 | #define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
64362 | #define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
64363 | #define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
64364 | #define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
64365 | #define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
64366 | #define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
64367 | #define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
64368 | #define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
64369 | //BIFPLR6_1_DEVICE_STATUS |
64370 | #define BIFPLR6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
64371 | #define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
64372 | #define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
64373 | #define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
64374 | #define BIFPLR6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
64375 | #define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
64376 | #define BIFPLR6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
64377 | #define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
64378 | #define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
64379 | #define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
64380 | #define BIFPLR6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
64381 | #define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
64382 | //BIFPLR6_1_LINK_CAP |
64383 | #define BIFPLR6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
64384 | #define BIFPLR6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
64385 | #define BIFPLR6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
64386 | #define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
64387 | #define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
64388 | #define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
64389 | #define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
64390 | #define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
64391 | #define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
64392 | #define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
64393 | #define BIFPLR6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
64394 | #define BIFPLR6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
64395 | #define BIFPLR6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
64396 | #define BIFPLR6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
64397 | #define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
64398 | #define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
64399 | #define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
64400 | #define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
64401 | #define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
64402 | #define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
64403 | #define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
64404 | #define BIFPLR6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
64405 | //BIFPLR6_1_LINK_CNTL |
64406 | #define BIFPLR6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
64407 | #define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
64408 | #define BIFPLR6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
64409 | #define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
64410 | #define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
64411 | #define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
64412 | #define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
64413 | #define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
64414 | #define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
64415 | #define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
64416 | #define BIFPLR6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
64417 | #define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
64418 | #define BIFPLR6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
64419 | #define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
64420 | #define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
64421 | #define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
64422 | #define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
64423 | #define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
64424 | #define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
64425 | #define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
64426 | //BIFPLR6_1_LINK_STATUS |
64427 | #define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
64428 | #define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
64429 | #define BIFPLR6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
64430 | #define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
64431 | #define BIFPLR6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
64432 | #define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
64433 | #define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
64434 | #define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
64435 | #define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
64436 | #define BIFPLR6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
64437 | #define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
64438 | #define BIFPLR6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
64439 | #define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
64440 | #define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
64441 | //BIFPLR6_1_SLOT_CAP |
64442 | #define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
64443 | #define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
64444 | #define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
64445 | #define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
64446 | #define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
64447 | #define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
64448 | #define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
64449 | #define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
64450 | #define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
64451 | #define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
64452 | #define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
64453 | #define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
64454 | #define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
64455 | #define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
64456 | #define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
64457 | #define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
64458 | #define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
64459 | #define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
64460 | #define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
64461 | #define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
64462 | #define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
64463 | #define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
64464 | #define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
64465 | #define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
64466 | //BIFPLR6_1_SLOT_CNTL |
64467 | #define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
64468 | #define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
64469 | #define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
64470 | #define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
64471 | #define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
64472 | #define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
64473 | #define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
64474 | #define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
64475 | #define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
64476 | #define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
64477 | #define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
64478 | #define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
64479 | #define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
64480 | #define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
64481 | #define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
64482 | #define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
64483 | #define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
64484 | #define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
64485 | #define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
64486 | #define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
64487 | #define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
64488 | #define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
64489 | #define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
64490 | #define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
64491 | //BIFPLR6_1_SLOT_STATUS |
64492 | #define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
64493 | #define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
64494 | #define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
64495 | #define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
64496 | #define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
64497 | #define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
64498 | #define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
64499 | #define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
64500 | #define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
64501 | #define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
64502 | #define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
64503 | #define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
64504 | #define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
64505 | #define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
64506 | #define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
64507 | #define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
64508 | #define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
64509 | #define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
64510 | //BIFPLR6_1_ROOT_CNTL |
64511 | #define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
64512 | #define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
64513 | #define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
64514 | #define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
64515 | #define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
64516 | #define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
64517 | #define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
64518 | #define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
64519 | #define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
64520 | #define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
64521 | //BIFPLR6_1_ROOT_CAP |
64522 | #define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
64523 | #define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
64524 | //BIFPLR6_1_ROOT_STATUS |
64525 | #define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
64526 | #define BIFPLR6_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
64527 | #define BIFPLR6_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
64528 | #define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
64529 | #define BIFPLR6_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
64530 | #define BIFPLR6_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
64531 | //BIFPLR6_1_DEVICE_CAP2 |
64532 | #define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
64533 | #define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
64534 | #define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
64535 | #define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
64536 | #define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
64537 | #define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
64538 | #define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
64539 | #define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
64540 | #define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
64541 | #define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
64542 | #define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
64543 | #define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
64544 | #define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
64545 | #define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
64546 | #define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
64547 | #define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
64548 | #define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
64549 | #define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
64550 | #define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
64551 | #define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
64552 | #define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
64553 | #define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
64554 | #define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
64555 | #define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
64556 | #define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
64557 | #define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
64558 | #define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
64559 | #define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
64560 | //BIFPLR6_1_DEVICE_CNTL2 |
64561 | #define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
64562 | #define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
64563 | #define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
64564 | #define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
64565 | #define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
64566 | #define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
64567 | #define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
64568 | #define BIFPLR6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
64569 | #define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
64570 | #define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
64571 | #define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
64572 | #define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
64573 | #define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
64574 | #define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
64575 | #define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
64576 | #define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
64577 | #define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
64578 | #define BIFPLR6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
64579 | #define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
64580 | #define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
64581 | //BIFPLR6_1_DEVICE_STATUS2 |
64582 | #define BIFPLR6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
64583 | #define BIFPLR6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
64584 | //BIFPLR6_1_LINK_CAP2 |
64585 | #define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
64586 | #define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
64587 | #define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
64588 | #define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
64589 | #define BIFPLR6_1_LINK_CAP2__RESERVED__SHIFT 0x13 |
64590 | #define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
64591 | #define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
64592 | #define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
64593 | #define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
64594 | #define BIFPLR6_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
64595 | //BIFPLR6_1_LINK_CNTL2 |
64596 | #define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
64597 | #define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
64598 | #define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
64599 | #define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
64600 | #define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
64601 | #define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
64602 | #define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
64603 | #define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
64604 | #define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
64605 | #define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
64606 | #define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
64607 | #define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
64608 | #define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
64609 | #define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
64610 | #define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
64611 | #define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
64612 | //BIFPLR6_1_LINK_STATUS2 |
64613 | #define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
64614 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
64615 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
64616 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
64617 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
64618 | #define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
64619 | #define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
64620 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
64621 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
64622 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
64623 | #define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
64624 | #define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
64625 | //BIFPLR6_1_SLOT_CAP2 |
64626 | #define BIFPLR6_1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
64627 | #define BIFPLR6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
64628 | //BIFPLR6_1_SLOT_CNTL2 |
64629 | #define BIFPLR6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
64630 | #define BIFPLR6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
64631 | //BIFPLR6_1_SLOT_STATUS2 |
64632 | #define BIFPLR6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
64633 | #define BIFPLR6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
64634 | //BIFPLR6_1_MSI_CAP_LIST |
64635 | #define BIFPLR6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
64636 | #define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
64637 | #define BIFPLR6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
64638 | #define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
64639 | //BIFPLR6_1_MSI_MSG_CNTL |
64640 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
64641 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
64642 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
64643 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
64644 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
64645 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
64646 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
64647 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
64648 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
64649 | #define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
64650 | //BIFPLR6_1_MSI_MSG_ADDR_LO |
64651 | #define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
64652 | #define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
64653 | //BIFPLR6_1_MSI_MSG_ADDR_HI |
64654 | #define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
64655 | #define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
64656 | //BIFPLR6_1_MSI_MSG_DATA |
64657 | #define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
64658 | #define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
64659 | //BIFPLR6_1_MSI_MSG_DATA_64 |
64660 | #define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
64661 | #define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
64662 | //BIFPLR6_1_SSID_CAP_LIST |
64663 | #define BIFPLR6_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
64664 | #define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
64665 | #define BIFPLR6_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
64666 | #define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
64667 | //BIFPLR6_1_SSID_CAP |
64668 | #define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
64669 | #define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
64670 | #define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
64671 | #define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
64672 | //BIFPLR6_1_MSI_MAP_CAP_LIST |
64673 | #define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
64674 | #define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
64675 | #define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
64676 | #define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
64677 | //BIFPLR6_1_MSI_MAP_CAP |
64678 | #define BIFPLR6_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
64679 | #define BIFPLR6_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
64680 | #define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
64681 | #define BIFPLR6_1_MSI_MAP_CAP__EN_MASK 0x0001L |
64682 | #define BIFPLR6_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
64683 | #define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
64684 | //BIFPLR6_1_MSI_MAP_ADDR_LO |
64685 | #define BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
64686 | #define BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
64687 | //BIFPLR6_1_MSI_MAP_ADDR_HI |
64688 | #define BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
64689 | #define BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
64690 | //BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
64691 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
64692 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
64693 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
64694 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
64695 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
64696 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
64697 | //BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR |
64698 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
64699 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
64700 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
64701 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
64702 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
64703 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
64704 | //BIFPLR6_1_PCIE_VENDOR_SPECIFIC1 |
64705 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
64706 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
64707 | //BIFPLR6_1_PCIE_VENDOR_SPECIFIC2 |
64708 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
64709 | #define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
64710 | //BIFPLR6_1_PCIE_VC_ENH_CAP_LIST |
64711 | #define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
64712 | #define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
64713 | #define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
64714 | #define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
64715 | #define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
64716 | #define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
64717 | //BIFPLR6_1_PCIE_PORT_VC_CAP_REG1 |
64718 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
64719 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
64720 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
64721 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
64722 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
64723 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
64724 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
64725 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
64726 | //BIFPLR6_1_PCIE_PORT_VC_CAP_REG2 |
64727 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
64728 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
64729 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
64730 | #define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
64731 | //BIFPLR6_1_PCIE_PORT_VC_CNTL |
64732 | #define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
64733 | #define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
64734 | #define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
64735 | #define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
64736 | //BIFPLR6_1_PCIE_PORT_VC_STATUS |
64737 | #define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
64738 | #define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
64739 | //BIFPLR6_1_PCIE_VC0_RESOURCE_CAP |
64740 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
64741 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
64742 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
64743 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
64744 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
64745 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
64746 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
64747 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
64748 | //BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL |
64749 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
64750 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
64751 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
64752 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
64753 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
64754 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
64755 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
64756 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
64757 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
64758 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
64759 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
64760 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
64761 | //BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS |
64762 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
64763 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
64764 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
64765 | #define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
64766 | //BIFPLR6_1_PCIE_VC1_RESOURCE_CAP |
64767 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
64768 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
64769 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
64770 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
64771 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
64772 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
64773 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
64774 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
64775 | //BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL |
64776 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
64777 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
64778 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
64779 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
64780 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
64781 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
64782 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
64783 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
64784 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
64785 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
64786 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
64787 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
64788 | //BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS |
64789 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
64790 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
64791 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
64792 | #define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
64793 | //BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
64794 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
64795 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
64796 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
64797 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
64798 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
64799 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
64800 | //BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1 |
64801 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
64802 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
64803 | //BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2 |
64804 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
64805 | #define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
64806 | //BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
64807 | #define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
64808 | #define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
64809 | #define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
64810 | #define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
64811 | #define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
64812 | #define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
64813 | //BIFPLR6_1_PCIE_UNCORR_ERR_STATUS |
64814 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
64815 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
64816 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
64817 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
64818 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
64819 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
64820 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
64821 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
64822 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
64823 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
64824 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
64825 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
64826 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
64827 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
64828 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
64829 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
64830 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
64831 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
64832 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
64833 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
64834 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
64835 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
64836 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
64837 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
64838 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
64839 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
64840 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
64841 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
64842 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
64843 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
64844 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
64845 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
64846 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
64847 | #define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
64848 | //BIFPLR6_1_PCIE_UNCORR_ERR_MASK |
64849 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
64850 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
64851 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
64852 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
64853 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
64854 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
64855 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
64856 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
64857 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
64858 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
64859 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
64860 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
64861 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
64862 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
64863 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
64864 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
64865 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
64866 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
64867 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
64868 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
64869 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
64870 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
64871 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
64872 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
64873 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
64874 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
64875 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
64876 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
64877 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
64878 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
64879 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
64880 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
64881 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
64882 | #define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
64883 | //BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY |
64884 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
64885 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
64886 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
64887 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
64888 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
64889 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
64890 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
64891 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
64892 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
64893 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
64894 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
64895 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
64896 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
64897 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
64898 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
64899 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
64900 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
64901 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
64902 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
64903 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
64904 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
64905 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
64906 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
64907 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
64908 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
64909 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
64910 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
64911 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
64912 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
64913 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
64914 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
64915 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
64916 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
64917 | #define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
64918 | //BIFPLR6_1_PCIE_CORR_ERR_STATUS |
64919 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
64920 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
64921 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
64922 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
64923 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
64924 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
64925 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
64926 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
64927 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
64928 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
64929 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
64930 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
64931 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
64932 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
64933 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
64934 | #define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
64935 | //BIFPLR6_1_PCIE_CORR_ERR_MASK |
64936 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
64937 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
64938 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
64939 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
64940 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
64941 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
64942 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
64943 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
64944 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
64945 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
64946 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
64947 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
64948 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
64949 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
64950 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
64951 | #define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
64952 | //BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL |
64953 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
64954 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
64955 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
64956 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
64957 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
64958 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
64959 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
64960 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
64961 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
64962 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
64963 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
64964 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
64965 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
64966 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
64967 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
64968 | #define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
64969 | //BIFPLR6_1_PCIE_HDR_LOG0 |
64970 | #define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
64971 | #define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
64972 | //BIFPLR6_1_PCIE_HDR_LOG1 |
64973 | #define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
64974 | #define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
64975 | //BIFPLR6_1_PCIE_HDR_LOG2 |
64976 | #define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
64977 | #define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
64978 | //BIFPLR6_1_PCIE_HDR_LOG3 |
64979 | #define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
64980 | #define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
64981 | //BIFPLR6_1_PCIE_ROOT_ERR_CMD |
64982 | #define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
64983 | #define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
64984 | #define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
64985 | #define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
64986 | #define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
64987 | #define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
64988 | //BIFPLR6_1_PCIE_ROOT_ERR_STATUS |
64989 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
64990 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
64991 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
64992 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
64993 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
64994 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
64995 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
64996 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
64997 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
64998 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
64999 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
65000 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
65001 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
65002 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
65003 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
65004 | #define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
65005 | //BIFPLR6_1_PCIE_ERR_SRC_ID |
65006 | #define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
65007 | #define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
65008 | #define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
65009 | #define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
65010 | //BIFPLR6_1_PCIE_TLP_PREFIX_LOG0 |
65011 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
65012 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
65013 | //BIFPLR6_1_PCIE_TLP_PREFIX_LOG1 |
65014 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
65015 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
65016 | //BIFPLR6_1_PCIE_TLP_PREFIX_LOG2 |
65017 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
65018 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
65019 | //BIFPLR6_1_PCIE_TLP_PREFIX_LOG3 |
65020 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
65021 | #define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
65022 | //BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST |
65023 | #define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
65024 | #define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
65025 | #define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
65026 | #define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
65027 | #define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
65028 | #define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
65029 | //BIFPLR6_1_PCIE_LINK_CNTL3 |
65030 | #define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
65031 | #define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
65032 | #define BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
65033 | #define BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
65034 | #define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
65035 | #define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
65036 | #define BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
65037 | #define BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
65038 | //BIFPLR6_1_PCIE_LANE_ERROR_STATUS |
65039 | #define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
65040 | #define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
65041 | #define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
65042 | #define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
65043 | //BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL |
65044 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65045 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65046 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65047 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65048 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65049 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65050 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65051 | #define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65052 | //BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL |
65053 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65054 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65055 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65056 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65057 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65058 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65059 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65060 | #define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65061 | //BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL |
65062 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65063 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65064 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65065 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65066 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65067 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65068 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65069 | #define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65070 | //BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL |
65071 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65072 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65073 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65074 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65075 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65076 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65077 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65078 | #define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65079 | //BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL |
65080 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65081 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65082 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65083 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65084 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65085 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65086 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65087 | #define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65088 | //BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL |
65089 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65090 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65091 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65092 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65093 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65094 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65095 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65096 | #define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65097 | //BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL |
65098 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65099 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65100 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65101 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65102 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65103 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65104 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65105 | #define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65106 | //BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL |
65107 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65108 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65109 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65110 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65111 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65112 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65113 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65114 | #define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65115 | //BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL |
65116 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65117 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65118 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65119 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65120 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65121 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65122 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65123 | #define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65124 | //BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL |
65125 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65126 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65127 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65128 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65129 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65130 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65131 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65132 | #define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65133 | //BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL |
65134 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65135 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65136 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65137 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65138 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65139 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65140 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65141 | #define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65142 | //BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL |
65143 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65144 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65145 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65146 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65147 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65148 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65149 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65150 | #define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65151 | //BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL |
65152 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65153 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65154 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65155 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65156 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65157 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65158 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65159 | #define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65160 | //BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL |
65161 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65162 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65163 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65164 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65165 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65166 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65167 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65168 | #define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65169 | //BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL |
65170 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65171 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65172 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65173 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65174 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65175 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65176 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65177 | #define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65178 | //BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL |
65179 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
65180 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
65181 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
65182 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
65183 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
65184 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
65185 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
65186 | #define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
65187 | //BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST |
65188 | #define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
65189 | #define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
65190 | #define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
65191 | #define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
65192 | #define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
65193 | #define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
65194 | //BIFPLR6_1_PCIE_ACS_CAP |
65195 | #define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
65196 | #define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
65197 | #define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
65198 | #define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
65199 | #define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
65200 | #define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
65201 | #define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
65202 | #define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
65203 | #define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
65204 | #define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
65205 | #define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
65206 | #define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
65207 | #define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
65208 | #define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
65209 | #define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
65210 | #define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
65211 | //BIFPLR6_1_PCIE_ACS_CNTL |
65212 | #define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
65213 | #define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
65214 | #define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
65215 | #define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
65216 | #define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
65217 | #define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
65218 | #define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
65219 | #define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
65220 | #define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
65221 | #define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
65222 | #define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
65223 | #define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
65224 | #define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
65225 | #define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
65226 | //BIFPLR6_1_PCIE_MC_ENH_CAP_LIST |
65227 | #define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
65228 | #define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
65229 | #define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
65230 | #define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
65231 | #define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
65232 | #define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
65233 | //BIFPLR6_1_PCIE_MC_CAP |
65234 | #define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
65235 | #define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
65236 | #define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
65237 | #define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
65238 | //BIFPLR6_1_PCIE_MC_CNTL |
65239 | #define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
65240 | #define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
65241 | #define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
65242 | #define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
65243 | //BIFPLR6_1_PCIE_MC_ADDR0 |
65244 | #define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
65245 | #define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
65246 | #define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
65247 | #define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
65248 | //BIFPLR6_1_PCIE_MC_ADDR1 |
65249 | #define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
65250 | #define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
65251 | //BIFPLR6_1_PCIE_MC_RCV0 |
65252 | #define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
65253 | #define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
65254 | //BIFPLR6_1_PCIE_MC_RCV1 |
65255 | #define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
65256 | #define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
65257 | //BIFPLR6_1_PCIE_MC_BLOCK_ALL0 |
65258 | #define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
65259 | #define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
65260 | //BIFPLR6_1_PCIE_MC_BLOCK_ALL1 |
65261 | #define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
65262 | #define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
65263 | //BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
65264 | #define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
65265 | #define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
65266 | //BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
65267 | #define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
65268 | #define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
65269 | //BIFPLR6_1_PCIE_MC_OVERLAY_BAR0 |
65270 | #define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
65271 | #define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
65272 | #define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
65273 | #define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
65274 | //BIFPLR6_1_PCIE_MC_OVERLAY_BAR1 |
65275 | #define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
65276 | #define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
65277 | //BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST |
65278 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
65279 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
65280 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
65281 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
65282 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
65283 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
65284 | //BIFPLR6_1_PCIE_L1_PM_SUB_CAP |
65285 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
65286 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
65287 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
65288 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
65289 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
65290 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
65291 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
65292 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
65293 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
65294 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
65295 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
65296 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
65297 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
65298 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
65299 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
65300 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
65301 | //BIFPLR6_1_PCIE_L1_PM_SUB_CNTL |
65302 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
65303 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
65304 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
65305 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
65306 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
65307 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
65308 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
65309 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
65310 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
65311 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
65312 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
65313 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
65314 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
65315 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
65316 | //BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2 |
65317 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
65318 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
65319 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
65320 | #define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
65321 | //BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST |
65322 | #define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
65323 | #define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
65324 | #define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
65325 | #define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
65326 | #define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
65327 | #define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
65328 | //BIFPLR6_1_PCIE_DPC_CAP_LIST |
65329 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
65330 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
65331 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
65332 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
65333 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
65334 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
65335 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
65336 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
65337 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
65338 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
65339 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
65340 | #define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
65341 | //BIFPLR6_1_PCIE_DPC_CNTL |
65342 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
65343 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
65344 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
65345 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
65346 | #define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
65347 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
65348 | #define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
65349 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
65350 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
65351 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
65352 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
65353 | #define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
65354 | #define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
65355 | #define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
65356 | //BIFPLR6_1_PCIE_DPC_STATUS |
65357 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
65358 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
65359 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
65360 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
65361 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
65362 | #define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
65363 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
65364 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
65365 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
65366 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
65367 | #define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
65368 | #define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
65369 | //BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID |
65370 | #define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
65371 | #define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
65372 | //BIFPLR6_1_PCIE_RP_PIO_STATUS |
65373 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
65374 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
65375 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
65376 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
65377 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
65378 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
65379 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
65380 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
65381 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
65382 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
65383 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
65384 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
65385 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
65386 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
65387 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
65388 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
65389 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
65390 | #define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
65391 | //BIFPLR6_1_PCIE_RP_PIO_MASK |
65392 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
65393 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
65394 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
65395 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
65396 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
65397 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
65398 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
65399 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
65400 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
65401 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
65402 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
65403 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
65404 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
65405 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
65406 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
65407 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
65408 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
65409 | #define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
65410 | //BIFPLR6_1_PCIE_RP_PIO_SEVERITY |
65411 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
65412 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
65413 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
65414 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
65415 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
65416 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
65417 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
65418 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
65419 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
65420 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
65421 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
65422 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
65423 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
65424 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
65425 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
65426 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
65427 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
65428 | #define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
65429 | //BIFPLR6_1_PCIE_RP_PIO_SYSERROR |
65430 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
65431 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
65432 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
65433 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
65434 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
65435 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
65436 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
65437 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
65438 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
65439 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
65440 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
65441 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
65442 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
65443 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
65444 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
65445 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
65446 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
65447 | #define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
65448 | //BIFPLR6_1_PCIE_RP_PIO_EXCEPTION |
65449 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
65450 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
65451 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
65452 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
65453 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
65454 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
65455 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
65456 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
65457 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
65458 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
65459 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
65460 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
65461 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
65462 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
65463 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
65464 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
65465 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
65466 | #define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
65467 | //BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0 |
65468 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
65469 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
65470 | //BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1 |
65471 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
65472 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
65473 | //BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2 |
65474 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
65475 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
65476 | //BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3 |
65477 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
65478 | #define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
65479 | //BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG |
65480 | #define BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
65481 | #define BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
65482 | //BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0 |
65483 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
65484 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
65485 | //BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1 |
65486 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
65487 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
65488 | //BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2 |
65489 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
65490 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
65491 | //BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3 |
65492 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
65493 | #define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
65494 | //BIFPLR6_1_PCIE_ESM_CAP_LIST |
65495 | #define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
65496 | #define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
65497 | #define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
65498 | #define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
65499 | #define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
65500 | #define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
65501 | //BIFPLR6_1_PCIE_ESM_HEADER_1 |
65502 | #define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
65503 | #define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
65504 | #define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
65505 | #define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
65506 | #define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
65507 | #define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
65508 | //BIFPLR6_1_PCIE_ESM_HEADER_2 |
65509 | #define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
65510 | #define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
65511 | //BIFPLR6_1_PCIE_ESM_STATUS |
65512 | #define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
65513 | #define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
65514 | #define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
65515 | #define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
65516 | //BIFPLR6_1_PCIE_ESM_CTRL |
65517 | #define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
65518 | #define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
65519 | #define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
65520 | #define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
65521 | #define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
65522 | #define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
65523 | //BIFPLR6_1_PCIE_ESM_CAP_1 |
65524 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
65525 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
65526 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
65527 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
65528 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
65529 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
65530 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
65531 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
65532 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
65533 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
65534 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
65535 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
65536 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
65537 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
65538 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
65539 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
65540 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
65541 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
65542 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
65543 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
65544 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
65545 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
65546 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
65547 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
65548 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
65549 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
65550 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
65551 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
65552 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
65553 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
65554 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
65555 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
65556 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
65557 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
65558 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
65559 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
65560 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
65561 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
65562 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
65563 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
65564 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
65565 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
65566 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
65567 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
65568 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
65569 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
65570 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
65571 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
65572 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
65573 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
65574 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
65575 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
65576 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
65577 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
65578 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
65579 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
65580 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
65581 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
65582 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
65583 | #define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
65584 | //BIFPLR6_1_PCIE_ESM_CAP_2 |
65585 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
65586 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
65587 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
65588 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
65589 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
65590 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
65591 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
65592 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
65593 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
65594 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
65595 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
65596 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
65597 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
65598 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
65599 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
65600 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
65601 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
65602 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
65603 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
65604 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
65605 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
65606 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
65607 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
65608 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
65609 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
65610 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
65611 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
65612 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
65613 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
65614 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
65615 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
65616 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
65617 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
65618 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
65619 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
65620 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
65621 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
65622 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
65623 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
65624 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
65625 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
65626 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
65627 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
65628 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
65629 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
65630 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
65631 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
65632 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
65633 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
65634 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
65635 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
65636 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
65637 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
65638 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
65639 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
65640 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
65641 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
65642 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
65643 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
65644 | #define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
65645 | //BIFPLR6_1_PCIE_ESM_CAP_3 |
65646 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
65647 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
65648 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
65649 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
65650 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
65651 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
65652 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
65653 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
65654 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
65655 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
65656 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
65657 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
65658 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
65659 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
65660 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
65661 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
65662 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
65663 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
65664 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
65665 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
65666 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
65667 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
65668 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
65669 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
65670 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
65671 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
65672 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
65673 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
65674 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
65675 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
65676 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
65677 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
65678 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
65679 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
65680 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
65681 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
65682 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
65683 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
65684 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
65685 | #define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
65686 | //BIFPLR6_1_PCIE_ESM_CAP_4 |
65687 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
65688 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
65689 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
65690 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
65691 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
65692 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
65693 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
65694 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
65695 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
65696 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
65697 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
65698 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
65699 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
65700 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
65701 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
65702 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
65703 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
65704 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
65705 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
65706 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
65707 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
65708 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
65709 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
65710 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
65711 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
65712 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
65713 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
65714 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
65715 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
65716 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
65717 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
65718 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
65719 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
65720 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
65721 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
65722 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
65723 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
65724 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
65725 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
65726 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
65727 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
65728 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
65729 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
65730 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
65731 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
65732 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
65733 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
65734 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
65735 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
65736 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
65737 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
65738 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
65739 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
65740 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
65741 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
65742 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
65743 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
65744 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
65745 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
65746 | #define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
65747 | //BIFPLR6_1_PCIE_ESM_CAP_5 |
65748 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
65749 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
65750 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
65751 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
65752 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
65753 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
65754 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
65755 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
65756 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
65757 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
65758 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
65759 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
65760 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
65761 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
65762 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
65763 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
65764 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
65765 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
65766 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
65767 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
65768 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
65769 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
65770 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
65771 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
65772 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
65773 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
65774 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
65775 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
65776 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
65777 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
65778 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
65779 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
65780 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
65781 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
65782 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
65783 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
65784 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
65785 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
65786 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
65787 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
65788 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
65789 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
65790 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
65791 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
65792 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
65793 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
65794 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
65795 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
65796 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
65797 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
65798 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
65799 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
65800 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
65801 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
65802 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
65803 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
65804 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
65805 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
65806 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
65807 | #define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
65808 | //BIFPLR6_1_PCIE_ESM_CAP_6 |
65809 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
65810 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
65811 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
65812 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
65813 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
65814 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
65815 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
65816 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
65817 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
65818 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
65819 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
65820 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
65821 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
65822 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
65823 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
65824 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
65825 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
65826 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
65827 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
65828 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
65829 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
65830 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
65831 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
65832 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
65833 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
65834 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
65835 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
65836 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
65837 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
65838 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
65839 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
65840 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
65841 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
65842 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
65843 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
65844 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
65845 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
65846 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
65847 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
65848 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
65849 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
65850 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
65851 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
65852 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
65853 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
65854 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
65855 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
65856 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
65857 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
65858 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
65859 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
65860 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
65861 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
65862 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
65863 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
65864 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
65865 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
65866 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
65867 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
65868 | #define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
65869 | //BIFPLR6_1_PCIE_ESM_CAP_7 |
65870 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
65871 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
65872 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
65873 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
65874 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
65875 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
65876 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
65877 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
65878 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
65879 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
65880 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
65881 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
65882 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
65883 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
65884 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
65885 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
65886 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
65887 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
65888 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
65889 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
65890 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
65891 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
65892 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
65893 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
65894 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
65895 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
65896 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
65897 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
65898 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
65899 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
65900 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
65901 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
65902 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
65903 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
65904 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
65905 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
65906 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
65907 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
65908 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
65909 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
65910 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
65911 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
65912 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
65913 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
65914 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
65915 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
65916 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
65917 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
65918 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
65919 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
65920 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
65921 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
65922 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
65923 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
65924 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
65925 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
65926 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
65927 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
65928 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
65929 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
65930 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
65931 | #define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
65932 | |
65933 | |
65934 | // addressBlock: nbio_pcie0_bifp0_pciedir_p |
65935 | //BIFP0_PCIEP_RESERVED |
65936 | #define BIFP0_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
65937 | #define BIFP0_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
65938 | //BIFP0_PCIEP_SCRATCH |
65939 | #define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
65940 | #define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
65941 | //BIFP0_PCIEP_PORT_CNTL |
65942 | #define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
65943 | #define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
65944 | #define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
65945 | #define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
65946 | #define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
65947 | #define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
65948 | #define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
65949 | #define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
65950 | #define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
65951 | #define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
65952 | #define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
65953 | #define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
65954 | #define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
65955 | #define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
65956 | #define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
65957 | #define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
65958 | #define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
65959 | #define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
65960 | #define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
65961 | #define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
65962 | //BIFP0_PCIE_TX_CNTL |
65963 | #define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
65964 | #define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
65965 | #define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
65966 | #define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
65967 | #define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
65968 | #define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
65969 | #define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
65970 | #define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
65971 | #define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
65972 | #define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
65973 | #define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
65974 | #define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
65975 | #define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
65976 | #define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
65977 | #define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
65978 | #define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
65979 | //BIFP0_PCIE_TX_REQUESTER_ID |
65980 | #define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
65981 | #define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
65982 | #define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
65983 | #define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
65984 | #define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
65985 | #define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
65986 | //BIFP0_PCIE_TX_VENDOR_SPECIFIC |
65987 | #define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
65988 | #define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
65989 | //BIFP0_PCIE_TX_REQUEST_NUM_CNTL |
65990 | #define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
65991 | #define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
65992 | #define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
65993 | #define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
65994 | #define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
65995 | #define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
65996 | //BIFP0_PCIE_TX_SEQ |
65997 | #define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
65998 | #define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
65999 | #define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
66000 | #define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
66001 | //BIFP0_PCIE_TX_REPLAY |
66002 | #define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
66003 | #define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
66004 | #define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
66005 | #define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
66006 | #define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
66007 | #define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
66008 | //BIFP0_PCIE_TX_ACK_LATENCY_LIMIT |
66009 | #define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
66010 | #define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
66011 | #define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
66012 | #define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
66013 | //BIFP0_PCIE_TX_CREDITS_ADVT_P |
66014 | #define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
66015 | #define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
66016 | #define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
66017 | #define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
66018 | //BIFP0_PCIE_TX_CREDITS_ADVT_NP |
66019 | #define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
66020 | #define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
66021 | #define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
66022 | #define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
66023 | //BIFP0_PCIE_TX_CREDITS_ADVT_CPL |
66024 | #define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
66025 | #define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
66026 | #define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
66027 | #define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
66028 | //BIFP0_PCIE_TX_CREDITS_INIT_P |
66029 | #define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
66030 | #define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
66031 | #define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
66032 | #define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
66033 | //BIFP0_PCIE_TX_CREDITS_INIT_NP |
66034 | #define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
66035 | #define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
66036 | #define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
66037 | #define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
66038 | //BIFP0_PCIE_TX_CREDITS_INIT_CPL |
66039 | #define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
66040 | #define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
66041 | #define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
66042 | #define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
66043 | //BIFP0_PCIE_TX_CREDITS_STATUS |
66044 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
66045 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
66046 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
66047 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
66048 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
66049 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
66050 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
66051 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
66052 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
66053 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
66054 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
66055 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
66056 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
66057 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
66058 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
66059 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
66060 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
66061 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
66062 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
66063 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
66064 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
66065 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
66066 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
66067 | #define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
66068 | //BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD |
66069 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
66070 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
66071 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
66072 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
66073 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
66074 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
66075 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
66076 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
66077 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
66078 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
66079 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
66080 | #define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
66081 | //BIFP0_PCIE_P_PORT_LANE_STATUS |
66082 | #define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
66083 | #define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
66084 | #define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
66085 | #define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
66086 | //BIFP0_PCIE_FC_P |
66087 | #define BIFP0_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
66088 | #define BIFP0_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
66089 | #define BIFP0_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
66090 | #define BIFP0_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
66091 | //BIFP0_PCIE_FC_NP |
66092 | #define BIFP0_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
66093 | #define BIFP0_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
66094 | #define BIFP0_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
66095 | #define BIFP0_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
66096 | //BIFP0_PCIE_FC_CPL |
66097 | #define BIFP0_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
66098 | #define BIFP0_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
66099 | #define BIFP0_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
66100 | #define BIFP0_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
66101 | //BIFP0_PCIE_ERR_CNTL |
66102 | #define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
66103 | #define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
66104 | #define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
66105 | #define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
66106 | #define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
66107 | #define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
66108 | #define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
66109 | #define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
66110 | #define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
66111 | #define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
66112 | #define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
66113 | #define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
66114 | #define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
66115 | #define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
66116 | #define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
66117 | #define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
66118 | #define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
66119 | #define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
66120 | #define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
66121 | #define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
66122 | #define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
66123 | #define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
66124 | #define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
66125 | #define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
66126 | #define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
66127 | #define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
66128 | #define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
66129 | #define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
66130 | //BIFP0_PCIE_RX_CNTL |
66131 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
66132 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
66133 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
66134 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
66135 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
66136 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
66137 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
66138 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
66139 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
66140 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
66141 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
66142 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
66143 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
66144 | #define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
66145 | #define BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
66146 | #define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
66147 | #define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
66148 | #define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
66149 | #define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
66150 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
66151 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
66152 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
66153 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
66154 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
66155 | #define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
66156 | #define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
66157 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
66158 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
66159 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
66160 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
66161 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
66162 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
66163 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
66164 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
66165 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
66166 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
66167 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
66168 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
66169 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
66170 | #define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
66171 | #define BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
66172 | #define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
66173 | #define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
66174 | #define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
66175 | #define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
66176 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
66177 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
66178 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
66179 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
66180 | #define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
66181 | #define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
66182 | #define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
66183 | //BIFP0_PCIE_RX_EXPECTED_SEQNUM |
66184 | #define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
66185 | #define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
66186 | //BIFP0_PCIE_RX_VENDOR_SPECIFIC |
66187 | #define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
66188 | #define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
66189 | #define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
66190 | #define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
66191 | //BIFP0_PCIE_RX_CNTL3 |
66192 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
66193 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
66194 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
66195 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
66196 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
66197 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
66198 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
66199 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
66200 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
66201 | #define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
66202 | //BIFP0_PCIE_RX_CREDITS_ALLOCATED_P |
66203 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
66204 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
66205 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
66206 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
66207 | //BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP |
66208 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
66209 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
66210 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
66211 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
66212 | //BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL |
66213 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
66214 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
66215 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
66216 | #define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
66217 | //BIFP0_PCIEP_ERROR_INJECT_PHYSICAL |
66218 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
66219 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
66220 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
66221 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
66222 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
66223 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
66224 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
66225 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
66226 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
66227 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
66228 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
66229 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
66230 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
66231 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
66232 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
66233 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
66234 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
66235 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
66236 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
66237 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
66238 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
66239 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
66240 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
66241 | #define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
66242 | //BIFP0_PCIEP_ERROR_INJECT_TRANSACTION |
66243 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
66244 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
66245 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
66246 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
66247 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
66248 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
66249 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
66250 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
66251 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
66252 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
66253 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
66254 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
66255 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
66256 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
66257 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
66258 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
66259 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
66260 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
66261 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
66262 | #define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
66263 | //BIFP0_PCIEP_NAK_COUNTER |
66264 | #define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
66265 | #define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
66266 | #define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
66267 | #define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
66268 | //BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
66269 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
66270 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
66271 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
66272 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
66273 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
66274 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
66275 | //BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
66276 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
66277 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
66278 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
66279 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
66280 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
66281 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
66282 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
66283 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
66284 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
66285 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
66286 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
66287 | #define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
66288 | //BIFP0_PCIE_LC_CNTL |
66289 | #define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
66290 | #define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
66291 | #define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
66292 | #define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
66293 | #define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
66294 | #define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
66295 | #define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
66296 | #define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
66297 | #define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
66298 | #define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
66299 | #define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
66300 | #define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
66301 | #define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
66302 | #define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
66303 | #define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
66304 | #define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
66305 | #define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
66306 | #define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
66307 | #define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
66308 | #define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
66309 | #define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
66310 | #define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
66311 | #define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
66312 | #define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
66313 | #define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
66314 | #define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
66315 | #define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
66316 | #define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
66317 | #define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
66318 | #define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
66319 | #define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
66320 | #define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
66321 | #define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
66322 | #define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
66323 | #define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
66324 | #define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
66325 | #define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
66326 | #define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
66327 | #define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
66328 | #define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
66329 | //BIFP0_PCIE_LC_TRAINING_CNTL |
66330 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
66331 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
66332 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
66333 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
66334 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
66335 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
66336 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
66337 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
66338 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
66339 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
66340 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
66341 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
66342 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
66343 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
66344 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
66345 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
66346 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
66347 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
66348 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
66349 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
66350 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
66351 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
66352 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
66353 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
66354 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
66355 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
66356 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
66357 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
66358 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
66359 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
66360 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
66361 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
66362 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
66363 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
66364 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
66365 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
66366 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
66367 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
66368 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
66369 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
66370 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
66371 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
66372 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
66373 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
66374 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
66375 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
66376 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
66377 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
66378 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
66379 | #define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
66380 | //BIFP0_PCIE_LC_LINK_WIDTH_CNTL |
66381 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
66382 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
66383 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
66384 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
66385 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
66386 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
66387 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
66388 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
66389 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
66390 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
66391 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
66392 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
66393 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
66394 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
66395 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
66396 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
66397 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
66398 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
66399 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
66400 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
66401 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
66402 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
66403 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
66404 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
66405 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
66406 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
66407 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
66408 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
66409 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
66410 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
66411 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
66412 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
66413 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
66414 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
66415 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
66416 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
66417 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
66418 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
66419 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
66420 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
66421 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
66422 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
66423 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
66424 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
66425 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
66426 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
66427 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
66428 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
66429 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
66430 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
66431 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
66432 | #define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
66433 | //BIFP0_PCIE_LC_N_FTS_CNTL |
66434 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
66435 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
66436 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
66437 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
66438 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
66439 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
66440 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
66441 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
66442 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
66443 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
66444 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
66445 | #define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
66446 | //BIFP0_PCIE_LC_SPEED_CNTL |
66447 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
66448 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
66449 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
66450 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
66451 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
66452 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
66453 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
66454 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
66455 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
66456 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
66457 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
66458 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
66459 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
66460 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
66461 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
66462 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
66463 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
66464 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
66465 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
66466 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
66467 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
66468 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
66469 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
66470 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
66471 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
66472 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
66473 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
66474 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
66475 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
66476 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
66477 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
66478 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
66479 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
66480 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
66481 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
66482 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
66483 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
66484 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
66485 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
66486 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
66487 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
66488 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
66489 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
66490 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
66491 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
66492 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
66493 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
66494 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
66495 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
66496 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
66497 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
66498 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
66499 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
66500 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
66501 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
66502 | #define BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
66503 | //BIFP0_PCIE_LC_STATE0 |
66504 | #define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
66505 | #define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
66506 | #define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
66507 | #define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
66508 | #define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
66509 | #define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
66510 | #define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
66511 | #define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
66512 | //BIFP0_PCIE_LC_STATE1 |
66513 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
66514 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
66515 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
66516 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
66517 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
66518 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
66519 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
66520 | #define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
66521 | //BIFP0_PCIE_LC_STATE2 |
66522 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
66523 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
66524 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
66525 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
66526 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
66527 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
66528 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
66529 | #define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
66530 | //BIFP0_PCIE_LC_STATE3 |
66531 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
66532 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
66533 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
66534 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
66535 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
66536 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
66537 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
66538 | #define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
66539 | //BIFP0_PCIE_LC_STATE4 |
66540 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
66541 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
66542 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
66543 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
66544 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
66545 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
66546 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
66547 | #define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
66548 | //BIFP0_PCIE_LC_STATE5 |
66549 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
66550 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
66551 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
66552 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
66553 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
66554 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
66555 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
66556 | #define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
66557 | //BIFP0_PCIE_LINK_MANAGEMENT_CNTL2 |
66558 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
66559 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
66560 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
66561 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
66562 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
66563 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
66564 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
66565 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
66566 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
66567 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
66568 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
66569 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
66570 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
66571 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
66572 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
66573 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
66574 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
66575 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
66576 | //BIFP0_PCIE_LC_CNTL2 |
66577 | #define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
66578 | #define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
66579 | #define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
66580 | #define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
66581 | #define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
66582 | #define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
66583 | #define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
66584 | #define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
66585 | #define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
66586 | #define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
66587 | #define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
66588 | #define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
66589 | #define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
66590 | #define BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
66591 | #define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
66592 | #define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
66593 | #define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
66594 | #define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
66595 | #define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
66596 | #define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
66597 | #define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
66598 | #define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
66599 | #define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
66600 | #define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
66601 | #define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
66602 | #define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
66603 | #define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
66604 | #define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
66605 | #define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
66606 | #define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
66607 | #define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
66608 | #define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
66609 | #define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
66610 | #define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
66611 | #define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
66612 | #define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
66613 | #define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
66614 | #define BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
66615 | #define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
66616 | #define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
66617 | #define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
66618 | #define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
66619 | #define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
66620 | #define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
66621 | #define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
66622 | #define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
66623 | #define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
66624 | #define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
66625 | //BIFP0_PCIE_LC_BW_CHANGE_CNTL |
66626 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
66627 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
66628 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
66629 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
66630 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
66631 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
66632 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
66633 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
66634 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
66635 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
66636 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
66637 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
66638 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
66639 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
66640 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
66641 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
66642 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
66643 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
66644 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
66645 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
66646 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
66647 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
66648 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
66649 | #define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
66650 | //BIFP0_PCIE_LC_CDR_CNTL |
66651 | #define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
66652 | #define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
66653 | #define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
66654 | #define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
66655 | #define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
66656 | #define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
66657 | //BIFP0_PCIE_LC_LANE_CNTL |
66658 | #define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
66659 | #define BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
66660 | #define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
66661 | #define BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
66662 | //BIFP0_PCIE_LC_CNTL3 |
66663 | #define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
66664 | #define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
66665 | #define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
66666 | #define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
66667 | #define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
66668 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
66669 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
66670 | #define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
66671 | #define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
66672 | #define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
66673 | #define BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
66674 | #define BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
66675 | #define BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
66676 | #define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
66677 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
66678 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
66679 | #define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
66680 | #define BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
66681 | #define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
66682 | #define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
66683 | #define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
66684 | #define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
66685 | #define BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
66686 | #define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
66687 | #define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
66688 | #define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
66689 | #define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
66690 | #define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
66691 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
66692 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
66693 | #define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
66694 | #define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
66695 | #define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
66696 | #define BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
66697 | #define BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
66698 | #define BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
66699 | #define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
66700 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
66701 | #define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
66702 | #define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
66703 | #define BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
66704 | #define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
66705 | #define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
66706 | #define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
66707 | #define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
66708 | #define BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
66709 | //BIFP0_PCIE_LC_CNTL4 |
66710 | #define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
66711 | #define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
66712 | #define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
66713 | #define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
66714 | #define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
66715 | #define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
66716 | #define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
66717 | #define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
66718 | #define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
66719 | #define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
66720 | #define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
66721 | #define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
66722 | #define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
66723 | #define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
66724 | #define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
66725 | #define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
66726 | #define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
66727 | #define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
66728 | #define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
66729 | #define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
66730 | #define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
66731 | #define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
66732 | #define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
66733 | #define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
66734 | #define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
66735 | #define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
66736 | #define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
66737 | #define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
66738 | #define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
66739 | #define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
66740 | #define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
66741 | #define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
66742 | #define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
66743 | #define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
66744 | #define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
66745 | #define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
66746 | #define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
66747 | #define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
66748 | #define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
66749 | #define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
66750 | #define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
66751 | #define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
66752 | #define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
66753 | #define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
66754 | //BIFP0_PCIE_LC_CNTL5 |
66755 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
66756 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
66757 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
66758 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
66759 | #define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
66760 | #define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
66761 | #define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
66762 | #define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
66763 | #define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
66764 | #define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
66765 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
66766 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
66767 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
66768 | #define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
66769 | #define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
66770 | #define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
66771 | #define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
66772 | #define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
66773 | #define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
66774 | #define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
66775 | //BIFP0_PCIE_LC_FORCE_COEFF |
66776 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
66777 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
66778 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
66779 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
66780 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
66781 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
66782 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
66783 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
66784 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
66785 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
66786 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
66787 | #define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
66788 | //BIFP0_PCIE_LC_BEST_EQ_SETTINGS |
66789 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
66790 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
66791 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
66792 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
66793 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
66794 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
66795 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
66796 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
66797 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
66798 | #define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
66799 | //BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF |
66800 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
66801 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
66802 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
66803 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
66804 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
66805 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
66806 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
66807 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
66808 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
66809 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
66810 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
66811 | #define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
66812 | //BIFP0_PCIE_LC_CNTL6 |
66813 | #define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
66814 | #define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
66815 | #define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
66816 | #define BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
66817 | #define BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
66818 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
66819 | #define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
66820 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
66821 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
66822 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
66823 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
66824 | #define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
66825 | #define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
66826 | #define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
66827 | #define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
66828 | #define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
66829 | #define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
66830 | #define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
66831 | #define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
66832 | #define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
66833 | #define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
66834 | #define BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
66835 | #define BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
66836 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
66837 | #define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
66838 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
66839 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
66840 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
66841 | #define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
66842 | #define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
66843 | #define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
66844 | #define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
66845 | #define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
66846 | #define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
66847 | #define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
66848 | #define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
66849 | //BIFP0_PCIE_LC_CNTL7 |
66850 | #define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
66851 | #define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
66852 | #define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
66853 | #define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
66854 | #define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
66855 | #define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
66856 | #define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
66857 | #define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
66858 | #define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
66859 | #define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
66860 | #define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
66861 | #define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
66862 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
66863 | #define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
66864 | #define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
66865 | #define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
66866 | #define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
66867 | #define BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
66868 | #define BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
66869 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
66870 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
66871 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
66872 | #define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
66873 | #define BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
66874 | #define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
66875 | #define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
66876 | #define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
66877 | #define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
66878 | #define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
66879 | #define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
66880 | #define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
66881 | #define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
66882 | #define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
66883 | #define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
66884 | #define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
66885 | #define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
66886 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
66887 | #define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
66888 | #define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
66889 | #define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
66890 | #define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
66891 | #define BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
66892 | #define BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
66893 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
66894 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
66895 | #define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
66896 | #define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
66897 | #define BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
66898 | //BIFP0_PCIE_LINK_MANAGEMENT_STATUS |
66899 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
66900 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
66901 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
66902 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
66903 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
66904 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
66905 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
66906 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
66907 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
66908 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
66909 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
66910 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
66911 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
66912 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
66913 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
66914 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
66915 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
66916 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
66917 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
66918 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
66919 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
66920 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
66921 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
66922 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
66923 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
66924 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
66925 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
66926 | #define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
66927 | //BIFP0_PCIE_LINK_MANAGEMENT_MASK |
66928 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
66929 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
66930 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
66931 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
66932 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
66933 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
66934 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
66935 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
66936 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
66937 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
66938 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
66939 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
66940 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
66941 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
66942 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
66943 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
66944 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
66945 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
66946 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
66947 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
66948 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
66949 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
66950 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
66951 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
66952 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
66953 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
66954 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
66955 | #define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
66956 | //BIFP0_PCIE_LINK_MANAGEMENT_CNTL |
66957 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
66958 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
66959 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
66960 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
66961 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
66962 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
66963 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
66964 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
66965 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
66966 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
66967 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
66968 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
66969 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
66970 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
66971 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
66972 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
66973 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
66974 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
66975 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
66976 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
66977 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
66978 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
66979 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
66980 | #define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
66981 | //BIFP0_PCIEP_STRAP_LC |
66982 | #define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
66983 | #define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
66984 | #define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
66985 | #define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
66986 | #define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
66987 | #define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
66988 | #define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
66989 | #define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
66990 | #define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
66991 | #define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
66992 | #define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
66993 | #define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
66994 | #define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
66995 | #define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
66996 | #define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
66997 | #define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
66998 | #define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
66999 | #define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
67000 | #define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
67001 | #define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
67002 | #define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
67003 | #define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
67004 | //BIFP0_PCIEP_STRAP_MISC |
67005 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
67006 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
67007 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
67008 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
67009 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
67010 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
67011 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
67012 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
67013 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
67014 | #define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
67015 | //BIFP0_PCIE_LC_L1_PM_SUBSTATE |
67016 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
67017 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
67018 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
67019 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
67020 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
67021 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
67022 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
67023 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
67024 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
67025 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
67026 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
67027 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
67028 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
67029 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
67030 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
67031 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
67032 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
67033 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
67034 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
67035 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
67036 | //BIFP0_PCIE_LC_L1_PM_SUBSTATE2 |
67037 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
67038 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
67039 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
67040 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
67041 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
67042 | #define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
67043 | //BIFP0_PCIE_LC_PORT_ORDER |
67044 | #define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
67045 | #define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
67046 | //BIFP0_PCIEP_BCH_ECC_CNTL |
67047 | #define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
67048 | #define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
67049 | #define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
67050 | #define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
67051 | #define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
67052 | #define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
67053 | //BIFP0_PCIEP_HPGI_PRIVATE |
67054 | #define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
67055 | #define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
67056 | #define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
67057 | #define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
67058 | //BIFP0_PCIEP_HPGI |
67059 | #define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
67060 | #define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
67061 | #define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
67062 | #define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
67063 | #define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
67064 | #define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
67065 | #define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
67066 | #define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
67067 | #define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
67068 | #define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
67069 | #define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
67070 | #define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
67071 | #define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
67072 | #define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
67073 | #define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
67074 | #define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
67075 | #define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
67076 | #define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
67077 | #define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
67078 | #define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
67079 | #define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
67080 | #define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
67081 | //BIFP0_PCIEP_HCNT_DESCRIPTOR |
67082 | #define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
67083 | #define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
67084 | #define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
67085 | #define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
67086 | //BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK |
67087 | #define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
67088 | #define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
67089 | #define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
67090 | #define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
67091 | |
67092 | |
67093 | // addressBlock: nbio_pcie0_bifp1_pciedir_p |
67094 | //BIFP1_PCIEP_RESERVED |
67095 | #define BIFP1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
67096 | #define BIFP1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
67097 | //BIFP1_PCIEP_SCRATCH |
67098 | #define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
67099 | #define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
67100 | //BIFP1_PCIEP_PORT_CNTL |
67101 | #define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
67102 | #define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
67103 | #define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
67104 | #define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
67105 | #define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
67106 | #define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
67107 | #define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
67108 | #define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
67109 | #define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
67110 | #define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
67111 | #define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
67112 | #define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
67113 | #define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
67114 | #define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
67115 | #define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
67116 | #define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
67117 | #define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
67118 | #define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
67119 | #define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
67120 | #define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
67121 | //BIFP1_PCIE_TX_CNTL |
67122 | #define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
67123 | #define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
67124 | #define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
67125 | #define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
67126 | #define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
67127 | #define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
67128 | #define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
67129 | #define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
67130 | #define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
67131 | #define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
67132 | #define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
67133 | #define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
67134 | #define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
67135 | #define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
67136 | #define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
67137 | #define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
67138 | //BIFP1_PCIE_TX_REQUESTER_ID |
67139 | #define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
67140 | #define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
67141 | #define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
67142 | #define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
67143 | #define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
67144 | #define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
67145 | //BIFP1_PCIE_TX_VENDOR_SPECIFIC |
67146 | #define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
67147 | #define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
67148 | //BIFP1_PCIE_TX_REQUEST_NUM_CNTL |
67149 | #define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
67150 | #define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
67151 | #define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
67152 | #define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
67153 | #define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
67154 | #define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
67155 | //BIFP1_PCIE_TX_SEQ |
67156 | #define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
67157 | #define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
67158 | #define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
67159 | #define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
67160 | //BIFP1_PCIE_TX_REPLAY |
67161 | #define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
67162 | #define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
67163 | #define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
67164 | #define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
67165 | #define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
67166 | #define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
67167 | //BIFP1_PCIE_TX_ACK_LATENCY_LIMIT |
67168 | #define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
67169 | #define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
67170 | #define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
67171 | #define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
67172 | //BIFP1_PCIE_TX_CREDITS_ADVT_P |
67173 | #define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
67174 | #define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
67175 | #define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
67176 | #define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
67177 | //BIFP1_PCIE_TX_CREDITS_ADVT_NP |
67178 | #define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
67179 | #define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
67180 | #define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
67181 | #define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
67182 | //BIFP1_PCIE_TX_CREDITS_ADVT_CPL |
67183 | #define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
67184 | #define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
67185 | #define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
67186 | #define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
67187 | //BIFP1_PCIE_TX_CREDITS_INIT_P |
67188 | #define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
67189 | #define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
67190 | #define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
67191 | #define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
67192 | //BIFP1_PCIE_TX_CREDITS_INIT_NP |
67193 | #define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
67194 | #define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
67195 | #define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
67196 | #define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
67197 | //BIFP1_PCIE_TX_CREDITS_INIT_CPL |
67198 | #define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
67199 | #define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
67200 | #define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
67201 | #define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
67202 | //BIFP1_PCIE_TX_CREDITS_STATUS |
67203 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
67204 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
67205 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
67206 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
67207 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
67208 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
67209 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
67210 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
67211 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
67212 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
67213 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
67214 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
67215 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
67216 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
67217 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
67218 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
67219 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
67220 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
67221 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
67222 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
67223 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
67224 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
67225 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
67226 | #define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
67227 | //BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD |
67228 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
67229 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
67230 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
67231 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
67232 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
67233 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
67234 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
67235 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
67236 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
67237 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
67238 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
67239 | #define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
67240 | //BIFP1_PCIE_P_PORT_LANE_STATUS |
67241 | #define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
67242 | #define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
67243 | #define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
67244 | #define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
67245 | //BIFP1_PCIE_FC_P |
67246 | #define BIFP1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
67247 | #define BIFP1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
67248 | #define BIFP1_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
67249 | #define BIFP1_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
67250 | //BIFP1_PCIE_FC_NP |
67251 | #define BIFP1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
67252 | #define BIFP1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
67253 | #define BIFP1_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
67254 | #define BIFP1_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
67255 | //BIFP1_PCIE_FC_CPL |
67256 | #define BIFP1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
67257 | #define BIFP1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
67258 | #define BIFP1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
67259 | #define BIFP1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
67260 | //BIFP1_PCIE_ERR_CNTL |
67261 | #define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
67262 | #define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
67263 | #define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
67264 | #define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
67265 | #define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
67266 | #define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
67267 | #define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
67268 | #define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
67269 | #define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
67270 | #define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
67271 | #define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
67272 | #define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
67273 | #define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
67274 | #define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
67275 | #define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
67276 | #define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
67277 | #define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
67278 | #define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
67279 | #define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
67280 | #define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
67281 | #define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
67282 | #define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
67283 | #define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
67284 | #define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
67285 | #define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
67286 | #define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
67287 | #define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
67288 | #define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
67289 | //BIFP1_PCIE_RX_CNTL |
67290 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
67291 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
67292 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
67293 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
67294 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
67295 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
67296 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
67297 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
67298 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
67299 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
67300 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
67301 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
67302 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
67303 | #define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
67304 | #define BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
67305 | #define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
67306 | #define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
67307 | #define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
67308 | #define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
67309 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
67310 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
67311 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
67312 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
67313 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
67314 | #define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
67315 | #define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
67316 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
67317 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
67318 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
67319 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
67320 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
67321 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
67322 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
67323 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
67324 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
67325 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
67326 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
67327 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
67328 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
67329 | #define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
67330 | #define BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
67331 | #define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
67332 | #define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
67333 | #define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
67334 | #define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
67335 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
67336 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
67337 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
67338 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
67339 | #define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
67340 | #define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
67341 | #define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
67342 | //BIFP1_PCIE_RX_EXPECTED_SEQNUM |
67343 | #define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
67344 | #define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
67345 | //BIFP1_PCIE_RX_VENDOR_SPECIFIC |
67346 | #define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
67347 | #define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
67348 | #define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
67349 | #define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
67350 | //BIFP1_PCIE_RX_CNTL3 |
67351 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
67352 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
67353 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
67354 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
67355 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
67356 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
67357 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
67358 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
67359 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
67360 | #define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
67361 | //BIFP1_PCIE_RX_CREDITS_ALLOCATED_P |
67362 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
67363 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
67364 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
67365 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
67366 | //BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP |
67367 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
67368 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
67369 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
67370 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
67371 | //BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL |
67372 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
67373 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
67374 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
67375 | #define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
67376 | //BIFP1_PCIEP_ERROR_INJECT_PHYSICAL |
67377 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
67378 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
67379 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
67380 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
67381 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
67382 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
67383 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
67384 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
67385 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
67386 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
67387 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
67388 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
67389 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
67390 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
67391 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
67392 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
67393 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
67394 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
67395 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
67396 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
67397 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
67398 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
67399 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
67400 | #define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
67401 | //BIFP1_PCIEP_ERROR_INJECT_TRANSACTION |
67402 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
67403 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
67404 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
67405 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
67406 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
67407 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
67408 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
67409 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
67410 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
67411 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
67412 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
67413 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
67414 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
67415 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
67416 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
67417 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
67418 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
67419 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
67420 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
67421 | #define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
67422 | //BIFP1_PCIEP_NAK_COUNTER |
67423 | #define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
67424 | #define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
67425 | #define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
67426 | #define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
67427 | //BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
67428 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
67429 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
67430 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
67431 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
67432 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
67433 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
67434 | //BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
67435 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
67436 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
67437 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
67438 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
67439 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
67440 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
67441 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
67442 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
67443 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
67444 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
67445 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
67446 | #define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
67447 | //BIFP1_PCIE_LC_CNTL |
67448 | #define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
67449 | #define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
67450 | #define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
67451 | #define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
67452 | #define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
67453 | #define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
67454 | #define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
67455 | #define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
67456 | #define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
67457 | #define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
67458 | #define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
67459 | #define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
67460 | #define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
67461 | #define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
67462 | #define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
67463 | #define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
67464 | #define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
67465 | #define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
67466 | #define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
67467 | #define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
67468 | #define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
67469 | #define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
67470 | #define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
67471 | #define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
67472 | #define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
67473 | #define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
67474 | #define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
67475 | #define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
67476 | #define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
67477 | #define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
67478 | #define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
67479 | #define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
67480 | #define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
67481 | #define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
67482 | #define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
67483 | #define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
67484 | #define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
67485 | #define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
67486 | #define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
67487 | #define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
67488 | //BIFP1_PCIE_LC_TRAINING_CNTL |
67489 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
67490 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
67491 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
67492 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
67493 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
67494 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
67495 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
67496 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
67497 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
67498 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
67499 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
67500 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
67501 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
67502 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
67503 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
67504 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
67505 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
67506 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
67507 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
67508 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
67509 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
67510 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
67511 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
67512 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
67513 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
67514 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
67515 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
67516 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
67517 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
67518 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
67519 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
67520 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
67521 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
67522 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
67523 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
67524 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
67525 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
67526 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
67527 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
67528 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
67529 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
67530 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
67531 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
67532 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
67533 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
67534 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
67535 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
67536 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
67537 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
67538 | #define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
67539 | //BIFP1_PCIE_LC_LINK_WIDTH_CNTL |
67540 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
67541 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
67542 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
67543 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
67544 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
67545 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
67546 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
67547 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
67548 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
67549 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
67550 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
67551 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
67552 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
67553 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
67554 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
67555 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
67556 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
67557 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
67558 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
67559 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
67560 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
67561 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
67562 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
67563 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
67564 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
67565 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
67566 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
67567 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
67568 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
67569 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
67570 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
67571 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
67572 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
67573 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
67574 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
67575 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
67576 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
67577 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
67578 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
67579 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
67580 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
67581 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
67582 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
67583 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
67584 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
67585 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
67586 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
67587 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
67588 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
67589 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
67590 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
67591 | #define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
67592 | //BIFP1_PCIE_LC_N_FTS_CNTL |
67593 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
67594 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
67595 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
67596 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
67597 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
67598 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
67599 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
67600 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
67601 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
67602 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
67603 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
67604 | #define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
67605 | //BIFP1_PCIE_LC_SPEED_CNTL |
67606 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
67607 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
67608 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
67609 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
67610 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
67611 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
67612 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
67613 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
67614 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
67615 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
67616 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
67617 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
67618 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
67619 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
67620 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
67621 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
67622 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
67623 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
67624 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
67625 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
67626 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
67627 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
67628 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
67629 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
67630 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
67631 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
67632 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
67633 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
67634 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
67635 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
67636 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
67637 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
67638 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
67639 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
67640 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
67641 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
67642 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
67643 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
67644 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
67645 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
67646 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
67647 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
67648 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
67649 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
67650 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
67651 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
67652 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
67653 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
67654 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
67655 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
67656 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
67657 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
67658 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
67659 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
67660 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
67661 | #define BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
67662 | //BIFP1_PCIE_LC_STATE0 |
67663 | #define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
67664 | #define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
67665 | #define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
67666 | #define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
67667 | #define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
67668 | #define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
67669 | #define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
67670 | #define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
67671 | //BIFP1_PCIE_LC_STATE1 |
67672 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
67673 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
67674 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
67675 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
67676 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
67677 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
67678 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
67679 | #define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
67680 | //BIFP1_PCIE_LC_STATE2 |
67681 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
67682 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
67683 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
67684 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
67685 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
67686 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
67687 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
67688 | #define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
67689 | //BIFP1_PCIE_LC_STATE3 |
67690 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
67691 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
67692 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
67693 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
67694 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
67695 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
67696 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
67697 | #define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
67698 | //BIFP1_PCIE_LC_STATE4 |
67699 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
67700 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
67701 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
67702 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
67703 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
67704 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
67705 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
67706 | #define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
67707 | //BIFP1_PCIE_LC_STATE5 |
67708 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
67709 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
67710 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
67711 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
67712 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
67713 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
67714 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
67715 | #define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
67716 | //BIFP1_PCIE_LINK_MANAGEMENT_CNTL2 |
67717 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
67718 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
67719 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
67720 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
67721 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
67722 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
67723 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
67724 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
67725 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
67726 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
67727 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
67728 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
67729 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
67730 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
67731 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
67732 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
67733 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
67734 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
67735 | //BIFP1_PCIE_LC_CNTL2 |
67736 | #define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
67737 | #define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
67738 | #define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
67739 | #define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
67740 | #define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
67741 | #define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
67742 | #define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
67743 | #define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
67744 | #define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
67745 | #define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
67746 | #define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
67747 | #define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
67748 | #define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
67749 | #define BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
67750 | #define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
67751 | #define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
67752 | #define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
67753 | #define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
67754 | #define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
67755 | #define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
67756 | #define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
67757 | #define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
67758 | #define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
67759 | #define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
67760 | #define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
67761 | #define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
67762 | #define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
67763 | #define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
67764 | #define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
67765 | #define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
67766 | #define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
67767 | #define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
67768 | #define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
67769 | #define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
67770 | #define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
67771 | #define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
67772 | #define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
67773 | #define BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
67774 | #define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
67775 | #define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
67776 | #define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
67777 | #define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
67778 | #define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
67779 | #define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
67780 | #define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
67781 | #define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
67782 | #define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
67783 | #define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
67784 | //BIFP1_PCIE_LC_BW_CHANGE_CNTL |
67785 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
67786 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
67787 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
67788 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
67789 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
67790 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
67791 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
67792 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
67793 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
67794 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
67795 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
67796 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
67797 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
67798 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
67799 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
67800 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
67801 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
67802 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
67803 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
67804 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
67805 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
67806 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
67807 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
67808 | #define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
67809 | //BIFP1_PCIE_LC_CDR_CNTL |
67810 | #define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
67811 | #define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
67812 | #define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
67813 | #define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
67814 | #define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
67815 | #define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
67816 | //BIFP1_PCIE_LC_LANE_CNTL |
67817 | #define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
67818 | #define BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
67819 | #define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
67820 | #define BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
67821 | //BIFP1_PCIE_LC_CNTL3 |
67822 | #define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
67823 | #define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
67824 | #define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
67825 | #define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
67826 | #define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
67827 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
67828 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
67829 | #define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
67830 | #define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
67831 | #define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
67832 | #define BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
67833 | #define BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
67834 | #define BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
67835 | #define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
67836 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
67837 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
67838 | #define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
67839 | #define BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
67840 | #define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
67841 | #define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
67842 | #define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
67843 | #define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
67844 | #define BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
67845 | #define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
67846 | #define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
67847 | #define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
67848 | #define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
67849 | #define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
67850 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
67851 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
67852 | #define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
67853 | #define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
67854 | #define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
67855 | #define BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
67856 | #define BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
67857 | #define BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
67858 | #define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
67859 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
67860 | #define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
67861 | #define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
67862 | #define BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
67863 | #define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
67864 | #define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
67865 | #define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
67866 | #define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
67867 | #define BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
67868 | //BIFP1_PCIE_LC_CNTL4 |
67869 | #define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
67870 | #define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
67871 | #define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
67872 | #define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
67873 | #define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
67874 | #define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
67875 | #define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
67876 | #define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
67877 | #define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
67878 | #define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
67879 | #define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
67880 | #define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
67881 | #define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
67882 | #define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
67883 | #define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
67884 | #define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
67885 | #define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
67886 | #define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
67887 | #define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
67888 | #define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
67889 | #define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
67890 | #define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
67891 | #define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
67892 | #define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
67893 | #define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
67894 | #define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
67895 | #define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
67896 | #define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
67897 | #define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
67898 | #define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
67899 | #define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
67900 | #define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
67901 | #define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
67902 | #define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
67903 | #define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
67904 | #define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
67905 | #define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
67906 | #define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
67907 | #define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
67908 | #define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
67909 | #define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
67910 | #define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
67911 | #define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
67912 | #define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
67913 | //BIFP1_PCIE_LC_CNTL5 |
67914 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
67915 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
67916 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
67917 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
67918 | #define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
67919 | #define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
67920 | #define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
67921 | #define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
67922 | #define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
67923 | #define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
67924 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
67925 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
67926 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
67927 | #define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
67928 | #define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
67929 | #define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
67930 | #define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
67931 | #define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
67932 | #define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
67933 | #define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
67934 | //BIFP1_PCIE_LC_FORCE_COEFF |
67935 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
67936 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
67937 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
67938 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
67939 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
67940 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
67941 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
67942 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
67943 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
67944 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
67945 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
67946 | #define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
67947 | //BIFP1_PCIE_LC_BEST_EQ_SETTINGS |
67948 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
67949 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
67950 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
67951 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
67952 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
67953 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
67954 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
67955 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
67956 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
67957 | #define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
67958 | //BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF |
67959 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
67960 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
67961 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
67962 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
67963 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
67964 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
67965 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
67966 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
67967 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
67968 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
67969 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
67970 | #define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
67971 | //BIFP1_PCIE_LC_CNTL6 |
67972 | #define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
67973 | #define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
67974 | #define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
67975 | #define BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
67976 | #define BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
67977 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
67978 | #define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
67979 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
67980 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
67981 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
67982 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
67983 | #define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
67984 | #define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
67985 | #define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
67986 | #define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
67987 | #define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
67988 | #define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
67989 | #define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
67990 | #define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
67991 | #define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
67992 | #define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
67993 | #define BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
67994 | #define BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
67995 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
67996 | #define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
67997 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
67998 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
67999 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
68000 | #define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
68001 | #define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
68002 | #define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
68003 | #define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
68004 | #define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
68005 | #define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
68006 | #define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
68007 | #define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
68008 | //BIFP1_PCIE_LC_CNTL7 |
68009 | #define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
68010 | #define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
68011 | #define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
68012 | #define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
68013 | #define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
68014 | #define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
68015 | #define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
68016 | #define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
68017 | #define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
68018 | #define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
68019 | #define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
68020 | #define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
68021 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
68022 | #define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
68023 | #define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
68024 | #define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
68025 | #define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
68026 | #define BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
68027 | #define BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
68028 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
68029 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
68030 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
68031 | #define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
68032 | #define BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
68033 | #define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
68034 | #define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
68035 | #define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
68036 | #define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
68037 | #define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
68038 | #define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
68039 | #define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
68040 | #define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
68041 | #define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
68042 | #define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
68043 | #define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
68044 | #define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
68045 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
68046 | #define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
68047 | #define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
68048 | #define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
68049 | #define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
68050 | #define BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
68051 | #define BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
68052 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
68053 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
68054 | #define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
68055 | #define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
68056 | #define BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
68057 | //BIFP1_PCIE_LINK_MANAGEMENT_STATUS |
68058 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
68059 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
68060 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
68061 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
68062 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
68063 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
68064 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
68065 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
68066 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
68067 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
68068 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
68069 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
68070 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
68071 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
68072 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
68073 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
68074 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
68075 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
68076 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
68077 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
68078 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
68079 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
68080 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
68081 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
68082 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
68083 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
68084 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
68085 | #define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
68086 | //BIFP1_PCIE_LINK_MANAGEMENT_MASK |
68087 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
68088 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
68089 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
68090 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
68091 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
68092 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
68093 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
68094 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
68095 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
68096 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
68097 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
68098 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
68099 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
68100 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
68101 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
68102 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
68103 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
68104 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
68105 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
68106 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
68107 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
68108 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
68109 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
68110 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
68111 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
68112 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
68113 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
68114 | #define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
68115 | //BIFP1_PCIE_LINK_MANAGEMENT_CNTL |
68116 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
68117 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
68118 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
68119 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
68120 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
68121 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
68122 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
68123 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
68124 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
68125 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
68126 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
68127 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
68128 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
68129 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
68130 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
68131 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
68132 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
68133 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
68134 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
68135 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
68136 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
68137 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
68138 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
68139 | #define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
68140 | //BIFP1_PCIEP_STRAP_LC |
68141 | #define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
68142 | #define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
68143 | #define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
68144 | #define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
68145 | #define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
68146 | #define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
68147 | #define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
68148 | #define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
68149 | #define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
68150 | #define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
68151 | #define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
68152 | #define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
68153 | #define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
68154 | #define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
68155 | #define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
68156 | #define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
68157 | #define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
68158 | #define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
68159 | #define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
68160 | #define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
68161 | #define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
68162 | #define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
68163 | //BIFP1_PCIEP_STRAP_MISC |
68164 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
68165 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
68166 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
68167 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
68168 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
68169 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
68170 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
68171 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
68172 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
68173 | #define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
68174 | //BIFP1_PCIE_LC_L1_PM_SUBSTATE |
68175 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
68176 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
68177 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
68178 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
68179 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
68180 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
68181 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
68182 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
68183 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
68184 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
68185 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
68186 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
68187 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
68188 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
68189 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
68190 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
68191 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
68192 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
68193 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
68194 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
68195 | //BIFP1_PCIE_LC_L1_PM_SUBSTATE2 |
68196 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
68197 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
68198 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
68199 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
68200 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
68201 | #define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
68202 | //BIFP1_PCIE_LC_PORT_ORDER |
68203 | #define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
68204 | #define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
68205 | //BIFP1_PCIEP_BCH_ECC_CNTL |
68206 | #define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
68207 | #define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
68208 | #define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
68209 | #define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
68210 | #define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
68211 | #define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
68212 | //BIFP1_PCIEP_HPGI_PRIVATE |
68213 | #define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
68214 | #define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
68215 | #define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
68216 | #define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
68217 | //BIFP1_PCIEP_HPGI |
68218 | #define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
68219 | #define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
68220 | #define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
68221 | #define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
68222 | #define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
68223 | #define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
68224 | #define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
68225 | #define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
68226 | #define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
68227 | #define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
68228 | #define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
68229 | #define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
68230 | #define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
68231 | #define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
68232 | #define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
68233 | #define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
68234 | #define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
68235 | #define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
68236 | #define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
68237 | #define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
68238 | #define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
68239 | #define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
68240 | //BIFP1_PCIEP_HCNT_DESCRIPTOR |
68241 | #define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
68242 | #define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
68243 | #define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
68244 | #define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
68245 | //BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK |
68246 | #define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
68247 | #define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
68248 | #define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
68249 | #define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
68250 | |
68251 | |
68252 | // addressBlock: nbio_pcie0_bifp2_pciedir_p |
68253 | //BIFP2_PCIEP_RESERVED |
68254 | #define BIFP2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
68255 | #define BIFP2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
68256 | //BIFP2_PCIEP_SCRATCH |
68257 | #define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
68258 | #define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
68259 | //BIFP2_PCIEP_PORT_CNTL |
68260 | #define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
68261 | #define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
68262 | #define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
68263 | #define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
68264 | #define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
68265 | #define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
68266 | #define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
68267 | #define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
68268 | #define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
68269 | #define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
68270 | #define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
68271 | #define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
68272 | #define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
68273 | #define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
68274 | #define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
68275 | #define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
68276 | #define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
68277 | #define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
68278 | #define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
68279 | #define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
68280 | //BIFP2_PCIE_TX_CNTL |
68281 | #define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
68282 | #define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
68283 | #define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
68284 | #define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
68285 | #define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
68286 | #define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
68287 | #define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
68288 | #define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
68289 | #define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
68290 | #define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
68291 | #define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
68292 | #define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
68293 | #define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
68294 | #define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
68295 | #define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
68296 | #define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
68297 | //BIFP2_PCIE_TX_REQUESTER_ID |
68298 | #define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
68299 | #define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
68300 | #define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
68301 | #define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
68302 | #define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
68303 | #define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
68304 | //BIFP2_PCIE_TX_VENDOR_SPECIFIC |
68305 | #define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
68306 | #define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
68307 | //BIFP2_PCIE_TX_REQUEST_NUM_CNTL |
68308 | #define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
68309 | #define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
68310 | #define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
68311 | #define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
68312 | #define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
68313 | #define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
68314 | //BIFP2_PCIE_TX_SEQ |
68315 | #define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
68316 | #define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
68317 | #define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
68318 | #define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
68319 | //BIFP2_PCIE_TX_REPLAY |
68320 | #define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
68321 | #define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
68322 | #define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
68323 | #define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
68324 | #define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
68325 | #define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
68326 | //BIFP2_PCIE_TX_ACK_LATENCY_LIMIT |
68327 | #define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
68328 | #define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
68329 | #define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
68330 | #define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
68331 | //BIFP2_PCIE_TX_CREDITS_ADVT_P |
68332 | #define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
68333 | #define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
68334 | #define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
68335 | #define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
68336 | //BIFP2_PCIE_TX_CREDITS_ADVT_NP |
68337 | #define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
68338 | #define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
68339 | #define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
68340 | #define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
68341 | //BIFP2_PCIE_TX_CREDITS_ADVT_CPL |
68342 | #define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
68343 | #define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
68344 | #define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
68345 | #define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
68346 | //BIFP2_PCIE_TX_CREDITS_INIT_P |
68347 | #define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
68348 | #define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
68349 | #define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
68350 | #define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
68351 | //BIFP2_PCIE_TX_CREDITS_INIT_NP |
68352 | #define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
68353 | #define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
68354 | #define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
68355 | #define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
68356 | //BIFP2_PCIE_TX_CREDITS_INIT_CPL |
68357 | #define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
68358 | #define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
68359 | #define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
68360 | #define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
68361 | //BIFP2_PCIE_TX_CREDITS_STATUS |
68362 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
68363 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
68364 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
68365 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
68366 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
68367 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
68368 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
68369 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
68370 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
68371 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
68372 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
68373 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
68374 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
68375 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
68376 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
68377 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
68378 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
68379 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
68380 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
68381 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
68382 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
68383 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
68384 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
68385 | #define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
68386 | //BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD |
68387 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
68388 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
68389 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
68390 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
68391 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
68392 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
68393 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
68394 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
68395 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
68396 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
68397 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
68398 | #define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
68399 | //BIFP2_PCIE_P_PORT_LANE_STATUS |
68400 | #define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
68401 | #define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
68402 | #define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
68403 | #define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
68404 | //BIFP2_PCIE_FC_P |
68405 | #define BIFP2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
68406 | #define BIFP2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
68407 | #define BIFP2_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
68408 | #define BIFP2_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
68409 | //BIFP2_PCIE_FC_NP |
68410 | #define BIFP2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
68411 | #define BIFP2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
68412 | #define BIFP2_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
68413 | #define BIFP2_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
68414 | //BIFP2_PCIE_FC_CPL |
68415 | #define BIFP2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
68416 | #define BIFP2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
68417 | #define BIFP2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
68418 | #define BIFP2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
68419 | //BIFP2_PCIE_ERR_CNTL |
68420 | #define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
68421 | #define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
68422 | #define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
68423 | #define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
68424 | #define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
68425 | #define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
68426 | #define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
68427 | #define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
68428 | #define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
68429 | #define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
68430 | #define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
68431 | #define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
68432 | #define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
68433 | #define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
68434 | #define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
68435 | #define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
68436 | #define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
68437 | #define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
68438 | #define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
68439 | #define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
68440 | #define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
68441 | #define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
68442 | #define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
68443 | #define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
68444 | #define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
68445 | #define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
68446 | #define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
68447 | #define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
68448 | //BIFP2_PCIE_RX_CNTL |
68449 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
68450 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
68451 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
68452 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
68453 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
68454 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
68455 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
68456 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
68457 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
68458 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
68459 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
68460 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
68461 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
68462 | #define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
68463 | #define BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
68464 | #define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
68465 | #define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
68466 | #define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
68467 | #define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
68468 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
68469 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
68470 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
68471 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
68472 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
68473 | #define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
68474 | #define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
68475 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
68476 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
68477 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
68478 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
68479 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
68480 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
68481 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
68482 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
68483 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
68484 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
68485 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
68486 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
68487 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
68488 | #define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
68489 | #define BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
68490 | #define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
68491 | #define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
68492 | #define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
68493 | #define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
68494 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
68495 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
68496 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
68497 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
68498 | #define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
68499 | #define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
68500 | #define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
68501 | //BIFP2_PCIE_RX_EXPECTED_SEQNUM |
68502 | #define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
68503 | #define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
68504 | //BIFP2_PCIE_RX_VENDOR_SPECIFIC |
68505 | #define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
68506 | #define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
68507 | #define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
68508 | #define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
68509 | //BIFP2_PCIE_RX_CNTL3 |
68510 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
68511 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
68512 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
68513 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
68514 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
68515 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
68516 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
68517 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
68518 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
68519 | #define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
68520 | //BIFP2_PCIE_RX_CREDITS_ALLOCATED_P |
68521 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
68522 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
68523 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
68524 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
68525 | //BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP |
68526 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
68527 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
68528 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
68529 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
68530 | //BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL |
68531 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
68532 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
68533 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
68534 | #define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
68535 | //BIFP2_PCIEP_ERROR_INJECT_PHYSICAL |
68536 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
68537 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
68538 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
68539 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
68540 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
68541 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
68542 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
68543 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
68544 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
68545 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
68546 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
68547 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
68548 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
68549 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
68550 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
68551 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
68552 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
68553 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
68554 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
68555 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
68556 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
68557 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
68558 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
68559 | #define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
68560 | //BIFP2_PCIEP_ERROR_INJECT_TRANSACTION |
68561 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
68562 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
68563 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
68564 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
68565 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
68566 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
68567 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
68568 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
68569 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
68570 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
68571 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
68572 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
68573 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
68574 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
68575 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
68576 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
68577 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
68578 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
68579 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
68580 | #define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
68581 | //BIFP2_PCIEP_NAK_COUNTER |
68582 | #define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
68583 | #define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
68584 | #define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
68585 | #define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
68586 | //BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
68587 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
68588 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
68589 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
68590 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
68591 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
68592 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
68593 | //BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
68594 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
68595 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
68596 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
68597 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
68598 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
68599 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
68600 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
68601 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
68602 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
68603 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
68604 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
68605 | #define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
68606 | //BIFP2_PCIE_LC_CNTL |
68607 | #define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
68608 | #define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
68609 | #define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
68610 | #define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
68611 | #define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
68612 | #define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
68613 | #define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
68614 | #define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
68615 | #define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
68616 | #define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
68617 | #define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
68618 | #define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
68619 | #define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
68620 | #define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
68621 | #define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
68622 | #define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
68623 | #define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
68624 | #define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
68625 | #define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
68626 | #define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
68627 | #define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
68628 | #define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
68629 | #define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
68630 | #define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
68631 | #define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
68632 | #define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
68633 | #define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
68634 | #define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
68635 | #define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
68636 | #define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
68637 | #define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
68638 | #define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
68639 | #define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
68640 | #define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
68641 | #define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
68642 | #define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
68643 | #define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
68644 | #define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
68645 | #define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
68646 | #define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
68647 | //BIFP2_PCIE_LC_TRAINING_CNTL |
68648 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
68649 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
68650 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
68651 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
68652 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
68653 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
68654 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
68655 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
68656 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
68657 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
68658 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
68659 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
68660 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
68661 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
68662 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
68663 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
68664 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
68665 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
68666 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
68667 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
68668 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
68669 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
68670 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
68671 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
68672 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
68673 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
68674 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
68675 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
68676 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
68677 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
68678 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
68679 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
68680 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
68681 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
68682 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
68683 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
68684 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
68685 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
68686 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
68687 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
68688 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
68689 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
68690 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
68691 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
68692 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
68693 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
68694 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
68695 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
68696 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
68697 | #define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
68698 | //BIFP2_PCIE_LC_LINK_WIDTH_CNTL |
68699 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
68700 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
68701 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
68702 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
68703 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
68704 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
68705 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
68706 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
68707 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
68708 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
68709 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
68710 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
68711 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
68712 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
68713 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
68714 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
68715 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
68716 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
68717 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
68718 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
68719 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
68720 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
68721 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
68722 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
68723 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
68724 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
68725 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
68726 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
68727 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
68728 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
68729 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
68730 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
68731 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
68732 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
68733 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
68734 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
68735 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
68736 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
68737 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
68738 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
68739 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
68740 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
68741 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
68742 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
68743 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
68744 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
68745 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
68746 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
68747 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
68748 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
68749 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
68750 | #define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
68751 | //BIFP2_PCIE_LC_N_FTS_CNTL |
68752 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
68753 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
68754 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
68755 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
68756 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
68757 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
68758 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
68759 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
68760 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
68761 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
68762 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
68763 | #define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
68764 | //BIFP2_PCIE_LC_SPEED_CNTL |
68765 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
68766 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
68767 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
68768 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
68769 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
68770 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
68771 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
68772 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
68773 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
68774 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
68775 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
68776 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
68777 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
68778 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
68779 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
68780 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
68781 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
68782 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
68783 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
68784 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
68785 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
68786 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
68787 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
68788 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
68789 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
68790 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
68791 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
68792 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
68793 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
68794 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
68795 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
68796 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
68797 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
68798 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
68799 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
68800 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
68801 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
68802 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
68803 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
68804 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
68805 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
68806 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
68807 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
68808 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
68809 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
68810 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
68811 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
68812 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
68813 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
68814 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
68815 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
68816 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
68817 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
68818 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
68819 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
68820 | #define BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
68821 | //BIFP2_PCIE_LC_STATE0 |
68822 | #define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
68823 | #define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
68824 | #define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
68825 | #define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
68826 | #define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
68827 | #define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
68828 | #define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
68829 | #define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
68830 | //BIFP2_PCIE_LC_STATE1 |
68831 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
68832 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
68833 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
68834 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
68835 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
68836 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
68837 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
68838 | #define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
68839 | //BIFP2_PCIE_LC_STATE2 |
68840 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
68841 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
68842 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
68843 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
68844 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
68845 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
68846 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
68847 | #define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
68848 | //BIFP2_PCIE_LC_STATE3 |
68849 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
68850 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
68851 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
68852 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
68853 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
68854 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
68855 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
68856 | #define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
68857 | //BIFP2_PCIE_LC_STATE4 |
68858 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
68859 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
68860 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
68861 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
68862 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
68863 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
68864 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
68865 | #define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
68866 | //BIFP2_PCIE_LC_STATE5 |
68867 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
68868 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
68869 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
68870 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
68871 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
68872 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
68873 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
68874 | #define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
68875 | //BIFP2_PCIE_LINK_MANAGEMENT_CNTL2 |
68876 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
68877 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
68878 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
68879 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
68880 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
68881 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
68882 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
68883 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
68884 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
68885 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
68886 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
68887 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
68888 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
68889 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
68890 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
68891 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
68892 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
68893 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
68894 | //BIFP2_PCIE_LC_CNTL2 |
68895 | #define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
68896 | #define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
68897 | #define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
68898 | #define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
68899 | #define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
68900 | #define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
68901 | #define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
68902 | #define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
68903 | #define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
68904 | #define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
68905 | #define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
68906 | #define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
68907 | #define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
68908 | #define BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
68909 | #define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
68910 | #define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
68911 | #define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
68912 | #define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
68913 | #define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
68914 | #define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
68915 | #define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
68916 | #define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
68917 | #define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
68918 | #define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
68919 | #define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
68920 | #define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
68921 | #define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
68922 | #define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
68923 | #define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
68924 | #define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
68925 | #define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
68926 | #define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
68927 | #define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
68928 | #define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
68929 | #define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
68930 | #define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
68931 | #define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
68932 | #define BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
68933 | #define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
68934 | #define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
68935 | #define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
68936 | #define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
68937 | #define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
68938 | #define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
68939 | #define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
68940 | #define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
68941 | #define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
68942 | #define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
68943 | //BIFP2_PCIE_LC_BW_CHANGE_CNTL |
68944 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
68945 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
68946 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
68947 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
68948 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
68949 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
68950 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
68951 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
68952 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
68953 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
68954 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
68955 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
68956 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
68957 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
68958 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
68959 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
68960 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
68961 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
68962 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
68963 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
68964 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
68965 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
68966 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
68967 | #define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
68968 | //BIFP2_PCIE_LC_CDR_CNTL |
68969 | #define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
68970 | #define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
68971 | #define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
68972 | #define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
68973 | #define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
68974 | #define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
68975 | //BIFP2_PCIE_LC_LANE_CNTL |
68976 | #define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
68977 | #define BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
68978 | #define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
68979 | #define BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
68980 | //BIFP2_PCIE_LC_CNTL3 |
68981 | #define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
68982 | #define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
68983 | #define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
68984 | #define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
68985 | #define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
68986 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
68987 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
68988 | #define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
68989 | #define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
68990 | #define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
68991 | #define BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
68992 | #define BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
68993 | #define BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
68994 | #define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
68995 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
68996 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
68997 | #define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
68998 | #define BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
68999 | #define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
69000 | #define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
69001 | #define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
69002 | #define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
69003 | #define BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
69004 | #define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
69005 | #define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
69006 | #define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
69007 | #define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
69008 | #define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
69009 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
69010 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
69011 | #define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
69012 | #define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
69013 | #define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
69014 | #define BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
69015 | #define BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
69016 | #define BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
69017 | #define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
69018 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
69019 | #define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
69020 | #define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
69021 | #define BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
69022 | #define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
69023 | #define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
69024 | #define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
69025 | #define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
69026 | #define BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
69027 | //BIFP2_PCIE_LC_CNTL4 |
69028 | #define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
69029 | #define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
69030 | #define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
69031 | #define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
69032 | #define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
69033 | #define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
69034 | #define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
69035 | #define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
69036 | #define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
69037 | #define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
69038 | #define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
69039 | #define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
69040 | #define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
69041 | #define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
69042 | #define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
69043 | #define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
69044 | #define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
69045 | #define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
69046 | #define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
69047 | #define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
69048 | #define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
69049 | #define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
69050 | #define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
69051 | #define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
69052 | #define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
69053 | #define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
69054 | #define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
69055 | #define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
69056 | #define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
69057 | #define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
69058 | #define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
69059 | #define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
69060 | #define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
69061 | #define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
69062 | #define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
69063 | #define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
69064 | #define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
69065 | #define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
69066 | #define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
69067 | #define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
69068 | #define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
69069 | #define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
69070 | #define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
69071 | #define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
69072 | //BIFP2_PCIE_LC_CNTL5 |
69073 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
69074 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
69075 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
69076 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
69077 | #define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
69078 | #define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
69079 | #define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
69080 | #define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
69081 | #define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
69082 | #define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
69083 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
69084 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
69085 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
69086 | #define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
69087 | #define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
69088 | #define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
69089 | #define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
69090 | #define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
69091 | #define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
69092 | #define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
69093 | //BIFP2_PCIE_LC_FORCE_COEFF |
69094 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
69095 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
69096 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
69097 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
69098 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
69099 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
69100 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
69101 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
69102 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
69103 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
69104 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
69105 | #define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
69106 | //BIFP2_PCIE_LC_BEST_EQ_SETTINGS |
69107 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
69108 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
69109 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
69110 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
69111 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
69112 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
69113 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
69114 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
69115 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
69116 | #define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
69117 | //BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF |
69118 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
69119 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
69120 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
69121 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
69122 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
69123 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
69124 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
69125 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
69126 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
69127 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
69128 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
69129 | #define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
69130 | //BIFP2_PCIE_LC_CNTL6 |
69131 | #define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
69132 | #define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
69133 | #define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
69134 | #define BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
69135 | #define BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
69136 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
69137 | #define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
69138 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
69139 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
69140 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
69141 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
69142 | #define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
69143 | #define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
69144 | #define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
69145 | #define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
69146 | #define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
69147 | #define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
69148 | #define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
69149 | #define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
69150 | #define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
69151 | #define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
69152 | #define BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
69153 | #define BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
69154 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
69155 | #define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
69156 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
69157 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
69158 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
69159 | #define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
69160 | #define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
69161 | #define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
69162 | #define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
69163 | #define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
69164 | #define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
69165 | #define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
69166 | #define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
69167 | //BIFP2_PCIE_LC_CNTL7 |
69168 | #define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
69169 | #define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
69170 | #define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
69171 | #define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
69172 | #define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
69173 | #define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
69174 | #define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
69175 | #define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
69176 | #define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
69177 | #define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
69178 | #define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
69179 | #define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
69180 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
69181 | #define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
69182 | #define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
69183 | #define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
69184 | #define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
69185 | #define BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
69186 | #define BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
69187 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
69188 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
69189 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
69190 | #define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
69191 | #define BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
69192 | #define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
69193 | #define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
69194 | #define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
69195 | #define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
69196 | #define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
69197 | #define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
69198 | #define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
69199 | #define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
69200 | #define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
69201 | #define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
69202 | #define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
69203 | #define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
69204 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
69205 | #define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
69206 | #define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
69207 | #define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
69208 | #define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
69209 | #define BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
69210 | #define BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
69211 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
69212 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
69213 | #define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
69214 | #define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
69215 | #define BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
69216 | //BIFP2_PCIE_LINK_MANAGEMENT_STATUS |
69217 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
69218 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
69219 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
69220 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
69221 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
69222 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
69223 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
69224 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
69225 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
69226 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
69227 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
69228 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
69229 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
69230 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
69231 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
69232 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
69233 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
69234 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
69235 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
69236 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
69237 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
69238 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
69239 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
69240 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
69241 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
69242 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
69243 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
69244 | #define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
69245 | //BIFP2_PCIE_LINK_MANAGEMENT_MASK |
69246 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
69247 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
69248 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
69249 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
69250 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
69251 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
69252 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
69253 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
69254 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
69255 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
69256 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
69257 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
69258 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
69259 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
69260 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
69261 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
69262 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
69263 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
69264 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
69265 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
69266 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
69267 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
69268 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
69269 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
69270 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
69271 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
69272 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
69273 | #define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
69274 | //BIFP2_PCIE_LINK_MANAGEMENT_CNTL |
69275 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
69276 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
69277 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
69278 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
69279 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
69280 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
69281 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
69282 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
69283 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
69284 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
69285 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
69286 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
69287 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
69288 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
69289 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
69290 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
69291 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
69292 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
69293 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
69294 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
69295 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
69296 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
69297 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
69298 | #define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
69299 | //BIFP2_PCIEP_STRAP_LC |
69300 | #define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
69301 | #define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
69302 | #define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
69303 | #define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
69304 | #define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
69305 | #define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
69306 | #define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
69307 | #define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
69308 | #define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
69309 | #define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
69310 | #define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
69311 | #define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
69312 | #define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
69313 | #define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
69314 | #define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
69315 | #define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
69316 | #define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
69317 | #define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
69318 | #define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
69319 | #define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
69320 | #define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
69321 | #define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
69322 | //BIFP2_PCIEP_STRAP_MISC |
69323 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
69324 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
69325 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
69326 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
69327 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
69328 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
69329 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
69330 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
69331 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
69332 | #define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
69333 | //BIFP2_PCIE_LC_L1_PM_SUBSTATE |
69334 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
69335 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
69336 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
69337 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
69338 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
69339 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
69340 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
69341 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
69342 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
69343 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
69344 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
69345 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
69346 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
69347 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
69348 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
69349 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
69350 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
69351 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
69352 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
69353 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
69354 | //BIFP2_PCIE_LC_L1_PM_SUBSTATE2 |
69355 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
69356 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
69357 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
69358 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
69359 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
69360 | #define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
69361 | //BIFP2_PCIE_LC_PORT_ORDER |
69362 | #define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
69363 | #define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
69364 | //BIFP2_PCIEP_BCH_ECC_CNTL |
69365 | #define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
69366 | #define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
69367 | #define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
69368 | #define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
69369 | #define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
69370 | #define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
69371 | //BIFP2_PCIEP_HPGI_PRIVATE |
69372 | #define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
69373 | #define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
69374 | #define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
69375 | #define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
69376 | //BIFP2_PCIEP_HPGI |
69377 | #define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
69378 | #define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
69379 | #define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
69380 | #define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
69381 | #define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
69382 | #define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
69383 | #define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
69384 | #define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
69385 | #define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
69386 | #define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
69387 | #define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
69388 | #define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
69389 | #define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
69390 | #define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
69391 | #define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
69392 | #define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
69393 | #define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
69394 | #define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
69395 | #define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
69396 | #define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
69397 | #define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
69398 | #define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
69399 | //BIFP2_PCIEP_HCNT_DESCRIPTOR |
69400 | #define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
69401 | #define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
69402 | #define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
69403 | #define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
69404 | //BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK |
69405 | #define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
69406 | #define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
69407 | #define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
69408 | #define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
69409 | |
69410 | |
69411 | // addressBlock: nbio_pcie0_bifp3_pciedir_p |
69412 | //BIFP3_PCIEP_RESERVED |
69413 | #define BIFP3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
69414 | #define BIFP3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
69415 | //BIFP3_PCIEP_SCRATCH |
69416 | #define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
69417 | #define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
69418 | //BIFP3_PCIEP_PORT_CNTL |
69419 | #define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
69420 | #define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
69421 | #define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
69422 | #define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
69423 | #define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
69424 | #define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
69425 | #define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
69426 | #define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
69427 | #define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
69428 | #define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
69429 | #define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
69430 | #define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
69431 | #define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
69432 | #define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
69433 | #define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
69434 | #define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
69435 | #define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
69436 | #define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
69437 | #define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
69438 | #define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
69439 | //BIFP3_PCIE_TX_CNTL |
69440 | #define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
69441 | #define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
69442 | #define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
69443 | #define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
69444 | #define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
69445 | #define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
69446 | #define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
69447 | #define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
69448 | #define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
69449 | #define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
69450 | #define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
69451 | #define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
69452 | #define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
69453 | #define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
69454 | #define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
69455 | #define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
69456 | //BIFP3_PCIE_TX_REQUESTER_ID |
69457 | #define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
69458 | #define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
69459 | #define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
69460 | #define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
69461 | #define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
69462 | #define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
69463 | //BIFP3_PCIE_TX_VENDOR_SPECIFIC |
69464 | #define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
69465 | #define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
69466 | //BIFP3_PCIE_TX_REQUEST_NUM_CNTL |
69467 | #define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
69468 | #define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
69469 | #define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
69470 | #define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
69471 | #define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
69472 | #define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
69473 | //BIFP3_PCIE_TX_SEQ |
69474 | #define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
69475 | #define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
69476 | #define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
69477 | #define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
69478 | //BIFP3_PCIE_TX_REPLAY |
69479 | #define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
69480 | #define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
69481 | #define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
69482 | #define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
69483 | #define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
69484 | #define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
69485 | //BIFP3_PCIE_TX_ACK_LATENCY_LIMIT |
69486 | #define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
69487 | #define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
69488 | #define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
69489 | #define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
69490 | //BIFP3_PCIE_TX_CREDITS_ADVT_P |
69491 | #define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
69492 | #define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
69493 | #define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
69494 | #define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
69495 | //BIFP3_PCIE_TX_CREDITS_ADVT_NP |
69496 | #define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
69497 | #define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
69498 | #define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
69499 | #define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
69500 | //BIFP3_PCIE_TX_CREDITS_ADVT_CPL |
69501 | #define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
69502 | #define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
69503 | #define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
69504 | #define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
69505 | //BIFP3_PCIE_TX_CREDITS_INIT_P |
69506 | #define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
69507 | #define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
69508 | #define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
69509 | #define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
69510 | //BIFP3_PCIE_TX_CREDITS_INIT_NP |
69511 | #define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
69512 | #define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
69513 | #define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
69514 | #define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
69515 | //BIFP3_PCIE_TX_CREDITS_INIT_CPL |
69516 | #define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
69517 | #define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
69518 | #define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
69519 | #define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
69520 | //BIFP3_PCIE_TX_CREDITS_STATUS |
69521 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
69522 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
69523 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
69524 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
69525 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
69526 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
69527 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
69528 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
69529 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
69530 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
69531 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
69532 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
69533 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
69534 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
69535 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
69536 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
69537 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
69538 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
69539 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
69540 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
69541 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
69542 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
69543 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
69544 | #define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
69545 | //BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD |
69546 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
69547 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
69548 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
69549 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
69550 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
69551 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
69552 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
69553 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
69554 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
69555 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
69556 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
69557 | #define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
69558 | //BIFP3_PCIE_P_PORT_LANE_STATUS |
69559 | #define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
69560 | #define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
69561 | #define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
69562 | #define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
69563 | //BIFP3_PCIE_FC_P |
69564 | #define BIFP3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
69565 | #define BIFP3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
69566 | #define BIFP3_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
69567 | #define BIFP3_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
69568 | //BIFP3_PCIE_FC_NP |
69569 | #define BIFP3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
69570 | #define BIFP3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
69571 | #define BIFP3_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
69572 | #define BIFP3_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
69573 | //BIFP3_PCIE_FC_CPL |
69574 | #define BIFP3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
69575 | #define BIFP3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
69576 | #define BIFP3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
69577 | #define BIFP3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
69578 | //BIFP3_PCIE_ERR_CNTL |
69579 | #define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
69580 | #define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
69581 | #define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
69582 | #define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
69583 | #define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
69584 | #define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
69585 | #define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
69586 | #define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
69587 | #define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
69588 | #define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
69589 | #define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
69590 | #define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
69591 | #define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
69592 | #define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
69593 | #define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
69594 | #define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
69595 | #define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
69596 | #define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
69597 | #define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
69598 | #define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
69599 | #define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
69600 | #define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
69601 | #define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
69602 | #define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
69603 | #define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
69604 | #define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
69605 | #define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
69606 | #define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
69607 | //BIFP3_PCIE_RX_CNTL |
69608 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
69609 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
69610 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
69611 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
69612 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
69613 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
69614 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
69615 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
69616 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
69617 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
69618 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
69619 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
69620 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
69621 | #define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
69622 | #define BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
69623 | #define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
69624 | #define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
69625 | #define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
69626 | #define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
69627 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
69628 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
69629 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
69630 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
69631 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
69632 | #define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
69633 | #define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
69634 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
69635 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
69636 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
69637 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
69638 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
69639 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
69640 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
69641 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
69642 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
69643 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
69644 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
69645 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
69646 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
69647 | #define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
69648 | #define BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
69649 | #define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
69650 | #define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
69651 | #define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
69652 | #define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
69653 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
69654 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
69655 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
69656 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
69657 | #define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
69658 | #define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
69659 | #define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
69660 | //BIFP3_PCIE_RX_EXPECTED_SEQNUM |
69661 | #define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
69662 | #define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
69663 | //BIFP3_PCIE_RX_VENDOR_SPECIFIC |
69664 | #define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
69665 | #define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
69666 | #define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
69667 | #define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
69668 | //BIFP3_PCIE_RX_CNTL3 |
69669 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
69670 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
69671 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
69672 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
69673 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
69674 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
69675 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
69676 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
69677 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
69678 | #define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
69679 | //BIFP3_PCIE_RX_CREDITS_ALLOCATED_P |
69680 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
69681 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
69682 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
69683 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
69684 | //BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP |
69685 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
69686 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
69687 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
69688 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
69689 | //BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL |
69690 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
69691 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
69692 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
69693 | #define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
69694 | //BIFP3_PCIEP_ERROR_INJECT_PHYSICAL |
69695 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
69696 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
69697 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
69698 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
69699 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
69700 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
69701 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
69702 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
69703 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
69704 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
69705 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
69706 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
69707 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
69708 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
69709 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
69710 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
69711 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
69712 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
69713 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
69714 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
69715 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
69716 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
69717 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
69718 | #define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
69719 | //BIFP3_PCIEP_ERROR_INJECT_TRANSACTION |
69720 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
69721 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
69722 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
69723 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
69724 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
69725 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
69726 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
69727 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
69728 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
69729 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
69730 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
69731 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
69732 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
69733 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
69734 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
69735 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
69736 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
69737 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
69738 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
69739 | #define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
69740 | //BIFP3_PCIEP_NAK_COUNTER |
69741 | #define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
69742 | #define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
69743 | #define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
69744 | #define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
69745 | //BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
69746 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
69747 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
69748 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
69749 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
69750 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
69751 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
69752 | //BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
69753 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
69754 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
69755 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
69756 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
69757 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
69758 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
69759 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
69760 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
69761 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
69762 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
69763 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
69764 | #define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
69765 | //BIFP3_PCIE_LC_CNTL |
69766 | #define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
69767 | #define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
69768 | #define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
69769 | #define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
69770 | #define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
69771 | #define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
69772 | #define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
69773 | #define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
69774 | #define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
69775 | #define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
69776 | #define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
69777 | #define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
69778 | #define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
69779 | #define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
69780 | #define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
69781 | #define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
69782 | #define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
69783 | #define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
69784 | #define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
69785 | #define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
69786 | #define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
69787 | #define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
69788 | #define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
69789 | #define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
69790 | #define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
69791 | #define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
69792 | #define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
69793 | #define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
69794 | #define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
69795 | #define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
69796 | #define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
69797 | #define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
69798 | #define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
69799 | #define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
69800 | #define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
69801 | #define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
69802 | #define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
69803 | #define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
69804 | #define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
69805 | #define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
69806 | //BIFP3_PCIE_LC_TRAINING_CNTL |
69807 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
69808 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
69809 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
69810 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
69811 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
69812 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
69813 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
69814 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
69815 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
69816 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
69817 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
69818 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
69819 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
69820 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
69821 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
69822 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
69823 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
69824 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
69825 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
69826 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
69827 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
69828 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
69829 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
69830 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
69831 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
69832 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
69833 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
69834 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
69835 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
69836 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
69837 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
69838 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
69839 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
69840 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
69841 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
69842 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
69843 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
69844 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
69845 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
69846 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
69847 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
69848 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
69849 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
69850 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
69851 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
69852 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
69853 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
69854 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
69855 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
69856 | #define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
69857 | //BIFP3_PCIE_LC_LINK_WIDTH_CNTL |
69858 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
69859 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
69860 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
69861 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
69862 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
69863 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
69864 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
69865 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
69866 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
69867 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
69868 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
69869 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
69870 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
69871 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
69872 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
69873 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
69874 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
69875 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
69876 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
69877 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
69878 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
69879 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
69880 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
69881 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
69882 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
69883 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
69884 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
69885 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
69886 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
69887 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
69888 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
69889 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
69890 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
69891 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
69892 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
69893 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
69894 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
69895 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
69896 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
69897 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
69898 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
69899 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
69900 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
69901 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
69902 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
69903 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
69904 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
69905 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
69906 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
69907 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
69908 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
69909 | #define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
69910 | //BIFP3_PCIE_LC_N_FTS_CNTL |
69911 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
69912 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
69913 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
69914 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
69915 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
69916 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
69917 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
69918 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
69919 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
69920 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
69921 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
69922 | #define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
69923 | //BIFP3_PCIE_LC_SPEED_CNTL |
69924 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
69925 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
69926 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
69927 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
69928 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
69929 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
69930 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
69931 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
69932 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
69933 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
69934 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
69935 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
69936 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
69937 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
69938 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
69939 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
69940 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
69941 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
69942 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
69943 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
69944 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
69945 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
69946 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
69947 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
69948 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
69949 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
69950 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
69951 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
69952 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
69953 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
69954 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
69955 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
69956 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
69957 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
69958 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
69959 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
69960 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
69961 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
69962 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
69963 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
69964 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
69965 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
69966 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
69967 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
69968 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
69969 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
69970 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
69971 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
69972 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
69973 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
69974 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
69975 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
69976 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
69977 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
69978 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
69979 | #define BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
69980 | //BIFP3_PCIE_LC_STATE0 |
69981 | #define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
69982 | #define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
69983 | #define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
69984 | #define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
69985 | #define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
69986 | #define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
69987 | #define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
69988 | #define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
69989 | //BIFP3_PCIE_LC_STATE1 |
69990 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
69991 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
69992 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
69993 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
69994 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
69995 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
69996 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
69997 | #define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
69998 | //BIFP3_PCIE_LC_STATE2 |
69999 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
70000 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
70001 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
70002 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
70003 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
70004 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
70005 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
70006 | #define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
70007 | //BIFP3_PCIE_LC_STATE3 |
70008 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
70009 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
70010 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
70011 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
70012 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
70013 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
70014 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
70015 | #define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
70016 | //BIFP3_PCIE_LC_STATE4 |
70017 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
70018 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
70019 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
70020 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
70021 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
70022 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
70023 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
70024 | #define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
70025 | //BIFP3_PCIE_LC_STATE5 |
70026 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
70027 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
70028 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
70029 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
70030 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
70031 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
70032 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
70033 | #define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
70034 | //BIFP3_PCIE_LINK_MANAGEMENT_CNTL2 |
70035 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
70036 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
70037 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
70038 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
70039 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
70040 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
70041 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
70042 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
70043 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
70044 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
70045 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
70046 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
70047 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
70048 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
70049 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
70050 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
70051 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
70052 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
70053 | //BIFP3_PCIE_LC_CNTL2 |
70054 | #define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
70055 | #define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
70056 | #define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
70057 | #define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
70058 | #define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
70059 | #define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
70060 | #define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
70061 | #define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
70062 | #define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
70063 | #define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
70064 | #define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
70065 | #define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
70066 | #define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
70067 | #define BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
70068 | #define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
70069 | #define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
70070 | #define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
70071 | #define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
70072 | #define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
70073 | #define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
70074 | #define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
70075 | #define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
70076 | #define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
70077 | #define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
70078 | #define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
70079 | #define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
70080 | #define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
70081 | #define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
70082 | #define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
70083 | #define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
70084 | #define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
70085 | #define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
70086 | #define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
70087 | #define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
70088 | #define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
70089 | #define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
70090 | #define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
70091 | #define BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
70092 | #define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
70093 | #define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
70094 | #define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
70095 | #define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
70096 | #define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
70097 | #define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
70098 | #define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
70099 | #define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
70100 | #define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
70101 | #define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
70102 | //BIFP3_PCIE_LC_BW_CHANGE_CNTL |
70103 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
70104 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
70105 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
70106 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
70107 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
70108 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
70109 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
70110 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
70111 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
70112 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
70113 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
70114 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
70115 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
70116 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
70117 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
70118 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
70119 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
70120 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
70121 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
70122 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
70123 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
70124 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
70125 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
70126 | #define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
70127 | //BIFP3_PCIE_LC_CDR_CNTL |
70128 | #define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
70129 | #define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
70130 | #define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
70131 | #define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
70132 | #define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
70133 | #define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
70134 | //BIFP3_PCIE_LC_LANE_CNTL |
70135 | #define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
70136 | #define BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
70137 | #define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
70138 | #define BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
70139 | //BIFP3_PCIE_LC_CNTL3 |
70140 | #define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
70141 | #define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
70142 | #define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
70143 | #define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
70144 | #define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
70145 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
70146 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
70147 | #define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
70148 | #define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
70149 | #define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
70150 | #define BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
70151 | #define BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
70152 | #define BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
70153 | #define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
70154 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
70155 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
70156 | #define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
70157 | #define BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
70158 | #define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
70159 | #define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
70160 | #define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
70161 | #define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
70162 | #define BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
70163 | #define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
70164 | #define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
70165 | #define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
70166 | #define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
70167 | #define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
70168 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
70169 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
70170 | #define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
70171 | #define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
70172 | #define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
70173 | #define BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
70174 | #define BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
70175 | #define BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
70176 | #define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
70177 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
70178 | #define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
70179 | #define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
70180 | #define BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
70181 | #define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
70182 | #define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
70183 | #define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
70184 | #define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
70185 | #define BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
70186 | //BIFP3_PCIE_LC_CNTL4 |
70187 | #define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
70188 | #define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
70189 | #define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
70190 | #define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
70191 | #define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
70192 | #define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
70193 | #define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
70194 | #define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
70195 | #define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
70196 | #define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
70197 | #define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
70198 | #define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
70199 | #define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
70200 | #define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
70201 | #define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
70202 | #define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
70203 | #define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
70204 | #define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
70205 | #define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
70206 | #define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
70207 | #define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
70208 | #define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
70209 | #define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
70210 | #define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
70211 | #define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
70212 | #define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
70213 | #define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
70214 | #define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
70215 | #define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
70216 | #define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
70217 | #define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
70218 | #define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
70219 | #define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
70220 | #define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
70221 | #define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
70222 | #define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
70223 | #define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
70224 | #define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
70225 | #define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
70226 | #define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
70227 | #define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
70228 | #define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
70229 | #define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
70230 | #define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
70231 | //BIFP3_PCIE_LC_CNTL5 |
70232 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
70233 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
70234 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
70235 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
70236 | #define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
70237 | #define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
70238 | #define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
70239 | #define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
70240 | #define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
70241 | #define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
70242 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
70243 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
70244 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
70245 | #define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
70246 | #define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
70247 | #define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
70248 | #define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
70249 | #define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
70250 | #define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
70251 | #define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
70252 | //BIFP3_PCIE_LC_FORCE_COEFF |
70253 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
70254 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
70255 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
70256 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
70257 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
70258 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
70259 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
70260 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
70261 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
70262 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
70263 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
70264 | #define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
70265 | //BIFP3_PCIE_LC_BEST_EQ_SETTINGS |
70266 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
70267 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
70268 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
70269 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
70270 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
70271 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
70272 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
70273 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
70274 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
70275 | #define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
70276 | //BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF |
70277 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
70278 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
70279 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
70280 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
70281 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
70282 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
70283 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
70284 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
70285 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
70286 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
70287 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
70288 | #define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
70289 | //BIFP3_PCIE_LC_CNTL6 |
70290 | #define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
70291 | #define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
70292 | #define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
70293 | #define BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
70294 | #define BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
70295 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
70296 | #define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
70297 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
70298 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
70299 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
70300 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
70301 | #define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
70302 | #define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
70303 | #define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
70304 | #define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
70305 | #define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
70306 | #define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
70307 | #define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
70308 | #define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
70309 | #define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
70310 | #define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
70311 | #define BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
70312 | #define BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
70313 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
70314 | #define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
70315 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
70316 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
70317 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
70318 | #define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
70319 | #define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
70320 | #define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
70321 | #define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
70322 | #define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
70323 | #define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
70324 | #define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
70325 | #define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
70326 | //BIFP3_PCIE_LC_CNTL7 |
70327 | #define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
70328 | #define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
70329 | #define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
70330 | #define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
70331 | #define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
70332 | #define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
70333 | #define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
70334 | #define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
70335 | #define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
70336 | #define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
70337 | #define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
70338 | #define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
70339 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
70340 | #define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
70341 | #define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
70342 | #define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
70343 | #define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
70344 | #define BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
70345 | #define BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
70346 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
70347 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
70348 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
70349 | #define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
70350 | #define BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
70351 | #define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
70352 | #define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
70353 | #define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
70354 | #define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
70355 | #define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
70356 | #define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
70357 | #define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
70358 | #define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
70359 | #define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
70360 | #define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
70361 | #define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
70362 | #define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
70363 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
70364 | #define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
70365 | #define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
70366 | #define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
70367 | #define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
70368 | #define BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
70369 | #define BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
70370 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
70371 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
70372 | #define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
70373 | #define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
70374 | #define BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
70375 | //BIFP3_PCIE_LINK_MANAGEMENT_STATUS |
70376 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
70377 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
70378 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
70379 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
70380 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
70381 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
70382 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
70383 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
70384 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
70385 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
70386 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
70387 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
70388 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
70389 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
70390 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
70391 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
70392 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
70393 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
70394 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
70395 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
70396 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
70397 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
70398 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
70399 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
70400 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
70401 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
70402 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
70403 | #define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
70404 | //BIFP3_PCIE_LINK_MANAGEMENT_MASK |
70405 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
70406 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
70407 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
70408 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
70409 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
70410 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
70411 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
70412 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
70413 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
70414 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
70415 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
70416 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
70417 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
70418 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
70419 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
70420 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
70421 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
70422 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
70423 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
70424 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
70425 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
70426 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
70427 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
70428 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
70429 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
70430 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
70431 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
70432 | #define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
70433 | //BIFP3_PCIE_LINK_MANAGEMENT_CNTL |
70434 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
70435 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
70436 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
70437 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
70438 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
70439 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
70440 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
70441 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
70442 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
70443 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
70444 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
70445 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
70446 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
70447 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
70448 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
70449 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
70450 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
70451 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
70452 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
70453 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
70454 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
70455 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
70456 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
70457 | #define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
70458 | //BIFP3_PCIEP_STRAP_LC |
70459 | #define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
70460 | #define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
70461 | #define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
70462 | #define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
70463 | #define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
70464 | #define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
70465 | #define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
70466 | #define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
70467 | #define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
70468 | #define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
70469 | #define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
70470 | #define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
70471 | #define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
70472 | #define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
70473 | #define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
70474 | #define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
70475 | #define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
70476 | #define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
70477 | #define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
70478 | #define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
70479 | #define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
70480 | #define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
70481 | //BIFP3_PCIEP_STRAP_MISC |
70482 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
70483 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
70484 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
70485 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
70486 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
70487 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
70488 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
70489 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
70490 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
70491 | #define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
70492 | //BIFP3_PCIE_LC_L1_PM_SUBSTATE |
70493 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
70494 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
70495 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
70496 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
70497 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
70498 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
70499 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
70500 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
70501 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
70502 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
70503 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
70504 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
70505 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
70506 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
70507 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
70508 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
70509 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
70510 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
70511 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
70512 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
70513 | //BIFP3_PCIE_LC_L1_PM_SUBSTATE2 |
70514 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
70515 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
70516 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
70517 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
70518 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
70519 | #define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
70520 | //BIFP3_PCIE_LC_PORT_ORDER |
70521 | #define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
70522 | #define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
70523 | //BIFP3_PCIEP_BCH_ECC_CNTL |
70524 | #define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
70525 | #define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
70526 | #define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
70527 | #define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
70528 | #define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
70529 | #define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
70530 | //BIFP3_PCIEP_HPGI_PRIVATE |
70531 | #define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
70532 | #define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
70533 | #define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
70534 | #define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
70535 | //BIFP3_PCIEP_HPGI |
70536 | #define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
70537 | #define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
70538 | #define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
70539 | #define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
70540 | #define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
70541 | #define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
70542 | #define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
70543 | #define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
70544 | #define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
70545 | #define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
70546 | #define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
70547 | #define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
70548 | #define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
70549 | #define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
70550 | #define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
70551 | #define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
70552 | #define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
70553 | #define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
70554 | #define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
70555 | #define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
70556 | #define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
70557 | #define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
70558 | //BIFP3_PCIEP_HCNT_DESCRIPTOR |
70559 | #define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
70560 | #define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
70561 | #define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
70562 | #define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
70563 | //BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK |
70564 | #define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
70565 | #define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
70566 | #define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
70567 | #define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
70568 | |
70569 | |
70570 | // addressBlock: nbio_pcie0_bifp4_pciedir_p |
70571 | //BIFP4_PCIEP_RESERVED |
70572 | #define BIFP4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
70573 | #define BIFP4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
70574 | //BIFP4_PCIEP_SCRATCH |
70575 | #define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
70576 | #define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
70577 | //BIFP4_PCIEP_PORT_CNTL |
70578 | #define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
70579 | #define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
70580 | #define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
70581 | #define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
70582 | #define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
70583 | #define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
70584 | #define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
70585 | #define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
70586 | #define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
70587 | #define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
70588 | #define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
70589 | #define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
70590 | #define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
70591 | #define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
70592 | #define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
70593 | #define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
70594 | #define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
70595 | #define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
70596 | #define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
70597 | #define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
70598 | //BIFP4_PCIE_TX_CNTL |
70599 | #define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
70600 | #define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
70601 | #define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
70602 | #define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
70603 | #define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
70604 | #define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
70605 | #define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
70606 | #define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
70607 | #define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
70608 | #define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
70609 | #define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
70610 | #define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
70611 | #define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
70612 | #define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
70613 | #define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
70614 | #define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
70615 | //BIFP4_PCIE_TX_REQUESTER_ID |
70616 | #define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
70617 | #define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
70618 | #define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
70619 | #define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
70620 | #define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
70621 | #define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
70622 | //BIFP4_PCIE_TX_VENDOR_SPECIFIC |
70623 | #define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
70624 | #define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
70625 | //BIFP4_PCIE_TX_REQUEST_NUM_CNTL |
70626 | #define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
70627 | #define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
70628 | #define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
70629 | #define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
70630 | #define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
70631 | #define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
70632 | //BIFP4_PCIE_TX_SEQ |
70633 | #define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
70634 | #define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
70635 | #define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
70636 | #define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
70637 | //BIFP4_PCIE_TX_REPLAY |
70638 | #define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
70639 | #define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
70640 | #define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
70641 | #define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
70642 | #define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
70643 | #define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
70644 | //BIFP4_PCIE_TX_ACK_LATENCY_LIMIT |
70645 | #define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
70646 | #define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
70647 | #define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
70648 | #define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
70649 | //BIFP4_PCIE_TX_CREDITS_ADVT_P |
70650 | #define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
70651 | #define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
70652 | #define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
70653 | #define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
70654 | //BIFP4_PCIE_TX_CREDITS_ADVT_NP |
70655 | #define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
70656 | #define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
70657 | #define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
70658 | #define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
70659 | //BIFP4_PCIE_TX_CREDITS_ADVT_CPL |
70660 | #define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
70661 | #define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
70662 | #define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
70663 | #define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
70664 | //BIFP4_PCIE_TX_CREDITS_INIT_P |
70665 | #define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
70666 | #define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
70667 | #define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
70668 | #define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
70669 | //BIFP4_PCIE_TX_CREDITS_INIT_NP |
70670 | #define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
70671 | #define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
70672 | #define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
70673 | #define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
70674 | //BIFP4_PCIE_TX_CREDITS_INIT_CPL |
70675 | #define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
70676 | #define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
70677 | #define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
70678 | #define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
70679 | //BIFP4_PCIE_TX_CREDITS_STATUS |
70680 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
70681 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
70682 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
70683 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
70684 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
70685 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
70686 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
70687 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
70688 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
70689 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
70690 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
70691 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
70692 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
70693 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
70694 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
70695 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
70696 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
70697 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
70698 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
70699 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
70700 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
70701 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
70702 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
70703 | #define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
70704 | //BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD |
70705 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
70706 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
70707 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
70708 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
70709 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
70710 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
70711 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
70712 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
70713 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
70714 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
70715 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
70716 | #define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
70717 | //BIFP4_PCIE_P_PORT_LANE_STATUS |
70718 | #define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
70719 | #define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
70720 | #define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
70721 | #define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
70722 | //BIFP4_PCIE_FC_P |
70723 | #define BIFP4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
70724 | #define BIFP4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
70725 | #define BIFP4_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
70726 | #define BIFP4_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
70727 | //BIFP4_PCIE_FC_NP |
70728 | #define BIFP4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
70729 | #define BIFP4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
70730 | #define BIFP4_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
70731 | #define BIFP4_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
70732 | //BIFP4_PCIE_FC_CPL |
70733 | #define BIFP4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
70734 | #define BIFP4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
70735 | #define BIFP4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
70736 | #define BIFP4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
70737 | //BIFP4_PCIE_ERR_CNTL |
70738 | #define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
70739 | #define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
70740 | #define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
70741 | #define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
70742 | #define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
70743 | #define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
70744 | #define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
70745 | #define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
70746 | #define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
70747 | #define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
70748 | #define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
70749 | #define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
70750 | #define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
70751 | #define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
70752 | #define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
70753 | #define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
70754 | #define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
70755 | #define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
70756 | #define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
70757 | #define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
70758 | #define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
70759 | #define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
70760 | #define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
70761 | #define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
70762 | #define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
70763 | #define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
70764 | #define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
70765 | #define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
70766 | //BIFP4_PCIE_RX_CNTL |
70767 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
70768 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
70769 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
70770 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
70771 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
70772 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
70773 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
70774 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
70775 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
70776 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
70777 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
70778 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
70779 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
70780 | #define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
70781 | #define BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
70782 | #define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
70783 | #define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
70784 | #define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
70785 | #define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
70786 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
70787 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
70788 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
70789 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
70790 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
70791 | #define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
70792 | #define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
70793 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
70794 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
70795 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
70796 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
70797 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
70798 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
70799 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
70800 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
70801 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
70802 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
70803 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
70804 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
70805 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
70806 | #define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
70807 | #define BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
70808 | #define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
70809 | #define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
70810 | #define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
70811 | #define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
70812 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
70813 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
70814 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
70815 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
70816 | #define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
70817 | #define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
70818 | #define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
70819 | //BIFP4_PCIE_RX_EXPECTED_SEQNUM |
70820 | #define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
70821 | #define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
70822 | //BIFP4_PCIE_RX_VENDOR_SPECIFIC |
70823 | #define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
70824 | #define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
70825 | #define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
70826 | #define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
70827 | //BIFP4_PCIE_RX_CNTL3 |
70828 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
70829 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
70830 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
70831 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
70832 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
70833 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
70834 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
70835 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
70836 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
70837 | #define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
70838 | //BIFP4_PCIE_RX_CREDITS_ALLOCATED_P |
70839 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
70840 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
70841 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
70842 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
70843 | //BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP |
70844 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
70845 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
70846 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
70847 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
70848 | //BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL |
70849 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
70850 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
70851 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
70852 | #define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
70853 | //BIFP4_PCIEP_ERROR_INJECT_PHYSICAL |
70854 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
70855 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
70856 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
70857 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
70858 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
70859 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
70860 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
70861 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
70862 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
70863 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
70864 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
70865 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
70866 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
70867 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
70868 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
70869 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
70870 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
70871 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
70872 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
70873 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
70874 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
70875 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
70876 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
70877 | #define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
70878 | //BIFP4_PCIEP_ERROR_INJECT_TRANSACTION |
70879 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
70880 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
70881 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
70882 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
70883 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
70884 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
70885 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
70886 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
70887 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
70888 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
70889 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
70890 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
70891 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
70892 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
70893 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
70894 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
70895 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
70896 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
70897 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
70898 | #define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
70899 | //BIFP4_PCIEP_NAK_COUNTER |
70900 | #define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
70901 | #define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
70902 | #define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
70903 | #define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
70904 | //BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
70905 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
70906 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
70907 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
70908 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
70909 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
70910 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
70911 | //BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
70912 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
70913 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
70914 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
70915 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
70916 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
70917 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
70918 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
70919 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
70920 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
70921 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
70922 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
70923 | #define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
70924 | //BIFP4_PCIE_LC_CNTL |
70925 | #define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
70926 | #define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
70927 | #define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
70928 | #define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
70929 | #define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
70930 | #define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
70931 | #define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
70932 | #define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
70933 | #define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
70934 | #define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
70935 | #define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
70936 | #define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
70937 | #define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
70938 | #define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
70939 | #define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
70940 | #define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
70941 | #define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
70942 | #define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
70943 | #define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
70944 | #define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
70945 | #define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
70946 | #define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
70947 | #define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
70948 | #define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
70949 | #define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
70950 | #define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
70951 | #define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
70952 | #define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
70953 | #define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
70954 | #define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
70955 | #define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
70956 | #define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
70957 | #define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
70958 | #define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
70959 | #define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
70960 | #define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
70961 | #define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
70962 | #define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
70963 | #define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
70964 | #define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
70965 | //BIFP4_PCIE_LC_TRAINING_CNTL |
70966 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
70967 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
70968 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
70969 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
70970 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
70971 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
70972 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
70973 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
70974 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
70975 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
70976 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
70977 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
70978 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
70979 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
70980 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
70981 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
70982 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
70983 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
70984 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
70985 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
70986 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
70987 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
70988 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
70989 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
70990 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
70991 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
70992 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
70993 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
70994 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
70995 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
70996 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
70997 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
70998 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
70999 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
71000 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
71001 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
71002 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
71003 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
71004 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
71005 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
71006 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
71007 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
71008 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
71009 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
71010 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
71011 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
71012 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
71013 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
71014 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
71015 | #define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
71016 | //BIFP4_PCIE_LC_LINK_WIDTH_CNTL |
71017 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
71018 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
71019 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
71020 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
71021 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
71022 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
71023 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
71024 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
71025 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
71026 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
71027 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
71028 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
71029 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
71030 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
71031 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
71032 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
71033 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
71034 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
71035 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
71036 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
71037 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
71038 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
71039 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
71040 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
71041 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
71042 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
71043 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
71044 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
71045 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
71046 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
71047 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
71048 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
71049 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
71050 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
71051 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
71052 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
71053 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
71054 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
71055 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
71056 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
71057 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
71058 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
71059 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
71060 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
71061 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
71062 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
71063 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
71064 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
71065 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
71066 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
71067 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
71068 | #define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
71069 | //BIFP4_PCIE_LC_N_FTS_CNTL |
71070 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
71071 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
71072 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
71073 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
71074 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
71075 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
71076 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
71077 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
71078 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
71079 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
71080 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
71081 | #define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
71082 | //BIFP4_PCIE_LC_SPEED_CNTL |
71083 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
71084 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
71085 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
71086 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
71087 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
71088 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
71089 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
71090 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
71091 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
71092 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
71093 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
71094 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
71095 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
71096 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
71097 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
71098 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
71099 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
71100 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
71101 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
71102 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
71103 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
71104 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
71105 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
71106 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
71107 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
71108 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
71109 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
71110 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
71111 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
71112 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
71113 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
71114 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
71115 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
71116 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
71117 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
71118 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
71119 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
71120 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
71121 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
71122 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
71123 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
71124 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
71125 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
71126 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
71127 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
71128 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
71129 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
71130 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
71131 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
71132 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
71133 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
71134 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
71135 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
71136 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
71137 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
71138 | #define BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
71139 | //BIFP4_PCIE_LC_STATE0 |
71140 | #define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
71141 | #define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
71142 | #define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
71143 | #define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
71144 | #define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
71145 | #define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
71146 | #define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
71147 | #define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
71148 | //BIFP4_PCIE_LC_STATE1 |
71149 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
71150 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
71151 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
71152 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
71153 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
71154 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
71155 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
71156 | #define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
71157 | //BIFP4_PCIE_LC_STATE2 |
71158 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
71159 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
71160 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
71161 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
71162 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
71163 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
71164 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
71165 | #define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
71166 | //BIFP4_PCIE_LC_STATE3 |
71167 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
71168 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
71169 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
71170 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
71171 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
71172 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
71173 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
71174 | #define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
71175 | //BIFP4_PCIE_LC_STATE4 |
71176 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
71177 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
71178 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
71179 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
71180 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
71181 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
71182 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
71183 | #define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
71184 | //BIFP4_PCIE_LC_STATE5 |
71185 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
71186 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
71187 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
71188 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
71189 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
71190 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
71191 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
71192 | #define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
71193 | //BIFP4_PCIE_LINK_MANAGEMENT_CNTL2 |
71194 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
71195 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
71196 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
71197 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
71198 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
71199 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
71200 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
71201 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
71202 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
71203 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
71204 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
71205 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
71206 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
71207 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
71208 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
71209 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
71210 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
71211 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
71212 | //BIFP4_PCIE_LC_CNTL2 |
71213 | #define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
71214 | #define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
71215 | #define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
71216 | #define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
71217 | #define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
71218 | #define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
71219 | #define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
71220 | #define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
71221 | #define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
71222 | #define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
71223 | #define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
71224 | #define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
71225 | #define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
71226 | #define BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
71227 | #define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
71228 | #define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
71229 | #define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
71230 | #define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
71231 | #define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
71232 | #define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
71233 | #define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
71234 | #define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
71235 | #define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
71236 | #define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
71237 | #define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
71238 | #define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
71239 | #define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
71240 | #define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
71241 | #define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
71242 | #define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
71243 | #define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
71244 | #define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
71245 | #define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
71246 | #define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
71247 | #define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
71248 | #define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
71249 | #define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
71250 | #define BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
71251 | #define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
71252 | #define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
71253 | #define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
71254 | #define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
71255 | #define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
71256 | #define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
71257 | #define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
71258 | #define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
71259 | #define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
71260 | #define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
71261 | //BIFP4_PCIE_LC_BW_CHANGE_CNTL |
71262 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
71263 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
71264 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
71265 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
71266 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
71267 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
71268 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
71269 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
71270 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
71271 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
71272 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
71273 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
71274 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
71275 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
71276 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
71277 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
71278 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
71279 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
71280 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
71281 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
71282 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
71283 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
71284 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
71285 | #define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
71286 | //BIFP4_PCIE_LC_CDR_CNTL |
71287 | #define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
71288 | #define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
71289 | #define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
71290 | #define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
71291 | #define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
71292 | #define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
71293 | //BIFP4_PCIE_LC_LANE_CNTL |
71294 | #define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
71295 | #define BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
71296 | #define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
71297 | #define BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
71298 | //BIFP4_PCIE_LC_CNTL3 |
71299 | #define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
71300 | #define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
71301 | #define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
71302 | #define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
71303 | #define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
71304 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
71305 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
71306 | #define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
71307 | #define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
71308 | #define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
71309 | #define BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
71310 | #define BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
71311 | #define BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
71312 | #define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
71313 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
71314 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
71315 | #define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
71316 | #define BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
71317 | #define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
71318 | #define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
71319 | #define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
71320 | #define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
71321 | #define BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
71322 | #define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
71323 | #define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
71324 | #define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
71325 | #define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
71326 | #define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
71327 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
71328 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
71329 | #define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
71330 | #define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
71331 | #define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
71332 | #define BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
71333 | #define BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
71334 | #define BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
71335 | #define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
71336 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
71337 | #define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
71338 | #define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
71339 | #define BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
71340 | #define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
71341 | #define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
71342 | #define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
71343 | #define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
71344 | #define BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
71345 | //BIFP4_PCIE_LC_CNTL4 |
71346 | #define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
71347 | #define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
71348 | #define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
71349 | #define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
71350 | #define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
71351 | #define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
71352 | #define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
71353 | #define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
71354 | #define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
71355 | #define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
71356 | #define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
71357 | #define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
71358 | #define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
71359 | #define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
71360 | #define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
71361 | #define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
71362 | #define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
71363 | #define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
71364 | #define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
71365 | #define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
71366 | #define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
71367 | #define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
71368 | #define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
71369 | #define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
71370 | #define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
71371 | #define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
71372 | #define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
71373 | #define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
71374 | #define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
71375 | #define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
71376 | #define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
71377 | #define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
71378 | #define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
71379 | #define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
71380 | #define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
71381 | #define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
71382 | #define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
71383 | #define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
71384 | #define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
71385 | #define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
71386 | #define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
71387 | #define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
71388 | #define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
71389 | #define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
71390 | //BIFP4_PCIE_LC_CNTL5 |
71391 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
71392 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
71393 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
71394 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
71395 | #define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
71396 | #define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
71397 | #define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
71398 | #define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
71399 | #define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
71400 | #define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
71401 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
71402 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
71403 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
71404 | #define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
71405 | #define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
71406 | #define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
71407 | #define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
71408 | #define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
71409 | #define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
71410 | #define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
71411 | //BIFP4_PCIE_LC_FORCE_COEFF |
71412 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
71413 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
71414 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
71415 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
71416 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
71417 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
71418 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
71419 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
71420 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
71421 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
71422 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
71423 | #define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
71424 | //BIFP4_PCIE_LC_BEST_EQ_SETTINGS |
71425 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
71426 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
71427 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
71428 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
71429 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
71430 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
71431 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
71432 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
71433 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
71434 | #define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
71435 | //BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF |
71436 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
71437 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
71438 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
71439 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
71440 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
71441 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
71442 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
71443 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
71444 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
71445 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
71446 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
71447 | #define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
71448 | //BIFP4_PCIE_LC_CNTL6 |
71449 | #define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
71450 | #define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
71451 | #define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
71452 | #define BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
71453 | #define BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
71454 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
71455 | #define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
71456 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
71457 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
71458 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
71459 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
71460 | #define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
71461 | #define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
71462 | #define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
71463 | #define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
71464 | #define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
71465 | #define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
71466 | #define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
71467 | #define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
71468 | #define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
71469 | #define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
71470 | #define BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
71471 | #define BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
71472 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
71473 | #define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
71474 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
71475 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
71476 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
71477 | #define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
71478 | #define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
71479 | #define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
71480 | #define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
71481 | #define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
71482 | #define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
71483 | #define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
71484 | #define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
71485 | //BIFP4_PCIE_LC_CNTL7 |
71486 | #define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
71487 | #define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
71488 | #define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
71489 | #define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
71490 | #define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
71491 | #define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
71492 | #define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
71493 | #define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
71494 | #define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
71495 | #define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
71496 | #define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
71497 | #define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
71498 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
71499 | #define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
71500 | #define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
71501 | #define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
71502 | #define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
71503 | #define BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
71504 | #define BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
71505 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
71506 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
71507 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
71508 | #define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
71509 | #define BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
71510 | #define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
71511 | #define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
71512 | #define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
71513 | #define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
71514 | #define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
71515 | #define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
71516 | #define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
71517 | #define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
71518 | #define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
71519 | #define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
71520 | #define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
71521 | #define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
71522 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
71523 | #define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
71524 | #define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
71525 | #define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
71526 | #define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
71527 | #define BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
71528 | #define BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
71529 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
71530 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
71531 | #define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
71532 | #define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
71533 | #define BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
71534 | //BIFP4_PCIE_LINK_MANAGEMENT_STATUS |
71535 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
71536 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
71537 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
71538 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
71539 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
71540 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
71541 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
71542 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
71543 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
71544 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
71545 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
71546 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
71547 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
71548 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
71549 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
71550 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
71551 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
71552 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
71553 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
71554 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
71555 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
71556 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
71557 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
71558 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
71559 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
71560 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
71561 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
71562 | #define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
71563 | //BIFP4_PCIE_LINK_MANAGEMENT_MASK |
71564 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
71565 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
71566 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
71567 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
71568 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
71569 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
71570 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
71571 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
71572 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
71573 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
71574 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
71575 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
71576 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
71577 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
71578 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
71579 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
71580 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
71581 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
71582 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
71583 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
71584 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
71585 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
71586 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
71587 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
71588 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
71589 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
71590 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
71591 | #define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
71592 | //BIFP4_PCIE_LINK_MANAGEMENT_CNTL |
71593 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
71594 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
71595 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
71596 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
71597 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
71598 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
71599 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
71600 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
71601 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
71602 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
71603 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
71604 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
71605 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
71606 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
71607 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
71608 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
71609 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
71610 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
71611 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
71612 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
71613 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
71614 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
71615 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
71616 | #define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
71617 | //BIFP4_PCIEP_STRAP_LC |
71618 | #define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
71619 | #define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
71620 | #define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
71621 | #define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
71622 | #define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
71623 | #define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
71624 | #define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
71625 | #define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
71626 | #define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
71627 | #define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
71628 | #define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
71629 | #define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
71630 | #define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
71631 | #define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
71632 | #define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
71633 | #define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
71634 | #define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
71635 | #define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
71636 | #define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
71637 | #define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
71638 | #define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
71639 | #define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
71640 | //BIFP4_PCIEP_STRAP_MISC |
71641 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
71642 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
71643 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
71644 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
71645 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
71646 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
71647 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
71648 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
71649 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
71650 | #define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
71651 | //BIFP4_PCIE_LC_L1_PM_SUBSTATE |
71652 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
71653 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
71654 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
71655 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
71656 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
71657 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
71658 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
71659 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
71660 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
71661 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
71662 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
71663 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
71664 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
71665 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
71666 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
71667 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
71668 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
71669 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
71670 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
71671 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
71672 | //BIFP4_PCIE_LC_L1_PM_SUBSTATE2 |
71673 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
71674 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
71675 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
71676 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
71677 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
71678 | #define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
71679 | //BIFP4_PCIE_LC_PORT_ORDER |
71680 | #define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
71681 | #define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
71682 | //BIFP4_PCIEP_BCH_ECC_CNTL |
71683 | #define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
71684 | #define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
71685 | #define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
71686 | #define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
71687 | #define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
71688 | #define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
71689 | //BIFP4_PCIEP_HPGI_PRIVATE |
71690 | #define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
71691 | #define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
71692 | #define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
71693 | #define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
71694 | //BIFP4_PCIEP_HPGI |
71695 | #define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
71696 | #define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
71697 | #define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
71698 | #define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
71699 | #define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
71700 | #define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
71701 | #define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
71702 | #define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
71703 | #define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
71704 | #define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
71705 | #define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
71706 | #define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
71707 | #define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
71708 | #define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
71709 | #define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
71710 | #define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
71711 | #define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
71712 | #define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
71713 | #define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
71714 | #define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
71715 | #define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
71716 | #define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
71717 | //BIFP4_PCIEP_HCNT_DESCRIPTOR |
71718 | #define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
71719 | #define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
71720 | #define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
71721 | #define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
71722 | //BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK |
71723 | #define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
71724 | #define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
71725 | #define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
71726 | #define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
71727 | |
71728 | |
71729 | // addressBlock: nbio_pcie0_bifp5_pciedir_p |
71730 | //BIFP5_PCIEP_RESERVED |
71731 | #define BIFP5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
71732 | #define BIFP5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
71733 | //BIFP5_PCIEP_SCRATCH |
71734 | #define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
71735 | #define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
71736 | //BIFP5_PCIEP_PORT_CNTL |
71737 | #define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
71738 | #define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
71739 | #define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
71740 | #define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
71741 | #define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
71742 | #define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
71743 | #define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
71744 | #define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
71745 | #define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
71746 | #define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
71747 | #define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
71748 | #define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
71749 | #define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
71750 | #define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
71751 | #define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
71752 | #define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
71753 | #define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
71754 | #define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
71755 | #define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
71756 | #define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
71757 | //BIFP5_PCIE_TX_CNTL |
71758 | #define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
71759 | #define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
71760 | #define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
71761 | #define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
71762 | #define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
71763 | #define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
71764 | #define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
71765 | #define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
71766 | #define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
71767 | #define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
71768 | #define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
71769 | #define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
71770 | #define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
71771 | #define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
71772 | #define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
71773 | #define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
71774 | //BIFP5_PCIE_TX_REQUESTER_ID |
71775 | #define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
71776 | #define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
71777 | #define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
71778 | #define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
71779 | #define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
71780 | #define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
71781 | //BIFP5_PCIE_TX_VENDOR_SPECIFIC |
71782 | #define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
71783 | #define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
71784 | //BIFP5_PCIE_TX_REQUEST_NUM_CNTL |
71785 | #define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
71786 | #define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
71787 | #define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
71788 | #define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
71789 | #define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
71790 | #define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
71791 | //BIFP5_PCIE_TX_SEQ |
71792 | #define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
71793 | #define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
71794 | #define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
71795 | #define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
71796 | //BIFP5_PCIE_TX_REPLAY |
71797 | #define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
71798 | #define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
71799 | #define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
71800 | #define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
71801 | #define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
71802 | #define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
71803 | //BIFP5_PCIE_TX_ACK_LATENCY_LIMIT |
71804 | #define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
71805 | #define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
71806 | #define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
71807 | #define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
71808 | //BIFP5_PCIE_TX_CREDITS_ADVT_P |
71809 | #define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
71810 | #define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
71811 | #define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
71812 | #define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
71813 | //BIFP5_PCIE_TX_CREDITS_ADVT_NP |
71814 | #define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
71815 | #define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
71816 | #define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
71817 | #define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
71818 | //BIFP5_PCIE_TX_CREDITS_ADVT_CPL |
71819 | #define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
71820 | #define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
71821 | #define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
71822 | #define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
71823 | //BIFP5_PCIE_TX_CREDITS_INIT_P |
71824 | #define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
71825 | #define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
71826 | #define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
71827 | #define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
71828 | //BIFP5_PCIE_TX_CREDITS_INIT_NP |
71829 | #define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
71830 | #define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
71831 | #define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
71832 | #define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
71833 | //BIFP5_PCIE_TX_CREDITS_INIT_CPL |
71834 | #define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
71835 | #define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
71836 | #define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
71837 | #define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
71838 | //BIFP5_PCIE_TX_CREDITS_STATUS |
71839 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
71840 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
71841 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
71842 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
71843 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
71844 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
71845 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
71846 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
71847 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
71848 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
71849 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
71850 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
71851 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
71852 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
71853 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
71854 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
71855 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
71856 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
71857 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
71858 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
71859 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
71860 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
71861 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
71862 | #define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
71863 | //BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD |
71864 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
71865 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
71866 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
71867 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
71868 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
71869 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
71870 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
71871 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
71872 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
71873 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
71874 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
71875 | #define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
71876 | //BIFP5_PCIE_P_PORT_LANE_STATUS |
71877 | #define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
71878 | #define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
71879 | #define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
71880 | #define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
71881 | //BIFP5_PCIE_FC_P |
71882 | #define BIFP5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
71883 | #define BIFP5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
71884 | #define BIFP5_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
71885 | #define BIFP5_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
71886 | //BIFP5_PCIE_FC_NP |
71887 | #define BIFP5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
71888 | #define BIFP5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
71889 | #define BIFP5_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
71890 | #define BIFP5_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
71891 | //BIFP5_PCIE_FC_CPL |
71892 | #define BIFP5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
71893 | #define BIFP5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
71894 | #define BIFP5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
71895 | #define BIFP5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
71896 | //BIFP5_PCIE_ERR_CNTL |
71897 | #define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
71898 | #define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
71899 | #define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
71900 | #define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
71901 | #define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
71902 | #define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
71903 | #define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
71904 | #define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
71905 | #define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
71906 | #define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
71907 | #define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
71908 | #define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
71909 | #define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
71910 | #define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
71911 | #define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
71912 | #define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
71913 | #define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
71914 | #define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
71915 | #define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
71916 | #define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
71917 | #define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
71918 | #define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
71919 | #define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
71920 | #define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
71921 | #define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
71922 | #define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
71923 | #define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
71924 | #define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
71925 | //BIFP5_PCIE_RX_CNTL |
71926 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
71927 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
71928 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
71929 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
71930 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
71931 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
71932 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
71933 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
71934 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
71935 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
71936 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
71937 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
71938 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
71939 | #define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
71940 | #define BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
71941 | #define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
71942 | #define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
71943 | #define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
71944 | #define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
71945 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
71946 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
71947 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
71948 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
71949 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
71950 | #define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
71951 | #define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
71952 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
71953 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
71954 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
71955 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
71956 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
71957 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
71958 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
71959 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
71960 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
71961 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
71962 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
71963 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
71964 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
71965 | #define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
71966 | #define BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
71967 | #define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
71968 | #define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
71969 | #define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
71970 | #define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
71971 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
71972 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
71973 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
71974 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
71975 | #define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
71976 | #define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
71977 | #define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
71978 | //BIFP5_PCIE_RX_EXPECTED_SEQNUM |
71979 | #define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
71980 | #define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
71981 | //BIFP5_PCIE_RX_VENDOR_SPECIFIC |
71982 | #define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
71983 | #define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
71984 | #define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
71985 | #define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
71986 | //BIFP5_PCIE_RX_CNTL3 |
71987 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
71988 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
71989 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
71990 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
71991 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
71992 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
71993 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
71994 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
71995 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
71996 | #define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
71997 | //BIFP5_PCIE_RX_CREDITS_ALLOCATED_P |
71998 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
71999 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
72000 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
72001 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
72002 | //BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP |
72003 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
72004 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
72005 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
72006 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
72007 | //BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL |
72008 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
72009 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
72010 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
72011 | #define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
72012 | //BIFP5_PCIEP_ERROR_INJECT_PHYSICAL |
72013 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
72014 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
72015 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
72016 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
72017 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
72018 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
72019 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
72020 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
72021 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
72022 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
72023 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
72024 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
72025 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
72026 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
72027 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
72028 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
72029 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
72030 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
72031 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
72032 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
72033 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
72034 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
72035 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
72036 | #define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
72037 | //BIFP5_PCIEP_ERROR_INJECT_TRANSACTION |
72038 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
72039 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
72040 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
72041 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
72042 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
72043 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
72044 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
72045 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
72046 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
72047 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
72048 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
72049 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
72050 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
72051 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
72052 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
72053 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
72054 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
72055 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
72056 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
72057 | #define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
72058 | //BIFP5_PCIEP_NAK_COUNTER |
72059 | #define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
72060 | #define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
72061 | #define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
72062 | #define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
72063 | //BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
72064 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
72065 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
72066 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
72067 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
72068 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
72069 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
72070 | //BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
72071 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
72072 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
72073 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
72074 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
72075 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
72076 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
72077 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
72078 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
72079 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
72080 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
72081 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
72082 | #define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
72083 | //BIFP5_PCIE_LC_CNTL |
72084 | #define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
72085 | #define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
72086 | #define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
72087 | #define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
72088 | #define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
72089 | #define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
72090 | #define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
72091 | #define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
72092 | #define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
72093 | #define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
72094 | #define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
72095 | #define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
72096 | #define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
72097 | #define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
72098 | #define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
72099 | #define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
72100 | #define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
72101 | #define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
72102 | #define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
72103 | #define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
72104 | #define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
72105 | #define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
72106 | #define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
72107 | #define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
72108 | #define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
72109 | #define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
72110 | #define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
72111 | #define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
72112 | #define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
72113 | #define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
72114 | #define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
72115 | #define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
72116 | #define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
72117 | #define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
72118 | #define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
72119 | #define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
72120 | #define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
72121 | #define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
72122 | #define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
72123 | #define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
72124 | //BIFP5_PCIE_LC_TRAINING_CNTL |
72125 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
72126 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
72127 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
72128 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
72129 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
72130 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
72131 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
72132 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
72133 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
72134 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
72135 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
72136 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
72137 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
72138 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
72139 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
72140 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
72141 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
72142 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
72143 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
72144 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
72145 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
72146 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
72147 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
72148 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
72149 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
72150 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
72151 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
72152 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
72153 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
72154 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
72155 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
72156 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
72157 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
72158 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
72159 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
72160 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
72161 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
72162 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
72163 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
72164 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
72165 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
72166 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
72167 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
72168 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
72169 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
72170 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
72171 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
72172 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
72173 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
72174 | #define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
72175 | //BIFP5_PCIE_LC_LINK_WIDTH_CNTL |
72176 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
72177 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
72178 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
72179 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
72180 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
72181 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
72182 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
72183 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
72184 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
72185 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
72186 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
72187 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
72188 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
72189 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
72190 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
72191 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
72192 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
72193 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
72194 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
72195 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
72196 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
72197 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
72198 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
72199 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
72200 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
72201 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
72202 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
72203 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
72204 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
72205 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
72206 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
72207 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
72208 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
72209 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
72210 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
72211 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
72212 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
72213 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
72214 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
72215 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
72216 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
72217 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
72218 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
72219 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
72220 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
72221 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
72222 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
72223 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
72224 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
72225 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
72226 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
72227 | #define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
72228 | //BIFP5_PCIE_LC_N_FTS_CNTL |
72229 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
72230 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
72231 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
72232 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
72233 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
72234 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
72235 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
72236 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
72237 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
72238 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
72239 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
72240 | #define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
72241 | //BIFP5_PCIE_LC_SPEED_CNTL |
72242 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
72243 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
72244 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
72245 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
72246 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
72247 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
72248 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
72249 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
72250 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
72251 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
72252 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
72253 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
72254 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
72255 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
72256 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
72257 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
72258 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
72259 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
72260 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
72261 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
72262 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
72263 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
72264 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
72265 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
72266 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
72267 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
72268 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
72269 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
72270 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
72271 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
72272 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
72273 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
72274 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
72275 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
72276 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
72277 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
72278 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
72279 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
72280 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
72281 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
72282 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
72283 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
72284 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
72285 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
72286 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
72287 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
72288 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
72289 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
72290 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
72291 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
72292 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
72293 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
72294 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
72295 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
72296 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
72297 | #define BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
72298 | //BIFP5_PCIE_LC_STATE0 |
72299 | #define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
72300 | #define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
72301 | #define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
72302 | #define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
72303 | #define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
72304 | #define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
72305 | #define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
72306 | #define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
72307 | //BIFP5_PCIE_LC_STATE1 |
72308 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
72309 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
72310 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
72311 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
72312 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
72313 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
72314 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
72315 | #define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
72316 | //BIFP5_PCIE_LC_STATE2 |
72317 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
72318 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
72319 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
72320 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
72321 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
72322 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
72323 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
72324 | #define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
72325 | //BIFP5_PCIE_LC_STATE3 |
72326 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
72327 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
72328 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
72329 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
72330 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
72331 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
72332 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
72333 | #define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
72334 | //BIFP5_PCIE_LC_STATE4 |
72335 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
72336 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
72337 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
72338 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
72339 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
72340 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
72341 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
72342 | #define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
72343 | //BIFP5_PCIE_LC_STATE5 |
72344 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
72345 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
72346 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
72347 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
72348 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
72349 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
72350 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
72351 | #define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
72352 | //BIFP5_PCIE_LINK_MANAGEMENT_CNTL2 |
72353 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
72354 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
72355 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
72356 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
72357 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
72358 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
72359 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
72360 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
72361 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
72362 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
72363 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
72364 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
72365 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
72366 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
72367 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
72368 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
72369 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
72370 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
72371 | //BIFP5_PCIE_LC_CNTL2 |
72372 | #define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
72373 | #define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
72374 | #define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
72375 | #define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
72376 | #define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
72377 | #define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
72378 | #define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
72379 | #define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
72380 | #define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
72381 | #define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
72382 | #define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
72383 | #define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
72384 | #define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
72385 | #define BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
72386 | #define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
72387 | #define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
72388 | #define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
72389 | #define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
72390 | #define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
72391 | #define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
72392 | #define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
72393 | #define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
72394 | #define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
72395 | #define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
72396 | #define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
72397 | #define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
72398 | #define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
72399 | #define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
72400 | #define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
72401 | #define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
72402 | #define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
72403 | #define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
72404 | #define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
72405 | #define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
72406 | #define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
72407 | #define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
72408 | #define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
72409 | #define BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
72410 | #define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
72411 | #define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
72412 | #define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
72413 | #define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
72414 | #define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
72415 | #define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
72416 | #define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
72417 | #define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
72418 | #define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
72419 | #define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
72420 | //BIFP5_PCIE_LC_BW_CHANGE_CNTL |
72421 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
72422 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
72423 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
72424 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
72425 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
72426 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
72427 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
72428 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
72429 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
72430 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
72431 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
72432 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
72433 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
72434 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
72435 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
72436 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
72437 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
72438 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
72439 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
72440 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
72441 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
72442 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
72443 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
72444 | #define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
72445 | //BIFP5_PCIE_LC_CDR_CNTL |
72446 | #define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
72447 | #define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
72448 | #define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
72449 | #define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
72450 | #define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
72451 | #define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
72452 | //BIFP5_PCIE_LC_LANE_CNTL |
72453 | #define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
72454 | #define BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
72455 | #define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
72456 | #define BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
72457 | //BIFP5_PCIE_LC_CNTL3 |
72458 | #define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
72459 | #define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
72460 | #define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
72461 | #define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
72462 | #define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
72463 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
72464 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
72465 | #define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
72466 | #define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
72467 | #define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
72468 | #define BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
72469 | #define BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
72470 | #define BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
72471 | #define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
72472 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
72473 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
72474 | #define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
72475 | #define BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
72476 | #define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
72477 | #define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
72478 | #define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
72479 | #define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
72480 | #define BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
72481 | #define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
72482 | #define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
72483 | #define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
72484 | #define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
72485 | #define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
72486 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
72487 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
72488 | #define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
72489 | #define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
72490 | #define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
72491 | #define BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
72492 | #define BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
72493 | #define BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
72494 | #define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
72495 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
72496 | #define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
72497 | #define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
72498 | #define BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
72499 | #define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
72500 | #define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
72501 | #define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
72502 | #define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
72503 | #define BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
72504 | //BIFP5_PCIE_LC_CNTL4 |
72505 | #define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
72506 | #define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
72507 | #define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
72508 | #define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
72509 | #define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
72510 | #define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
72511 | #define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
72512 | #define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
72513 | #define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
72514 | #define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
72515 | #define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
72516 | #define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
72517 | #define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
72518 | #define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
72519 | #define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
72520 | #define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
72521 | #define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
72522 | #define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
72523 | #define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
72524 | #define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
72525 | #define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
72526 | #define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
72527 | #define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
72528 | #define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
72529 | #define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
72530 | #define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
72531 | #define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
72532 | #define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
72533 | #define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
72534 | #define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
72535 | #define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
72536 | #define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
72537 | #define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
72538 | #define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
72539 | #define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
72540 | #define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
72541 | #define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
72542 | #define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
72543 | #define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
72544 | #define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
72545 | #define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
72546 | #define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
72547 | #define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
72548 | #define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
72549 | //BIFP5_PCIE_LC_CNTL5 |
72550 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
72551 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
72552 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
72553 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
72554 | #define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
72555 | #define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
72556 | #define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
72557 | #define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
72558 | #define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
72559 | #define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
72560 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
72561 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
72562 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
72563 | #define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
72564 | #define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
72565 | #define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
72566 | #define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
72567 | #define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
72568 | #define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
72569 | #define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
72570 | //BIFP5_PCIE_LC_FORCE_COEFF |
72571 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
72572 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
72573 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
72574 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
72575 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
72576 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
72577 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
72578 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
72579 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
72580 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
72581 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
72582 | #define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
72583 | //BIFP5_PCIE_LC_BEST_EQ_SETTINGS |
72584 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
72585 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
72586 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
72587 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
72588 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
72589 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
72590 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
72591 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
72592 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
72593 | #define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
72594 | //BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF |
72595 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
72596 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
72597 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
72598 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
72599 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
72600 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
72601 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
72602 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
72603 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
72604 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
72605 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
72606 | #define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
72607 | //BIFP5_PCIE_LC_CNTL6 |
72608 | #define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
72609 | #define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
72610 | #define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
72611 | #define BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
72612 | #define BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
72613 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
72614 | #define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
72615 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
72616 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
72617 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
72618 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
72619 | #define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
72620 | #define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
72621 | #define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
72622 | #define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
72623 | #define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
72624 | #define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
72625 | #define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
72626 | #define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
72627 | #define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
72628 | #define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
72629 | #define BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
72630 | #define BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
72631 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
72632 | #define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
72633 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
72634 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
72635 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
72636 | #define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
72637 | #define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
72638 | #define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
72639 | #define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
72640 | #define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
72641 | #define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
72642 | #define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
72643 | #define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
72644 | //BIFP5_PCIE_LC_CNTL7 |
72645 | #define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
72646 | #define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
72647 | #define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
72648 | #define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
72649 | #define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
72650 | #define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
72651 | #define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
72652 | #define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
72653 | #define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
72654 | #define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
72655 | #define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
72656 | #define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
72657 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
72658 | #define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
72659 | #define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
72660 | #define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
72661 | #define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
72662 | #define BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
72663 | #define BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
72664 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
72665 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
72666 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
72667 | #define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
72668 | #define BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
72669 | #define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
72670 | #define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
72671 | #define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
72672 | #define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
72673 | #define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
72674 | #define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
72675 | #define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
72676 | #define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
72677 | #define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
72678 | #define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
72679 | #define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
72680 | #define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
72681 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
72682 | #define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
72683 | #define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
72684 | #define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
72685 | #define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
72686 | #define BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
72687 | #define BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
72688 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
72689 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
72690 | #define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
72691 | #define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
72692 | #define BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
72693 | //BIFP5_PCIE_LINK_MANAGEMENT_STATUS |
72694 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
72695 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
72696 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
72697 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
72698 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
72699 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
72700 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
72701 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
72702 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
72703 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
72704 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
72705 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
72706 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
72707 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
72708 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
72709 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
72710 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
72711 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
72712 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
72713 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
72714 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
72715 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
72716 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
72717 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
72718 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
72719 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
72720 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
72721 | #define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
72722 | //BIFP5_PCIE_LINK_MANAGEMENT_MASK |
72723 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
72724 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
72725 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
72726 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
72727 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
72728 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
72729 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
72730 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
72731 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
72732 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
72733 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
72734 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
72735 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
72736 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
72737 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
72738 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
72739 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
72740 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
72741 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
72742 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
72743 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
72744 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
72745 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
72746 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
72747 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
72748 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
72749 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
72750 | #define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
72751 | //BIFP5_PCIE_LINK_MANAGEMENT_CNTL |
72752 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
72753 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
72754 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
72755 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
72756 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
72757 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
72758 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
72759 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
72760 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
72761 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
72762 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
72763 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
72764 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
72765 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
72766 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
72767 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
72768 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
72769 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
72770 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
72771 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
72772 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
72773 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
72774 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
72775 | #define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
72776 | //BIFP5_PCIEP_STRAP_LC |
72777 | #define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
72778 | #define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
72779 | #define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
72780 | #define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
72781 | #define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
72782 | #define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
72783 | #define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
72784 | #define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
72785 | #define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
72786 | #define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
72787 | #define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
72788 | #define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
72789 | #define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
72790 | #define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
72791 | #define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
72792 | #define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
72793 | #define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
72794 | #define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
72795 | #define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
72796 | #define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
72797 | #define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
72798 | #define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
72799 | //BIFP5_PCIEP_STRAP_MISC |
72800 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
72801 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
72802 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
72803 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
72804 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
72805 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
72806 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
72807 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
72808 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
72809 | #define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
72810 | //BIFP5_PCIE_LC_L1_PM_SUBSTATE |
72811 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
72812 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
72813 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
72814 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
72815 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
72816 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
72817 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
72818 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
72819 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
72820 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
72821 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
72822 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
72823 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
72824 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
72825 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
72826 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
72827 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
72828 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
72829 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
72830 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
72831 | //BIFP5_PCIE_LC_L1_PM_SUBSTATE2 |
72832 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
72833 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
72834 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
72835 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
72836 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
72837 | #define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
72838 | //BIFP5_PCIE_LC_PORT_ORDER |
72839 | #define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
72840 | #define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
72841 | //BIFP5_PCIEP_BCH_ECC_CNTL |
72842 | #define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
72843 | #define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
72844 | #define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
72845 | #define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
72846 | #define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
72847 | #define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
72848 | //BIFP5_PCIEP_HPGI_PRIVATE |
72849 | #define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
72850 | #define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
72851 | #define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
72852 | #define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
72853 | //BIFP5_PCIEP_HPGI |
72854 | #define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
72855 | #define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
72856 | #define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
72857 | #define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
72858 | #define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
72859 | #define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
72860 | #define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
72861 | #define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
72862 | #define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
72863 | #define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
72864 | #define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
72865 | #define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
72866 | #define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
72867 | #define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
72868 | #define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
72869 | #define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
72870 | #define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
72871 | #define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
72872 | #define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
72873 | #define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
72874 | #define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
72875 | #define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
72876 | //BIFP5_PCIEP_HCNT_DESCRIPTOR |
72877 | #define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
72878 | #define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
72879 | #define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
72880 | #define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
72881 | //BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK |
72882 | #define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
72883 | #define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
72884 | #define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
72885 | #define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
72886 | |
72887 | |
72888 | // addressBlock: nbio_pcie0_bifp6_pciedir_p |
72889 | //BIFP6_PCIEP_RESERVED |
72890 | #define BIFP6_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
72891 | #define BIFP6_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
72892 | //BIFP6_PCIEP_SCRATCH |
72893 | #define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
72894 | #define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
72895 | //BIFP6_PCIEP_PORT_CNTL |
72896 | #define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
72897 | #define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
72898 | #define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
72899 | #define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
72900 | #define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
72901 | #define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
72902 | #define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
72903 | #define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
72904 | #define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
72905 | #define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
72906 | #define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
72907 | #define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
72908 | #define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
72909 | #define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
72910 | #define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
72911 | #define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
72912 | #define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L |
72913 | #define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L |
72914 | #define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
72915 | #define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
72916 | //BIFP6_PCIE_TX_CNTL |
72917 | #define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
72918 | #define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
72919 | #define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
72920 | #define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
72921 | #define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
72922 | #define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
72923 | #define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 |
72924 | #define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
72925 | #define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
72926 | #define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
72927 | #define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
72928 | #define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
72929 | #define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
72930 | #define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
72931 | #define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L |
72932 | #define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
72933 | //BIFP6_PCIE_TX_REQUESTER_ID |
72934 | #define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
72935 | #define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
72936 | #define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
72937 | #define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
72938 | #define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
72939 | #define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
72940 | //BIFP6_PCIE_TX_VENDOR_SPECIFIC |
72941 | #define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
72942 | #define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
72943 | //BIFP6_PCIE_TX_REQUEST_NUM_CNTL |
72944 | #define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
72945 | #define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
72946 | #define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
72947 | #define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
72948 | #define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
72949 | #define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
72950 | //BIFP6_PCIE_TX_SEQ |
72951 | #define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
72952 | #define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
72953 | #define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
72954 | #define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
72955 | //BIFP6_PCIE_TX_REPLAY |
72956 | #define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
72957 | #define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
72958 | #define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
72959 | #define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
72960 | #define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
72961 | #define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
72962 | //BIFP6_PCIE_TX_ACK_LATENCY_LIMIT |
72963 | #define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
72964 | #define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
72965 | #define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
72966 | #define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
72967 | //BIFP6_PCIE_TX_CREDITS_ADVT_P |
72968 | #define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
72969 | #define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
72970 | #define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL |
72971 | #define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L |
72972 | //BIFP6_PCIE_TX_CREDITS_ADVT_NP |
72973 | #define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
72974 | #define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
72975 | #define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL |
72976 | #define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L |
72977 | //BIFP6_PCIE_TX_CREDITS_ADVT_CPL |
72978 | #define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
72979 | #define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
72980 | #define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL |
72981 | #define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L |
72982 | //BIFP6_PCIE_TX_CREDITS_INIT_P |
72983 | #define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
72984 | #define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
72985 | #define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
72986 | #define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
72987 | //BIFP6_PCIE_TX_CREDITS_INIT_NP |
72988 | #define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
72989 | #define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
72990 | #define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
72991 | #define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
72992 | //BIFP6_PCIE_TX_CREDITS_INIT_CPL |
72993 | #define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
72994 | #define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
72995 | #define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
72996 | #define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
72997 | //BIFP6_PCIE_TX_CREDITS_STATUS |
72998 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
72999 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
73000 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
73001 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
73002 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
73003 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
73004 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
73005 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
73006 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
73007 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
73008 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
73009 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
73010 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
73011 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
73012 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
73013 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
73014 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
73015 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
73016 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
73017 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
73018 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
73019 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
73020 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
73021 | #define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
73022 | //BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD |
73023 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
73024 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
73025 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
73026 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
73027 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
73028 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
73029 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
73030 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
73031 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
73032 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
73033 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
73034 | #define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
73035 | //BIFP6_PCIE_P_PORT_LANE_STATUS |
73036 | #define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
73037 | #define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
73038 | #define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
73039 | #define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
73040 | //BIFP6_PCIE_FC_P |
73041 | #define BIFP6_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
73042 | #define BIFP6_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 |
73043 | #define BIFP6_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL |
73044 | #define BIFP6_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L |
73045 | //BIFP6_PCIE_FC_NP |
73046 | #define BIFP6_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
73047 | #define BIFP6_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 |
73048 | #define BIFP6_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL |
73049 | #define BIFP6_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L |
73050 | //BIFP6_PCIE_FC_CPL |
73051 | #define BIFP6_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
73052 | #define BIFP6_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 |
73053 | #define BIFP6_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL |
73054 | #define BIFP6_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L |
73055 | //BIFP6_PCIE_ERR_CNTL |
73056 | #define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
73057 | #define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
73058 | #define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
73059 | #define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
73060 | #define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
73061 | #define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
73062 | #define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
73063 | #define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
73064 | #define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
73065 | #define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
73066 | #define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
73067 | #define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
73068 | #define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
73069 | #define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
73070 | #define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
73071 | #define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
73072 | #define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
73073 | #define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
73074 | #define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
73075 | #define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
73076 | #define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
73077 | #define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
73078 | #define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
73079 | #define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
73080 | #define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
73081 | #define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
73082 | #define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
73083 | #define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
73084 | //BIFP6_PCIE_RX_CNTL |
73085 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
73086 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
73087 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
73088 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
73089 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
73090 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
73091 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
73092 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
73093 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
73094 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
73095 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
73096 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
73097 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
73098 | #define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
73099 | #define BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
73100 | #define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
73101 | #define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
73102 | #define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
73103 | #define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
73104 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
73105 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
73106 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
73107 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
73108 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
73109 | #define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
73110 | #define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
73111 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
73112 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
73113 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
73114 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
73115 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
73116 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
73117 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
73118 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
73119 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
73120 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
73121 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
73122 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
73123 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
73124 | #define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
73125 | #define BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
73126 | #define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
73127 | #define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
73128 | #define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
73129 | #define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
73130 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
73131 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
73132 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
73133 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
73134 | #define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
73135 | #define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
73136 | #define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
73137 | //BIFP6_PCIE_RX_EXPECTED_SEQNUM |
73138 | #define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
73139 | #define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
73140 | //BIFP6_PCIE_RX_VENDOR_SPECIFIC |
73141 | #define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
73142 | #define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
73143 | #define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
73144 | #define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
73145 | //BIFP6_PCIE_RX_CNTL3 |
73146 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
73147 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
73148 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
73149 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
73150 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
73151 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
73152 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
73153 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
73154 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
73155 | #define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
73156 | //BIFP6_PCIE_RX_CREDITS_ALLOCATED_P |
73157 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
73158 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
73159 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
73160 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
73161 | //BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP |
73162 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
73163 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
73164 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
73165 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
73166 | //BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL |
73167 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
73168 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
73169 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
73170 | #define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
73171 | //BIFP6_PCIEP_ERROR_INJECT_PHYSICAL |
73172 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
73173 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
73174 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
73175 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
73176 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
73177 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
73178 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
73179 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
73180 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
73181 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
73182 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
73183 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 |
73184 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
73185 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
73186 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
73187 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
73188 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
73189 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
73190 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
73191 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
73192 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
73193 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
73194 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
73195 | #define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L |
73196 | //BIFP6_PCIEP_ERROR_INJECT_TRANSACTION |
73197 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
73198 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
73199 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
73200 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
73201 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
73202 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
73203 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
73204 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
73205 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
73206 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
73207 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
73208 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
73209 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
73210 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
73211 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
73212 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
73213 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
73214 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
73215 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
73216 | #define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
73217 | //BIFP6_PCIEP_NAK_COUNTER |
73218 | #define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
73219 | #define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
73220 | #define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
73221 | #define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
73222 | //BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS |
73223 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 |
73224 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 |
73225 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 |
73226 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L |
73227 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L |
73228 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L |
73229 | //BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES |
73230 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 |
73231 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa |
73232 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf |
73233 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 |
73234 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a |
73235 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f |
73236 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL |
73237 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L |
73238 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L |
73239 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L |
73240 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L |
73241 | #define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L |
73242 | //BIFP6_PCIE_LC_CNTL |
73243 | #define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
73244 | #define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
73245 | #define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
73246 | #define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
73247 | #define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
73248 | #define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
73249 | #define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
73250 | #define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
73251 | #define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
73252 | #define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
73253 | #define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
73254 | #define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
73255 | #define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
73256 | #define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
73257 | #define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
73258 | #define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
73259 | #define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
73260 | #define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
73261 | #define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
73262 | #define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
73263 | #define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
73264 | #define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
73265 | #define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
73266 | #define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
73267 | #define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
73268 | #define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
73269 | #define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
73270 | #define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
73271 | #define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
73272 | #define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
73273 | #define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
73274 | #define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
73275 | #define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
73276 | #define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
73277 | #define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
73278 | #define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
73279 | #define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
73280 | #define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
73281 | #define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
73282 | #define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
73283 | //BIFP6_PCIE_LC_TRAINING_CNTL |
73284 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
73285 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
73286 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
73287 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
73288 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
73289 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
73290 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
73291 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
73292 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
73293 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
73294 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
73295 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
73296 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
73297 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
73298 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
73299 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
73300 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
73301 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
73302 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
73303 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
73304 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
73305 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
73306 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
73307 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
73308 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
73309 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
73310 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
73311 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
73312 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
73313 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
73314 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
73315 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
73316 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
73317 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
73318 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
73319 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
73320 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
73321 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
73322 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
73323 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
73324 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
73325 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
73326 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
73327 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
73328 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
73329 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
73330 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
73331 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
73332 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
73333 | #define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
73334 | //BIFP6_PCIE_LC_LINK_WIDTH_CNTL |
73335 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
73336 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
73337 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
73338 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
73339 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
73340 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
73341 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
73342 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
73343 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
73344 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
73345 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
73346 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
73347 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
73348 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
73349 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
73350 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
73351 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
73352 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
73353 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
73354 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
73355 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
73356 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
73357 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
73358 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
73359 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
73360 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
73361 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
73362 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
73363 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
73364 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
73365 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
73366 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
73367 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
73368 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
73369 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
73370 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
73371 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
73372 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
73373 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
73374 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
73375 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
73376 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
73377 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
73378 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
73379 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
73380 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
73381 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
73382 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
73383 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
73384 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
73385 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
73386 | #define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
73387 | //BIFP6_PCIE_LC_N_FTS_CNTL |
73388 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
73389 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
73390 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
73391 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf |
73392 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
73393 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
73394 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
73395 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
73396 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
73397 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L |
73398 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
73399 | #define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
73400 | //BIFP6_PCIE_LC_SPEED_CNTL |
73401 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
73402 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
73403 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 |
73404 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 |
73405 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 |
73406 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 |
73407 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 |
73408 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 |
73409 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 |
73410 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa |
73411 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc |
73412 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd |
73413 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf |
73414 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 |
73415 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 |
73416 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 |
73417 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 |
73418 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 |
73419 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 |
73420 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 |
73421 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 |
73422 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 |
73423 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a |
73424 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b |
73425 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c |
73426 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d |
73427 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e |
73428 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f |
73429 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
73430 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
73431 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L |
73432 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L |
73433 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L |
73434 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L |
73435 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L |
73436 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L |
73437 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L |
73438 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L |
73439 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L |
73440 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L |
73441 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L |
73442 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L |
73443 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L |
73444 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L |
73445 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L |
73446 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L |
73447 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L |
73448 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L |
73449 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L |
73450 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L |
73451 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L |
73452 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L |
73453 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L |
73454 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L |
73455 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L |
73456 | #define BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L |
73457 | //BIFP6_PCIE_LC_STATE0 |
73458 | #define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
73459 | #define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
73460 | #define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
73461 | #define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
73462 | #define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
73463 | #define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
73464 | #define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
73465 | #define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
73466 | //BIFP6_PCIE_LC_STATE1 |
73467 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
73468 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
73469 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
73470 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
73471 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
73472 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
73473 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
73474 | #define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
73475 | //BIFP6_PCIE_LC_STATE2 |
73476 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
73477 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
73478 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
73479 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
73480 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
73481 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
73482 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
73483 | #define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
73484 | //BIFP6_PCIE_LC_STATE3 |
73485 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
73486 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
73487 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
73488 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
73489 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
73490 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
73491 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
73492 | #define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
73493 | //BIFP6_PCIE_LC_STATE4 |
73494 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
73495 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
73496 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
73497 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
73498 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
73499 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
73500 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
73501 | #define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
73502 | //BIFP6_PCIE_LC_STATE5 |
73503 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
73504 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
73505 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
73506 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
73507 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
73508 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
73509 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
73510 | #define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
73511 | //BIFP6_PCIE_LINK_MANAGEMENT_CNTL2 |
73512 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
73513 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
73514 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
73515 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
73516 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
73517 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
73518 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
73519 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
73520 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
73521 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
73522 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
73523 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
73524 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
73525 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
73526 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
73527 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
73528 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
73529 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
73530 | //BIFP6_PCIE_LC_CNTL2 |
73531 | #define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
73532 | #define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
73533 | #define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
73534 | #define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
73535 | #define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
73536 | #define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
73537 | #define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
73538 | #define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
73539 | #define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
73540 | #define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
73541 | #define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
73542 | #define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
73543 | #define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
73544 | #define BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 |
73545 | #define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
73546 | #define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
73547 | #define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
73548 | #define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
73549 | #define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
73550 | #define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
73551 | #define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
73552 | #define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
73553 | #define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
73554 | #define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
73555 | #define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
73556 | #define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
73557 | #define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
73558 | #define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
73559 | #define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
73560 | #define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
73561 | #define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
73562 | #define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
73563 | #define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
73564 | #define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
73565 | #define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
73566 | #define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
73567 | #define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
73568 | #define BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L |
73569 | #define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
73570 | #define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
73571 | #define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
73572 | #define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
73573 | #define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
73574 | #define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
73575 | #define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
73576 | #define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
73577 | #define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
73578 | #define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
73579 | //BIFP6_PCIE_LC_BW_CHANGE_CNTL |
73580 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
73581 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
73582 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
73583 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
73584 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
73585 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
73586 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
73587 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
73588 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
73589 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
73590 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
73591 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
73592 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
73593 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
73594 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
73595 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
73596 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
73597 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
73598 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
73599 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
73600 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
73601 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
73602 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
73603 | #define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
73604 | //BIFP6_PCIE_LC_CDR_CNTL |
73605 | #define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
73606 | #define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
73607 | #define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
73608 | #define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
73609 | #define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
73610 | #define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
73611 | //BIFP6_PCIE_LC_LANE_CNTL |
73612 | #define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
73613 | #define BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 |
73614 | #define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
73615 | #define BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L |
73616 | //BIFP6_PCIE_LC_CNTL3 |
73617 | #define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
73618 | #define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
73619 | #define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
73620 | #define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
73621 | #define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
73622 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
73623 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
73624 | #define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
73625 | #define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
73626 | #define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
73627 | #define BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc |
73628 | #define BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe |
73629 | #define BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
73630 | #define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
73631 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
73632 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
73633 | #define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
73634 | #define BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 |
73635 | #define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
73636 | #define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
73637 | #define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
73638 | #define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
73639 | #define BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f |
73640 | #define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
73641 | #define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
73642 | #define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
73643 | #define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
73644 | #define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
73645 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
73646 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
73647 | #define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
73648 | #define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
73649 | #define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
73650 | #define BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L |
73651 | #define BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L |
73652 | #define BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
73653 | #define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
73654 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
73655 | #define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
73656 | #define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
73657 | #define BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L |
73658 | #define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
73659 | #define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
73660 | #define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
73661 | #define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
73662 | #define BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L |
73663 | //BIFP6_PCIE_LC_CNTL4 |
73664 | #define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
73665 | #define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
73666 | #define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
73667 | #define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 |
73668 | #define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 |
73669 | #define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
73670 | #define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
73671 | #define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 |
73672 | #define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
73673 | #define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb |
73674 | #define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc |
73675 | #define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
73676 | #define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
73677 | #define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf |
73678 | #define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 |
73679 | #define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 |
73680 | #define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 |
73681 | #define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
73682 | #define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
73683 | #define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
73684 | #define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
73685 | #define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
73686 | #define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
73687 | #define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
73688 | #define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
73689 | #define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L |
73690 | #define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L |
73691 | #define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
73692 | #define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
73693 | #define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L |
73694 | #define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
73695 | #define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L |
73696 | #define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L |
73697 | #define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
73698 | #define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
73699 | #define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L |
73700 | #define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L |
73701 | #define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L |
73702 | #define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L |
73703 | #define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
73704 | #define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
73705 | #define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
73706 | #define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
73707 | #define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
73708 | //BIFP6_PCIE_LC_CNTL5 |
73709 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 |
73710 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 |
73711 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc |
73712 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 |
73713 | #define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
73714 | #define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
73715 | #define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
73716 | #define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
73717 | #define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
73718 | #define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
73719 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL |
73720 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L |
73721 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L |
73722 | #define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L |
73723 | #define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
73724 | #define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
73725 | #define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
73726 | #define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
73727 | #define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
73728 | #define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
73729 | //BIFP6_PCIE_LC_FORCE_COEFF |
73730 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 |
73731 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 |
73732 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 |
73733 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd |
73734 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 |
73735 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
73736 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L |
73737 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL |
73738 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L |
73739 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L |
73740 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L |
73741 | #define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
73742 | //BIFP6_PCIE_LC_BEST_EQ_SETTINGS |
73743 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
73744 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
73745 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
73746 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
73747 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
73748 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
73749 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
73750 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
73751 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
73752 | #define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
73753 | //BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF |
73754 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 |
73755 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 |
73756 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 |
73757 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd |
73758 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 |
73759 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 |
73760 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L |
73761 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL |
73762 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L |
73763 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L |
73764 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L |
73765 | #define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L |
73766 | //BIFP6_PCIE_LC_CNTL6 |
73767 | #define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
73768 | #define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
73769 | #define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
73770 | #define BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 |
73771 | #define BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 |
73772 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
73773 | #define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
73774 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
73775 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
73776 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
73777 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
73778 | #define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
73779 | #define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
73780 | #define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
73781 | #define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
73782 | #define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
73783 | #define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
73784 | #define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
73785 | #define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L |
73786 | #define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L |
73787 | #define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L |
73788 | #define BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L |
73789 | #define BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L |
73790 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
73791 | #define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
73792 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
73793 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
73794 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
73795 | #define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
73796 | #define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
73797 | #define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
73798 | #define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
73799 | #define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
73800 | #define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
73801 | #define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
73802 | #define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
73803 | //BIFP6_PCIE_LC_CNTL7 |
73804 | #define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
73805 | #define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
73806 | #define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
73807 | #define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
73808 | #define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
73809 | #define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
73810 | #define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
73811 | #define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
73812 | #define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
73813 | #define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
73814 | #define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
73815 | #define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
73816 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
73817 | #define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
73818 | #define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
73819 | #define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
73820 | #define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
73821 | #define BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 |
73822 | #define BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a |
73823 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
73824 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
73825 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
73826 | #define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
73827 | #define BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f |
73828 | #define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
73829 | #define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
73830 | #define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
73831 | #define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
73832 | #define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
73833 | #define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
73834 | #define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
73835 | #define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
73836 | #define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
73837 | #define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
73838 | #define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
73839 | #define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
73840 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
73841 | #define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
73842 | #define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
73843 | #define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
73844 | #define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
73845 | #define BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L |
73846 | #define BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L |
73847 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
73848 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
73849 | #define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
73850 | #define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
73851 | #define BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L |
73852 | //BIFP6_PCIE_LINK_MANAGEMENT_STATUS |
73853 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
73854 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
73855 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
73856 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
73857 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
73858 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
73859 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
73860 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
73861 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
73862 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
73863 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
73864 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
73865 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
73866 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
73867 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
73868 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
73869 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
73870 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
73871 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
73872 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
73873 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
73874 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
73875 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
73876 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
73877 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
73878 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
73879 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
73880 | #define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
73881 | //BIFP6_PCIE_LINK_MANAGEMENT_MASK |
73882 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
73883 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
73884 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
73885 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
73886 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
73887 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
73888 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
73889 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
73890 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
73891 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
73892 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
73893 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
73894 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
73895 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
73896 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
73897 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
73898 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
73899 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
73900 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
73901 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
73902 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
73903 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
73904 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
73905 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
73906 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
73907 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
73908 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
73909 | #define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
73910 | //BIFP6_PCIE_LINK_MANAGEMENT_CNTL |
73911 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
73912 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
73913 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
73914 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
73915 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
73916 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
73917 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
73918 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
73919 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
73920 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
73921 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
73922 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
73923 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
73924 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
73925 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
73926 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
73927 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
73928 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
73929 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
73930 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
73931 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
73932 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
73933 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
73934 | #define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
73935 | //BIFP6_PCIEP_STRAP_LC |
73936 | #define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
73937 | #define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
73938 | #define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
73939 | #define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
73940 | #define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
73941 | #define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
73942 | #define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
73943 | #define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
73944 | #define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
73945 | #define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
73946 | #define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
73947 | #define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
73948 | #define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
73949 | #define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
73950 | #define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
73951 | #define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
73952 | #define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
73953 | #define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
73954 | #define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
73955 | #define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
73956 | #define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
73957 | #define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
73958 | //BIFP6_PCIEP_STRAP_MISC |
73959 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
73960 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
73961 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
73962 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
73963 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
73964 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
73965 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
73966 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
73967 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
73968 | #define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
73969 | //BIFP6_PCIE_LC_L1_PM_SUBSTATE |
73970 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
73971 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
73972 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
73973 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
73974 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
73975 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
73976 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
73977 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
73978 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
73979 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
73980 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
73981 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
73982 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
73983 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
73984 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
73985 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
73986 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
73987 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
73988 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
73989 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
73990 | //BIFP6_PCIE_LC_L1_PM_SUBSTATE2 |
73991 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
73992 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
73993 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
73994 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
73995 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
73996 | #define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
73997 | //BIFP6_PCIE_LC_PORT_ORDER |
73998 | #define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
73999 | #define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
74000 | //BIFP6_PCIEP_BCH_ECC_CNTL |
74001 | #define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
74002 | #define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
74003 | #define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
74004 | #define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
74005 | #define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
74006 | #define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
74007 | //BIFP6_PCIEP_HPGI_PRIVATE |
74008 | #define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 |
74009 | #define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 |
74010 | #define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L |
74011 | #define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L |
74012 | //BIFP6_PCIEP_HPGI |
74013 | #define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 |
74014 | #define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 |
74015 | #define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 |
74016 | #define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 |
74017 | #define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 |
74018 | #define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 |
74019 | #define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 |
74020 | #define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa |
74021 | #define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb |
74022 | #define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf |
74023 | #define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 |
74024 | #define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L |
74025 | #define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L |
74026 | #define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L |
74027 | #define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L |
74028 | #define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L |
74029 | #define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L |
74030 | #define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L |
74031 | #define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L |
74032 | #define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L |
74033 | #define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L |
74034 | #define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L |
74035 | //BIFP6_PCIEP_HCNT_DESCRIPTOR |
74036 | #define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 |
74037 | #define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f |
74038 | #define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL |
74039 | #define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L |
74040 | //BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK |
74041 | #define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 |
74042 | #define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 |
74043 | #define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL |
74044 | #define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L |
74045 | |
74046 | |
74047 | // addressBlock: nbio_pcie0_pciedir |
74048 | //PCIE_RESERVED |
74049 | #define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
74050 | #define PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
74051 | //PCIE_SCRATCH |
74052 | #define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
74053 | #define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
74054 | //PCIE_RX_NUM_NAK |
74055 | #define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 |
74056 | #define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL |
74057 | //PCIE_RX_NUM_NAK_GENERATED |
74058 | #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 |
74059 | #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL |
74060 | //PCIE_CNTL |
74061 | #define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
74062 | #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 |
74063 | #define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
74064 | #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
74065 | #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 |
74066 | #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa |
74067 | #define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf |
74068 | #define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 |
74069 | #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 |
74070 | #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 |
74071 | #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 |
74072 | #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 |
74073 | #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 |
74074 | #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 |
74075 | #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 |
74076 | #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
74077 | #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f |
74078 | #define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
74079 | #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL |
74080 | #define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
74081 | #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
74082 | #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L |
74083 | #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L |
74084 | #define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L |
74085 | #define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L |
74086 | #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L |
74087 | #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L |
74088 | #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L |
74089 | #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L |
74090 | #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L |
74091 | #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L |
74092 | #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L |
74093 | #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
74094 | #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L |
74095 | //PCIE_CONFIG_CNTL |
74096 | #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 |
74097 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8 |
74098 | #define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9 |
74099 | #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
74100 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 |
74101 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 |
74102 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 |
74103 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 |
74104 | #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
74105 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b |
74106 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c |
74107 | #define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e |
74108 | #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL |
74109 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L |
74110 | #define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L |
74111 | #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L |
74112 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L |
74113 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L |
74114 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L |
74115 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L |
74116 | #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
74117 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L |
74118 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L |
74119 | #define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L |
74120 | //PCIE_TX_TRACKING_ADDR_LO |
74121 | #define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2 |
74122 | #define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL |
74123 | //PCIE_TX_TRACKING_ADDR_HI |
74124 | #define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0 |
74125 | #define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL |
74126 | //PCIE_TX_TRACKING_CTRL_STATUS |
74127 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0 |
74128 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1 |
74129 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8 |
74130 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf |
74131 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L |
74132 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL |
74133 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L |
74134 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L |
74135 | //PCIE_BW_BY_UNITID |
74136 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT 0x0 |
74137 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT 0x8 |
74138 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK 0x00000001L |
74139 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK 0x00007F00L |
74140 | //PCIE_CNTL2 |
74141 | #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 |
74142 | #define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 |
74143 | #define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 |
74144 | #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb |
74145 | #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc |
74146 | #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd |
74147 | #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe |
74148 | #define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 |
74149 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 |
74150 | #define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 |
74151 | #define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 |
74152 | #define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 |
74153 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 |
74154 | #define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 |
74155 | #define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 |
74156 | #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 |
74157 | #define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d |
74158 | #define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e |
74159 | #define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f |
74160 | #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L |
74161 | #define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL |
74162 | #define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L |
74163 | #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L |
74164 | #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L |
74165 | #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L |
74166 | #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L |
74167 | #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L |
74168 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L |
74169 | #define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L |
74170 | #define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L |
74171 | #define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L |
74172 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L |
74173 | #define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L |
74174 | #define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L |
74175 | #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L |
74176 | #define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L |
74177 | #define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L |
74178 | #define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L |
74179 | //PCIE_RX_CNTL2 |
74180 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
74181 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 |
74182 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 |
74183 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 |
74184 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 |
74185 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 |
74186 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 |
74187 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 |
74188 | #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc |
74189 | #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd |
74190 | #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe |
74191 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 |
74192 | #define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
74193 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
74194 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L |
74195 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L |
74196 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L |
74197 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L |
74198 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L |
74199 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L |
74200 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L |
74201 | #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L |
74202 | #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L |
74203 | #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L |
74204 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L |
74205 | #define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
74206 | //PCIE_TX_F0_ATTR_CNTL |
74207 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 |
74208 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 |
74209 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 |
74210 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 |
74211 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 |
74212 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa |
74213 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc |
74214 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L |
74215 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL |
74216 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L |
74217 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L |
74218 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L |
74219 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L |
74220 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L |
74221 | //PCIE_TX_SWUS_ATTR_CNTL |
74222 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0 |
74223 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2 |
74224 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4 |
74225 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6 |
74226 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8 |
74227 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa |
74228 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc |
74229 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L |
74230 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL |
74231 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L |
74232 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L |
74233 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L |
74234 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L |
74235 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L |
74236 | //PCIE_CI_CNTL |
74237 | #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 |
74238 | #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 |
74239 | #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 |
74240 | #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 |
74241 | #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 |
74242 | #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 |
74243 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa |
74244 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb |
74245 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc |
74246 | #define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10 |
74247 | #define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11 |
74248 | #define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12 |
74249 | #define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13 |
74250 | #define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14 |
74251 | #define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15 |
74252 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16 |
74253 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17 |
74254 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18 |
74255 | #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L |
74256 | #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L |
74257 | #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L |
74258 | #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L |
74259 | #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L |
74260 | #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L |
74261 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L |
74262 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L |
74263 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L |
74264 | #define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L |
74265 | #define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L |
74266 | #define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L |
74267 | #define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L |
74268 | #define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L |
74269 | #define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L |
74270 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L |
74271 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L |
74272 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L |
74273 | //PCIE_BUS_CNTL |
74274 | #define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 |
74275 | #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
74276 | #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc |
74277 | #define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L |
74278 | #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
74279 | #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L |
74280 | //PCIE_LC_STATE6 |
74281 | #define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 |
74282 | #define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 |
74283 | #define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 |
74284 | #define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 |
74285 | #define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL |
74286 | #define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L |
74287 | #define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L |
74288 | #define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L |
74289 | //PCIE_LC_STATE7 |
74290 | #define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 |
74291 | #define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 |
74292 | #define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 |
74293 | #define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 |
74294 | #define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL |
74295 | #define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L |
74296 | #define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L |
74297 | #define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L |
74298 | //PCIE_LC_STATE8 |
74299 | #define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 |
74300 | #define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 |
74301 | #define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 |
74302 | #define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 |
74303 | #define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL |
74304 | #define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L |
74305 | #define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L |
74306 | #define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L |
74307 | //PCIE_LC_STATE9 |
74308 | #define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 |
74309 | #define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 |
74310 | #define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 |
74311 | #define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 |
74312 | #define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL |
74313 | #define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L |
74314 | #define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L |
74315 | #define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L |
74316 | //PCIE_LC_STATE10 |
74317 | #define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 |
74318 | #define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 |
74319 | #define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 |
74320 | #define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 |
74321 | #define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL |
74322 | #define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L |
74323 | #define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L |
74324 | #define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L |
74325 | //PCIE_LC_STATE11 |
74326 | #define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 |
74327 | #define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 |
74328 | #define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 |
74329 | #define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 |
74330 | #define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL |
74331 | #define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L |
74332 | #define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L |
74333 | #define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L |
74334 | //PCIE_LC_STATUS1 |
74335 | #define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 |
74336 | #define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 |
74337 | #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 |
74338 | #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 |
74339 | #define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L |
74340 | #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L |
74341 | #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL |
74342 | #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L |
74343 | //PCIE_LC_STATUS2 |
74344 | #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 |
74345 | #define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 |
74346 | #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL |
74347 | #define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L |
74348 | //PCIE_WPR_CNTL |
74349 | #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 |
74350 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 |
74351 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 |
74352 | #define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 |
74353 | #define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 |
74354 | #define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 |
74355 | #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 |
74356 | #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L |
74357 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L |
74358 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L |
74359 | #define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L |
74360 | #define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L |
74361 | #define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L |
74362 | #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L |
74363 | //PCIE_RX_LAST_TLP0 |
74364 | #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 |
74365 | #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL |
74366 | //PCIE_RX_LAST_TLP1 |
74367 | #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 |
74368 | #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL |
74369 | //PCIE_RX_LAST_TLP2 |
74370 | #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 |
74371 | #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL |
74372 | //PCIE_RX_LAST_TLP3 |
74373 | #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 |
74374 | #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL |
74375 | //PCIE_TX_LAST_TLP0 |
74376 | #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 |
74377 | #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL |
74378 | //PCIE_TX_LAST_TLP1 |
74379 | #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 |
74380 | #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL |
74381 | //PCIE_TX_LAST_TLP2 |
74382 | #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 |
74383 | #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL |
74384 | //PCIE_TX_LAST_TLP3 |
74385 | #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 |
74386 | #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL |
74387 | //PCIE_I2C_REG_ADDR_EXPAND |
74388 | #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 |
74389 | #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL |
74390 | //PCIE_I2C_REG_DATA |
74391 | #define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 |
74392 | #define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL |
74393 | //PCIE_CFG_CNTL |
74394 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
74395 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
74396 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
74397 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
74398 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
74399 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
74400 | //PCIE_LC_PM_CNTL |
74401 | #define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0 |
74402 | #define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4 |
74403 | #define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8 |
74404 | #define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc |
74405 | #define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10 |
74406 | #define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14 |
74407 | #define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18 |
74408 | #define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c |
74409 | #define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL |
74410 | #define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L |
74411 | #define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L |
74412 | #define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L |
74413 | #define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L |
74414 | #define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L |
74415 | #define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L |
74416 | #define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L |
74417 | //PCIE_LC_PORT_ORDER_CNTL |
74418 | #define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0 |
74419 | #define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L |
74420 | //PCIE_P_CNTL |
74421 | #define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 |
74422 | #define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 |
74423 | #define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 |
74424 | #define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 |
74425 | #define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 |
74426 | #define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 |
74427 | #define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 |
74428 | #define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc |
74429 | #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd |
74430 | #define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe |
74431 | #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 |
74432 | #define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11 |
74433 | #define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L |
74434 | #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L |
74435 | #define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L |
74436 | #define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L |
74437 | #define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L |
74438 | #define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L |
74439 | #define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L |
74440 | #define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L |
74441 | #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L |
74442 | #define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L |
74443 | #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L |
74444 | #define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L |
74445 | //PCIE_P_BUF_STATUS |
74446 | #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 |
74447 | #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 |
74448 | #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL |
74449 | #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L |
74450 | //PCIE_P_DECODER_STATUS |
74451 | #define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 |
74452 | #define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL |
74453 | //PCIE_P_MISC_STATUS |
74454 | #define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 |
74455 | #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 |
74456 | #define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL |
74457 | #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L |
74458 | //PCIE_P_RCV_L0S_FTS_DET |
74459 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 |
74460 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 |
74461 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL |
74462 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L |
74463 | //PCIE_RX_AD |
74464 | #define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0 |
74465 | #define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1 |
74466 | #define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2 |
74467 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3 |
74468 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4 |
74469 | #define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5 |
74470 | #define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8 |
74471 | #define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9 |
74472 | #define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa |
74473 | #define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb |
74474 | #define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc |
74475 | #define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd |
74476 | #define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe |
74477 | #define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf |
74478 | #define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L |
74479 | #define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L |
74480 | #define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L |
74481 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L |
74482 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L |
74483 | #define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L |
74484 | #define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L |
74485 | #define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L |
74486 | #define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L |
74487 | #define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L |
74488 | #define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L |
74489 | #define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L |
74490 | #define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L |
74491 | #define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L |
74492 | //PCIE_SDP_CTRL |
74493 | #define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0 |
74494 | #define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4 |
74495 | #define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5 |
74496 | #define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6 |
74497 | #define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7 |
74498 | #define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8 |
74499 | #define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9 |
74500 | #define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa |
74501 | #define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb |
74502 | #define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc |
74503 | #define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd |
74504 | #define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe |
74505 | #define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf |
74506 | #define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL |
74507 | #define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L |
74508 | #define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L |
74509 | #define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L |
74510 | #define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L |
74511 | #define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L |
74512 | #define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L |
74513 | #define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L |
74514 | #define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L |
74515 | #define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L |
74516 | #define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L |
74517 | #define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L |
74518 | #define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L |
74519 | //NBIO_CLKREQb_MAP_CNTL |
74520 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP__SHIFT 0x0 |
74521 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP__SHIFT 0x4 |
74522 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP__SHIFT 0x8 |
74523 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP__SHIFT 0xc |
74524 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP__SHIFT 0x10 |
74525 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK__SHIFT 0x1c |
74526 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP_MASK 0x0000000FL |
74527 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP_MASK 0x000000F0L |
74528 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP_MASK 0x00000F00L |
74529 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP_MASK 0x0000F000L |
74530 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP_MASK 0x000F0000L |
74531 | #define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK_MASK 0x10000000L |
74532 | //PCIE_SDP_SWUS_SLV_ATTR_CTRL |
74533 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0 |
74534 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2 |
74535 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4 |
74536 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6 |
74537 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8 |
74538 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa |
74539 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc |
74540 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe |
74541 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10 |
74542 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L |
74543 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL |
74544 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L |
74545 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L |
74546 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L |
74547 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L |
74548 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L |
74549 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L |
74550 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L |
74551 | //PCIE_SDP_RC_SLV_ATTR_CTRL |
74552 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0 |
74553 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2 |
74554 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4 |
74555 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6 |
74556 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8 |
74557 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa |
74558 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc |
74559 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe |
74560 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10 |
74561 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L |
74562 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL |
74563 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L |
74564 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L |
74565 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L |
74566 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L |
74567 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L |
74568 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L |
74569 | #define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L |
74570 | //PCIE_PERF_COUNT_CNTL |
74571 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 |
74572 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 |
74573 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 |
74574 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L |
74575 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L |
74576 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L |
74577 | //PCIE_PERF_CNTL_TXCLK |
74578 | #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 |
74579 | #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 |
74580 | #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 |
74581 | #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 |
74582 | #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000FFL |
74583 | #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000FF00L |
74584 | #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00FF0000L |
74585 | #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xFF000000L |
74586 | //PCIE_PERF_COUNT0_TXCLK |
74587 | #define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 |
74588 | #define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xFFFFFFFFL |
74589 | //PCIE_PERF_COUNT1_TXCLK |
74590 | #define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 |
74591 | #define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xFFFFFFFFL |
74592 | //PCIE_PERF_CNTL_MST_R_CLK |
74593 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 |
74594 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 |
74595 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 |
74596 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 |
74597 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000FFL |
74598 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000FF00L |
74599 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L |
74600 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L |
74601 | //PCIE_PERF_COUNT0_MST_R_CLK |
74602 | #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 |
74603 | #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xFFFFFFFFL |
74604 | //PCIE_PERF_COUNT1_MST_R_CLK |
74605 | #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 |
74606 | #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xFFFFFFFFL |
74607 | //PCIE_PERF_CNTL_MST_C_CLK |
74608 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 |
74609 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 |
74610 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 |
74611 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 |
74612 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000FFL |
74613 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000FF00L |
74614 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L |
74615 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L |
74616 | //PCIE_PERF_COUNT0_MST_C_CLK |
74617 | #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 |
74618 | #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xFFFFFFFFL |
74619 | //PCIE_PERF_COUNT1_MST_C_CLK |
74620 | #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 |
74621 | #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xFFFFFFFFL |
74622 | //PCIE_PERF_CNTL_SLV_R_CLK |
74623 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 |
74624 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 |
74625 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 |
74626 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 |
74627 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000FFL |
74628 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000FF00L |
74629 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L |
74630 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L |
74631 | //PCIE_PERF_COUNT0_SLV_R_CLK |
74632 | #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 |
74633 | #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xFFFFFFFFL |
74634 | //PCIE_PERF_COUNT1_SLV_R_CLK |
74635 | #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 |
74636 | #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xFFFFFFFFL |
74637 | //PCIE_PERF_CNTL_SLV_S_C_CLK |
74638 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 |
74639 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 |
74640 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 |
74641 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 |
74642 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000FFL |
74643 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000FF00L |
74644 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L |
74645 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L |
74646 | //PCIE_PERF_COUNT0_SLV_S_C_CLK |
74647 | #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 |
74648 | #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xFFFFFFFFL |
74649 | //PCIE_PERF_COUNT1_SLV_S_C_CLK |
74650 | #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 |
74651 | #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xFFFFFFFFL |
74652 | //PCIE_PERF_CNTL_SLV_NS_C_CLK |
74653 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 |
74654 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 |
74655 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 |
74656 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 |
74657 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000FFL |
74658 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000FF00L |
74659 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L |
74660 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L |
74661 | //PCIE_PERF_COUNT0_SLV_NS_C_CLK |
74662 | #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 |
74663 | #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xFFFFFFFFL |
74664 | //PCIE_PERF_COUNT1_SLV_NS_C_CLK |
74665 | #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 |
74666 | #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xFFFFFFFFL |
74667 | //PCIE_PERF_CNTL_EVENT0_PORT_SEL |
74668 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 |
74669 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 |
74670 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 |
74671 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc |
74672 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 |
74673 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 |
74674 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 |
74675 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000FL |
74676 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000F0L |
74677 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000F00L |
74678 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L |
74679 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L |
74680 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L |
74681 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0F000000L |
74682 | //PCIE_PERF_CNTL_EVENT1_PORT_SEL |
74683 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 |
74684 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 |
74685 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 |
74686 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc |
74687 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 |
74688 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 |
74689 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 |
74690 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000FL |
74691 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000F0L |
74692 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000F00L |
74693 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L |
74694 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L |
74695 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L |
74696 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0F000000L |
74697 | //PCIE_PERF_CNTL_TXCLK2 |
74698 | #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 |
74699 | #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 |
74700 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 |
74701 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 |
74702 | #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL |
74703 | #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L |
74704 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L |
74705 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L |
74706 | //PCIE_PERF_COUNT0_TXCLK2 |
74707 | #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 |
74708 | #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL |
74709 | //PCIE_PERF_COUNT1_TXCLK2 |
74710 | #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 |
74711 | #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL |
74712 | //PCIE_PERF_CNTL_TXCLK3 |
74713 | #define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0 |
74714 | #define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8 |
74715 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10 |
74716 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18 |
74717 | #define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL |
74718 | #define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L |
74719 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L |
74720 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L |
74721 | //PCIE_PERF_COUNT0_TXCLK3 |
74722 | #define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0 |
74723 | #define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL |
74724 | //PCIE_PERF_COUNT1_TXCLK3 |
74725 | #define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0 |
74726 | #define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL |
74727 | //PCIE_PERF_CNTL_TXCLK4 |
74728 | #define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0 |
74729 | #define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8 |
74730 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10 |
74731 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18 |
74732 | #define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL |
74733 | #define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L |
74734 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L |
74735 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L |
74736 | //PCIE_PERF_COUNT0_TXCLK4 |
74737 | #define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0 |
74738 | #define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL |
74739 | //PCIE_PERF_COUNT1_TXCLK4 |
74740 | #define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0 |
74741 | #define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL |
74742 | //PCIE_PRBS_CLR |
74743 | #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 |
74744 | #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 |
74745 | #define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL |
74746 | #define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L |
74747 | //PCIE_PRBS_STATUS1 |
74748 | #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 |
74749 | #define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 |
74750 | #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL |
74751 | #define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L |
74752 | //PCIE_PRBS_STATUS2 |
74753 | #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 |
74754 | #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL |
74755 | //PCIE_PRBS_FREERUN |
74756 | #define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 |
74757 | #define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL |
74758 | //PCIE_PRBS_MISC |
74759 | #define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 |
74760 | #define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 |
74761 | #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 |
74762 | #define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 |
74763 | #define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 |
74764 | #define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 |
74765 | #define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe |
74766 | #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 |
74767 | #define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L |
74768 | #define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL |
74769 | #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L |
74770 | #define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L |
74771 | #define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L |
74772 | #define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L |
74773 | #define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L |
74774 | #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L |
74775 | //PCIE_PRBS_USER_PATTERN |
74776 | #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 |
74777 | #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL |
74778 | //PCIE_PRBS_LO_BITCNT |
74779 | #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 |
74780 | #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL |
74781 | //PCIE_PRBS_HI_BITCNT |
74782 | #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 |
74783 | #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL |
74784 | //PCIE_PRBS_ERRCNT_0 |
74785 | #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 |
74786 | #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL |
74787 | //PCIE_PRBS_ERRCNT_1 |
74788 | #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 |
74789 | #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL |
74790 | //PCIE_PRBS_ERRCNT_2 |
74791 | #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 |
74792 | #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL |
74793 | //PCIE_PRBS_ERRCNT_3 |
74794 | #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 |
74795 | #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL |
74796 | //PCIE_PRBS_ERRCNT_4 |
74797 | #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 |
74798 | #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL |
74799 | //PCIE_PRBS_ERRCNT_5 |
74800 | #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 |
74801 | #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL |
74802 | //PCIE_PRBS_ERRCNT_6 |
74803 | #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 |
74804 | #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL |
74805 | //PCIE_PRBS_ERRCNT_7 |
74806 | #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 |
74807 | #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL |
74808 | //PCIE_PRBS_ERRCNT_8 |
74809 | #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 |
74810 | #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL |
74811 | //PCIE_PRBS_ERRCNT_9 |
74812 | #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 |
74813 | #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL |
74814 | //PCIE_PRBS_ERRCNT_10 |
74815 | #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 |
74816 | #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL |
74817 | //PCIE_PRBS_ERRCNT_11 |
74818 | #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 |
74819 | #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL |
74820 | //PCIE_PRBS_ERRCNT_12 |
74821 | #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 |
74822 | #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL |
74823 | //PCIE_PRBS_ERRCNT_13 |
74824 | #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 |
74825 | #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL |
74826 | //PCIE_PRBS_ERRCNT_14 |
74827 | #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 |
74828 | #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL |
74829 | //PCIE_PRBS_ERRCNT_15 |
74830 | #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 |
74831 | #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL |
74832 | //SWRST_COMMAND_STATUS |
74833 | #define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 |
74834 | #define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 |
74835 | #define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 |
74836 | #define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 |
74837 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18 |
74838 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19 |
74839 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a |
74840 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b |
74841 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c |
74842 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d |
74843 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e |
74844 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f |
74845 | #define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L |
74846 | #define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L |
74847 | #define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L |
74848 | #define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L |
74849 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L |
74850 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L |
74851 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L |
74852 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L |
74853 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L |
74854 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L |
74855 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L |
74856 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L |
74857 | //SWRST_GENERAL_CONTROL |
74858 | #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 |
74859 | #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 |
74860 | #define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 |
74861 | #define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 |
74862 | #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 |
74863 | #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa |
74864 | #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc |
74865 | #define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT 0x11 |
74866 | #define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18 |
74867 | #define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19 |
74868 | #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L |
74869 | #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L |
74870 | #define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL |
74871 | #define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L |
74872 | #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L |
74873 | #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L |
74874 | #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L |
74875 | #define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK 0x00020000L |
74876 | #define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L |
74877 | #define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L |
74878 | //SWRST_COMMAND_0 |
74879 | #define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0 |
74880 | #define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8 |
74881 | #define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9 |
74882 | #define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa |
74883 | #define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb |
74884 | #define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc |
74885 | #define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd |
74886 | #define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe |
74887 | #define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf |
74888 | #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18 |
74889 | #define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19 |
74890 | #define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a |
74891 | #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b |
74892 | #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c |
74893 | #define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d |
74894 | #define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e |
74895 | #define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L |
74896 | #define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L |
74897 | #define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L |
74898 | #define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L |
74899 | #define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L |
74900 | #define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L |
74901 | #define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L |
74902 | #define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L |
74903 | #define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L |
74904 | #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L |
74905 | #define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L |
74906 | #define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L |
74907 | #define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L |
74908 | #define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L |
74909 | #define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L |
74910 | #define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L |
74911 | //SWRST_COMMAND_1 |
74912 | #define SWRST_COMMAND_1__RESETPCS0__SHIFT 0x0 |
74913 | #define SWRST_COMMAND_1__RESETPCS1__SHIFT 0x1 |
74914 | #define SWRST_COMMAND_1__RESETPCS2__SHIFT 0x2 |
74915 | #define SWRST_COMMAND_1__RESETPCS3__SHIFT 0x3 |
74916 | #define SWRST_COMMAND_1__RESETPCS4__SHIFT 0x4 |
74917 | #define SWRST_COMMAND_1__RESETPCS5__SHIFT 0x5 |
74918 | #define SWRST_COMMAND_1__RESETPCS6__SHIFT 0x6 |
74919 | #define SWRST_COMMAND_1__RESETPCS7__SHIFT 0x7 |
74920 | #define SWRST_COMMAND_1__RESETPCS8__SHIFT 0x8 |
74921 | #define SWRST_COMMAND_1__RESETPCS9__SHIFT 0x9 |
74922 | #define SWRST_COMMAND_1__RESETPCS10__SHIFT 0xa |
74923 | #define SWRST_COMMAND_1__RESETPCS11__SHIFT 0xb |
74924 | #define SWRST_COMMAND_1__RESETPCS12__SHIFT 0xc |
74925 | #define SWRST_COMMAND_1__RESETPCS13__SHIFT 0xd |
74926 | #define SWRST_COMMAND_1__RESETPCS14__SHIFT 0xe |
74927 | #define SWRST_COMMAND_1__RESETPCS15__SHIFT 0xf |
74928 | #define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15 |
74929 | #define SWRST_COMMAND_1__RESETAXIMST__SHIFT 0x16 |
74930 | #define SWRST_COMMAND_1__RESETAXISLV__SHIFT 0x17 |
74931 | #define SWRST_COMMAND_1__RESETAXIINT__SHIFT 0x18 |
74932 | #define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19 |
74933 | #define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a |
74934 | #define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b |
74935 | #define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c |
74936 | #define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d |
74937 | #define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e |
74938 | #define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f |
74939 | #define SWRST_COMMAND_1__RESETPCS0_MASK 0x00000001L |
74940 | #define SWRST_COMMAND_1__RESETPCS1_MASK 0x00000002L |
74941 | #define SWRST_COMMAND_1__RESETPCS2_MASK 0x00000004L |
74942 | #define SWRST_COMMAND_1__RESETPCS3_MASK 0x00000008L |
74943 | #define SWRST_COMMAND_1__RESETPCS4_MASK 0x00000010L |
74944 | #define SWRST_COMMAND_1__RESETPCS5_MASK 0x00000020L |
74945 | #define SWRST_COMMAND_1__RESETPCS6_MASK 0x00000040L |
74946 | #define SWRST_COMMAND_1__RESETPCS7_MASK 0x00000080L |
74947 | #define SWRST_COMMAND_1__RESETPCS8_MASK 0x00000100L |
74948 | #define SWRST_COMMAND_1__RESETPCS9_MASK 0x00000200L |
74949 | #define SWRST_COMMAND_1__RESETPCS10_MASK 0x00000400L |
74950 | #define SWRST_COMMAND_1__RESETPCS11_MASK 0x00000800L |
74951 | #define SWRST_COMMAND_1__RESETPCS12_MASK 0x00001000L |
74952 | #define SWRST_COMMAND_1__RESETPCS13_MASK 0x00002000L |
74953 | #define SWRST_COMMAND_1__RESETPCS14_MASK 0x00004000L |
74954 | #define SWRST_COMMAND_1__RESETPCS15_MASK 0x00008000L |
74955 | #define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L |
74956 | #define SWRST_COMMAND_1__RESETAXIMST_MASK 0x00400000L |
74957 | #define SWRST_COMMAND_1__RESETAXISLV_MASK 0x00800000L |
74958 | #define SWRST_COMMAND_1__RESETAXIINT_MASK 0x01000000L |
74959 | #define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L |
74960 | #define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L |
74961 | #define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L |
74962 | #define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L |
74963 | #define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L |
74964 | #define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L |
74965 | #define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L |
74966 | //SWRST_CONTROL_0 |
74967 | #define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0 |
74968 | #define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8 |
74969 | #define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9 |
74970 | #define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa |
74971 | #define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb |
74972 | #define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc |
74973 | #define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd |
74974 | #define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe |
74975 | #define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf |
74976 | #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18 |
74977 | #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19 |
74978 | #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a |
74979 | #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b |
74980 | #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c |
74981 | #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d |
74982 | #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e |
74983 | #define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L |
74984 | #define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L |
74985 | #define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L |
74986 | #define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L |
74987 | #define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L |
74988 | #define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L |
74989 | #define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L |
74990 | #define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L |
74991 | #define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L |
74992 | #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L |
74993 | #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L |
74994 | #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L |
74995 | #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L |
74996 | #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L |
74997 | #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L |
74998 | #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L |
74999 | //SWRST_CONTROL_1 |
75000 | #define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT 0x0 |
75001 | #define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT 0x1 |
75002 | #define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT 0x2 |
75003 | #define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT 0x3 |
75004 | #define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT 0x4 |
75005 | #define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT 0x5 |
75006 | #define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT 0x6 |
75007 | #define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT 0x7 |
75008 | #define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT 0x8 |
75009 | #define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT 0x9 |
75010 | #define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT 0xa |
75011 | #define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT 0xb |
75012 | #define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT 0xc |
75013 | #define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT 0xd |
75014 | #define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT 0xe |
75015 | #define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT 0xf |
75016 | #define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15 |
75017 | #define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT 0x16 |
75018 | #define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT 0x17 |
75019 | #define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT 0x18 |
75020 | #define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19 |
75021 | #define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a |
75022 | #define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b |
75023 | #define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c |
75024 | #define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d |
75025 | #define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e |
75026 | #define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f |
75027 | #define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK 0x00000001L |
75028 | #define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK 0x00000002L |
75029 | #define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK 0x00000004L |
75030 | #define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK 0x00000008L |
75031 | #define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK 0x00000010L |
75032 | #define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK 0x00000020L |
75033 | #define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK 0x00000040L |
75034 | #define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK 0x00000080L |
75035 | #define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK 0x00000100L |
75036 | #define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK 0x00000200L |
75037 | #define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK 0x00000400L |
75038 | #define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK 0x00000800L |
75039 | #define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK 0x00001000L |
75040 | #define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK 0x00002000L |
75041 | #define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK 0x00004000L |
75042 | #define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK 0x00008000L |
75043 | #define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L |
75044 | #define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK 0x00400000L |
75045 | #define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK 0x00800000L |
75046 | #define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK 0x01000000L |
75047 | #define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L |
75048 | #define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L |
75049 | #define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L |
75050 | #define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L |
75051 | #define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L |
75052 | #define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L |
75053 | #define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L |
75054 | //SWRST_CONTROL_2 |
75055 | #define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0 |
75056 | #define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8 |
75057 | #define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9 |
75058 | #define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa |
75059 | #define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb |
75060 | #define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc |
75061 | #define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd |
75062 | #define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe |
75063 | #define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf |
75064 | #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18 |
75065 | #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19 |
75066 | #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a |
75067 | #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b |
75068 | #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c |
75069 | #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d |
75070 | #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e |
75071 | #define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L |
75072 | #define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L |
75073 | #define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L |
75074 | #define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L |
75075 | #define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L |
75076 | #define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L |
75077 | #define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L |
75078 | #define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L |
75079 | #define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L |
75080 | #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L |
75081 | #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L |
75082 | #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L |
75083 | #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L |
75084 | #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L |
75085 | #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L |
75086 | #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L |
75087 | //SWRST_CONTROL_3 |
75088 | #define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT 0x0 |
75089 | #define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT 0x1 |
75090 | #define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT 0x2 |
75091 | #define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT 0x3 |
75092 | #define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT 0x4 |
75093 | #define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT 0x5 |
75094 | #define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT 0x6 |
75095 | #define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT 0x7 |
75096 | #define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT 0x8 |
75097 | #define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT 0x9 |
75098 | #define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT 0xa |
75099 | #define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT 0xb |
75100 | #define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT 0xc |
75101 | #define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT 0xd |
75102 | #define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT 0xe |
75103 | #define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT 0xf |
75104 | #define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15 |
75105 | #define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT 0x16 |
75106 | #define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT 0x17 |
75107 | #define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT 0x18 |
75108 | #define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19 |
75109 | #define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a |
75110 | #define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b |
75111 | #define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c |
75112 | #define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d |
75113 | #define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e |
75114 | #define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f |
75115 | #define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK 0x00000001L |
75116 | #define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK 0x00000002L |
75117 | #define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK 0x00000004L |
75118 | #define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK 0x00000008L |
75119 | #define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK 0x00000010L |
75120 | #define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK 0x00000020L |
75121 | #define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK 0x00000040L |
75122 | #define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK 0x00000080L |
75123 | #define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK 0x00000100L |
75124 | #define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK 0x00000200L |
75125 | #define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK 0x00000400L |
75126 | #define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK 0x00000800L |
75127 | #define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK 0x00001000L |
75128 | #define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK 0x00002000L |
75129 | #define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK 0x00004000L |
75130 | #define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK 0x00008000L |
75131 | #define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L |
75132 | #define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK 0x00400000L |
75133 | #define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK 0x00800000L |
75134 | #define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK 0x01000000L |
75135 | #define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L |
75136 | #define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L |
75137 | #define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L |
75138 | #define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L |
75139 | #define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L |
75140 | #define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L |
75141 | #define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L |
75142 | //SWRST_CONTROL_4 |
75143 | #define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0 |
75144 | #define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8 |
75145 | #define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9 |
75146 | #define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa |
75147 | #define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb |
75148 | #define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc |
75149 | #define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd |
75150 | #define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe |
75151 | #define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf |
75152 | #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18 |
75153 | #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19 |
75154 | #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a |
75155 | #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b |
75156 | #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c |
75157 | #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d |
75158 | #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e |
75159 | #define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L |
75160 | #define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L |
75161 | #define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L |
75162 | #define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L |
75163 | #define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L |
75164 | #define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L |
75165 | #define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L |
75166 | #define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L |
75167 | #define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L |
75168 | #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L |
75169 | #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L |
75170 | #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L |
75171 | #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L |
75172 | #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L |
75173 | #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L |
75174 | #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L |
75175 | //SWRST_CONTROL_5 |
75176 | #define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT 0x0 |
75177 | #define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT 0x1 |
75178 | #define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT 0x2 |
75179 | #define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT 0x3 |
75180 | #define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT 0x4 |
75181 | #define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT 0x5 |
75182 | #define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT 0x6 |
75183 | #define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT 0x7 |
75184 | #define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT 0x8 |
75185 | #define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT 0x9 |
75186 | #define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT 0xa |
75187 | #define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT 0xb |
75188 | #define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT 0xc |
75189 | #define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT 0xd |
75190 | #define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT 0xe |
75191 | #define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT 0xf |
75192 | #define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15 |
75193 | #define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT 0x16 |
75194 | #define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT 0x17 |
75195 | #define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT 0x18 |
75196 | #define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19 |
75197 | #define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a |
75198 | #define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b |
75199 | #define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c |
75200 | #define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d |
75201 | #define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e |
75202 | #define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f |
75203 | #define SWRST_CONTROL_5__PCSRESET0_WREN_MASK 0x00000001L |
75204 | #define SWRST_CONTROL_5__PCSRESET1_WREN_MASK 0x00000002L |
75205 | #define SWRST_CONTROL_5__PCSRESET2_WREN_MASK 0x00000004L |
75206 | #define SWRST_CONTROL_5__PCSRESET3_WREN_MASK 0x00000008L |
75207 | #define SWRST_CONTROL_5__PCSRESET4_WREN_MASK 0x00000010L |
75208 | #define SWRST_CONTROL_5__PCSRESET5_WREN_MASK 0x00000020L |
75209 | #define SWRST_CONTROL_5__PCSRESET6_WREN_MASK 0x00000040L |
75210 | #define SWRST_CONTROL_5__PCSRESET7_WREN_MASK 0x00000080L |
75211 | #define SWRST_CONTROL_5__PCSRESET8_WREN_MASK 0x00000100L |
75212 | #define SWRST_CONTROL_5__PCSRESET9_WREN_MASK 0x00000200L |
75213 | #define SWRST_CONTROL_5__PCSRESET10_WREN_MASK 0x00000400L |
75214 | #define SWRST_CONTROL_5__PCSRESET11_WREN_MASK 0x00000800L |
75215 | #define SWRST_CONTROL_5__PCSRESET12_WREN_MASK 0x00001000L |
75216 | #define SWRST_CONTROL_5__PCSRESET13_WREN_MASK 0x00002000L |
75217 | #define SWRST_CONTROL_5__PCSRESET14_WREN_MASK 0x00004000L |
75218 | #define SWRST_CONTROL_5__PCSRESET15_WREN_MASK 0x00008000L |
75219 | #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L |
75220 | #define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK 0x00400000L |
75221 | #define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK 0x00800000L |
75222 | #define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK 0x01000000L |
75223 | #define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L |
75224 | #define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L |
75225 | #define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L |
75226 | #define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L |
75227 | #define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L |
75228 | #define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L |
75229 | #define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L |
75230 | //SWRST_CONTROL_6 |
75231 | #define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0 |
75232 | #define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1 |
75233 | #define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2 |
75234 | #define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3 |
75235 | #define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4 |
75236 | #define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5 |
75237 | #define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6 |
75238 | #define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7 |
75239 | #define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8 |
75240 | #define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9 |
75241 | #define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa |
75242 | #define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L |
75243 | #define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L |
75244 | #define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L |
75245 | #define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L |
75246 | #define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L |
75247 | #define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L |
75248 | #define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L |
75249 | #define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L |
75250 | #define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L |
75251 | #define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L |
75252 | #define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L |
75253 | //SWRST_EP_COMMAND_0 |
75254 | #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 |
75255 | #define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 |
75256 | #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 |
75257 | #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa |
75258 | #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L |
75259 | #define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L |
75260 | #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L |
75261 | #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L |
75262 | //SWRST_EP_CONTROL_0 |
75263 | #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 |
75264 | #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 |
75265 | #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 |
75266 | #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa |
75267 | #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L |
75268 | #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L |
75269 | #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L |
75270 | #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L |
75271 | //CPM_CONTROL |
75272 | #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 |
75273 | #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 |
75274 | #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 |
75275 | #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 |
75276 | #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 |
75277 | #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 |
75278 | #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 |
75279 | #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 |
75280 | #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb |
75281 | #define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xc |
75282 | #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe |
75283 | #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf |
75284 | #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10 |
75285 | #define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11 |
75286 | #define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12 |
75287 | #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 |
75288 | #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 |
75289 | #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18 |
75290 | #define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19 |
75291 | #define CPM_CONTROL__SPARE_REGS__SHIFT 0x1a |
75292 | #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L |
75293 | #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L |
75294 | #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x00000004L |
75295 | #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L |
75296 | #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L |
75297 | #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L |
75298 | #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L |
75299 | #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L |
75300 | #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00000800L |
75301 | #define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x00003000L |
75302 | #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L |
75303 | #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L |
75304 | #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L |
75305 | #define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L |
75306 | #define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L |
75307 | #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L |
75308 | #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L |
75309 | #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L |
75310 | #define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L |
75311 | #define CPM_CONTROL__SPARE_REGS_MASK 0xFC000000L |
75312 | //SMN_APERTURE_ID_A |
75313 | #define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0 |
75314 | #define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT 0xc |
75315 | #define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL |
75316 | #define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK 0x00FFF000L |
75317 | //SMN_APERTURE_ID_B |
75318 | #define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0 |
75319 | #define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc |
75320 | #define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL |
75321 | #define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L |
75322 | //RSMU_MASTER_CONTROL |
75323 | #define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE__SHIFT 0x0 |
75324 | #define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE_MASK 0x00000001L |
75325 | //RSMU_SLAVE_CONTROL |
75326 | #define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO__SHIFT 0x0 |
75327 | #define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE__SHIFT 0x2 |
75328 | #define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO_MASK 0x00000001L |
75329 | #define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE_MASK 0x00000004L |
75330 | //RSMU_POWER_GATING_CONTROL |
75331 | #define RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY__SHIFT 0x0 |
75332 | #define RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY__SHIFT 0x1 |
75333 | #define RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY_MASK 0x00000001L |
75334 | #define RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY_MASK 0x00000002L |
75335 | //RSMU_BIOS_TIMER_CMD |
75336 | #define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS__SHIFT 0x0 |
75337 | #define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS_MASK 0xFFFFFFFFL |
75338 | //RSMU_BIOS_TIMER_CNTL |
75339 | #define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE__SHIFT 0x0 |
75340 | #define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE_MASK 0x000000FFL |
75341 | //LNCNT_CONTROL |
75342 | #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0 |
75343 | #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1 |
75344 | #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2 |
75345 | #define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3 |
75346 | #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4 |
75347 | #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L |
75348 | #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L |
75349 | #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L |
75350 | #define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L |
75351 | #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L |
75352 | //CFG_LNC_WINDOW_REGISTER |
75353 | #define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW__SHIFT 0x0 |
75354 | #define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW_MASK 0x00FFFFFFL |
75355 | //LNCNT_QUAN_THRD |
75356 | #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0 |
75357 | #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4 |
75358 | #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L |
75359 | #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L |
75360 | //LNCNT_WEIGHT |
75361 | #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0 |
75362 | #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10 |
75363 | #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL |
75364 | #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L |
75365 | //LNC_TOTAL_WACC_REGISTER |
75366 | #define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC__SHIFT 0x0 |
75367 | #define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC_MASK 0xFFFFFFFFL |
75368 | //LNC_BW_WACC_REGISTER |
75369 | #define LNC_BW_WACC_REGISTER__LNC_BW_WACC__SHIFT 0x0 |
75370 | #define LNC_BW_WACC_REGISTER__LNC_BW_WACC_MASK 0xFFFFFFFFL |
75371 | //LNC_CMN_WACC_REGISTER |
75372 | #define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC__SHIFT 0x0 |
75373 | #define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC_MASK 0xFFFFFFFFL |
75374 | //SMU_HP_STATUS_UPDATE |
75375 | #define SMU_HP_STATUS_UPDATE__SMU_HP_STATUS__SHIFT 0x0 |
75376 | #define SMU_HP_STATUS_UPDATE__SMU_HP_STATUS_MASK 0xFFFFFFFFL |
75377 | //HP_SMU_COMMAND_UPDATE |
75378 | #define HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND__SHIFT 0x0 |
75379 | #define HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND_MASK 0xFFFFFFFFL |
75380 | //SMU_HP_END_OF_INTERRUPT |
75381 | #define SMU_HP_END_OF_INTERRUPT__SMU_HP_EOI__SHIFT 0x0 |
75382 | #define SMU_HP_END_OF_INTERRUPT__SMU_HP_EOI_MASK 0x00000001L |
75383 | //SMU_INT_PIN_SHARING_PORT_INDICATOR |
75384 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0 |
75385 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x8 |
75386 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT 0x10 |
75387 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x000000FFL |
75388 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0x0000FF00L |
75389 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK 0x00FF0000L |
75390 | //PCIE_PGMST_CNTL |
75391 | #define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 |
75392 | #define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 |
75393 | #define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
75394 | #define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe |
75395 | #define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL |
75396 | #define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L |
75397 | #define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
75398 | #define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L |
75399 | //PCIE_PGSLV_CNTL |
75400 | #define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
75401 | #define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
75402 | //SMU_PCIE_FENCED1_REG |
75403 | #define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x0 |
75404 | #define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x00000001L |
75405 | //SMU_PCIE_FENCED2_REG |
75406 | |
75407 | |
75408 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
75409 | //NB_NBCFG1_NB_VENDOR_ID |
75410 | #define NB_NBCFG1_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
75411 | #define NB_NBCFG1_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
75412 | //NB_NBCFG1_NB_DEVICE_ID |
75413 | #define NB_NBCFG1_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
75414 | #define NB_NBCFG1_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
75415 | //NB_NBCFG1_NB_COMMAND |
75416 | #define NB_NBCFG1_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75417 | #define NB_NBCFG1_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75418 | #define NB_NBCFG1_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75419 | #define NB_NBCFG1_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75420 | #define NB_NBCFG1_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75421 | #define NB_NBCFG1_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75422 | //NB_NBCFG1_NB_STATUS |
75423 | #define NB_NBCFG1_NB_STATUS__CAP_LIST__SHIFT 0x4 |
75424 | #define NB_NBCFG1_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
75425 | #define NB_NBCFG1_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
75426 | #define NB_NBCFG1_NB_STATUS__CAP_LIST_MASK 0x0010L |
75427 | #define NB_NBCFG1_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
75428 | #define NB_NBCFG1_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
75429 | //NB_NBCFG1_NB_REVISION_ID |
75430 | #define NB_NBCFG1_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
75431 | #define NB_NBCFG1_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
75432 | #define NB_NBCFG1_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
75433 | #define NB_NBCFG1_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
75434 | //NB_NBCFG1_NB_REGPROG_INF |
75435 | #define NB_NBCFG1_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 |
75436 | #define NB_NBCFG1_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL |
75437 | //NB_NBCFG1_NB_SUB_CLASS |
75438 | #define NB_NBCFG1_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
75439 | #define NB_NBCFG1_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
75440 | //NB_NBCFG1_NB_BASE_CODE |
75441 | #define NB_NBCFG1_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
75442 | #define NB_NBCFG1_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
75443 | //NB_NBCFG1_NB_CACHE_LINE |
75444 | #define NB_NBCFG1_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
75445 | #define NB_NBCFG1_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
75446 | //NB_NBCFG1_NB_LATENCY |
75447 | #define NB_NBCFG1_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
75448 | #define NB_NBCFG1_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL |
75449 | //NB_NBCFG1_NB_HEADER |
75450 | #define NB_NBCFG1_NB_HEADER__HEADER_TYPE__SHIFT 0x0 |
75451 | #define NB_NBCFG1_NB_HEADER__DEVICE_TYPE__SHIFT 0x7 |
75452 | #define NB_NBCFG1_NB_HEADER__HEADER_TYPE_MASK 0x7FL |
75453 | #define NB_NBCFG1_NB_HEADER__DEVICE_TYPE_MASK 0x80L |
75454 | //NB_NBCFG1_NB_ADAPTER_ID |
75455 | #define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
75456 | #define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
75457 | #define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
75458 | #define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
75459 | //NB_NBCFG1_NB_CAPABILITIES_PTR |
75460 | #define NB_NBCFG1_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
75461 | #define NB_NBCFG1_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
75462 | //NB_NBCFG1_NB_HEADER_W |
75463 | #define NB_NBCFG1_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7 |
75464 | #define NB_NBCFG1_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L |
75465 | //NB_NBCFG1_NB_PCI_CTRL |
75466 | #define NB_NBCFG1_NB_PCI_CTRL__PMEDis__SHIFT 0x4 |
75467 | #define NB_NBCFG1_NB_PCI_CTRL__SErrDis__SHIFT 0x5 |
75468 | #define NB_NBCFG1_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 |
75469 | #define NB_NBCFG1_NB_PCI_CTRL__HPDis__SHIFT 0x1a |
75470 | #define NB_NBCFG1_NB_PCI_CTRL__PMEDis_MASK 0x00000010L |
75471 | #define NB_NBCFG1_NB_PCI_CTRL__SErrDis_MASK 0x00000020L |
75472 | #define NB_NBCFG1_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L |
75473 | #define NB_NBCFG1_NB_PCI_CTRL__HPDis_MASK 0x04000000L |
75474 | //NB_NBCFG1_NB_ADAPTER_ID_W |
75475 | #define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
75476 | #define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
75477 | #define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
75478 | #define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
75479 | //NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0 |
75480 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0 |
75481 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL |
75482 | //NB_NBCFG1_NB_SMN_INDEX_0 |
75483 | #define NB_NBCFG1_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0 |
75484 | #define NB_NBCFG1_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL |
75485 | //NB_NBCFG1_NB_SMN_DATA_0 |
75486 | #define NB_NBCFG1_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0 |
75487 | #define NB_NBCFG1_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL |
75488 | //NB_NBCFG1_NBCFG_SCRATCH_0 |
75489 | #define NB_NBCFG1_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 |
75490 | #define NB_NBCFG1_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL |
75491 | //NB_NBCFG1_NBCFG_SCRATCH_1 |
75492 | #define NB_NBCFG1_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 |
75493 | #define NB_NBCFG1_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL |
75494 | //NB_NBCFG1_NBCFG_SCRATCH_2 |
75495 | #define NB_NBCFG1_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 |
75496 | #define NB_NBCFG1_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL |
75497 | //NB_NBCFG1_NBCFG_SCRATCH_3 |
75498 | #define NB_NBCFG1_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 |
75499 | #define NB_NBCFG1_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL |
75500 | //NB_NBCFG1_NBCFG_SCRATCH_4 |
75501 | #define NB_NBCFG1_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 |
75502 | #define NB_NBCFG1_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL |
75503 | //NB_NBCFG1_NB_PCI_ARB |
75504 | #define NB_NBCFG1_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
75505 | #define NB_NBCFG1_NB_PCI_ARB__PMEMode__SHIFT 0x8 |
75506 | #define NB_NBCFG1_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 |
75507 | #define NB_NBCFG1_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa |
75508 | #define NB_NBCFG1_NB_PCI_ARB__PMETarget__SHIFT 0x10 |
75509 | #define NB_NBCFG1_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
75510 | #define NB_NBCFG1_NB_PCI_ARB__PMEMode_MASK 0x00000100L |
75511 | #define NB_NBCFG1_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L |
75512 | #define NB_NBCFG1_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L |
75513 | #define NB_NBCFG1_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L |
75514 | //NB_NBCFG1_NB_DRAM_SLOT1_BASE |
75515 | #define NB_NBCFG1_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 |
75516 | #define NB_NBCFG1_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L |
75517 | //NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1 |
75518 | #define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0 |
75519 | #define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
75520 | #define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L |
75521 | #define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
75522 | //NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1 |
75523 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0 |
75524 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL |
75525 | //NB_NBCFG1_NB_SMN_INDEX_1 |
75526 | #define NB_NBCFG1_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0 |
75527 | #define NB_NBCFG1_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL |
75528 | //NB_NBCFG1_NB_SMN_DATA_1 |
75529 | #define NB_NBCFG1_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0 |
75530 | #define NB_NBCFG1_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL |
75531 | //NB_NBCFG1_NB_INDEX_DATA_MUTEX0 |
75532 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 |
75533 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f |
75534 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL |
75535 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L |
75536 | //NB_NBCFG1_NB_INDEX_DATA_MUTEX1 |
75537 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 |
75538 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f |
75539 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL |
75540 | #define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L |
75541 | //NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2 |
75542 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0 |
75543 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL |
75544 | //NB_NBCFG1_NB_SMN_INDEX_2 |
75545 | #define NB_NBCFG1_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0 |
75546 | #define NB_NBCFG1_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL |
75547 | //NB_NBCFG1_NB_SMN_DATA_2 |
75548 | #define NB_NBCFG1_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0 |
75549 | #define NB_NBCFG1_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL |
75550 | //NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3 |
75551 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0 |
75552 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL |
75553 | //NB_NBCFG1_NB_SMN_INDEX_3 |
75554 | #define NB_NBCFG1_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0 |
75555 | #define NB_NBCFG1_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL |
75556 | //NB_NBCFG1_NB_SMN_DATA_3 |
75557 | #define NB_NBCFG1_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0 |
75558 | #define NB_NBCFG1_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL |
75559 | //NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4 |
75560 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0 |
75561 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL |
75562 | //NB_NBCFG1_NB_SMN_INDEX_4 |
75563 | #define NB_NBCFG1_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0 |
75564 | #define NB_NBCFG1_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL |
75565 | //NB_NBCFG1_NB_SMN_DATA_4 |
75566 | #define NB_NBCFG1_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0 |
75567 | #define NB_NBCFG1_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL |
75568 | //NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5 |
75569 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0 |
75570 | #define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL |
75571 | //NB_NBCFG1_NB_SMN_INDEX_5 |
75572 | #define NB_NBCFG1_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0 |
75573 | #define NB_NBCFG1_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL |
75574 | //NB_NBCFG1_NB_SMN_DATA_5 |
75575 | #define NB_NBCFG1_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0 |
75576 | #define NB_NBCFG1_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL |
75577 | //NB_NBCFG1_NB_PERF_CNT_CTRL |
75578 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0 |
75579 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1 |
75580 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2 |
75581 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8 |
75582 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf |
75583 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10 |
75584 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17 |
75585 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L |
75586 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L |
75587 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L |
75588 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L |
75589 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L |
75590 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L |
75591 | #define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L |
75592 | //NB_NBCFG1_NB_SMN_INDEX_6 |
75593 | #define NB_NBCFG1_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0 |
75594 | #define NB_NBCFG1_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL |
75595 | //NB_NBCFG1_NB_SMN_DATA_6 |
75596 | #define NB_NBCFG1_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0 |
75597 | #define NB_NBCFG1_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL |
75598 | |
75599 | |
75600 | // addressBlock: nbio_iohub_nb_iommushadow_iommushadow_cfgdecp |
75601 | //SHADOW_IOMMU_MMIO_CNTRL_0 |
75602 | #define SHADOW_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 |
75603 | #define SHADOW_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L |
75604 | //SHADOW_IOMMU_CAP_BASE_LO |
75605 | #define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
75606 | #define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 |
75607 | #define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
75608 | #define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L |
75609 | //SHADOW_IOMMU_CAP_BASE_HI |
75610 | #define SHADOW_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 |
75611 | #define SHADOW_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL |
75612 | |
75613 | |
75614 | // addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp |
75615 | //NB_PCIE0SHADOW0_COMMAND |
75616 | #define NB_PCIE0SHADOW0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75617 | #define NB_PCIE0SHADOW0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75618 | #define NB_PCIE0SHADOW0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75619 | #define NB_PCIE0SHADOW0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75620 | #define NB_PCIE0SHADOW0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75621 | #define NB_PCIE0SHADOW0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75622 | //NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY |
75623 | #define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
75624 | #define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
75625 | #define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
75626 | #define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
75627 | //NB_PCIE0SHADOW0_IO_BASE_LIMIT |
75628 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
75629 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
75630 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
75631 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
75632 | //NB_PCIE0SHADOW0_MEM_BASE_LIMIT |
75633 | #define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
75634 | #define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
75635 | #define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
75636 | #define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
75637 | //NB_PCIE0SHADOW0_PREF_BASE_LIMIT |
75638 | #define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
75639 | #define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
75640 | #define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
75641 | #define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
75642 | //NB_PCIE0SHADOW0_PREF_BASE_UPPER |
75643 | #define NB_PCIE0SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
75644 | #define NB_PCIE0SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
75645 | //NB_PCIE0SHADOW0_PREF_LIMIT_UPPER |
75646 | #define NB_PCIE0SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
75647 | #define NB_PCIE0SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
75648 | //NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI |
75649 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
75650 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
75651 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
75652 | #define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
75653 | //NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL |
75654 | #define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
75655 | #define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
75656 | #define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
75657 | #define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
75658 | #define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
75659 | #define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
75660 | //NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL |
75661 | #define NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
75662 | #define NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
75663 | //NB_PCIE0SHADOW0_PMI_STATUS_CNTL |
75664 | #define NB_PCIE0SHADOW0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
75665 | #define NB_PCIE0SHADOW0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
75666 | //NB_PCIE0SHADOW0_SLOT_CAP |
75667 | #define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
75668 | #define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
75669 | #define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
75670 | #define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
75671 | //NB_PCIE0SHADOW0_ROOT_CNTL |
75672 | #define NB_PCIE0SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
75673 | #define NB_PCIE0SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
75674 | //NB_PCIE0SHADOW0_DEVICE_CNTL2 |
75675 | #define NB_PCIE0SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
75676 | #define NB_PCIE0SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
75677 | |
75678 | |
75679 | // addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp |
75680 | //NB_PCIE0SHADOW1_COMMAND |
75681 | #define NB_PCIE0SHADOW1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75682 | #define NB_PCIE0SHADOW1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75683 | #define NB_PCIE0SHADOW1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75684 | #define NB_PCIE0SHADOW1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75685 | #define NB_PCIE0SHADOW1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75686 | #define NB_PCIE0SHADOW1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75687 | //NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY |
75688 | #define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
75689 | #define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
75690 | #define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
75691 | #define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
75692 | //NB_PCIE0SHADOW1_IO_BASE_LIMIT |
75693 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
75694 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
75695 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
75696 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
75697 | //NB_PCIE0SHADOW1_MEM_BASE_LIMIT |
75698 | #define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
75699 | #define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
75700 | #define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
75701 | #define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
75702 | //NB_PCIE0SHADOW1_PREF_BASE_LIMIT |
75703 | #define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
75704 | #define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
75705 | #define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
75706 | #define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
75707 | //NB_PCIE0SHADOW1_PREF_BASE_UPPER |
75708 | #define NB_PCIE0SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
75709 | #define NB_PCIE0SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
75710 | //NB_PCIE0SHADOW1_PREF_LIMIT_UPPER |
75711 | #define NB_PCIE0SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
75712 | #define NB_PCIE0SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
75713 | //NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI |
75714 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
75715 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
75716 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
75717 | #define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
75718 | //NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL |
75719 | #define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
75720 | #define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
75721 | #define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
75722 | #define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
75723 | #define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
75724 | #define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
75725 | //NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL |
75726 | #define NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
75727 | #define NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
75728 | //NB_PCIE0SHADOW1_PMI_STATUS_CNTL |
75729 | #define NB_PCIE0SHADOW1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
75730 | #define NB_PCIE0SHADOW1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
75731 | //NB_PCIE0SHADOW1_SLOT_CAP |
75732 | #define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
75733 | #define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
75734 | #define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
75735 | #define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
75736 | //NB_PCIE0SHADOW1_ROOT_CNTL |
75737 | #define NB_PCIE0SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
75738 | #define NB_PCIE0SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
75739 | //NB_PCIE0SHADOW1_DEVICE_CNTL2 |
75740 | #define NB_PCIE0SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
75741 | #define NB_PCIE0SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
75742 | |
75743 | |
75744 | // addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp |
75745 | //NB_PCIE0SHADOW2_COMMAND |
75746 | #define NB_PCIE0SHADOW2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75747 | #define NB_PCIE0SHADOW2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75748 | #define NB_PCIE0SHADOW2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75749 | #define NB_PCIE0SHADOW2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75750 | #define NB_PCIE0SHADOW2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75751 | #define NB_PCIE0SHADOW2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75752 | //NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY |
75753 | #define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
75754 | #define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
75755 | #define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
75756 | #define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
75757 | //NB_PCIE0SHADOW2_IO_BASE_LIMIT |
75758 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
75759 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
75760 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
75761 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
75762 | //NB_PCIE0SHADOW2_MEM_BASE_LIMIT |
75763 | #define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
75764 | #define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
75765 | #define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
75766 | #define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
75767 | //NB_PCIE0SHADOW2_PREF_BASE_LIMIT |
75768 | #define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
75769 | #define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
75770 | #define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
75771 | #define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
75772 | //NB_PCIE0SHADOW2_PREF_BASE_UPPER |
75773 | #define NB_PCIE0SHADOW2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
75774 | #define NB_PCIE0SHADOW2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
75775 | //NB_PCIE0SHADOW2_PREF_LIMIT_UPPER |
75776 | #define NB_PCIE0SHADOW2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
75777 | #define NB_PCIE0SHADOW2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
75778 | //NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI |
75779 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
75780 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
75781 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
75782 | #define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
75783 | //NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL |
75784 | #define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
75785 | #define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
75786 | #define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
75787 | #define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
75788 | #define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
75789 | #define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
75790 | //NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL |
75791 | #define NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
75792 | #define NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
75793 | //NB_PCIE0SHADOW2_PMI_STATUS_CNTL |
75794 | #define NB_PCIE0SHADOW2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
75795 | #define NB_PCIE0SHADOW2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
75796 | //NB_PCIE0SHADOW2_SLOT_CAP |
75797 | #define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
75798 | #define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
75799 | #define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
75800 | #define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
75801 | //NB_PCIE0SHADOW2_ROOT_CNTL |
75802 | #define NB_PCIE0SHADOW2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
75803 | #define NB_PCIE0SHADOW2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
75804 | //NB_PCIE0SHADOW2_DEVICE_CNTL2 |
75805 | #define NB_PCIE0SHADOW2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
75806 | #define NB_PCIE0SHADOW2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
75807 | |
75808 | |
75809 | // addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp |
75810 | //NB_PCIE0SHADOW3_COMMAND |
75811 | #define NB_PCIE0SHADOW3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75812 | #define NB_PCIE0SHADOW3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75813 | #define NB_PCIE0SHADOW3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75814 | #define NB_PCIE0SHADOW3_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75815 | #define NB_PCIE0SHADOW3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75816 | #define NB_PCIE0SHADOW3_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75817 | //NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY |
75818 | #define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
75819 | #define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
75820 | #define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
75821 | #define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
75822 | //NB_PCIE0SHADOW3_IO_BASE_LIMIT |
75823 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
75824 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
75825 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
75826 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
75827 | //NB_PCIE0SHADOW3_MEM_BASE_LIMIT |
75828 | #define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
75829 | #define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
75830 | #define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
75831 | #define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
75832 | //NB_PCIE0SHADOW3_PREF_BASE_LIMIT |
75833 | #define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
75834 | #define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
75835 | #define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
75836 | #define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
75837 | //NB_PCIE0SHADOW3_PREF_BASE_UPPER |
75838 | #define NB_PCIE0SHADOW3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
75839 | #define NB_PCIE0SHADOW3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
75840 | //NB_PCIE0SHADOW3_PREF_LIMIT_UPPER |
75841 | #define NB_PCIE0SHADOW3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
75842 | #define NB_PCIE0SHADOW3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
75843 | //NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI |
75844 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
75845 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
75846 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
75847 | #define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
75848 | //NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL |
75849 | #define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
75850 | #define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
75851 | #define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
75852 | #define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
75853 | #define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
75854 | #define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
75855 | //NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL |
75856 | #define NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
75857 | #define NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
75858 | //NB_PCIE0SHADOW3_PMI_STATUS_CNTL |
75859 | #define NB_PCIE0SHADOW3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
75860 | #define NB_PCIE0SHADOW3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
75861 | //NB_PCIE0SHADOW3_SLOT_CAP |
75862 | #define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
75863 | #define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
75864 | #define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
75865 | #define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
75866 | //NB_PCIE0SHADOW3_ROOT_CNTL |
75867 | #define NB_PCIE0SHADOW3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
75868 | #define NB_PCIE0SHADOW3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
75869 | //NB_PCIE0SHADOW3_DEVICE_CNTL2 |
75870 | #define NB_PCIE0SHADOW3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
75871 | #define NB_PCIE0SHADOW3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
75872 | |
75873 | |
75874 | // addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp |
75875 | //NB_PCIE0SHADOW4_COMMAND |
75876 | #define NB_PCIE0SHADOW4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75877 | #define NB_PCIE0SHADOW4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75878 | #define NB_PCIE0SHADOW4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75879 | #define NB_PCIE0SHADOW4_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75880 | #define NB_PCIE0SHADOW4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75881 | #define NB_PCIE0SHADOW4_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75882 | //NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY |
75883 | #define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
75884 | #define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
75885 | #define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
75886 | #define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
75887 | //NB_PCIE0SHADOW4_IO_BASE_LIMIT |
75888 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
75889 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
75890 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
75891 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
75892 | //NB_PCIE0SHADOW4_MEM_BASE_LIMIT |
75893 | #define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
75894 | #define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
75895 | #define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
75896 | #define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
75897 | //NB_PCIE0SHADOW4_PREF_BASE_LIMIT |
75898 | #define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
75899 | #define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
75900 | #define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
75901 | #define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
75902 | //NB_PCIE0SHADOW4_PREF_BASE_UPPER |
75903 | #define NB_PCIE0SHADOW4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
75904 | #define NB_PCIE0SHADOW4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
75905 | //NB_PCIE0SHADOW4_PREF_LIMIT_UPPER |
75906 | #define NB_PCIE0SHADOW4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
75907 | #define NB_PCIE0SHADOW4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
75908 | //NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI |
75909 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
75910 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
75911 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
75912 | #define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
75913 | //NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL |
75914 | #define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
75915 | #define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
75916 | #define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
75917 | #define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
75918 | #define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
75919 | #define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
75920 | //NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL |
75921 | #define NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
75922 | #define NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
75923 | //NB_PCIE0SHADOW4_PMI_STATUS_CNTL |
75924 | #define NB_PCIE0SHADOW4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
75925 | #define NB_PCIE0SHADOW4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
75926 | //NB_PCIE0SHADOW4_SLOT_CAP |
75927 | #define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
75928 | #define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
75929 | #define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
75930 | #define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
75931 | //NB_PCIE0SHADOW4_ROOT_CNTL |
75932 | #define NB_PCIE0SHADOW4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
75933 | #define NB_PCIE0SHADOW4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
75934 | //NB_PCIE0SHADOW4_DEVICE_CNTL2 |
75935 | #define NB_PCIE0SHADOW4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
75936 | #define NB_PCIE0SHADOW4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
75937 | |
75938 | |
75939 | // addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp |
75940 | //NB_PCIE0SHADOW5_COMMAND |
75941 | #define NB_PCIE0SHADOW5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
75942 | #define NB_PCIE0SHADOW5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
75943 | #define NB_PCIE0SHADOW5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
75944 | #define NB_PCIE0SHADOW5_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
75945 | #define NB_PCIE0SHADOW5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
75946 | #define NB_PCIE0SHADOW5_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
75947 | //NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY |
75948 | #define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
75949 | #define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
75950 | #define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
75951 | #define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
75952 | //NB_PCIE0SHADOW5_IO_BASE_LIMIT |
75953 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
75954 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
75955 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
75956 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
75957 | //NB_PCIE0SHADOW5_MEM_BASE_LIMIT |
75958 | #define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
75959 | #define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
75960 | #define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
75961 | #define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
75962 | //NB_PCIE0SHADOW5_PREF_BASE_LIMIT |
75963 | #define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
75964 | #define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
75965 | #define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
75966 | #define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
75967 | //NB_PCIE0SHADOW5_PREF_BASE_UPPER |
75968 | #define NB_PCIE0SHADOW5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
75969 | #define NB_PCIE0SHADOW5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
75970 | //NB_PCIE0SHADOW5_PREF_LIMIT_UPPER |
75971 | #define NB_PCIE0SHADOW5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
75972 | #define NB_PCIE0SHADOW5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
75973 | //NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI |
75974 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
75975 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
75976 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
75977 | #define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
75978 | //NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL |
75979 | #define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
75980 | #define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
75981 | #define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
75982 | #define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
75983 | #define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
75984 | #define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
75985 | //NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL |
75986 | #define NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
75987 | #define NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
75988 | //NB_PCIE0SHADOW5_PMI_STATUS_CNTL |
75989 | #define NB_PCIE0SHADOW5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
75990 | #define NB_PCIE0SHADOW5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
75991 | //NB_PCIE0SHADOW5_SLOT_CAP |
75992 | #define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
75993 | #define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
75994 | #define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
75995 | #define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
75996 | //NB_PCIE0SHADOW5_ROOT_CNTL |
75997 | #define NB_PCIE0SHADOW5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
75998 | #define NB_PCIE0SHADOW5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
75999 | //NB_PCIE0SHADOW5_DEVICE_CNTL2 |
76000 | #define NB_PCIE0SHADOW5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
76001 | #define NB_PCIE0SHADOW5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
76002 | |
76003 | |
76004 | // addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp |
76005 | //NB_PCIE0SHADOW6_COMMAND |
76006 | #define NB_PCIE0SHADOW6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
76007 | #define NB_PCIE0SHADOW6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
76008 | #define NB_PCIE0SHADOW6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
76009 | #define NB_PCIE0SHADOW6_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
76010 | #define NB_PCIE0SHADOW6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
76011 | #define NB_PCIE0SHADOW6_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
76012 | //NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY |
76013 | #define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
76014 | #define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
76015 | #define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
76016 | #define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
76017 | //NB_PCIE0SHADOW6_IO_BASE_LIMIT |
76018 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
76019 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
76020 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
76021 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
76022 | //NB_PCIE0SHADOW6_MEM_BASE_LIMIT |
76023 | #define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
76024 | #define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
76025 | #define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
76026 | #define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
76027 | //NB_PCIE0SHADOW6_PREF_BASE_LIMIT |
76028 | #define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
76029 | #define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
76030 | #define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
76031 | #define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
76032 | //NB_PCIE0SHADOW6_PREF_BASE_UPPER |
76033 | #define NB_PCIE0SHADOW6_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
76034 | #define NB_PCIE0SHADOW6_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
76035 | //NB_PCIE0SHADOW6_PREF_LIMIT_UPPER |
76036 | #define NB_PCIE0SHADOW6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
76037 | #define NB_PCIE0SHADOW6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
76038 | //NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI |
76039 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
76040 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
76041 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
76042 | #define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
76043 | //NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL |
76044 | #define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
76045 | #define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
76046 | #define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
76047 | #define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
76048 | #define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
76049 | #define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
76050 | //NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL |
76051 | #define NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
76052 | #define NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
76053 | //NB_PCIE0SHADOW6_PMI_STATUS_CNTL |
76054 | #define NB_PCIE0SHADOW6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
76055 | #define NB_PCIE0SHADOW6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
76056 | //NB_PCIE0SHADOW6_SLOT_CAP |
76057 | #define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
76058 | #define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
76059 | #define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
76060 | #define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
76061 | //NB_PCIE0SHADOW6_ROOT_CNTL |
76062 | #define NB_PCIE0SHADOW6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
76063 | #define NB_PCIE0SHADOW6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
76064 | //NB_PCIE0SHADOW6_DEVICE_CNTL2 |
76065 | #define NB_PCIE0SHADOW6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
76066 | #define NB_PCIE0SHADOW6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
76067 | |
76068 | |
76069 | // addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp |
76070 | //NB_NBIF1SHADOW0_COMMAND |
76071 | #define NB_NBIF1SHADOW0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
76072 | #define NB_NBIF1SHADOW0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
76073 | #define NB_NBIF1SHADOW0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
76074 | #define NB_NBIF1SHADOW0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
76075 | #define NB_NBIF1SHADOW0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
76076 | #define NB_NBIF1SHADOW0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
76077 | //NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY |
76078 | #define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
76079 | #define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
76080 | #define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
76081 | #define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
76082 | //NB_NBIF1SHADOW0_IO_BASE_LIMIT |
76083 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
76084 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
76085 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
76086 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
76087 | //NB_NBIF1SHADOW0_MEM_BASE_LIMIT |
76088 | #define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
76089 | #define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
76090 | #define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
76091 | #define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
76092 | //NB_NBIF1SHADOW0_PREF_BASE_LIMIT |
76093 | #define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
76094 | #define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
76095 | #define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
76096 | #define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
76097 | //NB_NBIF1SHADOW0_PREF_BASE_UPPER |
76098 | #define NB_NBIF1SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
76099 | #define NB_NBIF1SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
76100 | //NB_NBIF1SHADOW0_PREF_LIMIT_UPPER |
76101 | #define NB_NBIF1SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
76102 | #define NB_NBIF1SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
76103 | //NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI |
76104 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
76105 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
76106 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
76107 | #define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
76108 | //NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL |
76109 | #define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
76110 | #define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
76111 | #define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
76112 | #define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
76113 | #define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
76114 | #define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
76115 | //NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL |
76116 | #define NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
76117 | #define NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
76118 | //NB_NBIF1SHADOW0_PMI_STATUS_CNTL |
76119 | #define NB_NBIF1SHADOW0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
76120 | #define NB_NBIF1SHADOW0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
76121 | //NB_NBIF1SHADOW0_SLOT_CAP |
76122 | #define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
76123 | #define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
76124 | #define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
76125 | #define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
76126 | //NB_NBIF1SHADOW0_ROOT_CNTL |
76127 | #define NB_NBIF1SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
76128 | #define NB_NBIF1SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
76129 | //NB_NBIF1SHADOW0_DEVICE_CNTL2 |
76130 | #define NB_NBIF1SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
76131 | #define NB_NBIF1SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
76132 | |
76133 | |
76134 | // addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp |
76135 | //NB_NBIF1SHADOW1_COMMAND |
76136 | #define NB_NBIF1SHADOW1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
76137 | #define NB_NBIF1SHADOW1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
76138 | #define NB_NBIF1SHADOW1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
76139 | #define NB_NBIF1SHADOW1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
76140 | #define NB_NBIF1SHADOW1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
76141 | #define NB_NBIF1SHADOW1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
76142 | //NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY |
76143 | #define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
76144 | #define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
76145 | #define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
76146 | #define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
76147 | //NB_NBIF1SHADOW1_IO_BASE_LIMIT |
76148 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
76149 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
76150 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
76151 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
76152 | //NB_NBIF1SHADOW1_MEM_BASE_LIMIT |
76153 | #define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
76154 | #define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
76155 | #define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
76156 | #define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
76157 | //NB_NBIF1SHADOW1_PREF_BASE_LIMIT |
76158 | #define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
76159 | #define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
76160 | #define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
76161 | #define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
76162 | //NB_NBIF1SHADOW1_PREF_BASE_UPPER |
76163 | #define NB_NBIF1SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
76164 | #define NB_NBIF1SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
76165 | //NB_NBIF1SHADOW1_PREF_LIMIT_UPPER |
76166 | #define NB_NBIF1SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
76167 | #define NB_NBIF1SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
76168 | //NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI |
76169 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
76170 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
76171 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
76172 | #define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
76173 | //NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL |
76174 | #define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
76175 | #define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
76176 | #define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
76177 | #define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
76178 | #define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
76179 | #define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
76180 | //NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL |
76181 | #define NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
76182 | #define NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
76183 | //NB_NBIF1SHADOW1_PMI_STATUS_CNTL |
76184 | #define NB_NBIF1SHADOW1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
76185 | #define NB_NBIF1SHADOW1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
76186 | //NB_NBIF1SHADOW1_SLOT_CAP |
76187 | #define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
76188 | #define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
76189 | #define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
76190 | #define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
76191 | //NB_NBIF1SHADOW1_ROOT_CNTL |
76192 | #define NB_NBIF1SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
76193 | #define NB_NBIF1SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
76194 | //NB_NBIF1SHADOW1_DEVICE_CNTL2 |
76195 | #define NB_NBIF1SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
76196 | #define NB_NBIF1SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
76197 | |
76198 | |
76199 | // addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec |
76200 | //FASTREG_APERTURE |
76201 | #define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT 0x0 |
76202 | #define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT 0x10 |
76203 | #define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT 0x1f |
76204 | #define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK 0x00000FFFL |
76205 | #define FASTREG_APERTURE__FASTREG_NODE_ID_MASK 0x000F0000L |
76206 | #define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK 0x80000000L |
76207 | |
76208 | |
76209 | // addressBlock: nbio_iohub_nb_misc_misc_cfgdec |
76210 | //NB_CNTL |
76211 | #define NB_CNTL__HWINIT_WR_LOCK__SHIFT 0x7 |
76212 | #define NB_CNTL__HWINIT_WR_LOCK_MASK 0x00000080L |
76213 | //NB_SPARE1 |
76214 | #define NB_SPARE1__NB_SPARE1_RW__SHIFT 0x0 |
76215 | #define NB_SPARE1__NB_SPARE1_RW_MASK 0xFFFFFFFFL |
76216 | //NB_SPARE2 |
76217 | #define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT 0x0 |
76218 | #define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT 0x1 |
76219 | #define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT 0x2 |
76220 | #define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT 0x3 |
76221 | #define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT 0x4 |
76222 | #define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT 0x5 |
76223 | #define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT 0x6 |
76224 | #define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT 0x7 |
76225 | #define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT 0x8 |
76226 | #define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT 0x9 |
76227 | #define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT 0xa |
76228 | #define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT 0xb |
76229 | #define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT 0xc |
76230 | #define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT 0xd |
76231 | #define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT 0xe |
76232 | #define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT 0xf |
76233 | #define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT 0x10 |
76234 | #define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT 0x11 |
76235 | #define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT 0x12 |
76236 | #define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT 0x13 |
76237 | #define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT 0x14 |
76238 | #define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT 0x15 |
76239 | #define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT 0x16 |
76240 | #define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT 0x17 |
76241 | #define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT 0x18 |
76242 | #define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT 0x19 |
76243 | #define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT 0x1a |
76244 | #define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT 0x1b |
76245 | #define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT 0x1c |
76246 | #define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT 0x1d |
76247 | #define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT 0x1e |
76248 | #define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT 0x1f |
76249 | #define NB_SPARE2__NB_SPARE2_RW1C_0_MASK 0x00000001L |
76250 | #define NB_SPARE2__NB_SPARE2_RW1C_1_MASK 0x00000002L |
76251 | #define NB_SPARE2__NB_SPARE2_RW1C_2_MASK 0x00000004L |
76252 | #define NB_SPARE2__NB_SPARE2_RW1C_3_MASK 0x00000008L |
76253 | #define NB_SPARE2__NB_SPARE2_RW1C_4_MASK 0x00000010L |
76254 | #define NB_SPARE2__NB_SPARE2_RW1C_5_MASK 0x00000020L |
76255 | #define NB_SPARE2__NB_SPARE2_RW1C_6_MASK 0x00000040L |
76256 | #define NB_SPARE2__NB_SPARE2_RW1C_7_MASK 0x00000080L |
76257 | #define NB_SPARE2__NB_SPARE2_RW1C_8_MASK 0x00000100L |
76258 | #define NB_SPARE2__NB_SPARE2_RW1C_9_MASK 0x00000200L |
76259 | #define NB_SPARE2__NB_SPARE2_RW1C_10_MASK 0x00000400L |
76260 | #define NB_SPARE2__NB_SPARE2_RW1C_11_MASK 0x00000800L |
76261 | #define NB_SPARE2__NB_SPARE2_RW1C_12_MASK 0x00001000L |
76262 | #define NB_SPARE2__NB_SPARE2_RW1C_13_MASK 0x00002000L |
76263 | #define NB_SPARE2__NB_SPARE2_RW1C_14_MASK 0x00004000L |
76264 | #define NB_SPARE2__NB_SPARE2_RW1C_15_MASK 0x00008000L |
76265 | #define NB_SPARE2__NB_SPARE2_RW1C_16_MASK 0x00010000L |
76266 | #define NB_SPARE2__NB_SPARE2_RW1C_17_MASK 0x00020000L |
76267 | #define NB_SPARE2__NB_SPARE2_RW1C_18_MASK 0x00040000L |
76268 | #define NB_SPARE2__NB_SPARE2_RW1C_19_MASK 0x00080000L |
76269 | #define NB_SPARE2__NB_SPARE2_RW1C_20_MASK 0x00100000L |
76270 | #define NB_SPARE2__NB_SPARE2_RW1C_21_MASK 0x00200000L |
76271 | #define NB_SPARE2__NB_SPARE2_RW1C_22_MASK 0x00400000L |
76272 | #define NB_SPARE2__NB_SPARE2_RW1C_23_MASK 0x00800000L |
76273 | #define NB_SPARE2__NB_SPARE2_RW1C_24_MASK 0x01000000L |
76274 | #define NB_SPARE2__NB_SPARE2_RW1C_25_MASK 0x02000000L |
76275 | #define NB_SPARE2__NB_SPARE2_RW1C_26_MASK 0x04000000L |
76276 | #define NB_SPARE2__NB_SPARE2_RW1C_27_MASK 0x08000000L |
76277 | #define NB_SPARE2__NB_SPARE2_RW1C_28_MASK 0x10000000L |
76278 | #define NB_SPARE2__NB_SPARE2_RW1C_29_MASK 0x20000000L |
76279 | #define NB_SPARE2__NB_SPARE2_RW1C_30_MASK 0x40000000L |
76280 | #define NB_SPARE2__NB_SPARE2_RW1C_31_MASK 0x80000000L |
76281 | //NB_REVID |
76282 | #define NB_REVID__REVISION_ID__SHIFT 0x0 |
76283 | #define NB_REVID__REVISION_ID_MASK 0x000003FFL |
76284 | //IOHC_REFCLK_MODE |
76285 | #define IOHC_REFCLK_MODE__MODE_100MHZ__SHIFT 0x0 |
76286 | #define IOHC_REFCLK_MODE__MODE_25MHZ__SHIFT 0x1 |
76287 | #define IOHC_REFCLK_MODE__MODE_27MHZ__SHIFT 0x2 |
76288 | #define IOHC_REFCLK_MODE__MODE_100MHZ_MASK 0x00000001L |
76289 | #define IOHC_REFCLK_MODE__MODE_25MHZ_MASK 0x00000002L |
76290 | #define IOHC_REFCLK_MODE__MODE_27MHZ_MASK 0x00000004L |
76291 | //IOHC_PCIE_CRS_Count |
76292 | #define IOHC_PCIE_CRS_Count__CrsDelayCount__SHIFT 0x0 |
76293 | #define IOHC_PCIE_CRS_Count__CrsLimitCount__SHIFT 0x10 |
76294 | #define IOHC_PCIE_CRS_Count__CrsDelayCount_MASK 0x0000FFFFL |
76295 | #define IOHC_PCIE_CRS_Count__CrsLimitCount_MASK 0x0FFF0000L |
76296 | //IOHC_P2P_CNTL |
76297 | #define IOHC_P2P_CNTL__DLDownResetEn__SHIFT 0xb |
76298 | #define IOHC_P2P_CNTL__DLDownResetEn_MASK 0x00000800L |
76299 | //CFG_IOHC_PCI |
76300 | #define CFG_IOHC_PCI__CFG_IOHC_PCI_Dev0Fn2RegEn__SHIFT 0x0 |
76301 | #define CFG_IOHC_PCI__IOMMU_DIS__SHIFT 0x1f |
76302 | #define CFG_IOHC_PCI__CFG_IOHC_PCI_Dev0Fn2RegEn_MASK 0x00000001L |
76303 | #define CFG_IOHC_PCI__IOMMU_DIS_MASK 0x80000000L |
76304 | //NB_BUS_NUM_CNTL |
76305 | #define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT 0x0 |
76306 | #define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT 0x8 |
76307 | #define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK 0x000000FFL |
76308 | #define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK 0x00000100L |
76309 | //IOHC_AER_CNTL |
76310 | #define IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN__SHIFT 0x1 |
76311 | #define IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN_MASK 0x00000002L |
76312 | //NB_MMIOBASE |
76313 | #define NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
76314 | #define NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
76315 | //NB_MMIOLIMIT |
76316 | #define NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
76317 | #define NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
76318 | //NB_LOWER_TOP_OF_DRAM2 |
76319 | #define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
76320 | #define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
76321 | #define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
76322 | #define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
76323 | //NB_UPPER_TOP_OF_DRAM2 |
76324 | #define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
76325 | #define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000001FFL |
76326 | //NB_LOWER_DRAM2_BASE |
76327 | #define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT 0x17 |
76328 | #define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK 0xFF800000L |
76329 | //NB_UPPER_DRAM2_BASE |
76330 | #define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT 0x0 |
76331 | #define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK 0x000001FFL |
76332 | //SB_LOCATION |
76333 | #define SB_LOCATION__SBlocated_Port__SHIFT 0x0 |
76334 | #define SB_LOCATION__SBlocated_Core__SHIFT 0x10 |
76335 | #define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL |
76336 | #define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L |
76337 | //IOHC_GLUE_CG_LCLK_CTRL_0 |
76338 | #define IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4 |
76339 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16 |
76340 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17 |
76341 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18 |
76342 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19 |
76343 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a |
76344 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b |
76345 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c |
76346 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d |
76347 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e |
76348 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f |
76349 | #define IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L |
76350 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L |
76351 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L |
76352 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L |
76353 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L |
76354 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L |
76355 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L |
76356 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L |
76357 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L |
76358 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L |
76359 | #define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L |
76360 | //IOHC_GLUE_CG_LCLK_CTRL_1 |
76361 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT 0x16 |
76362 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT 0x17 |
76363 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT 0x18 |
76364 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT 0x19 |
76365 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT 0x1a |
76366 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT 0x1b |
76367 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT 0x1c |
76368 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT 0x1d |
76369 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT 0x1e |
76370 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT 0x1f |
76371 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK 0x00400000L |
76372 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK 0x00800000L |
76373 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK 0x01000000L |
76374 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK 0x02000000L |
76375 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK 0x04000000L |
76376 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK 0x08000000L |
76377 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK 0x10000000L |
76378 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK 0x20000000L |
76379 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK 0x40000000L |
76380 | #define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK 0x80000000L |
76381 | //IOHC_GLUE_CG_LCLK_CTRL_2 |
76382 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9__SHIFT 0x16 |
76383 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8__SHIFT 0x17 |
76384 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7__SHIFT 0x18 |
76385 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6__SHIFT 0x19 |
76386 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5__SHIFT 0x1a |
76387 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4__SHIFT 0x1b |
76388 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3__SHIFT 0x1c |
76389 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2__SHIFT 0x1d |
76390 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1__SHIFT 0x1e |
76391 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0__SHIFT 0x1f |
76392 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9_MASK 0x00400000L |
76393 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8_MASK 0x00800000L |
76394 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7_MASK 0x01000000L |
76395 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6_MASK 0x02000000L |
76396 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5_MASK 0x04000000L |
76397 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4_MASK 0x08000000L |
76398 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3_MASK 0x10000000L |
76399 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2_MASK 0x20000000L |
76400 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1_MASK 0x40000000L |
76401 | #define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0_MASK 0x80000000L |
76402 | //IOHC_PERF_CNTL |
76403 | #define IOHC_PERF_CNTL__EVENT0_SEL__SHIFT 0x0 |
76404 | #define IOHC_PERF_CNTL__EVENT1_SEL__SHIFT 0x8 |
76405 | #define IOHC_PERF_CNTL__EVENT2_SEL__SHIFT 0x10 |
76406 | #define IOHC_PERF_CNTL__EVENT3_SEL__SHIFT 0x18 |
76407 | #define IOHC_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL |
76408 | #define IOHC_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L |
76409 | #define IOHC_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L |
76410 | #define IOHC_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L |
76411 | //IOHC_PERF_COUNT0 |
76412 | #define IOHC_PERF_COUNT0__COUNTER0__SHIFT 0x0 |
76413 | #define IOHC_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL |
76414 | //IOHC_PERF_COUNT0_UPPER |
76415 | #define IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0 |
76416 | #define IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL |
76417 | //IOHC_PERF_COUNT1 |
76418 | #define IOHC_PERF_COUNT1__COUNTER1__SHIFT 0x0 |
76419 | #define IOHC_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL |
76420 | //IOHC_PERF_COUNT1_UPPER |
76421 | #define IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0 |
76422 | #define IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL |
76423 | //IOHC_PERF_COUNT2 |
76424 | #define IOHC_PERF_COUNT2__COUNTER2__SHIFT 0x0 |
76425 | #define IOHC_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL |
76426 | //IOHC_PERF_COUNT2_UPPER |
76427 | #define IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0 |
76428 | #define IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL |
76429 | //IOHC_PERF_COUNT3 |
76430 | #define IOHC_PERF_COUNT3__COUNTER3__SHIFT 0x0 |
76431 | #define IOHC_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL |
76432 | //IOHC_PERF_COUNT3_UPPER |
76433 | #define IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0 |
76434 | #define IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL |
76435 | //NB_PROG_DEVICE_REMAP_PBr0 |
76436 | #define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0 |
76437 | #define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL |
76438 | //NB_PROG_DEVICE_REMAP_PBr1 |
76439 | #define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0 |
76440 | #define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL |
76441 | //NB_PROG_DEVICE_REMAP_PBr2 |
76442 | #define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0 |
76443 | #define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL |
76444 | //NB_PROG_DEVICE_REMAP_PBr3 |
76445 | #define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0 |
76446 | #define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL |
76447 | //NB_PROG_DEVICE_REMAP_PBr4 |
76448 | #define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0 |
76449 | #define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL |
76450 | //NB_PROG_DEVICE_REMAP_PBr5 |
76451 | #define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0 |
76452 | #define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL |
76453 | //NB_PROG_DEVICE_REMAP_PBr6 |
76454 | #define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0 |
76455 | #define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL |
76456 | //NB_PROG_DEVICE_REMAP_PBr7 |
76457 | #define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0 |
76458 | #define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL |
76459 | //NB_PROG_DEVICE_REMAP_PBr8 |
76460 | #define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0 |
76461 | #define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL |
76462 | //SW_NMI_CNTL |
76463 | #define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0 |
76464 | #define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL |
76465 | //SW_SMI_CNTL |
76466 | #define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0 |
76467 | #define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL |
76468 | //SW_SCI_CNTL |
76469 | #define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0 |
76470 | #define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL |
76471 | //APML_SW_STATUS |
76472 | #define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0 |
76473 | #define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L |
76474 | //IOHC_FEATURE_CNTL |
76475 | #define IOHC_FEATURE_CNTL__HpPmpme_DevID_En__SHIFT 0x0 |
76476 | #define IOHC_FEATURE_CNTL__P2P_mode__SHIFT 0x1 |
76477 | #define IOHC_FEATURE_CNTL__IOHC_ARCH_MODE__SHIFT 0x3 |
76478 | #define IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED__SHIFT 0x16 |
76479 | #define IOHC_FEATURE_CNTL__IOHC_dGPU_MODE__SHIFT 0x1c |
76480 | #define IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL__SHIFT 0x1d |
76481 | #define IOHC_FEATURE_CNTL__HpPmpme_DevID_En_MASK 0x00000001L |
76482 | #define IOHC_FEATURE_CNTL__P2P_mode_MASK 0x00000006L |
76483 | #define IOHC_FEATURE_CNTL__IOHC_ARCH_MODE_MASK 0x00000008L |
76484 | #define IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED_MASK 0x00400000L |
76485 | #define IOHC_FEATURE_CNTL__IOHC_dGPU_MODE_MASK 0x10000000L |
76486 | #define IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL_MASK 0xE0000000L |
76487 | //SW_GIC_SPI_CNTL |
76488 | #define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0 |
76489 | #define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8 |
76490 | #define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10 |
76491 | #define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL |
76492 | #define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L |
76493 | #define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L |
76494 | //IOHC_INTERRUPT_EOI |
76495 | #define IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT 0x0 |
76496 | #define IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT 0x1 |
76497 | #define IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT 0x2 |
76498 | #define IOHC_INTERRUPT_EOI__SMI_EOI_MASK 0x00000001L |
76499 | #define IOHC_INTERRUPT_EOI__SCI_EOI_MASK 0x00000002L |
76500 | #define IOHC_INTERRUPT_EOI__NMI_EOI_MASK 0x00000004L |
76501 | //SW_SYNCFLOOD_CNTL |
76502 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0 |
76503 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1 |
76504 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L |
76505 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L |
76506 | //IOHC_PIN_CNTL |
76507 | #define IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE__SHIFT 0x0 |
76508 | #define IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE_MASK 0x00000001L |
76509 | //IOHC_INTR_CNTL |
76510 | #define IOHC_INTR_CNTL__NMI_DEST_ctrl__SHIFT 0x8 |
76511 | #define IOHC_INTR_CNTL__NMI_DEST_ctrl_MASK 0x0000FF00L |
76512 | //IOHC_FEATURE_CNTL2 |
76513 | #define IOHC_FEATURE_CNTL2__NMI_status__SHIFT 0x0 |
76514 | #define IOHC_FEATURE_CNTL2__SErr_status__SHIFT 0x1 |
76515 | #define IOHC_FEATURE_CNTL2__CrsStatus__SHIFT 0x10 |
76516 | #define IOHC_FEATURE_CNTL2__P_DMA_DROPPED__SHIFT 0x11 |
76517 | #define IOHC_FEATURE_CNTL2__NP_DMA_DROPPED__SHIFT 0x12 |
76518 | #define IOHC_FEATURE_CNTL2__NMI_status_MASK 0x00000001L |
76519 | #define IOHC_FEATURE_CNTL2__SErr_status_MASK 0x00000002L |
76520 | #define IOHC_FEATURE_CNTL2__CrsStatus_MASK 0x00010000L |
76521 | #define IOHC_FEATURE_CNTL2__P_DMA_DROPPED_MASK 0x00020000L |
76522 | #define IOHC_FEATURE_CNTL2__NP_DMA_DROPPED_MASK 0x00040000L |
76523 | //NB_TOP_OF_DRAM3 |
76524 | #define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 |
76525 | #define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f |
76526 | #define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3FFFFFFFL |
76527 | #define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000L |
76528 | //CAM_CONTROL |
76529 | #define CAM_CONTROL__CAM_En__SHIFT 0x0 |
76530 | #define CAM_CONTROL__Op__SHIFT 0x1 |
76531 | #define CAM_CONTROL__AccessType__SHIFT 0x2 |
76532 | #define CAM_CONTROL__DataMatchEn__SHIFT 0x3 |
76533 | #define CAM_CONTROL__VC__SHIFT 0x4 |
76534 | #define CAM_CONTROL__CrossTrigger__SHIFT 0x8 |
76535 | #define CAM_CONTROL__CAM_En_MASK 0x00000001L |
76536 | #define CAM_CONTROL__Op_MASK 0x00000002L |
76537 | #define CAM_CONTROL__AccessType_MASK 0x00000004L |
76538 | #define CAM_CONTROL__DataMatchEn_MASK 0x00000008L |
76539 | #define CAM_CONTROL__VC_MASK 0x00000070L |
76540 | #define CAM_CONTROL__CrossTrigger_MASK 0x0000FF00L |
76541 | //CAM_TARGET_INDEX_ADDR_BOTTOM |
76542 | #define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0 |
76543 | #define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL |
76544 | //CAM_TARGET_INDEX_ADDR_TOP |
76545 | #define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0 |
76546 | #define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL |
76547 | //CAM_TARGET_INDEX_DATA |
76548 | #define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0 |
76549 | #define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL |
76550 | //CAM_TARGET_INDEX_DATA_MASK |
76551 | #define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0 |
76552 | #define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL |
76553 | //CAM_TARGET_DATA_ADDR_BOTTOM |
76554 | #define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0 |
76555 | #define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL |
76556 | //CAM_TARGET_DATA_ADDR_TOP |
76557 | #define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0 |
76558 | #define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL |
76559 | //CAM_TARGET_DATA |
76560 | #define CAM_TARGET_DATA__Data__SHIFT 0x0 |
76561 | #define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL |
76562 | //CAM_TARGET_DATA_MASK |
76563 | #define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0 |
76564 | #define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL |
76565 | //P_DMA_DROPPED_LOG_LOWER |
76566 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 |
76567 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 |
76568 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 |
76569 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 |
76570 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 |
76571 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 |
76572 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 |
76573 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 |
76574 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 |
76575 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 |
76576 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa |
76577 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb |
76578 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc |
76579 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd |
76580 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe |
76581 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf |
76582 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 |
76583 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 |
76584 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 |
76585 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 |
76586 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 |
76587 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 |
76588 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 |
76589 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 |
76590 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 |
76591 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 |
76592 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a |
76593 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b |
76594 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c |
76595 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d |
76596 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e |
76597 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f |
76598 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L |
76599 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L |
76600 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L |
76601 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L |
76602 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L |
76603 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L |
76604 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L |
76605 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L |
76606 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L |
76607 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L |
76608 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L |
76609 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L |
76610 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L |
76611 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L |
76612 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L |
76613 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L |
76614 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L |
76615 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L |
76616 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L |
76617 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L |
76618 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L |
76619 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L |
76620 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L |
76621 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L |
76622 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L |
76623 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L |
76624 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L |
76625 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L |
76626 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L |
76627 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L |
76628 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L |
76629 | #define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L |
76630 | //P_DMA_DROPPED_LOG_UPPER |
76631 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 |
76632 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 |
76633 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 |
76634 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 |
76635 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 |
76636 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 |
76637 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 |
76638 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 |
76639 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 |
76640 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 |
76641 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa |
76642 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb |
76643 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc |
76644 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd |
76645 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe |
76646 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf |
76647 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 |
76648 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 |
76649 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 |
76650 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 |
76651 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 |
76652 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 |
76653 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 |
76654 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 |
76655 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 |
76656 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 |
76657 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a |
76658 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b |
76659 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c |
76660 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d |
76661 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e |
76662 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f |
76663 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L |
76664 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L |
76665 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L |
76666 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L |
76667 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L |
76668 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L |
76669 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L |
76670 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L |
76671 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L |
76672 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L |
76673 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L |
76674 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L |
76675 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L |
76676 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L |
76677 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L |
76678 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L |
76679 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L |
76680 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L |
76681 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L |
76682 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L |
76683 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L |
76684 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L |
76685 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L |
76686 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L |
76687 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L |
76688 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L |
76689 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L |
76690 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L |
76691 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L |
76692 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L |
76693 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L |
76694 | #define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L |
76695 | //NP_DMA_DROPPED_LOG_LOWER |
76696 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 |
76697 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 |
76698 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 |
76699 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 |
76700 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 |
76701 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 |
76702 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 |
76703 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 |
76704 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 |
76705 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 |
76706 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa |
76707 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb |
76708 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc |
76709 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd |
76710 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe |
76711 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf |
76712 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 |
76713 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 |
76714 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 |
76715 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 |
76716 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 |
76717 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 |
76718 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 |
76719 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 |
76720 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 |
76721 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 |
76722 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a |
76723 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b |
76724 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c |
76725 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d |
76726 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e |
76727 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f |
76728 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L |
76729 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L |
76730 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L |
76731 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L |
76732 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L |
76733 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L |
76734 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L |
76735 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L |
76736 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L |
76737 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L |
76738 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L |
76739 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L |
76740 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L |
76741 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L |
76742 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L |
76743 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L |
76744 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L |
76745 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L |
76746 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L |
76747 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L |
76748 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L |
76749 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L |
76750 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L |
76751 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L |
76752 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L |
76753 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L |
76754 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L |
76755 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L |
76756 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L |
76757 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L |
76758 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L |
76759 | #define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L |
76760 | //NP_DMA_DROPPED_LOG_UPPER |
76761 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 |
76762 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 |
76763 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 |
76764 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 |
76765 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 |
76766 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 |
76767 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 |
76768 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 |
76769 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 |
76770 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 |
76771 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa |
76772 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb |
76773 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc |
76774 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd |
76775 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe |
76776 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf |
76777 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 |
76778 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 |
76779 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 |
76780 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 |
76781 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 |
76782 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 |
76783 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 |
76784 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 |
76785 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 |
76786 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 |
76787 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a |
76788 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b |
76789 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c |
76790 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d |
76791 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e |
76792 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f |
76793 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L |
76794 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L |
76795 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L |
76796 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L |
76797 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L |
76798 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L |
76799 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L |
76800 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L |
76801 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L |
76802 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L |
76803 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L |
76804 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L |
76805 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L |
76806 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L |
76807 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L |
76808 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L |
76809 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L |
76810 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L |
76811 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L |
76812 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L |
76813 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L |
76814 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L |
76815 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L |
76816 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L |
76817 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L |
76818 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L |
76819 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L |
76820 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L |
76821 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L |
76822 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L |
76823 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L |
76824 | #define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L |
76825 | //PCIE_VDM_NODE0_CTRL4 |
76826 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0 |
76827 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8 |
76828 | #define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f |
76829 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL |
76830 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L |
76831 | #define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L |
76832 | //PCIE_VDM_CNTL2 |
76833 | #define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0 |
76834 | #define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT 0x4 |
76835 | #define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT 0x5 |
76836 | #define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT 0x6 |
76837 | #define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT 0xf |
76838 | #define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10 |
76839 | #define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L |
76840 | #define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK 0x00000010L |
76841 | #define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK 0x00000020L |
76842 | #define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK 0x00000040L |
76843 | #define PCIE_VDM_CNTL2__MCTPMasterValid_MASK 0x00008000L |
76844 | #define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L |
76845 | //PCIE_VDM_CNTL3 |
76846 | #define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf |
76847 | #define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10 |
76848 | #define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L |
76849 | #define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L |
76850 | //STALL_CONTROL_XBARPORT0_0 |
76851 | #define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0 |
76852 | #define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4 |
76853 | #define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8 |
76854 | #define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc |
76855 | #define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10 |
76856 | #define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c |
76857 | #define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L |
76858 | #define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L |
76859 | #define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L |
76860 | #define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L |
76861 | #define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L |
76862 | #define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L |
76863 | //STALL_CONTROL_XBARPORT0_1 |
76864 | #define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0 |
76865 | #define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4 |
76866 | #define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8 |
76867 | #define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc |
76868 | #define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10 |
76869 | #define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c |
76870 | #define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L |
76871 | #define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L |
76872 | #define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L |
76873 | #define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L |
76874 | #define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L |
76875 | #define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L |
76876 | //STALL_CONTROL_XBARPORT1_0 |
76877 | #define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0 |
76878 | #define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4 |
76879 | #define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8 |
76880 | #define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc |
76881 | #define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10 |
76882 | #define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c |
76883 | #define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L |
76884 | #define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L |
76885 | #define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L |
76886 | #define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L |
76887 | #define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L |
76888 | #define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L |
76889 | //STALL_CONTROL_XBARPORT1_1 |
76890 | #define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0 |
76891 | #define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4 |
76892 | #define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8 |
76893 | #define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc |
76894 | #define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10 |
76895 | #define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c |
76896 | #define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L |
76897 | #define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L |
76898 | #define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L |
76899 | #define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L |
76900 | #define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L |
76901 | #define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L |
76902 | //STALL_CONTROL_XBARPORT2_0 |
76903 | #define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0 |
76904 | #define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4 |
76905 | #define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8 |
76906 | #define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc |
76907 | #define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10 |
76908 | #define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c |
76909 | #define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L |
76910 | #define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L |
76911 | #define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L |
76912 | #define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L |
76913 | #define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L |
76914 | #define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L |
76915 | //STALL_CONTROL_XBARPORT2_1 |
76916 | #define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0 |
76917 | #define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4 |
76918 | #define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8 |
76919 | #define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc |
76920 | #define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10 |
76921 | #define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c |
76922 | #define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L |
76923 | #define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L |
76924 | #define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L |
76925 | #define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L |
76926 | #define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L |
76927 | #define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L |
76928 | //STALL_CONTROL_XBARPORT3_0 |
76929 | #define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0 |
76930 | #define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4 |
76931 | #define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8 |
76932 | #define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc |
76933 | #define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10 |
76934 | #define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c |
76935 | #define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L |
76936 | #define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L |
76937 | #define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L |
76938 | #define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L |
76939 | #define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L |
76940 | #define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L |
76941 | //STALL_CONTROL_XBARPORT3_1 |
76942 | #define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0 |
76943 | #define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4 |
76944 | #define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8 |
76945 | #define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc |
76946 | #define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10 |
76947 | #define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c |
76948 | #define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L |
76949 | #define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L |
76950 | #define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L |
76951 | #define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L |
76952 | #define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L |
76953 | #define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L |
76954 | //STALL_CONTROL_XBARPORT4_0 |
76955 | #define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0 |
76956 | #define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4 |
76957 | #define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8 |
76958 | #define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc |
76959 | #define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10 |
76960 | #define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c |
76961 | #define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L |
76962 | #define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L |
76963 | #define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L |
76964 | #define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L |
76965 | #define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L |
76966 | #define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L |
76967 | //STALL_CONTROL_XBARPORT4_1 |
76968 | #define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0 |
76969 | #define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4 |
76970 | #define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8 |
76971 | #define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc |
76972 | #define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10 |
76973 | #define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c |
76974 | #define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L |
76975 | #define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L |
76976 | #define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L |
76977 | #define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L |
76978 | #define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L |
76979 | #define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L |
76980 | //NB_DRAM3_BASE |
76981 | #define NB_DRAM3_BASE__DRAM3_BASE__SHIFT 0x0 |
76982 | #define NB_DRAM3_BASE__DRAM3_BASE_MASK 0x3FFFFFFFL |
76983 | //PSP_BASE_ADDR_LO |
76984 | #define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT 0x0 |
76985 | #define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT 0x8 |
76986 | #define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT 0x14 |
76987 | #define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK 0x00000001L |
76988 | #define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK 0x00000100L |
76989 | #define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK 0xFFF00000L |
76990 | //PSP_BASE_ADDR_HI |
76991 | #define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT 0x0 |
76992 | #define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK 0x0000FFFFL |
76993 | //SMU_BASE_ADDR_LO |
76994 | #define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT 0x0 |
76995 | #define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT 0x1 |
76996 | #define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT 0x14 |
76997 | #define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK 0x00000001L |
76998 | #define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK 0x00000002L |
76999 | #define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK 0xFFF00000L |
77000 | //SMU_BASE_ADDR_HI |
77001 | #define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT 0x0 |
77002 | #define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK 0x0000FFFFL |
77003 | //IOAPIC_BASE_ADDR_LO |
77004 | #define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN__SHIFT 0x0 |
77005 | #define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK__SHIFT 0x1 |
77006 | #define IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO__SHIFT 0x8 |
77007 | #define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN_MASK 0x00000001L |
77008 | #define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK_MASK 0x00000002L |
77009 | #define IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO_MASK 0xFFFFFF00L |
77010 | //IOAPIC_BASE_ADDR_HI |
77011 | #define IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI__SHIFT 0x0 |
77012 | #define IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI_MASK 0x0000FFFFL |
77013 | //FASTREG_BASE_ADDR_LO |
77014 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT 0x0 |
77015 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT 0x1 |
77016 | #define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT 0x14 |
77017 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK 0x00000001L |
77018 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK 0x00000002L |
77019 | #define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK 0xFFF00000L |
77020 | //FASTREG_BASE_ADDR_HI |
77021 | #define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT 0x0 |
77022 | #define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK 0x0000FFFFL |
77023 | //FASTREGCNTL_BASE_ADDR_LO |
77024 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT 0x0 |
77025 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT 0x1 |
77026 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT 0xc |
77027 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK 0x00000001L |
77028 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK 0x00000002L |
77029 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK 0xFFFFF000L |
77030 | //FASTREGCNTL_BASE_ADDR_HI |
77031 | #define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT 0x0 |
77032 | #define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK 0x0000FFFFL |
77033 | //SMMU_BASE_ADDR_LO |
77034 | #define SMMU_BASE_ADDR_LO__SMMU_MMIO_EN__SHIFT 0x0 |
77035 | #define SMMU_BASE_ADDR_LO__SMMU_MMIO_LOCK__SHIFT 0x1 |
77036 | #define SMMU_BASE_ADDR_LO__SMMU_BASE_ADDR_LO__SHIFT 0x13 |
77037 | #define SMMU_BASE_ADDR_LO__SMMU_MMIO_EN_MASK 0x00000001L |
77038 | #define SMMU_BASE_ADDR_LO__SMMU_MMIO_LOCK_MASK 0x00000002L |
77039 | #define SMMU_BASE_ADDR_LO__SMMU_BASE_ADDR_LO_MASK 0xFFF80000L |
77040 | //SMMU_BASE_ADDR_HI |
77041 | #define SMMU_BASE_ADDR_HI__SMMU_BASE_ADDR_HI__SHIFT 0x0 |
77042 | #define SMMU_BASE_ADDR_HI__SMMU_BASE_ADDR_HI_MASK 0x0000FFFFL |
77043 | //IOHC_PGMST_CNTL |
77044 | #define IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 |
77045 | #define IOHC_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 |
77046 | #define IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
77047 | #define IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT 0xe |
77048 | #define IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL |
77049 | #define IOHC_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L |
77050 | #define IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
77051 | #define IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK 0x0000C000L |
77052 | //IOHC_SDP_PORT_CONTROL |
77053 | #define IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0 |
77054 | #define IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis__SHIFT 0x6 |
77055 | #define IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT 0xf |
77056 | #define IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT 0x10 |
77057 | #define IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL |
77058 | #define IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis_MASK 0x00000FC0L |
77059 | #define IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK 0x00008000L |
77060 | #define IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK 0xFFFF0000L |
77061 | //IOHC_SDP_PARITY_CONTROL |
77062 | #define IOHC_SDP_PARITY_CONTROL__SDP_ParityDis__SHIFT 0x0 |
77063 | #define IOHC_SDP_PARITY_CONTROL__SDP_ParityDis_MASK 0x00000001L |
77064 | //IOHC_PGSLV_CNTL |
77065 | #define IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
77066 | #define IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
77067 | //SCRATCH_4 |
77068 | #define SCRATCH_4__SCRATCH_4__SHIFT 0x0 |
77069 | #define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL |
77070 | //SCRATCH_5 |
77071 | #define SCRATCH_5__SCRATCH_5__SHIFT 0x0 |
77072 | #define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL |
77073 | //SMU_BLOCK_CPU |
77074 | #define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT 0x0 |
77075 | #define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK 0x00000001L |
77076 | //SMU_BLOCK_CPU_STATUS |
77077 | #define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT 0x0 |
77078 | #define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK 0x00000001L |
77079 | //TRAP_STATUS |
77080 | #define TRAP_STATUS__TrapReqValid__SHIFT 0x0 |
77081 | #define TRAP_STATUS__TrapNumber__SHIFT 0x8 |
77082 | #define TRAP_STATUS__TrapReqValid_MASK 0x00000001L |
77083 | #define TRAP_STATUS__TrapNumber_MASK 0x00000F00L |
77084 | //TRAP_REQUEST0 |
77085 | #define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2 |
77086 | #define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL |
77087 | //TRAP_REQUEST1 |
77088 | #define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0 |
77089 | #define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL |
77090 | //TRAP_REQUEST2 |
77091 | #define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0 |
77092 | #define TRAP_REQUEST2__TrapAttr__SHIFT 0x8 |
77093 | #define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10 |
77094 | #define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL |
77095 | #define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L |
77096 | #define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L |
77097 | //TRAP_REQUEST3 |
77098 | #define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0 |
77099 | #define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4 |
77100 | #define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6 |
77101 | #define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7 |
77102 | #define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8 |
77103 | #define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9 |
77104 | #define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10 |
77105 | #define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L |
77106 | #define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L |
77107 | #define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L |
77108 | #define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L |
77109 | #define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L |
77110 | #define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L |
77111 | #define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L |
77112 | //TRAP_REQUEST4 |
77113 | #define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0 |
77114 | #define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x00000007L |
77115 | //TRAP_REQUEST5 |
77116 | #define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0 |
77117 | #define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4 |
77118 | #define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8 |
77119 | #define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L |
77120 | #define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L |
77121 | #define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L |
77122 | //TRAP_REQUEST_DATASTRB0 |
77123 | #define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0 |
77124 | #define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL |
77125 | //TRAP_REQUEST_DATASTRB1 |
77126 | #define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0 |
77127 | #define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL |
77128 | //TRAP_REQUEST_DATA0 |
77129 | #define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0 |
77130 | #define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL |
77131 | //TRAP_REQUEST_DATA1 |
77132 | #define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0 |
77133 | #define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL |
77134 | //TRAP_REQUEST_DATA2 |
77135 | #define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0 |
77136 | #define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL |
77137 | //TRAP_REQUEST_DATA3 |
77138 | #define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0 |
77139 | #define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL |
77140 | //TRAP_REQUEST_DATA4 |
77141 | #define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0 |
77142 | #define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL |
77143 | //TRAP_REQUEST_DATA5 |
77144 | #define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0 |
77145 | #define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL |
77146 | //TRAP_REQUEST_DATA6 |
77147 | #define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0 |
77148 | #define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL |
77149 | //TRAP_REQUEST_DATA7 |
77150 | #define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0 |
77151 | #define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL |
77152 | //TRAP_REQUEST_DATA8 |
77153 | #define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0 |
77154 | #define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL |
77155 | //TRAP_REQUEST_DATA9 |
77156 | #define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0 |
77157 | #define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL |
77158 | //TRAP_REQUEST_DATA10 |
77159 | #define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0 |
77160 | #define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL |
77161 | //TRAP_REQUEST_DATA11 |
77162 | #define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0 |
77163 | #define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL |
77164 | //TRAP_REQUEST_DATA12 |
77165 | #define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0 |
77166 | #define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL |
77167 | //TRAP_REQUEST_DATA13 |
77168 | #define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0 |
77169 | #define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL |
77170 | //TRAP_REQUEST_DATA14 |
77171 | #define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0 |
77172 | #define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL |
77173 | //TRAP_REQUEST_DATA15 |
77174 | #define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0 |
77175 | #define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL |
77176 | //TRAP_RESPONSE_CONTROL |
77177 | #define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0 |
77178 | #define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L |
77179 | //TRAP_RESPONSE0 |
77180 | #define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0 |
77181 | #define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4 |
77182 | #define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10 |
77183 | #define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L |
77184 | #define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L |
77185 | #define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x000F0000L |
77186 | //TRAP_RESPONSE_DATA0 |
77187 | #define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0 |
77188 | #define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL |
77189 | //TRAP_RESPONSE_DATA1 |
77190 | #define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0 |
77191 | #define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL |
77192 | //TRAP_RESPONSE_DATA2 |
77193 | #define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0 |
77194 | #define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL |
77195 | //TRAP_RESPONSE_DATA3 |
77196 | #define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0 |
77197 | #define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL |
77198 | //TRAP_RESPONSE_DATA4 |
77199 | #define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0 |
77200 | #define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL |
77201 | //TRAP_RESPONSE_DATA5 |
77202 | #define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0 |
77203 | #define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL |
77204 | //TRAP_RESPONSE_DATA6 |
77205 | #define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0 |
77206 | #define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL |
77207 | //TRAP_RESPONSE_DATA7 |
77208 | #define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0 |
77209 | #define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL |
77210 | //TRAP_RESPONSE_DATA8 |
77211 | #define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0 |
77212 | #define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL |
77213 | //TRAP_RESPONSE_DATA9 |
77214 | #define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0 |
77215 | #define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL |
77216 | //TRAP_RESPONSE_DATA10 |
77217 | #define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0 |
77218 | #define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL |
77219 | //TRAP_RESPONSE_DATA11 |
77220 | #define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0 |
77221 | #define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL |
77222 | //TRAP_RESPONSE_DATA12 |
77223 | #define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0 |
77224 | #define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL |
77225 | //TRAP_RESPONSE_DATA13 |
77226 | #define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0 |
77227 | #define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL |
77228 | //TRAP_RESPONSE_DATA14 |
77229 | #define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0 |
77230 | #define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL |
77231 | //TRAP_RESPONSE_DATA15 |
77232 | #define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0 |
77233 | #define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL |
77234 | //TRAP0_CONTROL0 |
77235 | #define TRAP0_CONTROL0__Trap0En__SHIFT 0x0 |
77236 | #define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT 0x3 |
77237 | #define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18 |
77238 | #define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L |
77239 | #define TRAP0_CONTROL0__Trap0SMUIntr_MASK 0x00000008L |
77240 | #define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0xFF000000L |
77241 | //TRAP0_ADDRESS_LO |
77242 | #define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2 |
77243 | #define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL |
77244 | //TRAP0_ADDRESS_HI |
77245 | #define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0 |
77246 | #define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0x0000FFFFL |
77247 | //TRAP0_COMMAND |
77248 | #define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0 |
77249 | #define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8 |
77250 | #define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL |
77251 | #define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L |
77252 | //TRAP0_ADDRESS_LO_MASK |
77253 | #define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2 |
77254 | #define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL |
77255 | //TRAP0_ADDRESS_HI_MASK |
77256 | #define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0 |
77257 | #define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0x0000FFFFL |
77258 | //TRAP0_COMMAND_MASK |
77259 | #define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0 |
77260 | #define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8 |
77261 | #define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL |
77262 | #define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L |
77263 | //TRAP1_CONTROL0 |
77264 | #define TRAP1_CONTROL0__Trap1En__SHIFT 0x0 |
77265 | #define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT 0x3 |
77266 | #define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18 |
77267 | #define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L |
77268 | #define TRAP1_CONTROL0__Trap1SMUIntr_MASK 0x00000008L |
77269 | #define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0xFF000000L |
77270 | //TRAP1_ADDRESS_LO |
77271 | #define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2 |
77272 | #define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL |
77273 | //TRAP1_ADDRESS_HI |
77274 | #define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0 |
77275 | #define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0x0000FFFFL |
77276 | //TRAP1_COMMAND |
77277 | #define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0 |
77278 | #define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8 |
77279 | #define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL |
77280 | #define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L |
77281 | //TRAP1_ADDRESS_LO_MASK |
77282 | #define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2 |
77283 | #define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL |
77284 | //TRAP1_ADDRESS_HI_MASK |
77285 | #define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0 |
77286 | #define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0x0000FFFFL |
77287 | //TRAP1_COMMAND_MASK |
77288 | #define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0 |
77289 | #define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8 |
77290 | #define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL |
77291 | #define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L |
77292 | //TRAP2_CONTROL0 |
77293 | #define TRAP2_CONTROL0__Trap2En__SHIFT 0x0 |
77294 | #define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT 0x3 |
77295 | #define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18 |
77296 | #define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L |
77297 | #define TRAP2_CONTROL0__Trap2SMUIntr_MASK 0x00000008L |
77298 | #define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0xFF000000L |
77299 | //TRAP2_ADDRESS_LO |
77300 | #define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2 |
77301 | #define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL |
77302 | //TRAP2_ADDRESS_HI |
77303 | #define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0 |
77304 | #define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0x0000FFFFL |
77305 | //TRAP2_COMMAND |
77306 | #define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0 |
77307 | #define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8 |
77308 | #define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL |
77309 | #define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L |
77310 | //TRAP2_ADDRESS_LO_MASK |
77311 | #define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2 |
77312 | #define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL |
77313 | //TRAP2_ADDRESS_HI_MASK |
77314 | #define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0 |
77315 | #define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0x0000FFFFL |
77316 | //TRAP2_COMMAND_MASK |
77317 | #define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0 |
77318 | #define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8 |
77319 | #define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL |
77320 | #define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L |
77321 | //TRAP3_CONTROL0 |
77322 | #define TRAP3_CONTROL0__Trap3En__SHIFT 0x0 |
77323 | #define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT 0x3 |
77324 | #define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18 |
77325 | #define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L |
77326 | #define TRAP3_CONTROL0__Trap3SMUIntr_MASK 0x00000008L |
77327 | #define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0xFF000000L |
77328 | //TRAP3_ADDRESS_LO |
77329 | #define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2 |
77330 | #define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL |
77331 | //TRAP3_ADDRESS_HI |
77332 | #define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0 |
77333 | #define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0x0000FFFFL |
77334 | //TRAP3_COMMAND |
77335 | #define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0 |
77336 | #define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8 |
77337 | #define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL |
77338 | #define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L |
77339 | //TRAP3_ADDRESS_LO_MASK |
77340 | #define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2 |
77341 | #define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL |
77342 | //TRAP3_ADDRESS_HI_MASK |
77343 | #define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0 |
77344 | #define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0x0000FFFFL |
77345 | //TRAP3_COMMAND_MASK |
77346 | #define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0 |
77347 | #define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8 |
77348 | #define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL |
77349 | #define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L |
77350 | //TRAP4_CONTROL0 |
77351 | #define TRAP4_CONTROL0__Trap4En__SHIFT 0x0 |
77352 | #define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT 0x3 |
77353 | #define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18 |
77354 | #define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L |
77355 | #define TRAP4_CONTROL0__Trap4SMUIntr_MASK 0x00000008L |
77356 | #define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0xFF000000L |
77357 | //TRAP4_ADDRESS_LO |
77358 | #define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2 |
77359 | #define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL |
77360 | //TRAP4_ADDRESS_HI |
77361 | #define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0 |
77362 | #define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0x0000FFFFL |
77363 | //TRAP4_COMMAND |
77364 | #define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0 |
77365 | #define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8 |
77366 | #define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL |
77367 | #define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L |
77368 | //TRAP4_ADDRESS_LO_MASK |
77369 | #define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2 |
77370 | #define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL |
77371 | //TRAP4_ADDRESS_HI_MASK |
77372 | #define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0 |
77373 | #define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0x0000FFFFL |
77374 | //TRAP4_COMMAND_MASK |
77375 | #define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0 |
77376 | #define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8 |
77377 | #define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL |
77378 | #define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L |
77379 | //TRAP5_CONTROL0 |
77380 | #define TRAP5_CONTROL0__Trap5En__SHIFT 0x0 |
77381 | #define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT 0x3 |
77382 | #define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18 |
77383 | #define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L |
77384 | #define TRAP5_CONTROL0__Trap5SMUIntr_MASK 0x00000008L |
77385 | #define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0xFF000000L |
77386 | //TRAP5_ADDRESS_LO |
77387 | #define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2 |
77388 | #define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL |
77389 | //TRAP5_ADDRESS_HI |
77390 | #define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0 |
77391 | #define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0x0000FFFFL |
77392 | //TRAP5_COMMAND |
77393 | #define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0 |
77394 | #define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8 |
77395 | #define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL |
77396 | #define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L |
77397 | //TRAP5_ADDRESS_LO_MASK |
77398 | #define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2 |
77399 | #define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL |
77400 | //TRAP5_ADDRESS_HI_MASK |
77401 | #define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0 |
77402 | #define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0x0000FFFFL |
77403 | //TRAP5_COMMAND_MASK |
77404 | #define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0 |
77405 | #define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8 |
77406 | #define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL |
77407 | #define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L |
77408 | //TRAP6_CONTROL0 |
77409 | #define TRAP6_CONTROL0__Trap6En__SHIFT 0x0 |
77410 | #define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT 0x3 |
77411 | #define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18 |
77412 | #define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L |
77413 | #define TRAP6_CONTROL0__Trap6SMUIntr_MASK 0x00000008L |
77414 | #define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0xFF000000L |
77415 | //TRAP6_ADDRESS_LO |
77416 | #define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2 |
77417 | #define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL |
77418 | //TRAP6_ADDRESS_HI |
77419 | #define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0 |
77420 | #define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0x0000FFFFL |
77421 | //TRAP6_COMMAND |
77422 | #define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0 |
77423 | #define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8 |
77424 | #define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL |
77425 | #define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L |
77426 | //TRAP6_ADDRESS_LO_MASK |
77427 | #define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2 |
77428 | #define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL |
77429 | //TRAP6_ADDRESS_HI_MASK |
77430 | #define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0 |
77431 | #define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0x0000FFFFL |
77432 | //TRAP6_COMMAND_MASK |
77433 | #define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0 |
77434 | #define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8 |
77435 | #define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL |
77436 | #define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L |
77437 | //TRAP7_CONTROL0 |
77438 | #define TRAP7_CONTROL0__Trap7En__SHIFT 0x0 |
77439 | #define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT 0x3 |
77440 | #define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18 |
77441 | #define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L |
77442 | #define TRAP7_CONTROL0__Trap7SMUIntr_MASK 0x00000008L |
77443 | #define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0xFF000000L |
77444 | //TRAP7_ADDRESS_LO |
77445 | #define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2 |
77446 | #define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL |
77447 | //TRAP7_ADDRESS_HI |
77448 | #define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0 |
77449 | #define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0x0000FFFFL |
77450 | //TRAP7_COMMAND |
77451 | #define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0 |
77452 | #define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8 |
77453 | #define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL |
77454 | #define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L |
77455 | //TRAP7_ADDRESS_LO_MASK |
77456 | #define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2 |
77457 | #define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL |
77458 | //TRAP7_ADDRESS_HI_MASK |
77459 | #define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0 |
77460 | #define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0x0000FFFFL |
77461 | //TRAP7_COMMAND_MASK |
77462 | #define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0 |
77463 | #define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8 |
77464 | #define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL |
77465 | #define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L |
77466 | //TRAP8_CONTROL0 |
77467 | #define TRAP8_CONTROL0__Trap8En__SHIFT 0x0 |
77468 | #define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT 0x3 |
77469 | #define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18 |
77470 | #define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L |
77471 | #define TRAP8_CONTROL0__Trap8SMUIntr_MASK 0x00000008L |
77472 | #define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0xFF000000L |
77473 | //TRAP8_ADDRESS_LO |
77474 | #define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2 |
77475 | #define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL |
77476 | //TRAP8_ADDRESS_HI |
77477 | #define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0 |
77478 | #define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0x0000FFFFL |
77479 | //TRAP8_COMMAND |
77480 | #define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0 |
77481 | #define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8 |
77482 | #define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL |
77483 | #define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L |
77484 | //TRAP8_ADDRESS_LO_MASK |
77485 | #define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2 |
77486 | #define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL |
77487 | //TRAP8_ADDRESS_HI_MASK |
77488 | #define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0 |
77489 | #define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0x0000FFFFL |
77490 | //TRAP8_COMMAND_MASK |
77491 | #define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0 |
77492 | #define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8 |
77493 | #define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL |
77494 | #define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L |
77495 | //TRAP9_CONTROL0 |
77496 | #define TRAP9_CONTROL0__Trap9En__SHIFT 0x0 |
77497 | #define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT 0x3 |
77498 | #define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18 |
77499 | #define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L |
77500 | #define TRAP9_CONTROL0__Trap9SMUIntr_MASK 0x00000008L |
77501 | #define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0xFF000000L |
77502 | //TRAP9_ADDRESS_LO |
77503 | #define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2 |
77504 | #define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL |
77505 | //TRAP9_ADDRESS_HI |
77506 | #define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0 |
77507 | #define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0x0000FFFFL |
77508 | //TRAP9_COMMAND |
77509 | #define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0 |
77510 | #define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8 |
77511 | #define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL |
77512 | #define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L |
77513 | //TRAP9_ADDRESS_LO_MASK |
77514 | #define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2 |
77515 | #define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL |
77516 | //TRAP9_ADDRESS_HI_MASK |
77517 | #define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0 |
77518 | #define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0x0000FFFFL |
77519 | //TRAP9_COMMAND_MASK |
77520 | #define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0 |
77521 | #define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8 |
77522 | #define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL |
77523 | #define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L |
77524 | //TRAP10_CONTROL0 |
77525 | #define TRAP10_CONTROL0__Trap10En__SHIFT 0x0 |
77526 | #define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT 0x3 |
77527 | #define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18 |
77528 | #define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L |
77529 | #define TRAP10_CONTROL0__Trap10SMUIntr_MASK 0x00000008L |
77530 | #define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0xFF000000L |
77531 | //TRAP10_ADDRESS_LO |
77532 | #define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2 |
77533 | #define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL |
77534 | //TRAP10_ADDRESS_HI |
77535 | #define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0 |
77536 | #define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0x0000FFFFL |
77537 | //TRAP10_COMMAND |
77538 | #define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0 |
77539 | #define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8 |
77540 | #define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL |
77541 | #define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L |
77542 | //TRAP10_ADDRESS_LO_MASK |
77543 | #define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2 |
77544 | #define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL |
77545 | //TRAP10_ADDRESS_HI_MASK |
77546 | #define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0 |
77547 | #define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0x0000FFFFL |
77548 | //TRAP10_COMMAND_MASK |
77549 | #define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0 |
77550 | #define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8 |
77551 | #define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL |
77552 | #define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L |
77553 | //TRAP11_CONTROL0 |
77554 | #define TRAP11_CONTROL0__Trap11En__SHIFT 0x0 |
77555 | #define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT 0x3 |
77556 | #define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18 |
77557 | #define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L |
77558 | #define TRAP11_CONTROL0__Trap11SMUIntr_MASK 0x00000008L |
77559 | #define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0xFF000000L |
77560 | //TRAP11_ADDRESS_LO |
77561 | #define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2 |
77562 | #define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL |
77563 | //TRAP11_ADDRESS_HI |
77564 | #define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0 |
77565 | #define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0x0000FFFFL |
77566 | //TRAP11_COMMAND |
77567 | #define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0 |
77568 | #define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8 |
77569 | #define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL |
77570 | #define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L |
77571 | //TRAP11_ADDRESS_LO_MASK |
77572 | #define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2 |
77573 | #define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL |
77574 | //TRAP11_ADDRESS_HI_MASK |
77575 | #define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0 |
77576 | #define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0x0000FFFFL |
77577 | //TRAP11_COMMAND_MASK |
77578 | #define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0 |
77579 | #define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8 |
77580 | #define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL |
77581 | #define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L |
77582 | //TRAP12_CONTROL0 |
77583 | #define TRAP12_CONTROL0__Trap12En__SHIFT 0x0 |
77584 | #define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT 0x3 |
77585 | #define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18 |
77586 | #define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L |
77587 | #define TRAP12_CONTROL0__Trap12SMUIntr_MASK 0x00000008L |
77588 | #define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0xFF000000L |
77589 | //TRAP12_ADDRESS_LO |
77590 | #define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2 |
77591 | #define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL |
77592 | //TRAP12_ADDRESS_HI |
77593 | #define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0 |
77594 | #define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0x0000FFFFL |
77595 | //TRAP12_COMMAND |
77596 | #define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0 |
77597 | #define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8 |
77598 | #define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL |
77599 | #define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L |
77600 | //TRAP12_ADDRESS_LO_MASK |
77601 | #define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2 |
77602 | #define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL |
77603 | //TRAP12_ADDRESS_HI_MASK |
77604 | #define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0 |
77605 | #define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0x0000FFFFL |
77606 | //TRAP12_COMMAND_MASK |
77607 | #define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0 |
77608 | #define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8 |
77609 | #define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL |
77610 | #define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L |
77611 | //TRAP13_CONTROL0 |
77612 | #define TRAP13_CONTROL0__Trap13En__SHIFT 0x0 |
77613 | #define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT 0x3 |
77614 | #define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18 |
77615 | #define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L |
77616 | #define TRAP13_CONTROL0__Trap13SMUIntr_MASK 0x00000008L |
77617 | #define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0xFF000000L |
77618 | //TRAP13_ADDRESS_LO |
77619 | #define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2 |
77620 | #define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL |
77621 | //TRAP13_ADDRESS_HI |
77622 | #define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0 |
77623 | #define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0x0000FFFFL |
77624 | //TRAP13_COMMAND |
77625 | #define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0 |
77626 | #define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8 |
77627 | #define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL |
77628 | #define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L |
77629 | //TRAP13_ADDRESS_LO_MASK |
77630 | #define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2 |
77631 | #define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL |
77632 | //TRAP13_ADDRESS_HI_MASK |
77633 | #define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0 |
77634 | #define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0x0000FFFFL |
77635 | //TRAP13_COMMAND_MASK |
77636 | #define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0 |
77637 | #define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8 |
77638 | #define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL |
77639 | #define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L |
77640 | //TRAP14_CONTROL0 |
77641 | #define TRAP14_CONTROL0__Trap14En__SHIFT 0x0 |
77642 | #define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT 0x3 |
77643 | #define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18 |
77644 | #define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L |
77645 | #define TRAP14_CONTROL0__Trap14SMUIntr_MASK 0x00000008L |
77646 | #define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0xFF000000L |
77647 | //TRAP14_ADDRESS_LO |
77648 | #define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2 |
77649 | #define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL |
77650 | //TRAP14_ADDRESS_HI |
77651 | #define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0 |
77652 | #define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0x0000FFFFL |
77653 | //TRAP14_COMMAND |
77654 | #define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0 |
77655 | #define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8 |
77656 | #define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL |
77657 | #define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L |
77658 | //TRAP14_ADDRESS_LO_MASK |
77659 | #define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2 |
77660 | #define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL |
77661 | //TRAP14_ADDRESS_HI_MASK |
77662 | #define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0 |
77663 | #define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0x0000FFFFL |
77664 | //TRAP14_COMMAND_MASK |
77665 | #define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0 |
77666 | #define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8 |
77667 | #define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL |
77668 | #define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L |
77669 | //TRAP15_CONTROL0 |
77670 | #define TRAP15_CONTROL0__Trap15En__SHIFT 0x0 |
77671 | #define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT 0x3 |
77672 | #define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18 |
77673 | #define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L |
77674 | #define TRAP15_CONTROL0__Trap15SMUIntr_MASK 0x00000008L |
77675 | #define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0xFF000000L |
77676 | //TRAP15_ADDRESS_LO |
77677 | #define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2 |
77678 | #define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL |
77679 | //TRAP15_ADDRESS_HI |
77680 | #define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0 |
77681 | #define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0x0000FFFFL |
77682 | //TRAP15_COMMAND |
77683 | #define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0 |
77684 | #define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8 |
77685 | #define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL |
77686 | #define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L |
77687 | //TRAP15_ADDRESS_LO_MASK |
77688 | #define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2 |
77689 | #define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL |
77690 | //TRAP15_ADDRESS_HI_MASK |
77691 | #define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0 |
77692 | #define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0x0000FFFFL |
77693 | //TRAP15_COMMAND_MASK |
77694 | #define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0 |
77695 | #define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8 |
77696 | #define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL |
77697 | #define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L |
77698 | //IOHC_REQDECODE_OVERRIDE |
77699 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT 0x0 |
77700 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT 0x4 |
77701 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT 0x8 |
77702 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT 0xc |
77703 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT 0x10 |
77704 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT 0x14 |
77705 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT 0x18 |
77706 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT 0x1c |
77707 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK 0x0000000FL |
77708 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK 0x000000F0L |
77709 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK 0x00000F00L |
77710 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK 0x0000F000L |
77711 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK 0x000F0000L |
77712 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK 0x00F00000L |
77713 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK 0x0F000000L |
77714 | #define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK 0xF0000000L |
77715 | //IOHC_RSPDECODE_OVERRIDE |
77716 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT 0x0 |
77717 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT 0x4 |
77718 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT 0x8 |
77719 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT 0xc |
77720 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT 0x10 |
77721 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT 0x14 |
77722 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT 0x18 |
77723 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT 0x1c |
77724 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK 0x0000000FL |
77725 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK 0x000000F0L |
77726 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK 0x00000F00L |
77727 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK 0x0000F000L |
77728 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK 0x000F0000L |
77729 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK 0x00F00000L |
77730 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK 0x0F000000L |
77731 | #define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK 0xF0000000L |
77732 | //IOHC_RSPPASSPW_OVERRIDE |
77733 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0__SHIFT 0x0 |
77734 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1__SHIFT 0x4 |
77735 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2__SHIFT 0x8 |
77736 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3__SHIFT 0xc |
77737 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4__SHIFT 0x10 |
77738 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5__SHIFT 0x14 |
77739 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6__SHIFT 0x18 |
77740 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7__SHIFT 0x1c |
77741 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0_MASK 0x0000000FL |
77742 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1_MASK 0x000000F0L |
77743 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2_MASK 0x00000F00L |
77744 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3_MASK 0x0000F000L |
77745 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4_MASK 0x000F0000L |
77746 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5_MASK 0x00F00000L |
77747 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6_MASK 0x0F000000L |
77748 | #define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7_MASK 0xF0000000L |
77749 | //IOHC_USERBIT_BYPASS |
77750 | #define IOHC_USERBIT_BYPASS__Userbit_Bypass__SHIFT 0x0 |
77751 | #define IOHC_USERBIT_BYPASS__Userbit_Bypass_MASK 0x00000001L |
77752 | //IOHC_SMN_MASTER_CNTL |
77753 | #define IOHC_SMN_MASTER_CNTL__SmnErrRspMap__SHIFT 0x0 |
77754 | #define IOHC_SMN_MASTER_CNTL__SmnErrRspMap_MASK 0x00000001L |
77755 | //IOHC_SMN_MASTER_STATUS |
77756 | #define IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus__SHIFT 0x0 |
77757 | #define IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus_MASK 0x00000001L |
77758 | //SB_COMMAND |
77759 | #define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
77760 | #define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
77761 | #define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
77762 | #define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
77763 | #define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
77764 | #define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
77765 | //SB_SUB_BUS_NUMBER_LATENCY |
77766 | #define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
77767 | #define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
77768 | #define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
77769 | #define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
77770 | //SB_IO_BASE_LIMIT |
77771 | #define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
77772 | #define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
77773 | #define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
77774 | #define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
77775 | //SB_MEM_BASE_LIMIT |
77776 | #define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
77777 | #define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
77778 | #define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
77779 | #define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
77780 | //SB_PREF_BASE_LIMIT |
77781 | #define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
77782 | #define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
77783 | #define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
77784 | #define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
77785 | //SB_PREF_BASE_UPPER |
77786 | #define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
77787 | #define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
77788 | //SB_PREF_LIMIT_UPPER |
77789 | #define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
77790 | #define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
77791 | //SB_IO_BASE_LIMIT_HI |
77792 | #define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
77793 | #define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
77794 | #define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
77795 | #define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
77796 | //SB_IRQ_BRIDGE_CNTL |
77797 | #define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
77798 | #define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
77799 | #define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
77800 | #define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
77801 | #define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
77802 | #define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
77803 | //SB_EXT_BRIDGE_CNTL |
77804 | #define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
77805 | #define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
77806 | //SB_PMI_STATUS_CNTL |
77807 | #define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
77808 | #define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
77809 | //SB_SLOT_CAP |
77810 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
77811 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
77812 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
77813 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
77814 | //SB_ROOT_CNTL |
77815 | #define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
77816 | #define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
77817 | //SB_DEVICE_CNTL2 |
77818 | #define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
77819 | #define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
77820 | //IOHC_QOS_CONTROL |
77821 | #define IOHC_QOS_CONTROL__VC0QoSPriority__SHIFT 0x0 |
77822 | #define IOHC_QOS_CONTROL__VC1QoSPriority__SHIFT 0x4 |
77823 | #define IOHC_QOS_CONTROL__VC2QoSPriority__SHIFT 0x8 |
77824 | #define IOHC_QOS_CONTROL__VC3QoSPriority__SHIFT 0xc |
77825 | #define IOHC_QOS_CONTROL__VC4QoSPriority__SHIFT 0x10 |
77826 | #define IOHC_QOS_CONTROL__VC5QoSPriority__SHIFT 0x14 |
77827 | #define IOHC_QOS_CONTROL__VC6QoSPriority__SHIFT 0x18 |
77828 | #define IOHC_QOS_CONTROL__VC7QoSPriority__SHIFT 0x1c |
77829 | #define IOHC_QOS_CONTROL__VC0QoSPriority_MASK 0x0000000FL |
77830 | #define IOHC_QOS_CONTROL__VC1QoSPriority_MASK 0x000000F0L |
77831 | #define IOHC_QOS_CONTROL__VC2QoSPriority_MASK 0x00000F00L |
77832 | #define IOHC_QOS_CONTROL__VC3QoSPriority_MASK 0x0000F000L |
77833 | #define IOHC_QOS_CONTROL__VC4QoSPriority_MASK 0x000F0000L |
77834 | #define IOHC_QOS_CONTROL__VC5QoSPriority_MASK 0x00F00000L |
77835 | #define IOHC_QOS_CONTROL__VC6QoSPriority_MASK 0x0F000000L |
77836 | #define IOHC_QOS_CONTROL__VC7QoSPriority_MASK 0xF0000000L |
77837 | //USB_QoS_CNTL |
77838 | #define USB_QoS_CNTL__UnitID0__SHIFT 0x0 |
77839 | #define USB_QoS_CNTL__UnitID0QoSPriority__SHIFT 0x8 |
77840 | #define USB_QoS_CNTL__UnitID0Enable__SHIFT 0xc |
77841 | #define USB_QoS_CNTL__UnitID1__SHIFT 0x10 |
77842 | #define USB_QoS_CNTL__UnitID1QoSPriority__SHIFT 0x18 |
77843 | #define USB_QoS_CNTL__UnitID1Enable__SHIFT 0x1c |
77844 | #define USB_QoS_CNTL__UnitID0_MASK 0x0000007FL |
77845 | #define USB_QoS_CNTL__UnitID0QoSPriority_MASK 0x00000F00L |
77846 | #define USB_QoS_CNTL__UnitID0Enable_MASK 0x00001000L |
77847 | #define USB_QoS_CNTL__UnitID1_MASK 0x007F0000L |
77848 | #define USB_QoS_CNTL__UnitID1QoSPriority_MASK 0x0F000000L |
77849 | #define USB_QoS_CNTL__UnitID1Enable_MASK 0x10000000L |
77850 | //IOHC_SION_S0_Client0_Req_BurstTarget_Lower |
77851 | #define IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT 0x0 |
77852 | #define IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77853 | //IOHC_SION_S0_Client0_Req_BurstTarget_Upper |
77854 | #define IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT 0x0 |
77855 | #define IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77856 | //IOHC_SION_S0_Client0_Req_TimeSlot_Lower |
77857 | #define IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT 0x0 |
77858 | #define IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77859 | //IOHC_SION_S0_Client0_Req_TimeSlot_Upper |
77860 | #define IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT 0x0 |
77861 | #define IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77862 | //IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower |
77863 | #define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
77864 | #define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77865 | //IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper |
77866 | #define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
77867 | #define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77868 | //IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower |
77869 | #define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
77870 | #define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77871 | //IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper |
77872 | #define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
77873 | #define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77874 | //IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower |
77875 | #define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
77876 | #define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77877 | //IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper |
77878 | #define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
77879 | #define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77880 | //IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower |
77881 | #define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
77882 | #define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77883 | //IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper |
77884 | #define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
77885 | #define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77886 | //IOHC_SION_S1_Client0_Req_BurstTarget_Lower |
77887 | #define IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT 0x0 |
77888 | #define IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77889 | //IOHC_SION_S1_Client0_Req_BurstTarget_Upper |
77890 | #define IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT 0x0 |
77891 | #define IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77892 | //IOHC_SION_S1_Client0_Req_TimeSlot_Lower |
77893 | #define IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT 0x0 |
77894 | #define IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77895 | //IOHC_SION_S1_Client0_Req_TimeSlot_Upper |
77896 | #define IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT 0x0 |
77897 | #define IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77898 | //IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower |
77899 | #define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
77900 | #define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77901 | //IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper |
77902 | #define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
77903 | #define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77904 | //IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower |
77905 | #define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
77906 | #define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77907 | //IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper |
77908 | #define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
77909 | #define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77910 | //IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower |
77911 | #define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
77912 | #define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77913 | //IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper |
77914 | #define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
77915 | #define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77916 | //IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower |
77917 | #define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
77918 | #define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77919 | //IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper |
77920 | #define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
77921 | #define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77922 | //IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower |
77923 | #define IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
77924 | #define IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
77925 | //IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper |
77926 | #define IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
77927 | #define IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
77928 | //IOHC_SION_Client0_DataPoolCredit_Alloc_Lower |
77929 | #define IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
77930 | #define IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
77931 | //IOHC_SION_Client0_DataPoolCredit_Alloc_Upper |
77932 | #define IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
77933 | #define IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
77934 | //IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower |
77935 | #define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
77936 | #define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
77937 | //IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper |
77938 | #define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
77939 | #define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
77940 | //IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower |
77941 | #define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
77942 | #define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
77943 | //IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper |
77944 | #define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
77945 | #define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
77946 | //IOHC_SION_S0_Client1_Req_BurstTarget_Lower |
77947 | #define IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT 0x0 |
77948 | #define IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77949 | //IOHC_SION_S0_Client1_Req_BurstTarget_Upper |
77950 | #define IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT 0x0 |
77951 | #define IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77952 | //IOHC_SION_S0_Client1_Req_TimeSlot_Lower |
77953 | #define IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT 0x0 |
77954 | #define IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77955 | //IOHC_SION_S0_Client1_Req_TimeSlot_Upper |
77956 | #define IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT 0x0 |
77957 | #define IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77958 | //IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower |
77959 | #define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
77960 | #define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77961 | //IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper |
77962 | #define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
77963 | #define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77964 | //IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower |
77965 | #define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
77966 | #define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77967 | //IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper |
77968 | #define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
77969 | #define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77970 | //IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower |
77971 | #define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
77972 | #define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77973 | //IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper |
77974 | #define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
77975 | #define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77976 | //IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower |
77977 | #define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
77978 | #define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77979 | //IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper |
77980 | #define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
77981 | #define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77982 | //IOHC_SION_S1_Client1_Req_BurstTarget_Lower |
77983 | #define IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT 0x0 |
77984 | #define IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77985 | //IOHC_SION_S1_Client1_Req_BurstTarget_Upper |
77986 | #define IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT 0x0 |
77987 | #define IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
77988 | //IOHC_SION_S1_Client1_Req_TimeSlot_Lower |
77989 | #define IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT 0x0 |
77990 | #define IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
77991 | //IOHC_SION_S1_Client1_Req_TimeSlot_Upper |
77992 | #define IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT 0x0 |
77993 | #define IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
77994 | //IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower |
77995 | #define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
77996 | #define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
77997 | //IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper |
77998 | #define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
77999 | #define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78000 | //IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower |
78001 | #define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78002 | #define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78003 | //IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper |
78004 | #define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78005 | #define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78006 | //IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower |
78007 | #define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78008 | #define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78009 | //IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper |
78010 | #define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78011 | #define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78012 | //IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower |
78013 | #define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78014 | #define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78015 | //IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper |
78016 | #define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78017 | #define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78018 | //IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower |
78019 | #define IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
78020 | #define IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78021 | //IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper |
78022 | #define IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
78023 | #define IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78024 | //IOHC_SION_Client1_DataPoolCredit_Alloc_Lower |
78025 | #define IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
78026 | #define IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78027 | //IOHC_SION_Client1_DataPoolCredit_Alloc_Upper |
78028 | #define IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
78029 | #define IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78030 | //IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower |
78031 | #define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78032 | #define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78033 | //IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper |
78034 | #define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78035 | #define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78036 | //IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower |
78037 | #define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78038 | #define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78039 | //IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper |
78040 | #define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78041 | #define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78042 | //IOHC_SION_S0_Client2_Req_BurstTarget_Lower |
78043 | #define IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT 0x0 |
78044 | #define IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78045 | //IOHC_SION_S0_Client2_Req_BurstTarget_Upper |
78046 | #define IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT 0x0 |
78047 | #define IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78048 | //IOHC_SION_S0_Client2_Req_TimeSlot_Lower |
78049 | #define IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT 0x0 |
78050 | #define IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78051 | //IOHC_SION_S0_Client2_Req_TimeSlot_Upper |
78052 | #define IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT 0x0 |
78053 | #define IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78054 | //IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower |
78055 | #define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
78056 | #define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78057 | //IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper |
78058 | #define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
78059 | #define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78060 | //IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower |
78061 | #define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78062 | #define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78063 | //IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper |
78064 | #define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78065 | #define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78066 | //IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower |
78067 | #define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78068 | #define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78069 | //IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper |
78070 | #define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78071 | #define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78072 | //IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower |
78073 | #define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78074 | #define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78075 | //IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper |
78076 | #define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78077 | #define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78078 | //IOHC_SION_S1_Client2_Req_BurstTarget_Lower |
78079 | #define IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT 0x0 |
78080 | #define IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78081 | //IOHC_SION_S1_Client2_Req_BurstTarget_Upper |
78082 | #define IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT 0x0 |
78083 | #define IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78084 | //IOHC_SION_S1_Client2_Req_TimeSlot_Lower |
78085 | #define IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT 0x0 |
78086 | #define IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78087 | //IOHC_SION_S1_Client2_Req_TimeSlot_Upper |
78088 | #define IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT 0x0 |
78089 | #define IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78090 | //IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower |
78091 | #define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
78092 | #define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78093 | //IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper |
78094 | #define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
78095 | #define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78096 | //IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower |
78097 | #define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78098 | #define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78099 | //IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper |
78100 | #define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78101 | #define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78102 | //IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower |
78103 | #define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78104 | #define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78105 | //IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper |
78106 | #define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78107 | #define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78108 | //IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower |
78109 | #define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78110 | #define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78111 | //IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper |
78112 | #define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78113 | #define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78114 | //IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower |
78115 | #define IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
78116 | #define IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78117 | //IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper |
78118 | #define IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
78119 | #define IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78120 | //IOHC_SION_Client2_DataPoolCredit_Alloc_Lower |
78121 | #define IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
78122 | #define IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78123 | //IOHC_SION_Client2_DataPoolCredit_Alloc_Upper |
78124 | #define IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
78125 | #define IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78126 | //IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower |
78127 | #define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78128 | #define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78129 | //IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper |
78130 | #define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78131 | #define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78132 | //IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower |
78133 | #define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78134 | #define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78135 | //IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper |
78136 | #define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78137 | #define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78138 | //IOHC_SION_S0_Client3_Req_BurstTarget_Lower |
78139 | #define IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT 0x0 |
78140 | #define IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78141 | //IOHC_SION_S0_Client3_Req_BurstTarget_Upper |
78142 | #define IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT 0x0 |
78143 | #define IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78144 | //IOHC_SION_S0_Client3_Req_TimeSlot_Lower |
78145 | #define IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT 0x0 |
78146 | #define IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78147 | //IOHC_SION_S0_Client3_Req_TimeSlot_Upper |
78148 | #define IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT 0x0 |
78149 | #define IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78150 | //IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower |
78151 | #define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
78152 | #define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78153 | //IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper |
78154 | #define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
78155 | #define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78156 | //IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower |
78157 | #define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78158 | #define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78159 | //IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper |
78160 | #define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78161 | #define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78162 | //IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower |
78163 | #define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78164 | #define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78165 | //IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper |
78166 | #define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78167 | #define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78168 | //IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower |
78169 | #define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78170 | #define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78171 | //IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper |
78172 | #define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78173 | #define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78174 | //IOHC_SION_S1_Client3_Req_BurstTarget_Lower |
78175 | #define IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT 0x0 |
78176 | #define IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78177 | //IOHC_SION_S1_Client3_Req_BurstTarget_Upper |
78178 | #define IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT 0x0 |
78179 | #define IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78180 | //IOHC_SION_S1_Client3_Req_TimeSlot_Lower |
78181 | #define IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT 0x0 |
78182 | #define IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78183 | //IOHC_SION_S1_Client3_Req_TimeSlot_Upper |
78184 | #define IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT 0x0 |
78185 | #define IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78186 | //IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower |
78187 | #define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
78188 | #define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78189 | //IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper |
78190 | #define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
78191 | #define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78192 | //IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower |
78193 | #define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78194 | #define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78195 | //IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper |
78196 | #define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78197 | #define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78198 | //IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower |
78199 | #define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78200 | #define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78201 | //IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper |
78202 | #define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78203 | #define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78204 | //IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower |
78205 | #define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78206 | #define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78207 | //IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper |
78208 | #define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78209 | #define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78210 | //IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower |
78211 | #define IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
78212 | #define IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78213 | //IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper |
78214 | #define IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
78215 | #define IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78216 | //IOHC_SION_Client3_DataPoolCredit_Alloc_Lower |
78217 | #define IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
78218 | #define IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78219 | //IOHC_SION_Client3_DataPoolCredit_Alloc_Upper |
78220 | #define IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
78221 | #define IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78222 | //IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower |
78223 | #define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78224 | #define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78225 | //IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper |
78226 | #define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78227 | #define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78228 | //IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower |
78229 | #define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78230 | #define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78231 | //IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper |
78232 | #define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78233 | #define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78234 | //IOHC_SION_S0_Client4_Req_BurstTarget_Lower |
78235 | #define IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower__SHIFT 0x0 |
78236 | #define IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78237 | //IOHC_SION_S0_Client4_Req_BurstTarget_Upper |
78238 | #define IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper__SHIFT 0x0 |
78239 | #define IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78240 | //IOHC_SION_S0_Client4_Req_TimeSlot_Lower |
78241 | #define IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower__SHIFT 0x0 |
78242 | #define IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78243 | //IOHC_SION_S0_Client4_Req_TimeSlot_Upper |
78244 | #define IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper__SHIFT 0x0 |
78245 | #define IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78246 | //IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower |
78247 | #define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
78248 | #define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78249 | //IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper |
78250 | #define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
78251 | #define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78252 | //IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower |
78253 | #define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78254 | #define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78255 | //IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper |
78256 | #define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78257 | #define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78258 | //IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower |
78259 | #define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78260 | #define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78261 | //IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper |
78262 | #define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78263 | #define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78264 | //IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower |
78265 | #define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78266 | #define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78267 | //IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper |
78268 | #define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78269 | #define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78270 | //IOHC_SION_S1_Client4_Req_BurstTarget_Lower |
78271 | #define IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower__SHIFT 0x0 |
78272 | #define IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78273 | //IOHC_SION_S1_Client4_Req_BurstTarget_Upper |
78274 | #define IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper__SHIFT 0x0 |
78275 | #define IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78276 | //IOHC_SION_S1_Client4_Req_TimeSlot_Lower |
78277 | #define IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower__SHIFT 0x0 |
78278 | #define IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78279 | //IOHC_SION_S1_Client4_Req_TimeSlot_Upper |
78280 | #define IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper__SHIFT 0x0 |
78281 | #define IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78282 | //IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower |
78283 | #define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
78284 | #define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78285 | //IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper |
78286 | #define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
78287 | #define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78288 | //IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower |
78289 | #define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
78290 | #define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78291 | //IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper |
78292 | #define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
78293 | #define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78294 | //IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower |
78295 | #define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
78296 | #define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
78297 | //IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper |
78298 | #define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
78299 | #define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
78300 | //IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower |
78301 | #define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
78302 | #define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
78303 | //IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper |
78304 | #define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
78305 | #define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
78306 | //IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower |
78307 | #define IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
78308 | #define IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78309 | //IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper |
78310 | #define IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
78311 | #define IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78312 | //IOHC_SION_Client4_DataPoolCredit_Alloc_Lower |
78313 | #define IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
78314 | #define IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78315 | //IOHC_SION_Client4_DataPoolCredit_Alloc_Upper |
78316 | #define IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
78317 | #define IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78318 | //IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower |
78319 | #define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78320 | #define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78321 | //IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper |
78322 | #define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78323 | #define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78324 | //IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower |
78325 | #define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
78326 | #define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
78327 | //IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper |
78328 | #define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
78329 | #define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
78330 | //IOHC_SION_LiveLock_WatchDog_Threshold |
78331 | #define IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold__SHIFT 0x0 |
78332 | #define IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold_MASK 0x000000FFL |
78333 | |
78334 | |
78335 | // addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec |
78336 | //PARITY_CONTROL_0 |
78337 | #define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0 |
78338 | #define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10 |
78339 | #define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL |
78340 | #define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L |
78341 | //PARITY_CONTROL_1 |
78342 | #define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0 |
78343 | #define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8 |
78344 | #define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb |
78345 | #define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10 |
78346 | #define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e |
78347 | #define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f |
78348 | #define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL |
78349 | #define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L |
78350 | #define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L |
78351 | #define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L |
78352 | #define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L |
78353 | #define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L |
78354 | //PARITY_SEVERITY_CONTROL_UNCORR_0 |
78355 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0 |
78356 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2 |
78357 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4 |
78358 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6 |
78359 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8 |
78360 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L |
78361 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL |
78362 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L |
78363 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L |
78364 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L |
78365 | //PARITY_SEVERITY_CONTROL_CORR_0 |
78366 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0 |
78367 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2 |
78368 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4 |
78369 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6 |
78370 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8 |
78371 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L |
78372 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL |
78373 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L |
78374 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L |
78375 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L |
78376 | //PARITY_SEVERITY_CONTROL_UCP_0 |
78377 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0 |
78378 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2 |
78379 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4 |
78380 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6 |
78381 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8 |
78382 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L |
78383 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL |
78384 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L |
78385 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L |
78386 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L |
78387 | //RAS_GLOBAL_STATUS_LO |
78388 | #define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0 |
78389 | #define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1 |
78390 | #define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2 |
78391 | #define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3 |
78392 | #define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6 |
78393 | #define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7 |
78394 | #define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8 |
78395 | #define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9 |
78396 | #define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa |
78397 | #define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb |
78398 | #define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc |
78399 | #define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd |
78400 | #define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe |
78401 | #define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf |
78402 | #define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L |
78403 | #define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L |
78404 | #define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L |
78405 | #define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L |
78406 | #define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L |
78407 | #define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L |
78408 | #define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L |
78409 | #define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L |
78410 | #define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L |
78411 | #define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L |
78412 | #define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L |
78413 | #define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L |
78414 | #define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L |
78415 | #define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L |
78416 | //RAS_GLOBAL_STATUS_HI |
78417 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0 |
78418 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT 0x1 |
78419 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT 0x2 |
78420 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT 0x3 |
78421 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT 0x4 |
78422 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT 0x5 |
78423 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT 0x6 |
78424 | #define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT 0x7 |
78425 | #define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr__SHIFT 0x8 |
78426 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L |
78427 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK 0x00000002L |
78428 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK 0x00000004L |
78429 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK 0x00000008L |
78430 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK 0x00000010L |
78431 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK 0x00000020L |
78432 | #define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK 0x00000040L |
78433 | #define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK 0x00000080L |
78434 | #define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr_MASK 0x00000100L |
78435 | //PARITY_ERROR_STATUS_UNCORR_GRP0 |
78436 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 |
78437 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 |
78438 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 |
78439 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 |
78440 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 |
78441 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 |
78442 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 |
78443 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 |
78444 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 |
78445 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 |
78446 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa |
78447 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb |
78448 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc |
78449 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd |
78450 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe |
78451 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf |
78452 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 |
78453 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 |
78454 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 |
78455 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 |
78456 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 |
78457 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 |
78458 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 |
78459 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 |
78460 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 |
78461 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 |
78462 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a |
78463 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b |
78464 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c |
78465 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d |
78466 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e |
78467 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f |
78468 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L |
78469 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L |
78470 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L |
78471 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L |
78472 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L |
78473 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L |
78474 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L |
78475 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L |
78476 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L |
78477 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L |
78478 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L |
78479 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L |
78480 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L |
78481 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L |
78482 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L |
78483 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L |
78484 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L |
78485 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L |
78486 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L |
78487 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L |
78488 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L |
78489 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L |
78490 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L |
78491 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L |
78492 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L |
78493 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L |
78494 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L |
78495 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L |
78496 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L |
78497 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L |
78498 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L |
78499 | #define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L |
78500 | //PARITY_ERROR_STATUS_UNCORR_GRP1 |
78501 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 |
78502 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 |
78503 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 |
78504 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 |
78505 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 |
78506 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 |
78507 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 |
78508 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 |
78509 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 |
78510 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 |
78511 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa |
78512 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb |
78513 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc |
78514 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd |
78515 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe |
78516 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf |
78517 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 |
78518 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 |
78519 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 |
78520 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 |
78521 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 |
78522 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 |
78523 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 |
78524 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 |
78525 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 |
78526 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 |
78527 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a |
78528 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b |
78529 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c |
78530 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d |
78531 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e |
78532 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f |
78533 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L |
78534 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L |
78535 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L |
78536 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L |
78537 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L |
78538 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L |
78539 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L |
78540 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L |
78541 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L |
78542 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L |
78543 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L |
78544 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L |
78545 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L |
78546 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L |
78547 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L |
78548 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L |
78549 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L |
78550 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L |
78551 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L |
78552 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L |
78553 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L |
78554 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L |
78555 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L |
78556 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L |
78557 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L |
78558 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L |
78559 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L |
78560 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L |
78561 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L |
78562 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L |
78563 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L |
78564 | #define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L |
78565 | //PARITY_ERROR_STATUS_UNCORR_GRP2 |
78566 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 |
78567 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 |
78568 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 |
78569 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 |
78570 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 |
78571 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 |
78572 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 |
78573 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 |
78574 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 |
78575 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 |
78576 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa |
78577 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb |
78578 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc |
78579 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd |
78580 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe |
78581 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf |
78582 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 |
78583 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 |
78584 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 |
78585 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 |
78586 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 |
78587 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 |
78588 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 |
78589 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 |
78590 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 |
78591 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 |
78592 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a |
78593 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b |
78594 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c |
78595 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d |
78596 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e |
78597 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f |
78598 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L |
78599 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L |
78600 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L |
78601 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L |
78602 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L |
78603 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L |
78604 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L |
78605 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L |
78606 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L |
78607 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L |
78608 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L |
78609 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L |
78610 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L |
78611 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L |
78612 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L |
78613 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L |
78614 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L |
78615 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L |
78616 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L |
78617 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L |
78618 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L |
78619 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L |
78620 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L |
78621 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L |
78622 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L |
78623 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L |
78624 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L |
78625 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L |
78626 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L |
78627 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L |
78628 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L |
78629 | #define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L |
78630 | //PARITY_ERROR_STATUS_UNCORR_GRP3 |
78631 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 |
78632 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 |
78633 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 |
78634 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 |
78635 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 |
78636 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 |
78637 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 |
78638 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 |
78639 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 |
78640 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 |
78641 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa |
78642 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb |
78643 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc |
78644 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd |
78645 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe |
78646 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf |
78647 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 |
78648 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 |
78649 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 |
78650 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 |
78651 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 |
78652 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 |
78653 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 |
78654 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 |
78655 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 |
78656 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 |
78657 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a |
78658 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b |
78659 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c |
78660 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d |
78661 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e |
78662 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f |
78663 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L |
78664 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L |
78665 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L |
78666 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L |
78667 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L |
78668 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L |
78669 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L |
78670 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L |
78671 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L |
78672 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L |
78673 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L |
78674 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L |
78675 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L |
78676 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L |
78677 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L |
78678 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L |
78679 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L |
78680 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L |
78681 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L |
78682 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L |
78683 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L |
78684 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L |
78685 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L |
78686 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L |
78687 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L |
78688 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L |
78689 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L |
78690 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L |
78691 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L |
78692 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L |
78693 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L |
78694 | #define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L |
78695 | //PARITY_ERROR_STATUS_UNCORR_GRP4 |
78696 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 |
78697 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 |
78698 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 |
78699 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 |
78700 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 |
78701 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 |
78702 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 |
78703 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 |
78704 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 |
78705 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 |
78706 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa |
78707 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb |
78708 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc |
78709 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd |
78710 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe |
78711 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf |
78712 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 |
78713 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 |
78714 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 |
78715 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 |
78716 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 |
78717 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 |
78718 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 |
78719 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 |
78720 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 |
78721 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 |
78722 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a |
78723 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b |
78724 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c |
78725 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d |
78726 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e |
78727 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f |
78728 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L |
78729 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L |
78730 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L |
78731 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L |
78732 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L |
78733 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L |
78734 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L |
78735 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L |
78736 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L |
78737 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L |
78738 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L |
78739 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L |
78740 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L |
78741 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L |
78742 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L |
78743 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L |
78744 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L |
78745 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L |
78746 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L |
78747 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L |
78748 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L |
78749 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L |
78750 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L |
78751 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L |
78752 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L |
78753 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L |
78754 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L |
78755 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L |
78756 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L |
78757 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L |
78758 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L |
78759 | #define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L |
78760 | //PARITY_ERROR_STATUS_CORR_GRP0 |
78761 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 |
78762 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 |
78763 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 |
78764 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 |
78765 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 |
78766 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 |
78767 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 |
78768 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 |
78769 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 |
78770 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 |
78771 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa |
78772 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb |
78773 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc |
78774 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd |
78775 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe |
78776 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf |
78777 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 |
78778 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 |
78779 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 |
78780 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 |
78781 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 |
78782 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 |
78783 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 |
78784 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 |
78785 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 |
78786 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 |
78787 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a |
78788 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b |
78789 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c |
78790 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d |
78791 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e |
78792 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f |
78793 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L |
78794 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L |
78795 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L |
78796 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L |
78797 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L |
78798 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L |
78799 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L |
78800 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L |
78801 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L |
78802 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L |
78803 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L |
78804 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L |
78805 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L |
78806 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L |
78807 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L |
78808 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L |
78809 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L |
78810 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L |
78811 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L |
78812 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L |
78813 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L |
78814 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L |
78815 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L |
78816 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L |
78817 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L |
78818 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L |
78819 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L |
78820 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L |
78821 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L |
78822 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L |
78823 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L |
78824 | #define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L |
78825 | //PARITY_ERROR_STATUS_CORR_GRP1 |
78826 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 |
78827 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 |
78828 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 |
78829 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 |
78830 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 |
78831 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 |
78832 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 |
78833 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 |
78834 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 |
78835 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 |
78836 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa |
78837 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb |
78838 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc |
78839 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd |
78840 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe |
78841 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf |
78842 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 |
78843 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 |
78844 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 |
78845 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 |
78846 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 |
78847 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 |
78848 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 |
78849 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 |
78850 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 |
78851 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 |
78852 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a |
78853 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b |
78854 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c |
78855 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d |
78856 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e |
78857 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f |
78858 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L |
78859 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L |
78860 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L |
78861 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L |
78862 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L |
78863 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L |
78864 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L |
78865 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L |
78866 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L |
78867 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L |
78868 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L |
78869 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L |
78870 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L |
78871 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L |
78872 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L |
78873 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L |
78874 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L |
78875 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L |
78876 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L |
78877 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L |
78878 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L |
78879 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L |
78880 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L |
78881 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L |
78882 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L |
78883 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L |
78884 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L |
78885 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L |
78886 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L |
78887 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L |
78888 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L |
78889 | #define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L |
78890 | //PARITY_ERROR_STATUS_CORR_GRP2 |
78891 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 |
78892 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 |
78893 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 |
78894 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 |
78895 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 |
78896 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 |
78897 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 |
78898 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 |
78899 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 |
78900 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 |
78901 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa |
78902 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb |
78903 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc |
78904 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd |
78905 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe |
78906 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf |
78907 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 |
78908 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 |
78909 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 |
78910 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 |
78911 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 |
78912 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 |
78913 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 |
78914 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 |
78915 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 |
78916 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 |
78917 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a |
78918 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b |
78919 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c |
78920 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d |
78921 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e |
78922 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f |
78923 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L |
78924 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L |
78925 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L |
78926 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L |
78927 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L |
78928 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L |
78929 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L |
78930 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L |
78931 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L |
78932 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L |
78933 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L |
78934 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L |
78935 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L |
78936 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L |
78937 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L |
78938 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L |
78939 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L |
78940 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L |
78941 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L |
78942 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L |
78943 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L |
78944 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L |
78945 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L |
78946 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L |
78947 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L |
78948 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L |
78949 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L |
78950 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L |
78951 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L |
78952 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L |
78953 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L |
78954 | #define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L |
78955 | //PARITY_ERROR_STATUS_CORR_GRP3 |
78956 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 |
78957 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 |
78958 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 |
78959 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 |
78960 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 |
78961 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 |
78962 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 |
78963 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 |
78964 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 |
78965 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 |
78966 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa |
78967 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb |
78968 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc |
78969 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd |
78970 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe |
78971 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf |
78972 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 |
78973 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 |
78974 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 |
78975 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 |
78976 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 |
78977 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 |
78978 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 |
78979 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 |
78980 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 |
78981 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 |
78982 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a |
78983 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b |
78984 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c |
78985 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d |
78986 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e |
78987 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f |
78988 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L |
78989 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L |
78990 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L |
78991 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L |
78992 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L |
78993 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L |
78994 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L |
78995 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L |
78996 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L |
78997 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L |
78998 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L |
78999 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L |
79000 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L |
79001 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L |
79002 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L |
79003 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L |
79004 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L |
79005 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L |
79006 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L |
79007 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L |
79008 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L |
79009 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L |
79010 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L |
79011 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L |
79012 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L |
79013 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L |
79014 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L |
79015 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L |
79016 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L |
79017 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L |
79018 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L |
79019 | #define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L |
79020 | //PARITY_ERROR_STATUS_CORR_GRP4 |
79021 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 |
79022 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 |
79023 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 |
79024 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 |
79025 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 |
79026 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 |
79027 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 |
79028 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 |
79029 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 |
79030 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 |
79031 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa |
79032 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb |
79033 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc |
79034 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd |
79035 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe |
79036 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf |
79037 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 |
79038 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 |
79039 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 |
79040 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 |
79041 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 |
79042 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 |
79043 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 |
79044 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 |
79045 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 |
79046 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 |
79047 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a |
79048 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b |
79049 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c |
79050 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d |
79051 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e |
79052 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f |
79053 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L |
79054 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L |
79055 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L |
79056 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L |
79057 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L |
79058 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L |
79059 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L |
79060 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L |
79061 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L |
79062 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L |
79063 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L |
79064 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L |
79065 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L |
79066 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L |
79067 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L |
79068 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L |
79069 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L |
79070 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L |
79071 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L |
79072 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L |
79073 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L |
79074 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L |
79075 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L |
79076 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L |
79077 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L |
79078 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L |
79079 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L |
79080 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L |
79081 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L |
79082 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L |
79083 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L |
79084 | #define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L |
79085 | //PARITY_COUNTER_CORR_GRP0 |
79086 | #define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0 |
79087 | #define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f |
79088 | #define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL |
79089 | #define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L |
79090 | //PARITY_COUNTER_CORR_GRP1 |
79091 | #define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0 |
79092 | #define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f |
79093 | #define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL |
79094 | #define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L |
79095 | //PARITY_COUNTER_CORR_GRP2 |
79096 | #define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0 |
79097 | #define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f |
79098 | #define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL |
79099 | #define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L |
79100 | //PARITY_COUNTER_CORR_GRP3 |
79101 | #define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0 |
79102 | #define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f |
79103 | #define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL |
79104 | #define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L |
79105 | //PARITY_COUNTER_CORR_GRP4 |
79106 | #define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0 |
79107 | #define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f |
79108 | #define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL |
79109 | #define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L |
79110 | //PARITY_ERROR_STATUS_UCP_GRP0 |
79111 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0 |
79112 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1 |
79113 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2 |
79114 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3 |
79115 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4 |
79116 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5 |
79117 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6 |
79118 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7 |
79119 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8 |
79120 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9 |
79121 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa |
79122 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb |
79123 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc |
79124 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd |
79125 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe |
79126 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf |
79127 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10 |
79128 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11 |
79129 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12 |
79130 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13 |
79131 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14 |
79132 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15 |
79133 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16 |
79134 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17 |
79135 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18 |
79136 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19 |
79137 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a |
79138 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b |
79139 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c |
79140 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d |
79141 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e |
79142 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f |
79143 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L |
79144 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L |
79145 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L |
79146 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L |
79147 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L |
79148 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L |
79149 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L |
79150 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L |
79151 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L |
79152 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L |
79153 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L |
79154 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L |
79155 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L |
79156 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L |
79157 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L |
79158 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L |
79159 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L |
79160 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L |
79161 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L |
79162 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L |
79163 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L |
79164 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L |
79165 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L |
79166 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L |
79167 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L |
79168 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L |
79169 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L |
79170 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L |
79171 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L |
79172 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L |
79173 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L |
79174 | #define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L |
79175 | //PARITY_ERROR_STATUS_UCP_GRP1 |
79176 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0 |
79177 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1 |
79178 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2 |
79179 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3 |
79180 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4 |
79181 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5 |
79182 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6 |
79183 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7 |
79184 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8 |
79185 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9 |
79186 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa |
79187 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb |
79188 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc |
79189 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd |
79190 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe |
79191 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf |
79192 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10 |
79193 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11 |
79194 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12 |
79195 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13 |
79196 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14 |
79197 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15 |
79198 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16 |
79199 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17 |
79200 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18 |
79201 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19 |
79202 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a |
79203 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b |
79204 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c |
79205 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d |
79206 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e |
79207 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f |
79208 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L |
79209 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L |
79210 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L |
79211 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L |
79212 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L |
79213 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L |
79214 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L |
79215 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L |
79216 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L |
79217 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L |
79218 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L |
79219 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L |
79220 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L |
79221 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L |
79222 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L |
79223 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L |
79224 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L |
79225 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L |
79226 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L |
79227 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L |
79228 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L |
79229 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L |
79230 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L |
79231 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L |
79232 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L |
79233 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L |
79234 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L |
79235 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L |
79236 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L |
79237 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L |
79238 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L |
79239 | #define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L |
79240 | //PARITY_ERROR_STATUS_UCP_GRP2 |
79241 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0 |
79242 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1 |
79243 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2 |
79244 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3 |
79245 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4 |
79246 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5 |
79247 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6 |
79248 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7 |
79249 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8 |
79250 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9 |
79251 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa |
79252 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb |
79253 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc |
79254 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd |
79255 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe |
79256 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf |
79257 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10 |
79258 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11 |
79259 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12 |
79260 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13 |
79261 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14 |
79262 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15 |
79263 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16 |
79264 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17 |
79265 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18 |
79266 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19 |
79267 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a |
79268 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b |
79269 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c |
79270 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d |
79271 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e |
79272 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f |
79273 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L |
79274 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L |
79275 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L |
79276 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L |
79277 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L |
79278 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L |
79279 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L |
79280 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L |
79281 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L |
79282 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L |
79283 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L |
79284 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L |
79285 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L |
79286 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L |
79287 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L |
79288 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L |
79289 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L |
79290 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L |
79291 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L |
79292 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L |
79293 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L |
79294 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L |
79295 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L |
79296 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L |
79297 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L |
79298 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L |
79299 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L |
79300 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L |
79301 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L |
79302 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L |
79303 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L |
79304 | #define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L |
79305 | //PARITY_ERROR_STATUS_UCP_GRP3 |
79306 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0 |
79307 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1 |
79308 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2 |
79309 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3 |
79310 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4 |
79311 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5 |
79312 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6 |
79313 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7 |
79314 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8 |
79315 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9 |
79316 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa |
79317 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb |
79318 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc |
79319 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd |
79320 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe |
79321 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf |
79322 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10 |
79323 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11 |
79324 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12 |
79325 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13 |
79326 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14 |
79327 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15 |
79328 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16 |
79329 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17 |
79330 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18 |
79331 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19 |
79332 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a |
79333 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b |
79334 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c |
79335 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d |
79336 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e |
79337 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f |
79338 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L |
79339 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L |
79340 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L |
79341 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L |
79342 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L |
79343 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L |
79344 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L |
79345 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L |
79346 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L |
79347 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L |
79348 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L |
79349 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L |
79350 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L |
79351 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L |
79352 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L |
79353 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L |
79354 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L |
79355 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L |
79356 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L |
79357 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L |
79358 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L |
79359 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L |
79360 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L |
79361 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L |
79362 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L |
79363 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L |
79364 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L |
79365 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L |
79366 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L |
79367 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L |
79368 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L |
79369 | #define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L |
79370 | //PARITY_ERROR_STATUS_UCP_GRP4 |
79371 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0 |
79372 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1 |
79373 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2 |
79374 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3 |
79375 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4 |
79376 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5 |
79377 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6 |
79378 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7 |
79379 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8 |
79380 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9 |
79381 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa |
79382 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb |
79383 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc |
79384 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd |
79385 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe |
79386 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf |
79387 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10 |
79388 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11 |
79389 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12 |
79390 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13 |
79391 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14 |
79392 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15 |
79393 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16 |
79394 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17 |
79395 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18 |
79396 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19 |
79397 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a |
79398 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b |
79399 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c |
79400 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d |
79401 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e |
79402 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f |
79403 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L |
79404 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L |
79405 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L |
79406 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L |
79407 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L |
79408 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L |
79409 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L |
79410 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L |
79411 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L |
79412 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L |
79413 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L |
79414 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L |
79415 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L |
79416 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L |
79417 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L |
79418 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L |
79419 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L |
79420 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L |
79421 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L |
79422 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L |
79423 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L |
79424 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L |
79425 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L |
79426 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L |
79427 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L |
79428 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L |
79429 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L |
79430 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L |
79431 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L |
79432 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L |
79433 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L |
79434 | #define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L |
79435 | //PARITY_COUNTER_UCP_GRP0 |
79436 | #define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0 |
79437 | #define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f |
79438 | #define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL |
79439 | #define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L |
79440 | //PARITY_COUNTER_UCP_GRP1 |
79441 | #define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0 |
79442 | #define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f |
79443 | #define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL |
79444 | #define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L |
79445 | //PARITY_COUNTER_UCP_GRP2 |
79446 | #define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0 |
79447 | #define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f |
79448 | #define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL |
79449 | #define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L |
79450 | //PARITY_COUNTER_UCP_GRP3 |
79451 | #define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0 |
79452 | #define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f |
79453 | #define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL |
79454 | #define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L |
79455 | //PARITY_COUNTER_UCP_GRP4 |
79456 | #define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0 |
79457 | #define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f |
79458 | #define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL |
79459 | #define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L |
79460 | //MISC_SEVERITY_CONTROL |
79461 | #define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4 |
79462 | #define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6 |
79463 | #define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L |
79464 | #define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L |
79465 | //MISC_RAS_CONTROL |
79466 | #define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2 |
79467 | #define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT 0x3 |
79468 | #define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9 |
79469 | #define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa |
79470 | #define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb |
79471 | #define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc |
79472 | #define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd |
79473 | #define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe |
79474 | #define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf |
79475 | #define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10 |
79476 | #define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11 |
79477 | #define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L |
79478 | #define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK 0x00000008L |
79479 | #define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L |
79480 | #define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L |
79481 | #define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L |
79482 | #define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L |
79483 | #define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L |
79484 | #define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L |
79485 | #define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L |
79486 | #define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L |
79487 | #define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L |
79488 | //RAS_SCRATCH_0 |
79489 | #define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
79490 | #define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
79491 | //RAS_SCRATCH_1 |
79492 | #define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
79493 | #define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
79494 | //ErrEvent_ACTION_CONTROL |
79495 | #define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79496 | #define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79497 | #define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79498 | #define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79499 | #define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79500 | #define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79501 | #define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79502 | #define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79503 | //ParitySerr_ACTION_CONTROL |
79504 | #define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79505 | #define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79506 | #define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79507 | #define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79508 | #define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79509 | #define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79510 | #define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79511 | #define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79512 | //ParityFatal_ACTION_CONTROL |
79513 | #define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79514 | #define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79515 | #define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79516 | #define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79517 | #define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79518 | #define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79519 | #define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79520 | #define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79521 | //ParityNonFatal_ACTION_CONTROL |
79522 | #define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79523 | #define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79524 | #define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79525 | #define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79526 | #define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79527 | #define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79528 | #define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79529 | #define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79530 | //ParityCorr_ACTION_CONTROL |
79531 | #define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79532 | #define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79533 | #define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79534 | #define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79535 | #define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79536 | #define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79537 | #define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79538 | #define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79539 | //PCIE0PortASerr_ACTION_CONTROL |
79540 | #define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79541 | #define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79542 | #define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79543 | #define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79544 | #define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79545 | #define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79546 | #define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79547 | #define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79548 | //PCIE0PortAIntFatal_ACTION_CONTROL |
79549 | #define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79550 | #define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79551 | #define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79552 | #define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79553 | #define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79554 | #define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79555 | #define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79556 | #define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79557 | //PCIE0PortAIntNonFatal_ACTION_CONTROL |
79558 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79559 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79560 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79561 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79562 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79563 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79564 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79565 | #define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79566 | //PCIE0PortAIntCorr_ACTION_CONTROL |
79567 | #define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79568 | #define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79569 | #define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79570 | #define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79571 | #define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79572 | #define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79573 | #define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79574 | #define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79575 | //PCIE0PortAExtFatal_ACTION_CONTROL |
79576 | #define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79577 | #define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79578 | #define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79579 | #define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79580 | #define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79581 | #define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79582 | #define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79583 | #define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79584 | //PCIE0PortAExtNonFatal_ACTION_CONTROL |
79585 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79586 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79587 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79588 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79589 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79590 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79591 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79592 | #define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79593 | //PCIE0PortAExtCorr_ACTION_CONTROL |
79594 | #define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79595 | #define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79596 | #define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79597 | #define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79598 | #define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79599 | #define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79600 | #define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79601 | #define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79602 | //PCIE0PortAParityErr_ACTION_CONTROL |
79603 | #define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79604 | #define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79605 | #define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79606 | #define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79607 | #define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79608 | #define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79609 | #define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79610 | #define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79611 | //PCIE0PortBSerr_ACTION_CONTROL |
79612 | #define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79613 | #define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79614 | #define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79615 | #define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79616 | #define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79617 | #define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79618 | #define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79619 | #define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79620 | //PCIE0PortBIntFatal_ACTION_CONTROL |
79621 | #define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79622 | #define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79623 | #define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79624 | #define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79625 | #define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79626 | #define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79627 | #define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79628 | #define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79629 | //PCIE0PortBIntNonFatal_ACTION_CONTROL |
79630 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79631 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79632 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79633 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79634 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79635 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79636 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79637 | #define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79638 | //PCIE0PortBIntCorr_ACTION_CONTROL |
79639 | #define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79640 | #define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79641 | #define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79642 | #define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79643 | #define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79644 | #define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79645 | #define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79646 | #define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79647 | //PCIE0PortBExtFatal_ACTION_CONTROL |
79648 | #define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79649 | #define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79650 | #define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79651 | #define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79652 | #define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79653 | #define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79654 | #define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79655 | #define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79656 | //PCIE0PortBExtNonFatal_ACTION_CONTROL |
79657 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79658 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79659 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79660 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79661 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79662 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79663 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79664 | #define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79665 | //PCIE0PortBExtCorr_ACTION_CONTROL |
79666 | #define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79667 | #define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79668 | #define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79669 | #define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79670 | #define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79671 | #define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79672 | #define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79673 | #define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79674 | //PCIE0PortBParityErr_ACTION_CONTROL |
79675 | #define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79676 | #define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79677 | #define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79678 | #define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79679 | #define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79680 | #define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79681 | #define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79682 | #define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79683 | //PCIE0PortCSerr_ACTION_CONTROL |
79684 | #define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79685 | #define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79686 | #define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79687 | #define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79688 | #define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79689 | #define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79690 | #define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79691 | #define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79692 | //PCIE0PortCIntFatal_ACTION_CONTROL |
79693 | #define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79694 | #define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79695 | #define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79696 | #define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79697 | #define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79698 | #define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79699 | #define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79700 | #define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79701 | //PCIE0PortCIntNonFatal_ACTION_CONTROL |
79702 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79703 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79704 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79705 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79706 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79707 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79708 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79709 | #define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79710 | //PCIE0PortCIntCorr_ACTION_CONTROL |
79711 | #define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79712 | #define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79713 | #define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79714 | #define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79715 | #define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79716 | #define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79717 | #define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79718 | #define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79719 | //PCIE0PortCExtFatal_ACTION_CONTROL |
79720 | #define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79721 | #define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79722 | #define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79723 | #define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79724 | #define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79725 | #define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79726 | #define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79727 | #define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79728 | //PCIE0PortCExtNonFatal_ACTION_CONTROL |
79729 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79730 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79731 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79732 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79733 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79734 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79735 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79736 | #define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79737 | //PCIE0PortCExtCorr_ACTION_CONTROL |
79738 | #define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79739 | #define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79740 | #define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79741 | #define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79742 | #define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79743 | #define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79744 | #define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79745 | #define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79746 | //PCIE0PortCParityErr_ACTION_CONTROL |
79747 | #define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79748 | #define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79749 | #define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79750 | #define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79751 | #define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79752 | #define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79753 | #define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79754 | #define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79755 | //PCIE0PortDSerr_ACTION_CONTROL |
79756 | #define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79757 | #define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79758 | #define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79759 | #define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79760 | #define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79761 | #define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79762 | #define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79763 | #define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79764 | //PCIE0PortDIntFatal_ACTION_CONTROL |
79765 | #define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79766 | #define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79767 | #define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79768 | #define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79769 | #define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79770 | #define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79771 | #define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79772 | #define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79773 | //PCIE0PortDIntNonFatal_ACTION_CONTROL |
79774 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79775 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79776 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79777 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79778 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79779 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79780 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79781 | #define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79782 | //PCIE0PortDIntCorr_ACTION_CONTROL |
79783 | #define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79784 | #define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79785 | #define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79786 | #define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79787 | #define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79788 | #define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79789 | #define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79790 | #define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79791 | //PCIE0PortDExtFatal_ACTION_CONTROL |
79792 | #define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79793 | #define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79794 | #define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79795 | #define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79796 | #define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79797 | #define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79798 | #define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79799 | #define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79800 | //PCIE0PortDExtNonFatal_ACTION_CONTROL |
79801 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79802 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79803 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79804 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79805 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79806 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79807 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79808 | #define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79809 | //PCIE0PortDExtCorr_ACTION_CONTROL |
79810 | #define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79811 | #define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79812 | #define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79813 | #define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79814 | #define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79815 | #define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79816 | #define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79817 | #define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79818 | //PCIE0PortDParityErr_ACTION_CONTROL |
79819 | #define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79820 | #define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79821 | #define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79822 | #define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79823 | #define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79824 | #define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79825 | #define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79826 | #define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79827 | //PCIE0PortESerr_ACTION_CONTROL |
79828 | #define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79829 | #define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79830 | #define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79831 | #define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79832 | #define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79833 | #define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79834 | #define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79835 | #define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79836 | //PCIE0PortEIntFatal_ACTION_CONTROL |
79837 | #define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79838 | #define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79839 | #define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79840 | #define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79841 | #define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79842 | #define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79843 | #define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79844 | #define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79845 | //PCIE0PortEIntNonFatal_ACTION_CONTROL |
79846 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79847 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79848 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79849 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79850 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79851 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79852 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79853 | #define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79854 | //PCIE0PortEIntCorr_ACTION_CONTROL |
79855 | #define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79856 | #define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79857 | #define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79858 | #define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79859 | #define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79860 | #define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79861 | #define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79862 | #define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79863 | //PCIE0PortEExtFatal_ACTION_CONTROL |
79864 | #define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79865 | #define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79866 | #define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79867 | #define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79868 | #define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79869 | #define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79870 | #define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79871 | #define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79872 | //PCIE0PortEExtNonFatal_ACTION_CONTROL |
79873 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79874 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79875 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79876 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79877 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79878 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79879 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79880 | #define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79881 | //PCIE0PortEExtCorr_ACTION_CONTROL |
79882 | #define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79883 | #define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79884 | #define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79885 | #define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79886 | #define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79887 | #define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79888 | #define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79889 | #define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79890 | //PCIE0PortEParityErr_ACTION_CONTROL |
79891 | #define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79892 | #define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79893 | #define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79894 | #define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79895 | #define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79896 | #define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79897 | #define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79898 | #define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79899 | //PCIE0PortFSerr_ACTION_CONTROL |
79900 | #define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79901 | #define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79902 | #define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79903 | #define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79904 | #define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79905 | #define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79906 | #define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79907 | #define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79908 | //PCIE0PortFIntFatal_ACTION_CONTROL |
79909 | #define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79910 | #define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79911 | #define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79912 | #define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79913 | #define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79914 | #define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79915 | #define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79916 | #define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79917 | //PCIE0PortFIntNonFatal_ACTION_CONTROL |
79918 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79919 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79920 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79921 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79922 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79923 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79924 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79925 | #define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79926 | //PCIE0PortFIntCorr_ACTION_CONTROL |
79927 | #define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79928 | #define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79929 | #define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79930 | #define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79931 | #define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79932 | #define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79933 | #define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79934 | #define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79935 | //PCIE0PortFExtFatal_ACTION_CONTROL |
79936 | #define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79937 | #define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79938 | #define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79939 | #define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79940 | #define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79941 | #define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79942 | #define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79943 | #define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79944 | //PCIE0PortFExtNonFatal_ACTION_CONTROL |
79945 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79946 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79947 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79948 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79949 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79950 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79951 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79952 | #define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79953 | //PCIE0PortFExtCorr_ACTION_CONTROL |
79954 | #define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79955 | #define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79956 | #define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79957 | #define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79958 | #define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79959 | #define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79960 | #define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79961 | #define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79962 | //PCIE0PortFParityErr_ACTION_CONTROL |
79963 | #define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79964 | #define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79965 | #define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79966 | #define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79967 | #define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79968 | #define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79969 | #define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79970 | #define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79971 | //PCIE0PortGSerr_ACTION_CONTROL |
79972 | #define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79973 | #define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79974 | #define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79975 | #define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79976 | #define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79977 | #define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79978 | #define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79979 | #define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79980 | //PCIE0PortGIntFatal_ACTION_CONTROL |
79981 | #define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79982 | #define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79983 | #define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79984 | #define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79985 | #define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79986 | #define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79987 | #define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79988 | #define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79989 | //PCIE0PortGIntNonFatal_ACTION_CONTROL |
79990 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
79991 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
79992 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
79993 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
79994 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
79995 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
79996 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
79997 | #define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
79998 | //PCIE0PortGIntCorr_ACTION_CONTROL |
79999 | #define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80000 | #define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80001 | #define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80002 | #define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80003 | #define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80004 | #define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80005 | #define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80006 | #define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80007 | //PCIE0PortGExtFatal_ACTION_CONTROL |
80008 | #define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80009 | #define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80010 | #define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80011 | #define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80012 | #define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80013 | #define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80014 | #define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80015 | #define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80016 | //PCIE0PortGExtNonFatal_ACTION_CONTROL |
80017 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80018 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80019 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80020 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80021 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80022 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80023 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80024 | #define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80025 | //PCIE0PortGExtCorr_ACTION_CONTROL |
80026 | #define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80027 | #define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80028 | #define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80029 | #define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80030 | #define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80031 | #define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80032 | #define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80033 | #define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80034 | //PCIE0PortGParityErr_ACTION_CONTROL |
80035 | #define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80036 | #define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80037 | #define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80038 | #define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80039 | #define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80040 | #define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80041 | #define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80042 | #define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80043 | //NBIF1PortASerr_ACTION_CONTROL |
80044 | #define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80045 | #define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80046 | #define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80047 | #define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80048 | #define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80049 | #define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80050 | #define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80051 | #define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80052 | //NBIF1PortAIntFatal_ACTION_CONTROL |
80053 | #define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80054 | #define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80055 | #define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80056 | #define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80057 | #define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80058 | #define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80059 | #define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80060 | #define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80061 | //NBIF1PortAIntNonFatal_ACTION_CONTROL |
80062 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80063 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80064 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80065 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80066 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80067 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80068 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80069 | #define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80070 | //NBIF1PortAIntCorr_ACTION_CONTROL |
80071 | #define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80072 | #define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80073 | #define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80074 | #define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80075 | #define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80076 | #define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80077 | #define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80078 | #define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80079 | //NBIF1PortAExtFatal_ACTION_CONTROL |
80080 | #define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80081 | #define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80082 | #define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80083 | #define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80084 | #define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80085 | #define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80086 | #define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80087 | #define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80088 | //NBIF1PortAExtNonFatal_ACTION_CONTROL |
80089 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80090 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80091 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80092 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80093 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80094 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80095 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80096 | #define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80097 | //NBIF1PortAExtCorr_ACTION_CONTROL |
80098 | #define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80099 | #define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80100 | #define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80101 | #define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80102 | #define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80103 | #define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80104 | #define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80105 | #define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80106 | //NBIF1PortAParityErr_ACTION_CONTROL |
80107 | #define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80108 | #define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80109 | #define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80110 | #define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80111 | #define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80112 | #define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80113 | #define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80114 | #define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80115 | //NBIF1PortBSerr_ACTION_CONTROL |
80116 | #define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80117 | #define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80118 | #define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80119 | #define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80120 | #define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80121 | #define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80122 | #define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80123 | #define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80124 | //NBIF1PortBIntFatal_ACTION_CONTROL |
80125 | #define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80126 | #define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80127 | #define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80128 | #define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80129 | #define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80130 | #define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80131 | #define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80132 | #define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80133 | //NBIF1PortBIntNonFatal_ACTION_CONTROL |
80134 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80135 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80136 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80137 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80138 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80139 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80140 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80141 | #define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80142 | //NBIF1PortBIntCorr_ACTION_CONTROL |
80143 | #define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80144 | #define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80145 | #define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80146 | #define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80147 | #define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80148 | #define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80149 | #define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80150 | #define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80151 | //NBIF1PortBExtFatal_ACTION_CONTROL |
80152 | #define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80153 | #define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80154 | #define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80155 | #define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80156 | #define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80157 | #define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80158 | #define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80159 | #define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80160 | //NBIF1PortBExtNonFatal_ACTION_CONTROL |
80161 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80162 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80163 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80164 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80165 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80166 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80167 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80168 | #define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80169 | //NBIF1PortBExtCorr_ACTION_CONTROL |
80170 | #define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80171 | #define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80172 | #define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80173 | #define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80174 | #define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80175 | #define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80176 | #define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80177 | #define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80178 | //NBIF1PortBParityErr_ACTION_CONTROL |
80179 | #define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
80180 | #define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 |
80181 | #define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 |
80182 | #define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 |
80183 | #define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
80184 | #define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L |
80185 | #define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L |
80186 | #define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L |
80187 | //SYNCFLOOD_STATUS |
80188 | #define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0 |
80189 | #define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1 |
80190 | #define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2 |
80191 | #define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4 |
80192 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT 0x8 |
80193 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT 0x9 |
80194 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT 0xa |
80195 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT 0xb |
80196 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT 0xc |
80197 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT 0xd |
80198 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT 0xe |
80199 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT 0xf |
80200 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT 0x10 |
80201 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT 0x11 |
80202 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT 0x12 |
80203 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT 0x13 |
80204 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT 0x14 |
80205 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT 0x15 |
80206 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT 0x16 |
80207 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT 0x17 |
80208 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT 0x18 |
80209 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT 0x19 |
80210 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT 0x1a |
80211 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT 0x1b |
80212 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT 0x1c |
80213 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT 0x1d |
80214 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT 0x1e |
80215 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT 0x1f |
80216 | #define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L |
80217 | #define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L |
80218 | #define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L |
80219 | #define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L |
80220 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK 0x00000100L |
80221 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK 0x00000200L |
80222 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK 0x00000400L |
80223 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK 0x00000800L |
80224 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK 0x00001000L |
80225 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK 0x00002000L |
80226 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK 0x00004000L |
80227 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK 0x00008000L |
80228 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK 0x00010000L |
80229 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK 0x00020000L |
80230 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK 0x00040000L |
80231 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK 0x00080000L |
80232 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK 0x00100000L |
80233 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK 0x00200000L |
80234 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK 0x00400000L |
80235 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK 0x00800000L |
80236 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK 0x01000000L |
80237 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK 0x02000000L |
80238 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK 0x04000000L |
80239 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK 0x08000000L |
80240 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK 0x10000000L |
80241 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK 0x20000000L |
80242 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK 0x40000000L |
80243 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK 0x80000000L |
80244 | //NMI_STATUS |
80245 | #define NMI_STATUS__NMIFromPin__SHIFT 0x0 |
80246 | #define NMI_STATUS__NMIFromPin_MASK 0x00000001L |
80247 | //POISON_ACTION_CONTROL |
80248 | #define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT 0x0 |
80249 | #define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT 0x1 |
80250 | #define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT 0x3 |
80251 | #define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT 0x4 |
80252 | #define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT 0x8 |
80253 | #define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT 0x9 |
80254 | #define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT 0xb |
80255 | #define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT 0xc |
80256 | #define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT 0x10 |
80257 | #define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT 0x11 |
80258 | #define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT 0x13 |
80259 | #define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT 0x14 |
80260 | #define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK 0x00000001L |
80261 | #define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK 0x00000006L |
80262 | #define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK 0x00000008L |
80263 | #define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK 0x00000010L |
80264 | #define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK 0x00000100L |
80265 | #define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK 0x00000600L |
80266 | #define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK 0x00000800L |
80267 | #define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK 0x00001000L |
80268 | #define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK 0x00010000L |
80269 | #define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK 0x00060000L |
80270 | #define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK 0x00080000L |
80271 | #define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK 0x00100000L |
80272 | //INTERNAL_POISON_STATUS |
80273 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT 0x0 |
80274 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT 0x1 |
80275 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT 0x2 |
80276 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT 0x3 |
80277 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT 0x4 |
80278 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT 0x5 |
80279 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT 0x6 |
80280 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT 0x7 |
80281 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK 0x00000001L |
80282 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK 0x00000002L |
80283 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK 0x00000004L |
80284 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK 0x00000008L |
80285 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK 0x00000010L |
80286 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK 0x00000020L |
80287 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK 0x00000040L |
80288 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK 0x00000080L |
80289 | //INTERNAL_POISON_MASK |
80290 | #define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT 0x0 |
80291 | #define INTERNAL_POISON_MASK__IntPoisonMask_MASK 0x000000FFL |
80292 | //EGRESS_POISON_STATUS_LO |
80293 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0 |
80294 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1 |
80295 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2 |
80296 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3 |
80297 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4 |
80298 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5 |
80299 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6 |
80300 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7 |
80301 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8 |
80302 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9 |
80303 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa |
80304 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb |
80305 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc |
80306 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd |
80307 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe |
80308 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf |
80309 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10 |
80310 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11 |
80311 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12 |
80312 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13 |
80313 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14 |
80314 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15 |
80315 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16 |
80316 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17 |
80317 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18 |
80318 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19 |
80319 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a |
80320 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b |
80321 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c |
80322 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d |
80323 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e |
80324 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f |
80325 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L |
80326 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L |
80327 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L |
80328 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L |
80329 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L |
80330 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L |
80331 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L |
80332 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L |
80333 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L |
80334 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L |
80335 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L |
80336 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L |
80337 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L |
80338 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L |
80339 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L |
80340 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L |
80341 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L |
80342 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L |
80343 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L |
80344 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L |
80345 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L |
80346 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L |
80347 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L |
80348 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L |
80349 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L |
80350 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L |
80351 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L |
80352 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L |
80353 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L |
80354 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L |
80355 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L |
80356 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L |
80357 | //EGRESS_POISON_STATUS_HI |
80358 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0 |
80359 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1 |
80360 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2 |
80361 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3 |
80362 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4 |
80363 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5 |
80364 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6 |
80365 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7 |
80366 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8 |
80367 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9 |
80368 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa |
80369 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb |
80370 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc |
80371 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd |
80372 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe |
80373 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf |
80374 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10 |
80375 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11 |
80376 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12 |
80377 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13 |
80378 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14 |
80379 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15 |
80380 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16 |
80381 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17 |
80382 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18 |
80383 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19 |
80384 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a |
80385 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b |
80386 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c |
80387 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d |
80388 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e |
80389 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f |
80390 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L |
80391 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L |
80392 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L |
80393 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L |
80394 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L |
80395 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L |
80396 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L |
80397 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L |
80398 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L |
80399 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L |
80400 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L |
80401 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L |
80402 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L |
80403 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L |
80404 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L |
80405 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L |
80406 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L |
80407 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L |
80408 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L |
80409 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L |
80410 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L |
80411 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L |
80412 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L |
80413 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L |
80414 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L |
80415 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L |
80416 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L |
80417 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L |
80418 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L |
80419 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L |
80420 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L |
80421 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L |
80422 | //EGRESS_POISON_MASK_LO |
80423 | #define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0 |
80424 | #define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL |
80425 | //EGRESS_POISON_MASK_HI |
80426 | #define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0 |
80427 | #define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL |
80428 | //EGRESS_POISON_SEVERITY_DOWN |
80429 | #define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0 |
80430 | #define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL |
80431 | //EGRESS_POISON_SEVERITY_UPPER |
80432 | #define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0 |
80433 | #define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL |
80434 | //APML_STATUS |
80435 | #define APML_STATUS__APML_Corr__SHIFT 0x0 |
80436 | #define APML_STATUS__APML_NonFatal__SHIFT 0x1 |
80437 | #define APML_STATUS__APML_Fatal__SHIFT 0x2 |
80438 | #define APML_STATUS__APML_Serr__SHIFT 0x3 |
80439 | #define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4 |
80440 | #define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5 |
80441 | #define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6 |
80442 | #define APML_STATUS__APML_Corr_MASK 0x00000001L |
80443 | #define APML_STATUS__APML_NonFatal_MASK 0x00000002L |
80444 | #define APML_STATUS__APML_Fatal_MASK 0x00000004L |
80445 | #define APML_STATUS__APML_Serr_MASK 0x00000008L |
80446 | #define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L |
80447 | #define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L |
80448 | #define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L |
80449 | //APML_CONTROL |
80450 | #define APML_CONTROL__APML_NMI_En__SHIFT 0x0 |
80451 | #define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1 |
80452 | #define APML_CONTROL__APML_OutputDis__SHIFT 0x8 |
80453 | #define APML_CONTROL__APML_NMI_En_MASK 0x00000001L |
80454 | #define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L |
80455 | #define APML_CONTROL__APML_OutputDis_MASK 0x00000100L |
80456 | //APML_TRIGGER |
80457 | #define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0 |
80458 | #define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L |
80459 | |
80460 | |
80461 | // addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec |
80462 | //PSP_SYNCFLOOD_STATUS |
80463 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl__SHIFT 0x0 |
80464 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML__SHIFT 0x1 |
80465 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin__SHIFT 0x2 |
80466 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate__SHIFT 0x4 |
80467 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8__SHIFT 0x8 |
80468 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9__SHIFT 0x9 |
80469 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10__SHIFT 0xa |
80470 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11__SHIFT 0xb |
80471 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12__SHIFT 0xc |
80472 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13__SHIFT 0xd |
80473 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14__SHIFT 0xe |
80474 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15__SHIFT 0xf |
80475 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16__SHIFT 0x10 |
80476 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17__SHIFT 0x11 |
80477 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18__SHIFT 0x12 |
80478 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19__SHIFT 0x13 |
80479 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20__SHIFT 0x14 |
80480 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21__SHIFT 0x15 |
80481 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22__SHIFT 0x16 |
80482 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23__SHIFT 0x17 |
80483 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24__SHIFT 0x18 |
80484 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25__SHIFT 0x19 |
80485 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26__SHIFT 0x1a |
80486 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27__SHIFT 0x1b |
80487 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28__SHIFT 0x1c |
80488 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29__SHIFT 0x1d |
80489 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30__SHIFT 0x1e |
80490 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31__SHIFT 0x1f |
80491 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl_MASK 0x00000001L |
80492 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML_MASK 0x00000002L |
80493 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin_MASK 0x00000004L |
80494 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate_MASK 0x00000010L |
80495 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8_MASK 0x00000100L |
80496 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9_MASK 0x00000200L |
80497 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10_MASK 0x00000400L |
80498 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11_MASK 0x00000800L |
80499 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12_MASK 0x00001000L |
80500 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13_MASK 0x00002000L |
80501 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14_MASK 0x00004000L |
80502 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15_MASK 0x00008000L |
80503 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16_MASK 0x00010000L |
80504 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17_MASK 0x00020000L |
80505 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18_MASK 0x00040000L |
80506 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19_MASK 0x00080000L |
80507 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20_MASK 0x00100000L |
80508 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21_MASK 0x00200000L |
80509 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22_MASK 0x00400000L |
80510 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23_MASK 0x00800000L |
80511 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24_MASK 0x01000000L |
80512 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25_MASK 0x02000000L |
80513 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26_MASK 0x04000000L |
80514 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27_MASK 0x08000000L |
80515 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28_MASK 0x10000000L |
80516 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29_MASK 0x20000000L |
80517 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30_MASK 0x40000000L |
80518 | #define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31_MASK 0x80000000L |
80519 | //PSP_INTERNAL_POISON_STATUS |
80520 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0__SHIFT 0x0 |
80521 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1__SHIFT 0x1 |
80522 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2__SHIFT 0x2 |
80523 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3__SHIFT 0x3 |
80524 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4__SHIFT 0x4 |
80525 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5__SHIFT 0x5 |
80526 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6__SHIFT 0x6 |
80527 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7__SHIFT 0x7 |
80528 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0_MASK 0x00000001L |
80529 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1_MASK 0x00000002L |
80530 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2_MASK 0x00000004L |
80531 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3_MASK 0x00000008L |
80532 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4_MASK 0x00000010L |
80533 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5_MASK 0x00000020L |
80534 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6_MASK 0x00000040L |
80535 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7_MASK 0x00000080L |
80536 | //PSP_EGRESS_POISON_STATUS_LO |
80537 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0__SHIFT 0x0 |
80538 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1__SHIFT 0x1 |
80539 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2__SHIFT 0x2 |
80540 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3__SHIFT 0x3 |
80541 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4__SHIFT 0x4 |
80542 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5__SHIFT 0x5 |
80543 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6__SHIFT 0x6 |
80544 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7__SHIFT 0x7 |
80545 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8__SHIFT 0x8 |
80546 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9__SHIFT 0x9 |
80547 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10__SHIFT 0xa |
80548 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11__SHIFT 0xb |
80549 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12__SHIFT 0xc |
80550 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13__SHIFT 0xd |
80551 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14__SHIFT 0xe |
80552 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15__SHIFT 0xf |
80553 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16__SHIFT 0x10 |
80554 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17__SHIFT 0x11 |
80555 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18__SHIFT 0x12 |
80556 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19__SHIFT 0x13 |
80557 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20__SHIFT 0x14 |
80558 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21__SHIFT 0x15 |
80559 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22__SHIFT 0x16 |
80560 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23__SHIFT 0x17 |
80561 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24__SHIFT 0x18 |
80562 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25__SHIFT 0x19 |
80563 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26__SHIFT 0x1a |
80564 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27__SHIFT 0x1b |
80565 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28__SHIFT 0x1c |
80566 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29__SHIFT 0x1d |
80567 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30__SHIFT 0x1e |
80568 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31__SHIFT 0x1f |
80569 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0_MASK 0x00000001L |
80570 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1_MASK 0x00000002L |
80571 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2_MASK 0x00000004L |
80572 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3_MASK 0x00000008L |
80573 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4_MASK 0x00000010L |
80574 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5_MASK 0x00000020L |
80575 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6_MASK 0x00000040L |
80576 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7_MASK 0x00000080L |
80577 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8_MASK 0x00000100L |
80578 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9_MASK 0x00000200L |
80579 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10_MASK 0x00000400L |
80580 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11_MASK 0x00000800L |
80581 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12_MASK 0x00001000L |
80582 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13_MASK 0x00002000L |
80583 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14_MASK 0x00004000L |
80584 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15_MASK 0x00008000L |
80585 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16_MASK 0x00010000L |
80586 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17_MASK 0x00020000L |
80587 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18_MASK 0x00040000L |
80588 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19_MASK 0x00080000L |
80589 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20_MASK 0x00100000L |
80590 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21_MASK 0x00200000L |
80591 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22_MASK 0x00400000L |
80592 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23_MASK 0x00800000L |
80593 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24_MASK 0x01000000L |
80594 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25_MASK 0x02000000L |
80595 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26_MASK 0x04000000L |
80596 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27_MASK 0x08000000L |
80597 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28_MASK 0x10000000L |
80598 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29_MASK 0x20000000L |
80599 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30_MASK 0x40000000L |
80600 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31_MASK 0x80000000L |
80601 | //PSP_EGRESS_POISON_STATUS_HI |
80602 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0__SHIFT 0x0 |
80603 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1__SHIFT 0x1 |
80604 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2__SHIFT 0x2 |
80605 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3__SHIFT 0x3 |
80606 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4__SHIFT 0x4 |
80607 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5__SHIFT 0x5 |
80608 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6__SHIFT 0x6 |
80609 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7__SHIFT 0x7 |
80610 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8__SHIFT 0x8 |
80611 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9__SHIFT 0x9 |
80612 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10__SHIFT 0xa |
80613 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11__SHIFT 0xb |
80614 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12__SHIFT 0xc |
80615 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13__SHIFT 0xd |
80616 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14__SHIFT 0xe |
80617 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15__SHIFT 0xf |
80618 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16__SHIFT 0x10 |
80619 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17__SHIFT 0x11 |
80620 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18__SHIFT 0x12 |
80621 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19__SHIFT 0x13 |
80622 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20__SHIFT 0x14 |
80623 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21__SHIFT 0x15 |
80624 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22__SHIFT 0x16 |
80625 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23__SHIFT 0x17 |
80626 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24__SHIFT 0x18 |
80627 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25__SHIFT 0x19 |
80628 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26__SHIFT 0x1a |
80629 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27__SHIFT 0x1b |
80630 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28__SHIFT 0x1c |
80631 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29__SHIFT 0x1d |
80632 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30__SHIFT 0x1e |
80633 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31__SHIFT 0x1f |
80634 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0_MASK 0x00000001L |
80635 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1_MASK 0x00000002L |
80636 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2_MASK 0x00000004L |
80637 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3_MASK 0x00000008L |
80638 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4_MASK 0x00000010L |
80639 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5_MASK 0x00000020L |
80640 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6_MASK 0x00000040L |
80641 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7_MASK 0x00000080L |
80642 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8_MASK 0x00000100L |
80643 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9_MASK 0x00000200L |
80644 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10_MASK 0x00000400L |
80645 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11_MASK 0x00000800L |
80646 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12_MASK 0x00001000L |
80647 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13_MASK 0x00002000L |
80648 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14_MASK 0x00004000L |
80649 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15_MASK 0x00008000L |
80650 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16_MASK 0x00010000L |
80651 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17_MASK 0x00020000L |
80652 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18_MASK 0x00040000L |
80653 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19_MASK 0x00080000L |
80654 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20_MASK 0x00100000L |
80655 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21_MASK 0x00200000L |
80656 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22_MASK 0x00400000L |
80657 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23_MASK 0x00800000L |
80658 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24_MASK 0x01000000L |
80659 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25_MASK 0x02000000L |
80660 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26_MASK 0x04000000L |
80661 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27_MASK 0x08000000L |
80662 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28_MASK 0x10000000L |
80663 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29_MASK 0x20000000L |
80664 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30_MASK 0x40000000L |
80665 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31_MASK 0x80000000L |
80666 | //PSP_PARITY_CONTROL_0 |
80667 | #define PSP_PARITY_CONTROL_0__PspParityCorrThreshold__SHIFT 0x0 |
80668 | #define PSP_PARITY_CONTROL_0__PspParityUCPThreshold__SHIFT 0x10 |
80669 | #define PSP_PARITY_CONTROL_0__PspParityCorrThreshold_MASK 0x0000FFFFL |
80670 | #define PSP_PARITY_CONTROL_0__PspParityUCPThreshold_MASK 0xFFFF0000L |
80671 | //PSP_PARITY_STATUS |
80672 | #define PSP_PARITY_STATUS__ParityErrCorr__SHIFT 0x0 |
80673 | #define PSP_PARITY_STATUS__ParityErrNonFatal__SHIFT 0x1 |
80674 | #define PSP_PARITY_STATUS__ParityErrFatal__SHIFT 0x2 |
80675 | #define PSP_PARITY_STATUS__ParityErrSerr__SHIFT 0x3 |
80676 | #define PSP_PARITY_STATUS__ParityErrCorr_MASK 0x00000001L |
80677 | #define PSP_PARITY_STATUS__ParityErrNonFatal_MASK 0x00000002L |
80678 | #define PSP_PARITY_STATUS__ParityErrFatal_MASK 0x00000004L |
80679 | #define PSP_PARITY_STATUS__ParityErrSerr_MASK 0x00000008L |
80680 | //PSP_PARITY_ERROR_STATUS_UNCORR_GRP0 |
80681 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 |
80682 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 |
80683 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 |
80684 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 |
80685 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 |
80686 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 |
80687 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 |
80688 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 |
80689 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 |
80690 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 |
80691 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa |
80692 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb |
80693 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc |
80694 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd |
80695 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe |
80696 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf |
80697 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 |
80698 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 |
80699 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 |
80700 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 |
80701 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 |
80702 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 |
80703 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 |
80704 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 |
80705 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 |
80706 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 |
80707 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a |
80708 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b |
80709 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c |
80710 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d |
80711 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e |
80712 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f |
80713 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L |
80714 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L |
80715 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L |
80716 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L |
80717 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L |
80718 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L |
80719 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L |
80720 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L |
80721 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L |
80722 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L |
80723 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L |
80724 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L |
80725 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L |
80726 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L |
80727 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L |
80728 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L |
80729 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L |
80730 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L |
80731 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L |
80732 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L |
80733 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L |
80734 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L |
80735 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L |
80736 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L |
80737 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L |
80738 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L |
80739 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L |
80740 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L |
80741 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L |
80742 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L |
80743 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L |
80744 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L |
80745 | //PSP_PARITY_ERROR_STATUS_UNCORR_GRP1 |
80746 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 |
80747 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 |
80748 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 |
80749 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 |
80750 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 |
80751 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 |
80752 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 |
80753 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 |
80754 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 |
80755 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 |
80756 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa |
80757 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb |
80758 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc |
80759 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd |
80760 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe |
80761 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf |
80762 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 |
80763 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 |
80764 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 |
80765 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 |
80766 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 |
80767 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 |
80768 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 |
80769 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 |
80770 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 |
80771 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 |
80772 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a |
80773 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b |
80774 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c |
80775 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d |
80776 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e |
80777 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f |
80778 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L |
80779 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L |
80780 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L |
80781 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L |
80782 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L |
80783 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L |
80784 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L |
80785 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L |
80786 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L |
80787 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L |
80788 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L |
80789 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L |
80790 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L |
80791 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L |
80792 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L |
80793 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L |
80794 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L |
80795 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L |
80796 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L |
80797 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L |
80798 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L |
80799 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L |
80800 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L |
80801 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L |
80802 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L |
80803 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L |
80804 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L |
80805 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L |
80806 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L |
80807 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L |
80808 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L |
80809 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L |
80810 | //PSP_PARITY_ERROR_STATUS_UNCORR_GRP2 |
80811 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 |
80812 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 |
80813 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 |
80814 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 |
80815 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 |
80816 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 |
80817 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 |
80818 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 |
80819 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 |
80820 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 |
80821 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa |
80822 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb |
80823 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc |
80824 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd |
80825 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe |
80826 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf |
80827 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 |
80828 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 |
80829 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 |
80830 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 |
80831 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 |
80832 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 |
80833 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 |
80834 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 |
80835 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 |
80836 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 |
80837 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a |
80838 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b |
80839 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c |
80840 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d |
80841 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e |
80842 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f |
80843 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L |
80844 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L |
80845 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L |
80846 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L |
80847 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L |
80848 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L |
80849 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L |
80850 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L |
80851 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L |
80852 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L |
80853 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L |
80854 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L |
80855 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L |
80856 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L |
80857 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L |
80858 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L |
80859 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L |
80860 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L |
80861 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L |
80862 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L |
80863 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L |
80864 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L |
80865 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L |
80866 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L |
80867 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L |
80868 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L |
80869 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L |
80870 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L |
80871 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L |
80872 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L |
80873 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L |
80874 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L |
80875 | //PSP_PARITY_ERROR_STATUS_UNCORR_GRP3 |
80876 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 |
80877 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 |
80878 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 |
80879 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 |
80880 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 |
80881 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 |
80882 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 |
80883 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 |
80884 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 |
80885 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 |
80886 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa |
80887 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb |
80888 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc |
80889 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd |
80890 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe |
80891 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf |
80892 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 |
80893 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 |
80894 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 |
80895 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 |
80896 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 |
80897 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 |
80898 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 |
80899 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 |
80900 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 |
80901 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 |
80902 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a |
80903 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b |
80904 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c |
80905 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d |
80906 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e |
80907 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f |
80908 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L |
80909 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L |
80910 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L |
80911 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L |
80912 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L |
80913 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L |
80914 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L |
80915 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L |
80916 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L |
80917 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L |
80918 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L |
80919 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L |
80920 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L |
80921 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L |
80922 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L |
80923 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L |
80924 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L |
80925 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L |
80926 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L |
80927 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L |
80928 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L |
80929 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L |
80930 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L |
80931 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L |
80932 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L |
80933 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L |
80934 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L |
80935 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L |
80936 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L |
80937 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L |
80938 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L |
80939 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L |
80940 | //PSP_PARITY_ERROR_STATUS_UNCORR_GRP4 |
80941 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 |
80942 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 |
80943 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 |
80944 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 |
80945 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 |
80946 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 |
80947 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 |
80948 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 |
80949 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 |
80950 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 |
80951 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa |
80952 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb |
80953 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc |
80954 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd |
80955 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe |
80956 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf |
80957 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 |
80958 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 |
80959 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 |
80960 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 |
80961 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 |
80962 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 |
80963 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 |
80964 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 |
80965 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 |
80966 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 |
80967 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a |
80968 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b |
80969 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c |
80970 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d |
80971 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e |
80972 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f |
80973 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L |
80974 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L |
80975 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L |
80976 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L |
80977 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L |
80978 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L |
80979 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L |
80980 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L |
80981 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L |
80982 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L |
80983 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L |
80984 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L |
80985 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L |
80986 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L |
80987 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L |
80988 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L |
80989 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L |
80990 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L |
80991 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L |
80992 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L |
80993 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L |
80994 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L |
80995 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L |
80996 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L |
80997 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L |
80998 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L |
80999 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L |
81000 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L |
81001 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L |
81002 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L |
81003 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L |
81004 | #define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L |
81005 | //PSP_PARITY_ERROR_STATUS_UCP_GRP0 |
81006 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0 |
81007 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1 |
81008 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2 |
81009 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3 |
81010 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4 |
81011 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5 |
81012 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6 |
81013 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7 |
81014 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8 |
81015 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9 |
81016 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa |
81017 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb |
81018 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc |
81019 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd |
81020 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe |
81021 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf |
81022 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10 |
81023 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11 |
81024 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12 |
81025 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13 |
81026 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14 |
81027 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15 |
81028 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16 |
81029 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17 |
81030 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18 |
81031 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19 |
81032 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a |
81033 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b |
81034 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c |
81035 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d |
81036 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e |
81037 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f |
81038 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L |
81039 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L |
81040 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L |
81041 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L |
81042 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L |
81043 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L |
81044 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L |
81045 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L |
81046 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L |
81047 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L |
81048 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L |
81049 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L |
81050 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L |
81051 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L |
81052 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L |
81053 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L |
81054 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L |
81055 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L |
81056 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L |
81057 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L |
81058 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L |
81059 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L |
81060 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L |
81061 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L |
81062 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L |
81063 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L |
81064 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L |
81065 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L |
81066 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L |
81067 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L |
81068 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L |
81069 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L |
81070 | //PSP_PARITY_ERROR_STATUS_UCP_GRP1 |
81071 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0 |
81072 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1 |
81073 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2 |
81074 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3 |
81075 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4 |
81076 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5 |
81077 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6 |
81078 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7 |
81079 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8 |
81080 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9 |
81081 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa |
81082 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb |
81083 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc |
81084 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd |
81085 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe |
81086 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf |
81087 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10 |
81088 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11 |
81089 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12 |
81090 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13 |
81091 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14 |
81092 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15 |
81093 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16 |
81094 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17 |
81095 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18 |
81096 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19 |
81097 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a |
81098 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b |
81099 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c |
81100 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d |
81101 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e |
81102 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f |
81103 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L |
81104 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L |
81105 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L |
81106 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L |
81107 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L |
81108 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L |
81109 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L |
81110 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L |
81111 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L |
81112 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L |
81113 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L |
81114 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L |
81115 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L |
81116 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L |
81117 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L |
81118 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L |
81119 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L |
81120 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L |
81121 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L |
81122 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L |
81123 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L |
81124 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L |
81125 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L |
81126 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L |
81127 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L |
81128 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L |
81129 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L |
81130 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L |
81131 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L |
81132 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L |
81133 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L |
81134 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L |
81135 | //PSP_PARITY_ERROR_STATUS_UCP_GRP2 |
81136 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0 |
81137 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1 |
81138 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2 |
81139 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3 |
81140 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4 |
81141 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5 |
81142 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6 |
81143 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7 |
81144 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8 |
81145 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9 |
81146 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa |
81147 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb |
81148 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc |
81149 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd |
81150 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe |
81151 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf |
81152 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10 |
81153 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11 |
81154 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12 |
81155 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13 |
81156 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14 |
81157 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15 |
81158 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16 |
81159 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17 |
81160 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18 |
81161 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19 |
81162 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a |
81163 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b |
81164 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c |
81165 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d |
81166 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e |
81167 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f |
81168 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L |
81169 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L |
81170 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L |
81171 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L |
81172 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L |
81173 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L |
81174 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L |
81175 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L |
81176 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L |
81177 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L |
81178 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L |
81179 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L |
81180 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L |
81181 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L |
81182 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L |
81183 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L |
81184 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L |
81185 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L |
81186 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L |
81187 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L |
81188 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L |
81189 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L |
81190 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L |
81191 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L |
81192 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L |
81193 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L |
81194 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L |
81195 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L |
81196 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L |
81197 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L |
81198 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L |
81199 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L |
81200 | //PSP_PARITY_ERROR_STATUS_UCP_GRP3 |
81201 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0 |
81202 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1 |
81203 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2 |
81204 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3 |
81205 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4 |
81206 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5 |
81207 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6 |
81208 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7 |
81209 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8 |
81210 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9 |
81211 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa |
81212 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb |
81213 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc |
81214 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd |
81215 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe |
81216 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf |
81217 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10 |
81218 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11 |
81219 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12 |
81220 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13 |
81221 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14 |
81222 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15 |
81223 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16 |
81224 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17 |
81225 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18 |
81226 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19 |
81227 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a |
81228 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b |
81229 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c |
81230 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d |
81231 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e |
81232 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f |
81233 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L |
81234 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L |
81235 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L |
81236 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L |
81237 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L |
81238 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L |
81239 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L |
81240 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L |
81241 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L |
81242 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L |
81243 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L |
81244 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L |
81245 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L |
81246 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L |
81247 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L |
81248 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L |
81249 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L |
81250 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L |
81251 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L |
81252 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L |
81253 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L |
81254 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L |
81255 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L |
81256 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L |
81257 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L |
81258 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L |
81259 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L |
81260 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L |
81261 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L |
81262 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L |
81263 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L |
81264 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L |
81265 | //PSP_PARITY_ERROR_STATUS_UCP_GRP4 |
81266 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0 |
81267 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1 |
81268 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2 |
81269 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3 |
81270 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4 |
81271 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5 |
81272 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6 |
81273 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7 |
81274 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8 |
81275 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9 |
81276 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa |
81277 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb |
81278 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc |
81279 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd |
81280 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe |
81281 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf |
81282 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10 |
81283 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11 |
81284 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12 |
81285 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13 |
81286 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14 |
81287 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15 |
81288 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16 |
81289 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17 |
81290 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18 |
81291 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19 |
81292 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a |
81293 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b |
81294 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c |
81295 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d |
81296 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e |
81297 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f |
81298 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L |
81299 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L |
81300 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L |
81301 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L |
81302 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L |
81303 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L |
81304 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L |
81305 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L |
81306 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L |
81307 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L |
81308 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L |
81309 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L |
81310 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L |
81311 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L |
81312 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L |
81313 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L |
81314 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L |
81315 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L |
81316 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L |
81317 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L |
81318 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L |
81319 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L |
81320 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L |
81321 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L |
81322 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L |
81323 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L |
81324 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L |
81325 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L |
81326 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L |
81327 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L |
81328 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L |
81329 | #define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L |
81330 | //PSP_PARITY_COUNTER_UCP_GRP0 |
81331 | #define PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0 |
81332 | #define PSP_PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f |
81333 | #define PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL |
81334 | #define PSP_PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L |
81335 | //PSP_PARITY_COUNTER_UCP_GRP1 |
81336 | #define PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0 |
81337 | #define PSP_PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f |
81338 | #define PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL |
81339 | #define PSP_PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L |
81340 | //PSP_PARITY_COUNTER_UCP_GRP2 |
81341 | #define PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0 |
81342 | #define PSP_PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f |
81343 | #define PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL |
81344 | #define PSP_PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L |
81345 | //PSP_PARITY_COUNTER_UCP_GRP3 |
81346 | #define PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0 |
81347 | #define PSP_PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f |
81348 | #define PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL |
81349 | #define PSP_PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L |
81350 | //PSP_PARITY_COUNTER_UCP_GRP4 |
81351 | #define PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0 |
81352 | #define PSP_PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f |
81353 | #define PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL |
81354 | #define PSP_PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L |
81355 | //PSP_PARITY_ERROR_STATUS_CORR_GRP0 |
81356 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 |
81357 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 |
81358 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 |
81359 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 |
81360 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 |
81361 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 |
81362 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 |
81363 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 |
81364 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 |
81365 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 |
81366 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa |
81367 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb |
81368 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc |
81369 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd |
81370 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe |
81371 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf |
81372 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 |
81373 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 |
81374 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 |
81375 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 |
81376 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 |
81377 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 |
81378 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 |
81379 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 |
81380 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 |
81381 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 |
81382 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a |
81383 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b |
81384 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c |
81385 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d |
81386 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e |
81387 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f |
81388 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L |
81389 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L |
81390 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L |
81391 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L |
81392 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L |
81393 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L |
81394 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L |
81395 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L |
81396 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L |
81397 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L |
81398 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L |
81399 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L |
81400 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L |
81401 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L |
81402 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L |
81403 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L |
81404 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L |
81405 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L |
81406 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L |
81407 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L |
81408 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L |
81409 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L |
81410 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L |
81411 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L |
81412 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L |
81413 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L |
81414 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L |
81415 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L |
81416 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L |
81417 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L |
81418 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L |
81419 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L |
81420 | //PSP_PARITY_ERROR_STATUS_CORR_GRP1 |
81421 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 |
81422 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 |
81423 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 |
81424 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 |
81425 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 |
81426 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 |
81427 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 |
81428 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 |
81429 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 |
81430 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 |
81431 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa |
81432 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb |
81433 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc |
81434 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd |
81435 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe |
81436 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf |
81437 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 |
81438 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 |
81439 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 |
81440 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 |
81441 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 |
81442 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 |
81443 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 |
81444 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 |
81445 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 |
81446 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 |
81447 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a |
81448 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b |
81449 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c |
81450 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d |
81451 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e |
81452 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f |
81453 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L |
81454 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L |
81455 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L |
81456 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L |
81457 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L |
81458 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L |
81459 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L |
81460 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L |
81461 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L |
81462 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L |
81463 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L |
81464 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L |
81465 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L |
81466 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L |
81467 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L |
81468 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L |
81469 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L |
81470 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L |
81471 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L |
81472 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L |
81473 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L |
81474 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L |
81475 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L |
81476 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L |
81477 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L |
81478 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L |
81479 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L |
81480 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L |
81481 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L |
81482 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L |
81483 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L |
81484 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L |
81485 | //PSP_PARITY_ERROR_STATUS_CORR_GRP2 |
81486 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 |
81487 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 |
81488 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 |
81489 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 |
81490 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 |
81491 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 |
81492 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 |
81493 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 |
81494 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 |
81495 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 |
81496 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa |
81497 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb |
81498 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc |
81499 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd |
81500 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe |
81501 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf |
81502 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 |
81503 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 |
81504 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 |
81505 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 |
81506 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 |
81507 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 |
81508 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 |
81509 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 |
81510 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 |
81511 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 |
81512 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a |
81513 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b |
81514 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c |
81515 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d |
81516 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e |
81517 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f |
81518 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L |
81519 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L |
81520 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L |
81521 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L |
81522 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L |
81523 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L |
81524 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L |
81525 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L |
81526 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L |
81527 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L |
81528 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L |
81529 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L |
81530 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L |
81531 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L |
81532 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L |
81533 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L |
81534 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L |
81535 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L |
81536 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L |
81537 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L |
81538 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L |
81539 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L |
81540 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L |
81541 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L |
81542 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L |
81543 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L |
81544 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L |
81545 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L |
81546 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L |
81547 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L |
81548 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L |
81549 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L |
81550 | //PSP_PARITY_ERROR_STATUS_CORR_GRP3 |
81551 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 |
81552 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 |
81553 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 |
81554 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 |
81555 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 |
81556 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 |
81557 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 |
81558 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 |
81559 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 |
81560 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 |
81561 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa |
81562 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb |
81563 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc |
81564 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd |
81565 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe |
81566 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf |
81567 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 |
81568 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 |
81569 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 |
81570 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 |
81571 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 |
81572 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 |
81573 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 |
81574 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 |
81575 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 |
81576 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 |
81577 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a |
81578 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b |
81579 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c |
81580 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d |
81581 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e |
81582 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f |
81583 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L |
81584 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L |
81585 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L |
81586 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L |
81587 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L |
81588 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L |
81589 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L |
81590 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L |
81591 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L |
81592 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L |
81593 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L |
81594 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L |
81595 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L |
81596 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L |
81597 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L |
81598 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L |
81599 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L |
81600 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L |
81601 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L |
81602 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L |
81603 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L |
81604 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L |
81605 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L |
81606 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L |
81607 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L |
81608 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L |
81609 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L |
81610 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L |
81611 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L |
81612 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L |
81613 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L |
81614 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L |
81615 | //PSP_PARITY_ERROR_STATUS_CORR_GRP4 |
81616 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 |
81617 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 |
81618 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 |
81619 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 |
81620 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 |
81621 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 |
81622 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 |
81623 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 |
81624 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 |
81625 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 |
81626 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa |
81627 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb |
81628 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc |
81629 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd |
81630 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe |
81631 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf |
81632 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 |
81633 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 |
81634 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 |
81635 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 |
81636 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 |
81637 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 |
81638 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 |
81639 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 |
81640 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 |
81641 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 |
81642 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a |
81643 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b |
81644 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c |
81645 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d |
81646 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e |
81647 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f |
81648 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L |
81649 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L |
81650 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L |
81651 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L |
81652 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L |
81653 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L |
81654 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L |
81655 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L |
81656 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L |
81657 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L |
81658 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L |
81659 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L |
81660 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L |
81661 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L |
81662 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L |
81663 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L |
81664 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L |
81665 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L |
81666 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L |
81667 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L |
81668 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L |
81669 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L |
81670 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L |
81671 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L |
81672 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L |
81673 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L |
81674 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L |
81675 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L |
81676 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L |
81677 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L |
81678 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L |
81679 | #define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L |
81680 | //PSP_PARITY_COUNTER_CORR_GRP0 |
81681 | #define PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0 |
81682 | #define PSP_PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f |
81683 | #define PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL |
81684 | #define PSP_PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L |
81685 | //PSP_PARITY_COUNTER_CORR_GRP1 |
81686 | #define PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0 |
81687 | #define PSP_PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f |
81688 | #define PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL |
81689 | #define PSP_PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L |
81690 | //PSP_PARITY_COUNTER_CORR_GRP2 |
81691 | #define PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0 |
81692 | #define PSP_PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f |
81693 | #define PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL |
81694 | #define PSP_PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L |
81695 | //PSP_PARITY_COUNTER_CORR_GRP3 |
81696 | #define PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0 |
81697 | #define PSP_PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f |
81698 | #define PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL |
81699 | #define PSP_PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L |
81700 | //PSP_PARITY_COUNTER_CORR_GRP4 |
81701 | #define PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0 |
81702 | #define PSP_PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f |
81703 | #define PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL |
81704 | #define PSP_PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L |
81705 | //PSP_ParitySerr_ACTION_CONTROL |
81706 | #define PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
81707 | #define PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
81708 | //PSP_ParityFatal_ACTION_CONTROL |
81709 | #define PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
81710 | #define PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
81711 | //PSP_ParityNonFatal_ACTION_CONTROL |
81712 | #define PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
81713 | #define PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
81714 | //PSP_ParityCorr_ACTION_CONTROL |
81715 | #define PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 |
81716 | #define PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L |
81717 | |
81718 | |
81719 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp |
81720 | //NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL |
81721 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
81722 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
81723 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
81724 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
81725 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
81726 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
81727 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
81728 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
81729 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
81730 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
81731 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
81732 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
81733 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
81734 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
81735 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
81736 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
81737 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
81738 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
81739 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
81740 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
81741 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
81742 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
81743 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
81744 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
81745 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
81746 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
81747 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
81748 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
81749 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
81750 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
81751 | //NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS |
81752 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
81753 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
81754 | //NB_PCIE0DEVINDCFG0_STEERING_CNTL |
81755 | #define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
81756 | #define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
81757 | #define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
81758 | #define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
81759 | //NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0 |
81760 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
81761 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
81762 | //NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1 |
81763 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
81764 | #define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
81765 | |
81766 | |
81767 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp |
81768 | //NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL |
81769 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
81770 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
81771 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
81772 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
81773 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
81774 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
81775 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
81776 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
81777 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
81778 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
81779 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
81780 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
81781 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
81782 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
81783 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
81784 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
81785 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
81786 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
81787 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
81788 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
81789 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
81790 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
81791 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
81792 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
81793 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
81794 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
81795 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
81796 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
81797 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
81798 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
81799 | //NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS |
81800 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
81801 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
81802 | //NB_PCIE0DEVINDCFG1_STEERING_CNTL |
81803 | #define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
81804 | #define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
81805 | #define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
81806 | #define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
81807 | //NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0 |
81808 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
81809 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
81810 | //NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1 |
81811 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
81812 | #define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
81813 | |
81814 | |
81815 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp |
81816 | //NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL |
81817 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
81818 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
81819 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
81820 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
81821 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
81822 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
81823 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
81824 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
81825 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
81826 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
81827 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
81828 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
81829 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
81830 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
81831 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
81832 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
81833 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
81834 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
81835 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
81836 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
81837 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
81838 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
81839 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
81840 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
81841 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
81842 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
81843 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
81844 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
81845 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
81846 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
81847 | //NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS |
81848 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
81849 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
81850 | //NB_PCIE0DEVINDCFG2_STEERING_CNTL |
81851 | #define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
81852 | #define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
81853 | #define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
81854 | #define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
81855 | //NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0 |
81856 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
81857 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
81858 | //NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1 |
81859 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
81860 | #define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
81861 | |
81862 | |
81863 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp |
81864 | //NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL |
81865 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
81866 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
81867 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
81868 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
81869 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
81870 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
81871 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
81872 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
81873 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
81874 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
81875 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
81876 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
81877 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
81878 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
81879 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
81880 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
81881 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
81882 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
81883 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
81884 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
81885 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
81886 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
81887 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
81888 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
81889 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
81890 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
81891 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
81892 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
81893 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
81894 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
81895 | //NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS |
81896 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
81897 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
81898 | //NB_PCIE0DEVINDCFG3_STEERING_CNTL |
81899 | #define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
81900 | #define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
81901 | #define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
81902 | #define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
81903 | //NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0 |
81904 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
81905 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
81906 | //NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1 |
81907 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
81908 | #define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
81909 | |
81910 | |
81911 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp |
81912 | //NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL |
81913 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
81914 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
81915 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
81916 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
81917 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
81918 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
81919 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
81920 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
81921 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
81922 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
81923 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
81924 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
81925 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
81926 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
81927 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
81928 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
81929 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
81930 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
81931 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
81932 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
81933 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
81934 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
81935 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
81936 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
81937 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
81938 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
81939 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
81940 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
81941 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
81942 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
81943 | //NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS |
81944 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
81945 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
81946 | //NB_PCIE0DEVINDCFG4_STEERING_CNTL |
81947 | #define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
81948 | #define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
81949 | #define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
81950 | #define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
81951 | //NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0 |
81952 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
81953 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
81954 | //NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1 |
81955 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
81956 | #define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
81957 | |
81958 | |
81959 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp |
81960 | //NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL |
81961 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
81962 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
81963 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
81964 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
81965 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
81966 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
81967 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
81968 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
81969 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
81970 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
81971 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
81972 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
81973 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
81974 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
81975 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
81976 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
81977 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
81978 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
81979 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
81980 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
81981 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
81982 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
81983 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
81984 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
81985 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
81986 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
81987 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
81988 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
81989 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
81990 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
81991 | //NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS |
81992 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
81993 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
81994 | //NB_PCIE0DEVINDCFG5_STEERING_CNTL |
81995 | #define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
81996 | #define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
81997 | #define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
81998 | #define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
81999 | //NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0 |
82000 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
82001 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
82002 | //NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1 |
82003 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
82004 | #define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
82005 | |
82006 | |
82007 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp |
82008 | //NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL |
82009 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
82010 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
82011 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
82012 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
82013 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
82014 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
82015 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
82016 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
82017 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
82018 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
82019 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
82020 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
82021 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
82022 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
82023 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
82024 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
82025 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
82026 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
82027 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
82028 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
82029 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
82030 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
82031 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
82032 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
82033 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
82034 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
82035 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
82036 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
82037 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
82038 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
82039 | //NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS |
82040 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
82041 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
82042 | //NB_PCIE0DEVINDCFG6_STEERING_CNTL |
82043 | #define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
82044 | #define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
82045 | #define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
82046 | #define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
82047 | //NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0 |
82048 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
82049 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
82050 | //NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1 |
82051 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
82052 | #define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
82053 | |
82054 | |
82055 | // addressBlock: nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp |
82056 | //NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL |
82057 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
82058 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
82059 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
82060 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
82061 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
82062 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
82063 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
82064 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
82065 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
82066 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
82067 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
82068 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
82069 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
82070 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
82071 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
82072 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
82073 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
82074 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
82075 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
82076 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
82077 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
82078 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
82079 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
82080 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
82081 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
82082 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
82083 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
82084 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
82085 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
82086 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
82087 | //NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS |
82088 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
82089 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
82090 | //NB_NBIF1DEVINDCFG0_STEERING_CNTL |
82091 | #define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
82092 | #define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
82093 | #define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
82094 | #define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
82095 | //NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0 |
82096 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
82097 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
82098 | //NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1 |
82099 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
82100 | #define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
82101 | |
82102 | |
82103 | // addressBlock: nbio_iohub_nb_NBIF1devindcfg1_devind_cfgdecp |
82104 | //NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL |
82105 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
82106 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
82107 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
82108 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
82109 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
82110 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
82111 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
82112 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
82113 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
82114 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
82115 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
82116 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
82117 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
82118 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
82119 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
82120 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
82121 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
82122 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
82123 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
82124 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
82125 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
82126 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
82127 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
82128 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
82129 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
82130 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
82131 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
82132 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
82133 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
82134 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
82135 | //NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS |
82136 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
82137 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
82138 | //NB_NBIF1DEVINDCFG1_STEERING_CNTL |
82139 | #define NB_NBIF1DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
82140 | #define NB_NBIF1DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
82141 | #define NB_NBIF1DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
82142 | #define NB_NBIF1DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
82143 | //NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0 |
82144 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
82145 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
82146 | //NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1 |
82147 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
82148 | #define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
82149 | |
82150 | |
82151 | // addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp |
82152 | //NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL |
82153 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 |
82154 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 |
82155 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 |
82156 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 |
82157 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 |
82158 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 |
82159 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 |
82160 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 |
82161 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 |
82162 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa |
82163 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 |
82164 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 |
82165 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 |
82166 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 |
82167 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 |
82168 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L |
82169 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L |
82170 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L |
82171 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L |
82172 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L |
82173 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L |
82174 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L |
82175 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L |
82176 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L |
82177 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L |
82178 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L |
82179 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L |
82180 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L |
82181 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L |
82182 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L |
82183 | //NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS |
82184 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 |
82185 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L |
82186 | //NB_INTSBDEVINDCFG0_STEERING_CNTL |
82187 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
82188 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
82189 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
82190 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
82191 | //NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0 |
82192 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
82193 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
82194 | //NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1 |
82195 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
82196 | #define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
82197 | |
82198 | |
82199 | // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
82200 | //NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID |
82201 | #define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
82202 | #define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 |
82203 | #define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL |
82204 | #define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L |
82205 | //NB_PCIEDUMMY0_1_STATUS_COMMAND |
82206 | #define NB_PCIEDUMMY0_1_STATUS_COMMAND__COMMAND__SHIFT 0x0 |
82207 | #define NB_PCIEDUMMY0_1_STATUS_COMMAND__STATUS__SHIFT 0x10 |
82208 | #define NB_PCIEDUMMY0_1_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL |
82209 | #define NB_PCIEDUMMY0_1_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L |
82210 | //NB_PCIEDUMMY0_1_CLASS_CODE_REVID |
82211 | #define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__REVID__SHIFT 0x0 |
82212 | #define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 |
82213 | #define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__REVID_MASK 0x000000FFL |
82214 | #define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L |
82215 | //NB_PCIEDUMMY0_1_HEADER_TYPE |
82216 | #define NB_PCIEDUMMY0_1_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 |
82217 | #define NB_PCIEDUMMY0_1_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 |
82218 | #define NB_PCIEDUMMY0_1_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L |
82219 | #define NB_PCIEDUMMY0_1_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L |
82220 | //NB_PCIEDUMMY0_1_HEADER_TYPE_W |
82221 | #define NB_PCIEDUMMY0_1_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 |
82222 | #define NB_PCIEDUMMY0_1_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L |
82223 | |
82224 | |
82225 | // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
82226 | //NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID |
82227 | #define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
82228 | #define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 |
82229 | #define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL |
82230 | #define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L |
82231 | //NB_PCIEDUMMY1_1_STATUS_COMMAND |
82232 | #define NB_PCIEDUMMY1_1_STATUS_COMMAND__COMMAND__SHIFT 0x0 |
82233 | #define NB_PCIEDUMMY1_1_STATUS_COMMAND__STATUS__SHIFT 0x10 |
82234 | #define NB_PCIEDUMMY1_1_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL |
82235 | #define NB_PCIEDUMMY1_1_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L |
82236 | //NB_PCIEDUMMY1_1_CLASS_CODE_REVID |
82237 | #define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__REVID__SHIFT 0x0 |
82238 | #define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 |
82239 | #define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__REVID_MASK 0x000000FFL |
82240 | #define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L |
82241 | //NB_PCIEDUMMY1_1_HEADER_TYPE |
82242 | #define NB_PCIEDUMMY1_1_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 |
82243 | #define NB_PCIEDUMMY1_1_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 |
82244 | #define NB_PCIEDUMMY1_1_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L |
82245 | #define NB_PCIEDUMMY1_1_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L |
82246 | //NB_PCIEDUMMY1_1_HEADER_TYPE_W |
82247 | #define NB_PCIEDUMMY1_1_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 |
82248 | #define NB_PCIEDUMMY1_1_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L |
82249 | |
82250 | |
82251 | // addressBlock: nbio_iohub_iommu_indcfg_iommuind_cfgdec |
82252 | //IOMMU_SMN_INDEX_0 |
82253 | #define IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0__SHIFT 0x0 |
82254 | #define IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0_MASK 0xFFFFFFFFL |
82255 | //IOMMU_SMN_DATA_0 |
82256 | #define IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0__SHIFT 0x0 |
82257 | #define IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0_MASK 0xFFFFFFFFL |
82258 | //IOMMU_SMN_INDEX_1 |
82259 | #define IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1__SHIFT 0x0 |
82260 | #define IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1_MASK 0xFFFFFFFFL |
82261 | //IOMMU_SMN_DATA_1 |
82262 | #define IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1__SHIFT 0x0 |
82263 | #define IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1_MASK 0xFFFFFFFFL |
82264 | |
82265 | |
82266 | // addressBlock: nbio_iohub_ioapic_indcfg_ioapicind_cfgdec |
82267 | //IOAPIC_MIO_INDEX |
82268 | #define IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data__SHIFT 0x0 |
82269 | #define IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data_MASK 0xFFFFFFFFL |
82270 | //IOAPIC_MIO_DATA |
82271 | #define IOAPIC_MIO_DATA__IOAPIC_MIO_DATA__SHIFT 0x0 |
82272 | #define IOAPIC_MIO_DATA__IOAPIC_MIO_DATA_MASK 0xFFFFFFFFL |
82273 | |
82274 | |
82275 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec |
82276 | //NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX |
82277 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82278 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82279 | //NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA |
82280 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82281 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82282 | |
82283 | |
82284 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec |
82285 | //NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX |
82286 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82287 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82288 | //NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA |
82289 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82290 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82291 | |
82292 | |
82293 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec |
82294 | //NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX |
82295 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82296 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82297 | //NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA |
82298 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82299 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82300 | |
82301 | |
82302 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec |
82303 | //NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX |
82304 | #define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82305 | #define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82306 | //NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA |
82307 | #define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82308 | #define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82309 | |
82310 | |
82311 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec |
82312 | //NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX |
82313 | #define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82314 | #define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82315 | //NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA |
82316 | #define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82317 | #define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82318 | |
82319 | |
82320 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec |
82321 | //NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX |
82322 | #define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82323 | #define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82324 | //NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA |
82325 | #define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82326 | #define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82327 | |
82328 | |
82329 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec |
82330 | //NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX |
82331 | #define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82332 | #define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82333 | //NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA |
82334 | #define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82335 | #define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82336 | |
82337 | |
82338 | // addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec |
82339 | //NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX |
82340 | #define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82341 | #define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82342 | //NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA |
82343 | #define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82344 | #define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82345 | |
82346 | |
82347 | // addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg1_pciercbdgind_cfgdec |
82348 | //NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX |
82349 | #define NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
82350 | #define NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
82351 | //NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA |
82352 | #define NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
82353 | #define NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
82354 | |
82355 | |
82356 | // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
82357 | //IOMMU_L2_1_IOMMU_VENDOR_ID |
82358 | #define IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
82359 | #define IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
82360 | //IOMMU_L2_1_IOMMU_DEVICE_ID |
82361 | #define IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
82362 | #define IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
82363 | //IOMMU_L2_1_IOMMU_COMMAND |
82364 | #define IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
82365 | #define IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
82366 | #define IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
82367 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved1__SHIFT 0x3 |
82368 | #define IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6 |
82369 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved0__SHIFT 0x7 |
82370 | #define IOMMU_L2_1_IOMMU_COMMAND__SERR_EN__SHIFT 0x8 |
82371 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved2__SHIFT 0x9 |
82372 | #define IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa |
82373 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved__SHIFT 0xb |
82374 | #define IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
82375 | #define IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
82376 | #define IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
82377 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved1_MASK 0x0038L |
82378 | #define IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L |
82379 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved0_MASK 0x0080L |
82380 | #define IOMMU_L2_1_IOMMU_COMMAND__SERR_EN_MASK 0x0100L |
82381 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved2_MASK 0x0200L |
82382 | #define IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L |
82383 | #define IOMMU_L2_1_IOMMU_COMMAND__Reserved_MASK 0xF800L |
82384 | //IOMMU_L2_1_IOMMU_STATUS |
82385 | #define IOMMU_L2_1_IOMMU_STATUS__Reserved__SHIFT 0x0 |
82386 | #define IOMMU_L2_1_IOMMU_STATUS__INT_Status__SHIFT 0x3 |
82387 | #define IOMMU_L2_1_IOMMU_STATUS__CAP_LIST__SHIFT 0x4 |
82388 | #define IOMMU_L2_1_IOMMU_STATUS__Reserved1__SHIFT 0x5 |
82389 | #define IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8 |
82390 | #define IOMMU_L2_1_IOMMU_STATUS__Reserved2__SHIFT 0x9 |
82391 | #define IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
82392 | #define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
82393 | #define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
82394 | #define IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
82395 | #define IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
82396 | #define IOMMU_L2_1_IOMMU_STATUS__Reserved_MASK 0x0007L |
82397 | #define IOMMU_L2_1_IOMMU_STATUS__INT_Status_MASK 0x0008L |
82398 | #define IOMMU_L2_1_IOMMU_STATUS__CAP_LIST_MASK 0x0010L |
82399 | #define IOMMU_L2_1_IOMMU_STATUS__Reserved1_MASK 0x00E0L |
82400 | #define IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L |
82401 | #define IOMMU_L2_1_IOMMU_STATUS__Reserved2_MASK 0x0600L |
82402 | #define IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
82403 | #define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
82404 | #define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
82405 | #define IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
82406 | #define IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
82407 | //IOMMU_L2_1_IOMMU_REVISION_ID |
82408 | #define IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
82409 | #define IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
82410 | #define IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
82411 | #define IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
82412 | //IOMMU_L2_1_IOMMU_REGPROG_INF |
82413 | #define IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 |
82414 | #define IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL |
82415 | //IOMMU_L2_1_IOMMU_SUB_CLASS |
82416 | #define IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
82417 | #define IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
82418 | //IOMMU_L2_1_IOMMU_BASE_CODE |
82419 | #define IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
82420 | #define IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
82421 | //IOMMU_L2_1_IOMMU_CACHE_LINE |
82422 | #define IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
82423 | #define IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
82424 | //IOMMU_L2_1_IOMMU_LATENCY |
82425 | #define IOMMU_L2_1_IOMMU_LATENCY__LATENCY__SHIFT 0x0 |
82426 | #define IOMMU_L2_1_IOMMU_LATENCY__LATENCY_MASK 0xFFL |
82427 | //IOMMU_L2_1_IOMMU_HEADER |
82428 | #define IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0 |
82429 | #define IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL |
82430 | //IOMMU_L2_1_IOMMU_BIST |
82431 | #define IOMMU_L2_1_IOMMU_BIST__BIST_COMP__SHIFT 0x0 |
82432 | #define IOMMU_L2_1_IOMMU_BIST__BIST_STRT__SHIFT 0x6 |
82433 | #define IOMMU_L2_1_IOMMU_BIST__BIST_CAP__SHIFT 0x7 |
82434 | #define IOMMU_L2_1_IOMMU_BIST__BIST_COMP_MASK 0x0FL |
82435 | #define IOMMU_L2_1_IOMMU_BIST__BIST_STRT_MASK 0x40L |
82436 | #define IOMMU_L2_1_IOMMU_BIST__BIST_CAP_MASK 0x80L |
82437 | //IOMMU_L2_1_IOMMU_ADAPTER_ID |
82438 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
82439 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
82440 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
82441 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
82442 | //IOMMU_L2_1_IOMMU_CAPABILITIES_PTR |
82443 | #define IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
82444 | #define IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
82445 | //IOMMU_L2_1_IOMMU_INTERRUPT_LINE |
82446 | #define IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
82447 | #define IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
82448 | //IOMMU_L2_1_IOMMU_INTERRUPT_PIN |
82449 | #define IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
82450 | #define IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
82451 | //IOMMU_L2_1_IOMMU_CAP_HEADER |
82452 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0 |
82453 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8 |
82454 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10 |
82455 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13 |
82456 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18 |
82457 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19 |
82458 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a |
82459 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b |
82460 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c |
82461 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d |
82462 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL |
82463 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L |
82464 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L |
82465 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L |
82466 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L |
82467 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L |
82468 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L |
82469 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L |
82470 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L |
82471 | #define IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L |
82472 | //IOMMU_L2_1_IOMMU_CAP_BASE_LO |
82473 | #define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
82474 | #define IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1 |
82475 | #define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 |
82476 | #define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
82477 | #define IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL |
82478 | #define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L |
82479 | //IOMMU_L2_1_IOMMU_CAP_BASE_HI |
82480 | #define IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 |
82481 | #define IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL |
82482 | //IOMMU_L2_1_IOMMU_CAP_RANGE |
82483 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0 |
82484 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5 |
82485 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7 |
82486 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8 |
82487 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10 |
82488 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18 |
82489 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL |
82490 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L |
82491 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L |
82492 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L |
82493 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L |
82494 | #define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L |
82495 | //IOMMU_L2_1_IOMMU_CAP_MISC |
82496 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 |
82497 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5 |
82498 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8 |
82499 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf |
82500 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 |
82501 | #define IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17 |
82502 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b |
82503 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL |
82504 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L |
82505 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L |
82506 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L |
82507 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L |
82508 | #define IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L |
82509 | #define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L |
82510 | //IOMMU_L2_1_IOMMU_CAP_MISC_1 |
82511 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 |
82512 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 |
82513 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 |
82514 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf |
82515 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f |
82516 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL |
82517 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L |
82518 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L |
82519 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L |
82520 | #define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L |
82521 | //IOMMU_L2_1_IOMMU_MSI_CAP |
82522 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 |
82523 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 |
82524 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10 |
82525 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 |
82526 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 |
82527 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17 |
82528 | #define IOMMU_L2_1_IOMMU_MSI_CAP__Reserved__SHIFT 0x18 |
82529 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL |
82530 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L |
82531 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L |
82532 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L |
82533 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L |
82534 | #define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L |
82535 | #define IOMMU_L2_1_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L |
82536 | //IOMMU_L2_1_IOMMU_MSI_ADDR_LO |
82537 | #define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0 |
82538 | #define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 |
82539 | #define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L |
82540 | #define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL |
82541 | //IOMMU_L2_1_IOMMU_MSI_ADDR_HI |
82542 | #define IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 |
82543 | #define IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL |
82544 | //IOMMU_L2_1_IOMMU_MSI_DATA |
82545 | #define IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0 |
82546 | #define IOMMU_L2_1_IOMMU_MSI_DATA__Reserved__SHIFT 0x10 |
82547 | #define IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL |
82548 | #define IOMMU_L2_1_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L |
82549 | //IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP |
82550 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 |
82551 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 |
82552 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 |
82553 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 |
82554 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 |
82555 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b |
82556 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL |
82557 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L |
82558 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L |
82559 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L |
82560 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L |
82561 | #define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L |
82562 | //IOMMU_L2_1_IOMMU_ADAPTER_ID_W |
82563 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0 |
82564 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10 |
82565 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL |
82566 | #define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L |
82567 | //IOMMU_L2_1_IOMMU_CONTROL_W |
82568 | #define IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0 |
82569 | #define IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4 |
82570 | #define IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 |
82571 | #define IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 |
82572 | #define IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa |
82573 | #define IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd |
82574 | #define IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L |
82575 | #define IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L |
82576 | #define IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L |
82577 | #define IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L |
82578 | #define IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L |
82579 | #define IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L |
82580 | //IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W |
82581 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 |
82582 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 |
82583 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2 |
82584 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 |
82585 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 |
82586 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5 |
82587 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6 |
82588 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 |
82589 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8 |
82590 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 |
82591 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa |
82592 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc |
82593 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd |
82594 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 |
82595 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18 |
82596 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a |
82597 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c |
82598 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e |
82599 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L |
82600 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L |
82601 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L |
82602 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L |
82603 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L |
82604 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L |
82605 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L |
82606 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L |
82607 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L |
82608 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L |
82609 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L |
82610 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L |
82611 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L |
82612 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L |
82613 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L |
82614 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L |
82615 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L |
82616 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L |
82617 | //IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W |
82618 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 |
82619 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4 |
82620 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 |
82621 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8 |
82622 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9 |
82623 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa |
82624 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb |
82625 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd |
82626 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe |
82627 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf |
82628 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 |
82629 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11 |
82630 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12 |
82631 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13 |
82632 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14 |
82633 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15 |
82634 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL |
82635 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L |
82636 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L |
82637 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L |
82638 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L |
82639 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L |
82640 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L |
82641 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L |
82642 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L |
82643 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L |
82644 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L |
82645 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L |
82646 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L |
82647 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L |
82648 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L |
82649 | #define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L |
82650 | //IOMMU_L2_1_IOMMU_RANGE_W |
82651 | #define IOMMU_L2_1_IOMMU_RANGE_W__Reserved__SHIFT 0x0 |
82652 | #define IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7 |
82653 | #define IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8 |
82654 | #define IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10 |
82655 | #define IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18 |
82656 | #define IOMMU_L2_1_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL |
82657 | #define IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L |
82658 | #define IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L |
82659 | #define IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L |
82660 | #define IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L |
82661 | //IOMMU_L2_1_IOMMU_DSFX_CONTROL |
82662 | #define IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0 |
82663 | #define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18 |
82664 | #define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c |
82665 | #define IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL |
82666 | #define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L |
82667 | #define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L |
82668 | //IOMMU_L2_1_IOMMU_DSSX_DUMMY_0 |
82669 | #define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0 |
82670 | #define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18 |
82671 | #define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL |
82672 | #define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L |
82673 | //IOMMU_L2_1_IOMMU_DSCX_DUMMY_0 |
82674 | #define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0 |
82675 | #define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18 |
82676 | #define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL |
82677 | #define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L |
82678 | //IOMMU_L2_1_L2B_POISON_DVM_CNTRL |
82679 | #define IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0 |
82680 | #define IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L |
82681 | //IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control |
82682 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
82683 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
82684 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8 |
82685 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe |
82686 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
82687 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
82688 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L |
82689 | #define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L |
82690 | //IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control |
82691 | #define IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4 |
82692 | #define IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L |
82693 | //IOMMU_L2_1_SMMU_MMIO_IDR0_W |
82694 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0 |
82695 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1 |
82696 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2 |
82697 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4 |
82698 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5 |
82699 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6 |
82700 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8 |
82701 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9 |
82702 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa |
82703 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb |
82704 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc |
82705 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd |
82706 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe |
82707 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf |
82708 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10 |
82709 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11 |
82710 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12 |
82711 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13 |
82712 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14 |
82713 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15 |
82714 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18 |
82715 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a |
82716 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b |
82717 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d |
82718 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L |
82719 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L |
82720 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL |
82721 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L |
82722 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L |
82723 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L |
82724 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L |
82725 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L |
82726 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L |
82727 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L |
82728 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L |
82729 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L |
82730 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L |
82731 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L |
82732 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L |
82733 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L |
82734 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L |
82735 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L |
82736 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L |
82737 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L |
82738 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L |
82739 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L |
82740 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L |
82741 | #define IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L |
82742 | //IOMMU_L2_1_SMMU_MMIO_IDR1_W |
82743 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0 |
82744 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6 |
82745 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb |
82746 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10 |
82747 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15 |
82748 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a |
82749 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b |
82750 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c |
82751 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d |
82752 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e |
82753 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL |
82754 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L |
82755 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L |
82756 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L |
82757 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L |
82758 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L |
82759 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L |
82760 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L |
82761 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L |
82762 | #define IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L |
82763 | //IOMMU_L2_1_SMMU_MMIO_IDR2_W |
82764 | #define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0 |
82765 | #define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa |
82766 | #define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL |
82767 | #define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L |
82768 | //IOMMU_L2_1_SMMU_MMIO_IDR3_W |
82769 | #define IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2 |
82770 | #define IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L |
82771 | //IOMMU_L2_1_SMMU_MMIO_IDR5_W |
82772 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0 |
82773 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4 |
82774 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5 |
82775 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6 |
82776 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10 |
82777 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L |
82778 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L |
82779 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L |
82780 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L |
82781 | #define IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L |
82782 | //IOMMU_L2_1_SMMU_MMIO_IIDR_W |
82783 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0 |
82784 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc |
82785 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10 |
82786 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14 |
82787 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL |
82788 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L |
82789 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L |
82790 | #define IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L |
82791 | //IOMMU_L2_1_SMMU_AIDR_W |
82792 | #define IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0 |
82793 | #define IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4 |
82794 | #define IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL |
82795 | #define IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L |
82796 | |
82797 | |
82798 | // addressBlock: nbio_iohub_iommu_l2indx_l2indxcfg |
82799 | //L2_STATUS_1 |
82800 | #define L2_STATUS_1__L2STATUS1__SHIFT 0x0 |
82801 | #define L2_STATUS_1__L2STATUS1_MASK 0xFFFFFFFFL |
82802 | //L2_SB_LOCATION |
82803 | #define L2_SB_LOCATION__SBlocated_Port__SHIFT 0x0 |
82804 | #define L2_SB_LOCATION__SBlocated_Core__SHIFT 0x10 |
82805 | #define L2_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL |
82806 | #define L2_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L |
82807 | //L2_CONTROL_5 |
82808 | #define L2_CONTROL_5__QueueArbFBPri__SHIFT 0x0 |
82809 | #define L2_CONTROL_5__FC1Dis__SHIFT 0x2 |
82810 | #define L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT 0x3 |
82811 | #define L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT 0x4 |
82812 | #define L2_CONTROL_5__FC3Dis__SHIFT 0x6 |
82813 | #define L2_CONTROL_5__RESERVED__SHIFT 0x7 |
82814 | #define L2_CONTROL_5__ForceTWonVC7__SHIFT 0xb |
82815 | #define L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT 0xc |
82816 | #define L2_CONTROL_5__PCTRL_hysteresis__SHIFT 0x13 |
82817 | #define L2_CONTROL_5__DTCUpdatePri__SHIFT 0x19 |
82818 | #define L2_CONTROL_5__QueueArbFBPri_MASK 0x00000001L |
82819 | #define L2_CONTROL_5__FC1Dis_MASK 0x00000004L |
82820 | #define L2_CONTROL_5__DTCUpdateVOneIVZero_MASK 0x00000008L |
82821 | #define L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK 0x00000010L |
82822 | #define L2_CONTROL_5__FC3Dis_MASK 0x00000040L |
82823 | #define L2_CONTROL_5__RESERVED_MASK 0x00000780L |
82824 | #define L2_CONTROL_5__ForceTWonVC7_MASK 0x00000800L |
82825 | #define L2_CONTROL_5__GST_partial_ptc_cntrl_MASK 0x0007F000L |
82826 | #define L2_CONTROL_5__PCTRL_hysteresis_MASK 0x01F80000L |
82827 | #define L2_CONTROL_5__DTCUpdatePri_MASK 0x02000000L |
82828 | //L2_CONTROL_6 |
82829 | #define L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT 0x0 |
82830 | #define L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT 0x8 |
82831 | #define L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT 0x10 |
82832 | #define L2_CONTROL_6__Perf2Threshold__SHIFT 0x18 |
82833 | #define L2_CONTROL_6__SeqInvBurstLimitInv_MASK 0x000000FFL |
82834 | #define L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK 0x0000FF00L |
82835 | #define L2_CONTROL_6__SeqInvBurstLimitEn_MASK 0x00010000L |
82836 | #define L2_CONTROL_6__Perf2Threshold_MASK 0xFF000000L |
82837 | //L2_PDC_CONTROL |
82838 | #define L2_PDC_CONTROL__RESERVED__SHIFT 0x0 |
82839 | #define L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT 0x3 |
82840 | #define L2_PDC_CONTROL__PDCParityEn__SHIFT 0x4 |
82841 | #define L2_PDC_CONTROL__PDCInvalidationSel__SHIFT 0x8 |
82842 | #define L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT 0xa |
82843 | #define L2_PDC_CONTROL__PDCSearchDirection__SHIFT 0xc |
82844 | #define L2_PDC_CONTROL__PDCBypass__SHIFT 0xd |
82845 | #define L2_PDC_CONTROL__PDCParitySupport__SHIFT 0xf |
82846 | #define L2_PDC_CONTROL__PDCWays__SHIFT 0x10 |
82847 | #define L2_PDC_CONTROL__PDCEntries__SHIFT 0x1c |
82848 | #define L2_PDC_CONTROL__RESERVED_MASK 0x00000003L |
82849 | #define L2_PDC_CONTROL__PDCLRUUpdatePri_MASK 0x00000008L |
82850 | #define L2_PDC_CONTROL__PDCParityEn_MASK 0x00000010L |
82851 | #define L2_PDC_CONTROL__PDCInvalidationSel_MASK 0x00000300L |
82852 | #define L2_PDC_CONTROL__PDCSoftInvalidate_MASK 0x00000400L |
82853 | #define L2_PDC_CONTROL__PDCSearchDirection_MASK 0x00001000L |
82854 | #define L2_PDC_CONTROL__PDCBypass_MASK 0x00002000L |
82855 | #define L2_PDC_CONTROL__PDCParitySupport_MASK 0x00008000L |
82856 | #define L2_PDC_CONTROL__PDCWays_MASK 0x00FF0000L |
82857 | #define L2_PDC_CONTROL__PDCEntries_MASK 0xF0000000L |
82858 | //L2_PDC_HASH_CONTROL |
82859 | #define L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT 0x10 |
82860 | #define L2_PDC_HASH_CONTROL__PDCAddressMask_MASK 0xFFFF0000L |
82861 | //L2_PDC_WAY_CONTROL |
82862 | #define L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT 0x0 |
82863 | #define L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT 0x10 |
82864 | #define L2_PDC_WAY_CONTROL__PDCWayDisable_MASK 0x0000FFFFL |
82865 | #define L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK 0xFFFF0000L |
82866 | //L2B_UPDATE_FILTER_CNTL |
82867 | #define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT 0x0 |
82868 | #define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT 0x1 |
82869 | #define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK 0x00000001L |
82870 | #define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK 0x0000001EL |
82871 | //L2_TW_CONTROL |
82872 | #define L2_TW_CONTROL__RESERVED__SHIFT 0x0 |
82873 | #define L2_TW_CONTROL__TWForceCoherent__SHIFT 0x6 |
82874 | #define L2_TW_CONTROL__TWPrefetchEn__SHIFT 0x8 |
82875 | #define L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT 0x9 |
82876 | #define L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT 0xa |
82877 | #define L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT 0xb |
82878 | #define L2_TW_CONTROL__TWPrefetchRange__SHIFT 0xc |
82879 | #define L2_TW_CONTROL__TWFilter_Dis__SHIFT 0x10 |
82880 | #define L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT 0x11 |
82881 | #define L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT 0x12 |
82882 | #define L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT 0x13 |
82883 | #define L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT 0x14 |
82884 | #define L2_TW_CONTROL__TWGuestPrefetchEn__SHIFT 0x15 |
82885 | #define L2_TW_CONTROL__TWGuestPrefetchRange__SHIFT 0x16 |
82886 | #define L2_TW_CONTROL__RESERVED_MASK 0x0000003FL |
82887 | #define L2_TW_CONTROL__TWForceCoherent_MASK 0x00000040L |
82888 | #define L2_TW_CONTROL__TWPrefetchEn_MASK 0x00000100L |
82889 | #define L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK 0x00000200L |
82890 | #define L2_TW_CONTROL__TWPTEOnUntransExcl_MASK 0x00000400L |
82891 | #define L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK 0x00000800L |
82892 | #define L2_TW_CONTROL__TWPrefetchRange_MASK 0x00007000L |
82893 | #define L2_TW_CONTROL__TWFilter_Dis_MASK 0x00010000L |
82894 | #define L2_TW_CONTROL__TWFilter_64B_Dis_MASK 0x00020000L |
82895 | #define L2_TW_CONTROL__TWContWalkOnPErrDis_MASK 0x00040000L |
82896 | #define L2_TW_CONTROL__TWSetAccessBit_Dis_MASK 0x00080000L |
82897 | #define L2_TW_CONTROL__TWClearAPBit_Dis_MASK 0x00100000L |
82898 | #define L2_TW_CONTROL__TWGuestPrefetchEn_MASK 0x00200000L |
82899 | #define L2_TW_CONTROL__TWGuestPrefetchRange_MASK 0x01C00000L |
82900 | //L2_CP_CONTROL |
82901 | #define L2_CP_CONTROL__CPPrefetchDis__SHIFT 0x0 |
82902 | #define L2_CP_CONTROL__CPFlushOnWait__SHIFT 0x1 |
82903 | #define L2_CP_CONTROL__CPFlushOnInv__SHIFT 0x2 |
82904 | #define L2_CP_CONTROL__CPRdDelay__SHIFT 0x10 |
82905 | #define L2_CP_CONTROL__CPPrefetchDis_MASK 0x00000001L |
82906 | #define L2_CP_CONTROL__CPFlushOnWait_MASK 0x00000002L |
82907 | #define L2_CP_CONTROL__CPFlushOnInv_MASK 0x00000004L |
82908 | #define L2_CP_CONTROL__CPRdDelay_MASK 0xFFFF0000L |
82909 | //L2_CP_CONTROL_1 |
82910 | #define L2_CP_CONTROL_1__CPL1Off__SHIFT 0x0 |
82911 | #define L2_CP_CONTROL_1__Reserved__SHIFT 0x10 |
82912 | #define L2_CP_CONTROL_1__CPL1Off_MASK 0x0000FFFFL |
82913 | #define L2_CP_CONTROL_1__Reserved_MASK 0xFFFF0000L |
82914 | //IOMMU_L2_GUEST_ADDR_CNTRL |
82915 | #define IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK__SHIFT 0x0 |
82916 | #define IOMMU_L2_GUEST_ADDR_CNTRL__Reserved__SHIFT 0x18 |
82917 | #define IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK_MASK 0x00FFFFFFL |
82918 | #define IOMMU_L2_GUEST_ADDR_CNTRL__Reserved_MASK 0xFF000000L |
82919 | //L2_TW_CONTROL_1 |
82920 | #define L2_TW_CONTROL_1__TWDebugEn__SHIFT 0x0 |
82921 | #define L2_TW_CONTROL_1__TWDebugNoWrap__SHIFT 0x1 |
82922 | #define L2_TW_CONTROL_1__TWDebugForceDisable__SHIFT 0x2 |
82923 | #define L2_TW_CONTROL_1__TWDebugMask__SHIFT 0xf |
82924 | #define L2_TW_CONTROL_1__TWDebugEn_MASK 0x00000001L |
82925 | #define L2_TW_CONTROL_1__TWDebugNoWrap_MASK 0x00000002L |
82926 | #define L2_TW_CONTROL_1__TWDebugForceDisable_MASK 0x00000004L |
82927 | #define L2_TW_CONTROL_1__TWDebugMask_MASK 0xFFFF8000L |
82928 | //L2_TW_CONTROL_2 |
82929 | #define L2_TW_CONTROL_2__TWDebugAddrLo__SHIFT 0xc |
82930 | #define L2_TW_CONTROL_2__TWDebugAddrLo_MASK 0xFFFFF000L |
82931 | //L2_TW_CONTROL_3 |
82932 | #define L2_TW_CONTROL_3__TWDebugAddrHi__SHIFT 0x0 |
82933 | #define L2_TW_CONTROL_3__TWDebugAddrHi_MASK 0xFFFFFFFFL |
82934 | //L2_CREDIT_CONTROL_0 |
82935 | #define L2_CREDIT_CONTROL_0__FC1Credits__SHIFT 0x0 |
82936 | #define L2_CREDIT_CONTROL_0__FC1Override__SHIFT 0x7 |
82937 | #define L2_CREDIT_CONTROL_0__FC2Credits__SHIFT 0x8 |
82938 | #define L2_CREDIT_CONTROL_0__FC2Override__SHIFT 0xe |
82939 | #define L2_CREDIT_CONTROL_0__FC3Credits__SHIFT 0xf |
82940 | #define L2_CREDIT_CONTROL_0__FC3Override__SHIFT 0x15 |
82941 | #define L2_CREDIT_CONTROL_0__MultATSCredits__SHIFT 0x16 |
82942 | #define L2_CREDIT_CONTROL_0__FC1Credits_MASK 0x0000007FL |
82943 | #define L2_CREDIT_CONTROL_0__FC1Override_MASK 0x00000080L |
82944 | #define L2_CREDIT_CONTROL_0__FC2Credits_MASK 0x00003F00L |
82945 | #define L2_CREDIT_CONTROL_0__FC2Override_MASK 0x00004000L |
82946 | #define L2_CREDIT_CONTROL_0__FC3Credits_MASK 0x001F8000L |
82947 | #define L2_CREDIT_CONTROL_0__FC3Override_MASK 0x00200000L |
82948 | #define L2_CREDIT_CONTROL_0__MultATSCredits_MASK 0xFFC00000L |
82949 | //L2_CREDIT_CONTROL_1 |
82950 | #define L2_CREDIT_CONTROL_1__PDTIECredits__SHIFT 0x0 |
82951 | #define L2_CREDIT_CONTROL_1__RESERVED__SHIFT 0x7 |
82952 | #define L2_CREDIT_CONTROL_1__TWELCredits__SHIFT 0x8 |
82953 | #define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT 0x10 |
82954 | #define L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT 0x14 |
82955 | #define L2_CREDIT_CONTROL_1__PDTIECredits_MASK 0x0000003FL |
82956 | #define L2_CREDIT_CONTROL_1__RESERVED_MASK 0x00000080L |
82957 | #define L2_CREDIT_CONTROL_1__TWELCredits_MASK 0x00003F00L |
82958 | #define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK 0x000F0000L |
82959 | #define L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK 0x00F00000L |
82960 | //L2_ERR_RULE_CONTROL_0 |
82961 | #define L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT 0x0 |
82962 | #define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT 0x4 |
82963 | #define L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK 0x00000001L |
82964 | #define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK 0xFFFFFFF0L |
82965 | //L2_ERR_RULE_CONTROL_1 |
82966 | #define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT 0x0 |
82967 | #define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK 0xFFFFFFFFL |
82968 | //L2_ERR_RULE_CONTROL_2 |
82969 | #define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT 0x0 |
82970 | #define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK 0xFFFFFFFFL |
82971 | //L2_L2B_CK_GATE_CONTROL |
82972 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT 0x0 |
82973 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT 0x1 |
82974 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT 0x2 |
82975 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT 0x3 |
82976 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT 0x4 |
82977 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT 0x6 |
82978 | #define L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT 0x8 |
82979 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK 0x00000001L |
82980 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK 0x00000002L |
82981 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK 0x00000004L |
82982 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK 0x00000008L |
82983 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK 0x00000030L |
82984 | #define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK 0x000000C0L |
82985 | #define L2_L2B_CK_GATE_CONTROL__Reserved_MASK 0xFFFFFF00L |
82986 | //PPR_CONTROL |
82987 | #define PPR_CONTROL__PPR_IntTimeDelay__SHIFT 0x0 |
82988 | #define PPR_CONTROL__PPR_IntReqDelay__SHIFT 0x8 |
82989 | #define PPR_CONTROL__PPR_IntCoallesce_En__SHIFT 0x10 |
82990 | #define PPR_CONTROL__Reserved__SHIFT 0x11 |
82991 | #define PPR_CONTROL__PPR_IntTimeDelay_MASK 0x000000FFL |
82992 | #define PPR_CONTROL__PPR_IntReqDelay_MASK 0x0000FF00L |
82993 | #define PPR_CONTROL__PPR_IntCoallesce_En_MASK 0x00010000L |
82994 | #define PPR_CONTROL__Reserved_MASK 0xFFFE0000L |
82995 | //L2_L2B_PGSIZE_CONTROL |
82996 | #define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT 0x0 |
82997 | #define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT 0x8 |
82998 | #define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK 0x0000007FL |
82999 | #define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK 0x00007F00L |
83000 | //L2_L2B_MEMPWR_GATE_1 |
83001 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_LS_EN__SHIFT 0x0 |
83002 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_DS_EN__SHIFT 0x1 |
83003 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_SD_EN__SHIFT 0x2 |
83004 | #define L2_L2B_MEMPWR_GATE_1__L2B_IP_PGMEM_SEL__SHIFT 0x3 |
83005 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_CACHE_PGMEM_SEL__SHIFT 0x4 |
83006 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_LS_EN_MASK 0x00000001L |
83007 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_DS_EN_MASK 0x00000002L |
83008 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_SD_EN_MASK 0x00000004L |
83009 | #define L2_L2B_MEMPWR_GATE_1__L2B_IP_PGMEM_SEL_MASK 0x00000008L |
83010 | #define L2_L2B_MEMPWR_GATE_1__L2BREG_CACHE_PGMEM_SEL_MASK 0x00000010L |
83011 | //L2_L2B_MEMPWR_GATE_2 |
83012 | #define L2_L2B_MEMPWR_GATE_2__L2BREG_LS_thres__SHIFT 0x0 |
83013 | #define L2_L2B_MEMPWR_GATE_2__L2BREG_LS_thres_MASK 0xFFFFFFFFL |
83014 | //L2_L2B_MEMPWR_GATE_3 |
83015 | #define L2_L2B_MEMPWR_GATE_3__L2BREG_DS_thres__SHIFT 0x0 |
83016 | #define L2_L2B_MEMPWR_GATE_3__L2BREG_DS_thres_MASK 0xFFFFFFFFL |
83017 | //L2_L2B_MEMPWR_GATE_4 |
83018 | #define L2_L2B_MEMPWR_GATE_4__L2BREG_SD_thres__SHIFT 0x0 |
83019 | #define L2_L2B_MEMPWR_GATE_4__L2BREG_SD_thres_MASK 0xFFFFFFFFL |
83020 | //L2_PERF_CNTL_2 |
83021 | #define L2_PERF_CNTL_2__L2PerfEvent4__SHIFT 0x0 |
83022 | #define L2_PERF_CNTL_2__L2PerfEvent5__SHIFT 0x8 |
83023 | #define L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT 0x10 |
83024 | #define L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT 0x18 |
83025 | #define L2_PERF_CNTL_2__L2PerfEvent4_MASK 0x000000FFL |
83026 | #define L2_PERF_CNTL_2__L2PerfEvent5_MASK 0x0000FF00L |
83027 | #define L2_PERF_CNTL_2__L2PerfCountUpper4_MASK 0x00FF0000L |
83028 | #define L2_PERF_CNTL_2__L2PerfCountUpper5_MASK 0xFF000000L |
83029 | //L2_PERF_COUNT_4 |
83030 | #define L2_PERF_COUNT_4__L2PerfCount4__SHIFT 0x0 |
83031 | #define L2_PERF_COUNT_4__L2PerfCount4_MASK 0xFFFFFFFFL |
83032 | //L2_PERF_COUNT_5 |
83033 | #define L2_PERF_COUNT_5__L2PerfCount5__SHIFT 0x0 |
83034 | #define L2_PERF_COUNT_5__L2PerfCount5_MASK 0xFFFFFFFFL |
83035 | //L2_PERF_CNTL_3 |
83036 | #define L2_PERF_CNTL_3__L2PerfEvent6__SHIFT 0x0 |
83037 | #define L2_PERF_CNTL_3__L2PerfEvent7__SHIFT 0x8 |
83038 | #define L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT 0x10 |
83039 | #define L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT 0x18 |
83040 | #define L2_PERF_CNTL_3__L2PerfEvent6_MASK 0x000000FFL |
83041 | #define L2_PERF_CNTL_3__L2PerfEvent7_MASK 0x0000FF00L |
83042 | #define L2_PERF_CNTL_3__L2PerfCountUpper6_MASK 0x00FF0000L |
83043 | #define L2_PERF_CNTL_3__L2PerfCountUpper7_MASK 0xFF000000L |
83044 | //L2_PERF_COUNT_6 |
83045 | #define L2_PERF_COUNT_6__L2PerfCount6__SHIFT 0x0 |
83046 | #define L2_PERF_COUNT_6__L2PerfCount6_MASK 0xFFFFFFFFL |
83047 | //L2_PERF_COUNT_7 |
83048 | #define L2_PERF_COUNT_7__L2PerfCount7__SHIFT 0x0 |
83049 | #define L2_PERF_COUNT_7__L2PerfCount7_MASK 0xFFFFFFFFL |
83050 | //L2_L2B_DVM_CTRL_0 |
83051 | #define L2_L2B_DVM_CTRL_0__DVM_INTGFX_REQID__SHIFT 0x0 |
83052 | #define L2_L2B_DVM_CTRL_0__DVM_INTGFX_QUEUEID__SHIFT 0x10 |
83053 | #define L2_L2B_DVM_CTRL_0__DVM_INTGFX_REQID_MASK 0x0000FFFFL |
83054 | #define L2_L2B_DVM_CTRL_0__DVM_INTGFX_QUEUEID_MASK 0xFFFF0000L |
83055 | //L2_L2B_DVM_CTRL_1 |
83056 | #define L2_L2B_DVM_CTRL_1__DVM_INTGFX_MAXPEND__SHIFT 0x0 |
83057 | #define L2_L2B_DVM_CTRL_1__DVM_IOTLB_INV_PGSIZE__SHIFT 0x8 |
83058 | #define L2_L2B_DVM_CTRL_1__DVM_TLB_INV_PGSIZE__SHIFT 0xb |
83059 | #define L2_L2B_DVM_CTRL_1__DVM_V1_Disable__SHIFT 0xe |
83060 | #define L2_L2B_DVM_CTRL_1__DVM_REMAP_TYPE__SHIFT 0xf |
83061 | #define L2_L2B_DVM_CTRL_1__DVM_INTGFX_MAXPEND_MASK 0x000000FFL |
83062 | #define L2_L2B_DVM_CTRL_1__DVM_IOTLB_INV_PGSIZE_MASK 0x00000700L |
83063 | #define L2_L2B_DVM_CTRL_1__DVM_TLB_INV_PGSIZE_MASK 0x00003800L |
83064 | #define L2_L2B_DVM_CTRL_1__DVM_V1_Disable_MASK 0x00004000L |
83065 | #define L2_L2B_DVM_CTRL_1__DVM_REMAP_TYPE_MASK 0x00FF8000L |
83066 | //L2B_SDP_MAXCRED |
83067 | #define L2B_SDP_MAXCRED__L2B_RDRSP_MAXCRED__SHIFT 0x0 |
83068 | #define L2B_SDP_MAXCRED__L2B_WRRSP_MAXCRED__SHIFT 0xc |
83069 | #define L2B_SDP_MAXCRED__L2B_REQ_MAXCRED__SHIFT 0x14 |
83070 | #define L2B_SDP_MAXCRED__L2B_DATA_MAXCRED__SHIFT 0x18 |
83071 | #define L2B_SDP_MAXCRED__L2B_RDRSP_MAXCRED_MASK 0x00000FFFL |
83072 | #define L2B_SDP_MAXCRED__L2B_WRRSP_MAXCRED_MASK 0x000FF000L |
83073 | #define L2B_SDP_MAXCRED__L2B_REQ_MAXCRED_MASK 0x00F00000L |
83074 | #define L2B_SDP_MAXCRED__L2B_DATA_MAXCRED_MASK 0x0F000000L |
83075 | //L2B_SDP_PARITY_ERROR_EN |
83076 | #define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT 0x0 |
83077 | #define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT 0x1 |
83078 | #define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT 0x2 |
83079 | #define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK 0x00000001L |
83080 | #define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK 0x00000002L |
83081 | #define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK 0x00000004L |
83082 | //L2_ECO_CNTRL_1 |
83083 | #define L2_ECO_CNTRL_1__L2_ECO_1__SHIFT 0x0 |
83084 | #define L2_ECO_CNTRL_1__L2_ECO_1_MASK 0xFFFFFFFFL |
83085 | //L2_L2B_MEMPWR_GATE_5 |
83086 | #define L2_L2B_MEMPWR_GATE_5__L2BREG_LS_Req_Maintain_Cnt__SHIFT 0x0 |
83087 | #define L2_L2B_MEMPWR_GATE_5__L2BREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
83088 | //L2_L2B_MEMPWR_GATE_6 |
83089 | #define L2_L2B_MEMPWR_GATE_6__L2BREG_LS_Exit_Maintain_Cnt__SHIFT 0x0 |
83090 | #define L2_L2B_MEMPWR_GATE_6__L2BREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
83091 | //L2_L2B_MEMPWR_GATE_7 |
83092 | #define L2_L2B_MEMPWR_GATE_7__L2BREG_DS_Req_Maintain_Cnt__SHIFT 0x0 |
83093 | #define L2_L2B_MEMPWR_GATE_7__L2BREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
83094 | //L2_L2B_MEMPWR_GATE_8 |
83095 | #define L2_L2B_MEMPWR_GATE_8__L2BREG_DS_Exit_Maintain_Cnt__SHIFT 0x0 |
83096 | #define L2_L2B_MEMPWR_GATE_8__L2BREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
83097 | //L2_L2B_MEMPWR_GATE_9 |
83098 | #define L2_L2B_MEMPWR_GATE_9__L2BREG_SD_Req_Maintain_Cnt__SHIFT 0x0 |
83099 | #define L2_L2B_MEMPWR_GATE_9__L2BREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
83100 | //L2_L2B_MEMPWR_GATE_10 |
83101 | #define L2_L2B_MEMPWR_GATE_10__L2BREG_SD_Exit_Maintain_Cnt__SHIFT 0x0 |
83102 | #define L2_L2B_MEMPWR_GATE_10__L2BREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
83103 | |
83104 | |
83105 | // addressBlock: nbio_iohub_iommu_l2bshdw_l2bshdw |
83106 | //SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY |
83107 | #define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SECONDARY_BUS__SHIFT 0x8 |
83108 | #define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SUB_BUS_NUM__SHIFT 0x10 |
83109 | #define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SECONDARY_BUS_MASK 0x0000FF00L |
83110 | #define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SUB_BUS_NUM_MASK 0x00FF0000L |
83111 | //SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY |
83112 | #define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SECONDARY_BUS__SHIFT 0x8 |
83113 | #define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SUB_BUS_NUM__SHIFT 0x10 |
83114 | #define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SECONDARY_BUS_MASK 0x0000FF00L |
83115 | #define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SUB_BUS_NUM_MASK 0x00FF0000L |
83116 | //SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY |
83117 | #define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SECONDARY_BUS__SHIFT 0x8 |
83118 | #define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SUB_BUS_NUM__SHIFT 0x10 |
83119 | #define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SECONDARY_BUS_MASK 0x0000FF00L |
83120 | #define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SUB_BUS_NUM_MASK 0x00FF0000L |
83121 | //SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY |
83122 | #define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SECONDARY_BUS__SHIFT 0x8 |
83123 | #define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SUB_BUS_NUM__SHIFT 0x10 |
83124 | #define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SECONDARY_BUS_MASK 0x0000FF00L |
83125 | #define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SUB_BUS_NUM_MASK 0x00FF0000L |
83126 | //SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY |
83127 | #define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SECONDARY_BUS__SHIFT 0x8 |
83128 | #define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SUB_BUS_NUM__SHIFT 0x10 |
83129 | #define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SECONDARY_BUS_MASK 0x0000FF00L |
83130 | #define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SUB_BUS_NUM_MASK 0x00FF0000L |
83131 | //SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY |
83132 | #define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SECONDARY_BUS__SHIFT 0x8 |
83133 | #define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SUB_BUS_NUM__SHIFT 0x10 |
83134 | #define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SECONDARY_BUS_MASK 0x0000FF00L |
83135 | #define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SUB_BUS_NUM_MASK 0x00FF0000L |
83136 | //SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY |
83137 | #define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SECONDARY_BUS__SHIFT 0x8 |
83138 | #define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SUB_BUS_NUM__SHIFT 0x10 |
83139 | #define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SECONDARY_BUS_MASK 0x0000FF00L |
83140 | #define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SUB_BUS_NUM_MASK 0x00FF0000L |
83141 | //SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY |
83142 | #define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SECONDARY_BUS__SHIFT 0x8 |
83143 | #define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SUB_BUS_NUM__SHIFT 0x10 |
83144 | #define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SECONDARY_BUS_MASK 0x0000FF00L |
83145 | #define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SUB_BUS_NUM_MASK 0x00FF0000L |
83146 | //SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY |
83147 | #define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SECONDARY_BUS__SHIFT 0x8 |
83148 | #define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SUB_BUS_NUM__SHIFT 0x10 |
83149 | #define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SECONDARY_BUS_MASK 0x0000FF00L |
83150 | #define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SUB_BUS_NUM_MASK 0x00FF0000L |
83151 | //SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY |
83152 | #define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SECONDARY_BUS__SHIFT 0x8 |
83153 | #define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SUB_BUS_NUM__SHIFT 0x10 |
83154 | #define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SECONDARY_BUS_MASK 0x0000FF00L |
83155 | #define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SUB_BUS_NUM_MASK 0x00FF0000L |
83156 | |
83157 | |
83158 | // addressBlock: nbio_iohub_iommu_l2bpsp_l2bpsp |
83159 | //L2BPSP_ERR_REP_ENABLE |
83160 | #define L2BPSP_ERR_REP_ENABLE__HE_SUP__SHIFT 0x0 |
83161 | #define L2BPSP_ERR_REP_ENABLE__Reserved__SHIFT 0x1 |
83162 | #define L2BPSP_ERR_REP_ENABLE__HE_SUP_MASK 0x00000001L |
83163 | #define L2BPSP_ERR_REP_ENABLE__Reserved_MASK 0xFFFFFFFEL |
83164 | //L2BPSP_HW_ERR_STATUS_0 |
83165 | #define L2BPSP_HW_ERR_STATUS_0__HEV__SHIFT 0x0 |
83166 | #define L2BPSP_HW_ERR_STATUS_0__HEO__SHIFT 0x1 |
83167 | #define L2BPSP_HW_ERR_STATUS_0__Reserved__SHIFT 0x3 |
83168 | #define L2BPSP_HW_ERR_STATUS_0__HEV_MASK 0x00000001L |
83169 | #define L2BPSP_HW_ERR_STATUS_0__HEO_MASK 0x00000002L |
83170 | #define L2BPSP_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFF8L |
83171 | //L2BPSP_HW_ERR_STATUS_1 |
83172 | #define L2BPSP_HW_ERR_STATUS_1__Reserved__SHIFT 0x0 |
83173 | #define L2BPSP_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL |
83174 | //L2BPSP_HW_ERR_LOWER_0 |
83175 | #define L2BPSP_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0 |
83176 | #define L2BPSP_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL |
83177 | //L2BPSP_HW_ERR_LOWER_1 |
83178 | #define L2BPSP_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0 |
83179 | #define L2BPSP_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL |
83180 | //L2BPSP_HW_ERR_UPPER_0 |
83181 | #define L2BPSP_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0 |
83182 | #define L2BPSP_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL |
83183 | //L2BPSP_HW_ERR_UPPER_1 |
83184 | #define L2BPSP_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0 |
83185 | #define L2BPSP_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c |
83186 | #define L2BPSP_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL |
83187 | #define L2BPSP_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L |
83188 | |
83189 | |
83190 | // addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec |
83191 | //FEATURES_ENABLE |
83192 | #define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT 0x2 |
83193 | #define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT 0x4 |
83194 | #define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT 0x5 |
83195 | #define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT 0x8 |
83196 | #define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT 0x9 |
83197 | #define FEATURES_ENABLE__Ioapic_id_ext_en_MASK 0x00000004L |
83198 | #define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK 0x00000010L |
83199 | #define FEATURES_ENABLE__Ioapic_secondary_en_MASK 0x00000020L |
83200 | #define FEATURES_ENABLE__Ioapic_processor_mode_MASK 0x00000100L |
83201 | #define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK 0x00000200L |
83202 | //IOAPIC_BR0_INTERRUPT_ROUTING |
83203 | #define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp__SHIFT 0x0 |
83204 | #define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz__SHIFT 0x4 |
83205 | #define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map__SHIFT 0x10 |
83206 | #define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp_MASK 0x00000007L |
83207 | #define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz_MASK 0x00000030L |
83208 | #define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map_MASK 0x001F0000L |
83209 | //IOAPIC_BR1_INTERRUPT_ROUTING |
83210 | #define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp__SHIFT 0x0 |
83211 | #define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz__SHIFT 0x4 |
83212 | #define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map__SHIFT 0x10 |
83213 | #define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp_MASK 0x00000007L |
83214 | #define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz_MASK 0x00000030L |
83215 | #define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map_MASK 0x001F0000L |
83216 | //IOAPIC_BR2_INTERRUPT_ROUTING |
83217 | #define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp__SHIFT 0x0 |
83218 | #define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz__SHIFT 0x4 |
83219 | #define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map__SHIFT 0x10 |
83220 | #define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp_MASK 0x00000007L |
83221 | #define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz_MASK 0x00000030L |
83222 | #define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map_MASK 0x001F0000L |
83223 | //IOAPIC_BR3_INTERRUPT_ROUTING |
83224 | #define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp__SHIFT 0x0 |
83225 | #define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz__SHIFT 0x4 |
83226 | #define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map__SHIFT 0x10 |
83227 | #define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp_MASK 0x00000007L |
83228 | #define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz_MASK 0x00000030L |
83229 | #define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map_MASK 0x001F0000L |
83230 | //IOAPIC_BR4_INTERRUPT_ROUTING |
83231 | #define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp__SHIFT 0x0 |
83232 | #define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz__SHIFT 0x4 |
83233 | #define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map__SHIFT 0x10 |
83234 | #define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp_MASK 0x00000007L |
83235 | #define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz_MASK 0x00000030L |
83236 | #define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map_MASK 0x001F0000L |
83237 | //IOAPIC_BR5_INTERRUPT_ROUTING |
83238 | #define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp__SHIFT 0x0 |
83239 | #define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz__SHIFT 0x4 |
83240 | #define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map__SHIFT 0x10 |
83241 | #define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp_MASK 0x00000007L |
83242 | #define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz_MASK 0x00000030L |
83243 | #define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map_MASK 0x001F0000L |
83244 | //IOAPIC_BR6_INTERRUPT_ROUTING |
83245 | #define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp__SHIFT 0x0 |
83246 | #define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz__SHIFT 0x4 |
83247 | #define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map__SHIFT 0x10 |
83248 | #define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp_MASK 0x00000007L |
83249 | #define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz_MASK 0x00000030L |
83250 | #define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map_MASK 0x001F0000L |
83251 | //IOAPIC_BR7_INTERRUPT_ROUTING |
83252 | #define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp__SHIFT 0x0 |
83253 | #define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz__SHIFT 0x4 |
83254 | #define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map__SHIFT 0x10 |
83255 | #define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp_MASK 0x00000007L |
83256 | #define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz_MASK 0x00000030L |
83257 | #define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map_MASK 0x001F0000L |
83258 | //IOAPIC_BR8_INTERRUPT_ROUTING |
83259 | #define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp__SHIFT 0x0 |
83260 | #define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz__SHIFT 0x4 |
83261 | #define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map__SHIFT 0x10 |
83262 | #define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp_MASK 0x00000007L |
83263 | #define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz_MASK 0x00000030L |
83264 | #define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map_MASK 0x001F0000L |
83265 | //IOAPIC_SERIAL_IRQ_STATUS |
83266 | #define IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts__SHIFT 0x0 |
83267 | #define IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts_MASK 0xFFFFFFFFL |
83268 | //IOAPIC_SCRATCH_0 |
83269 | #define IOAPIC_SCRATCH_0__Scratch_0__SHIFT 0x0 |
83270 | #define IOAPIC_SCRATCH_0__Scratch_0_MASK 0xFFFFFFFFL |
83271 | //IOAPIC_SCRATCH_1 |
83272 | #define IOAPIC_SCRATCH_1__Scratch_1__SHIFT 0x0 |
83273 | #define IOAPIC_SCRATCH_1__Scratch_1_MASK 0xFFFFFFFFL |
83274 | //IOAPIC_GLUE_CG_LCLK_CTRL_0 |
83275 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4 |
83276 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16 |
83277 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17 |
83278 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18 |
83279 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19 |
83280 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a |
83281 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b |
83282 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c |
83283 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d |
83284 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e |
83285 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f |
83286 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L |
83287 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L |
83288 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L |
83289 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L |
83290 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L |
83291 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L |
83292 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L |
83293 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L |
83294 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L |
83295 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L |
83296 | #define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L |
83297 | //IOAPIC_SDP_PORT_CONTROL |
83298 | #define IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0 |
83299 | #define IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL |
83300 | //IOAPIC_PERF_CNTL |
83301 | #define IOAPIC_PERF_CNTL__EVENT0_SEL__SHIFT 0x0 |
83302 | #define IOAPIC_PERF_CNTL__EVENT1_SEL__SHIFT 0x8 |
83303 | #define IOAPIC_PERF_CNTL__EVENT2_SEL__SHIFT 0x10 |
83304 | #define IOAPIC_PERF_CNTL__EVENT3_SEL__SHIFT 0x18 |
83305 | #define IOAPIC_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL |
83306 | #define IOAPIC_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L |
83307 | #define IOAPIC_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L |
83308 | #define IOAPIC_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L |
83309 | //IOAPIC_PERF_COUNT0 |
83310 | #define IOAPIC_PERF_COUNT0__COUNTER0__SHIFT 0x0 |
83311 | #define IOAPIC_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL |
83312 | //IOAPIC_PERF_COUNT0_UPPER |
83313 | #define IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0 |
83314 | #define IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL |
83315 | //IOAPIC_PERF_COUNT1 |
83316 | #define IOAPIC_PERF_COUNT1__COUNTER1__SHIFT 0x0 |
83317 | #define IOAPIC_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL |
83318 | //IOAPIC_PERF_COUNT1_UPPER |
83319 | #define IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0 |
83320 | #define IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL |
83321 | //IOAPIC_PERF_COUNT2 |
83322 | #define IOAPIC_PERF_COUNT2__COUNTER2__SHIFT 0x0 |
83323 | #define IOAPIC_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL |
83324 | //IOAPIC_PERF_COUNT2_UPPER |
83325 | #define IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0 |
83326 | #define IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL |
83327 | //IOAPIC_PERF_COUNT3 |
83328 | #define IOAPIC_PERF_COUNT3__COUNTER3__SHIFT 0x0 |
83329 | #define IOAPIC_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL |
83330 | //IOAPIC_PERF_COUNT3_UPPER |
83331 | #define IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0 |
83332 | #define IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL |
83333 | //IOAPIC_PGSLV_CONTROL |
83334 | #define IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis__SHIFT 0x0 |
83335 | #define IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis_MASK 0x0000001FL |
83336 | |
83337 | |
83338 | // addressBlock: nbio_iohub_nb_ioapicshdw_ioapic_shdwdec |
83339 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0 |
83340 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0 |
83341 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL |
83342 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1 |
83343 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0 |
83344 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL |
83345 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2 |
83346 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0 |
83347 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL |
83348 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3 |
83349 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0 |
83350 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL |
83351 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4 |
83352 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0 |
83353 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL |
83354 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5 |
83355 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0 |
83356 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL |
83357 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6 |
83358 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0 |
83359 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL |
83360 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7 |
83361 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0 |
83362 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL |
83363 | //IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8 |
83364 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0 |
83365 | #define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL |
83366 | |
83367 | |
83368 | // addressBlock: nbio_iohub_iommu_l1_PCIE0_iommul1cfg |
83369 | //IOMMU_L1_PCIE0_L1_PERF_CNTL |
83370 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT 0x0 |
83371 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT 0x8 |
83372 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT 0x10 |
83373 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT 0x18 |
83374 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0_MASK 0x000000FFL |
83375 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1_MASK 0x0000FF00L |
83376 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK 0x00FF0000L |
83377 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK 0xFF000000L |
83378 | //IOMMU_L1_PCIE0_L1_PERF_COUNT_0 |
83379 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT 0x0 |
83380 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK 0xFFFFFFFFL |
83381 | //IOMMU_L1_PCIE0_L1_PERF_COUNT_1 |
83382 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT 0x0 |
83383 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK 0xFFFFFFFFL |
83384 | //IOMMU_L1_PCIE0_L1_PERF_CNTL_B |
83385 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT 0x0 |
83386 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT 0x8 |
83387 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT 0x10 |
83388 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT 0x18 |
83389 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK 0x000000FFL |
83390 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK 0x0000FF00L |
83391 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK 0x00FF0000L |
83392 | #define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK 0xFF000000L |
83393 | //IOMMU_L1_PCIE0_L1_PERF_COUNT_B0 |
83394 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT 0x0 |
83395 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK 0xFFFFFFFFL |
83396 | //IOMMU_L1_PCIE0_L1_PERF_COUNT_B1 |
83397 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT 0x0 |
83398 | #define IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK 0xFFFFFFFFL |
83399 | //IOMMU_L1_PCIE0_L1_SB_LOCATION |
83400 | #define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port__SHIFT 0x0 |
83401 | #define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core__SHIFT 0x10 |
83402 | #define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL |
83403 | #define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L |
83404 | //IOMMU_L1_PCIE0_L1_CNTRL_0 |
83405 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis__SHIFT 0x0 |
83406 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis__SHIFT 0x1 |
83407 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only__SHIFT 0x2 |
83408 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only__SHIFT 0x3 |
83409 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0__SHIFT 0x4 |
83410 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED__SHIFT 0x5 |
83411 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits__SHIFT 0x8 |
83412 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1__SHIFT 0xe |
83413 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks__SHIFT 0x14 |
83414 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries__SHIFT 0x18 |
83415 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT 0x1c |
83416 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT 0x1d |
83417 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT 0x1f |
83418 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis_MASK 0x00000001L |
83419 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis_MASK 0x00000002L |
83420 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only_MASK 0x00000004L |
83421 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only_MASK 0x00000008L |
83422 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0_MASK 0x00000010L |
83423 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED_MASK 0x00000020L |
83424 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits_MASK 0x00003F00L |
83425 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1_MASK 0x000FC000L |
83426 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks_MASK 0x00300000L |
83427 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries_MASK 0x0F000000L |
83428 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis_MASK 0x10000000L |
83429 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK 0x60000000L |
83430 | #define IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis_MASK 0x80000000L |
83431 | //IOMMU_L1_PCIE0_L1_CNTRL_1 |
83432 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED__SHIFT 0x0 |
83433 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass__SHIFT 0x9 |
83434 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn__SHIFT 0xa |
83435 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn__SHIFT 0xb |
83436 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis__SHIFT 0xc |
83437 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis__SHIFT 0xd |
83438 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis__SHIFT 0x14 |
83439 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en__SHIFT 0x15 |
83440 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn__SHIFT 0x16 |
83441 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse__SHIFT 0x17 |
83442 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT 0x1a |
83443 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT 0x1b |
83444 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT 0x1c |
83445 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT 0x1d |
83446 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT 0x1e |
83447 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT 0x1f |
83448 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED_MASK 0x000001FFL |
83449 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass_MASK 0x00000200L |
83450 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn_MASK 0x00000400L |
83451 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn_MASK 0x00000800L |
83452 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis_MASK 0x00001000L |
83453 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis_MASK 0x000FE000L |
83454 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis_MASK 0x00100000L |
83455 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en_MASK 0x00200000L |
83456 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn_MASK 0x00400000L |
83457 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse_MASK 0x03800000L |
83458 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid_MASK 0x04000000L |
83459 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave_MASK 0x08000000L |
83460 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK 0x10000000L |
83461 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn_MASK 0x20000000L |
83462 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En_MASK 0x40000000L |
83463 | #define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En_MASK 0x80000000L |
83464 | //IOMMU_L1_PCIE0_L1_CNTRL_2 |
83465 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable__SHIFT 0x0 |
83466 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT 0x1 |
83467 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT 0x2 |
83468 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT 0x3 |
83469 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED__SHIFT 0x4 |
83470 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE__SHIFT 0x18 |
83471 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT 0x1b |
83472 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT 0x1c |
83473 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn__SHIFT 0x1d |
83474 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT 0x1e |
83475 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT 0x1f |
83476 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable_MASK 0x00000001L |
83477 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK 0x00000002L |
83478 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis_MASK 0x00000004L |
83479 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK 0x00000008L |
83480 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED_MASK 0x00FFFFF0L |
83481 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE_MASK 0x07000000L |
83482 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK 0x08000000L |
83483 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK 0x10000000L |
83484 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn_MASK 0x20000000L |
83485 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK 0x40000000L |
83486 | #define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK 0x80000000L |
83487 | //IOMMU_L1_PCIE0_L1_CNTRL_3 |
83488 | #define IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT 0x0 |
83489 | #define IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK 0xFFFFFFFFL |
83490 | //IOMMU_L1_PCIE0_L1_BANK_SEL_0 |
83491 | #define IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT 0x0 |
83492 | #define IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0_MASK 0x0000FFFFL |
83493 | //IOMMU_L1_PCIE0_L1_BANK_DISABLE_0 |
83494 | #define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT 0x0 |
83495 | #define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT 0x8 |
83496 | #define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK 0x0000003FL |
83497 | #define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK 0x00003F00L |
83498 | //IOMMU_L1_PCIE0_L1_WQ_STATUS_0 |
83499 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0__SHIFT 0x0 |
83500 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1__SHIFT 0x3 |
83501 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2__SHIFT 0x6 |
83502 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3__SHIFT 0x9 |
83503 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4__SHIFT 0xc |
83504 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5__SHIFT 0xf |
83505 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6__SHIFT 0x12 |
83506 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7__SHIFT 0x15 |
83507 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8__SHIFT 0x18 |
83508 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9__SHIFT 0x1b |
83509 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0_MASK 0x00000007L |
83510 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1_MASK 0x00000038L |
83511 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2_MASK 0x000001C0L |
83512 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3_MASK 0x00000E00L |
83513 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4_MASK 0x00007000L |
83514 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5_MASK 0x00038000L |
83515 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6_MASK 0x001C0000L |
83516 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7_MASK 0x00E00000L |
83517 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8_MASK 0x07000000L |
83518 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9_MASK 0x38000000L |
83519 | //IOMMU_L1_PCIE0_L1_WQ_STATUS_1 |
83520 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10__SHIFT 0x0 |
83521 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11__SHIFT 0x3 |
83522 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12__SHIFT 0x6 |
83523 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13__SHIFT 0x9 |
83524 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14__SHIFT 0xc |
83525 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15__SHIFT 0xf |
83526 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16__SHIFT 0x12 |
83527 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17__SHIFT 0x15 |
83528 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18__SHIFT 0x18 |
83529 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19__SHIFT 0x1b |
83530 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10_MASK 0x00000007L |
83531 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11_MASK 0x00000038L |
83532 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12_MASK 0x000001C0L |
83533 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13_MASK 0x00000E00L |
83534 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14_MASK 0x00007000L |
83535 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15_MASK 0x00038000L |
83536 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16_MASK 0x001C0000L |
83537 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17_MASK 0x00E00000L |
83538 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18_MASK 0x07000000L |
83539 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19_MASK 0x38000000L |
83540 | //IOMMU_L1_PCIE0_L1_WQ_STATUS_2 |
83541 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20__SHIFT 0x0 |
83542 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21__SHIFT 0x3 |
83543 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22__SHIFT 0x6 |
83544 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23__SHIFT 0x9 |
83545 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24__SHIFT 0xc |
83546 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25__SHIFT 0xf |
83547 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26__SHIFT 0x12 |
83548 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27__SHIFT 0x15 |
83549 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28__SHIFT 0x18 |
83550 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29__SHIFT 0x1b |
83551 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20_MASK 0x00000007L |
83552 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21_MASK 0x00000038L |
83553 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22_MASK 0x000001C0L |
83554 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23_MASK 0x00000E00L |
83555 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24_MASK 0x00007000L |
83556 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25_MASK 0x00038000L |
83557 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26_MASK 0x001C0000L |
83558 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27_MASK 0x00E00000L |
83559 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28_MASK 0x07000000L |
83560 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29_MASK 0x38000000L |
83561 | //IOMMU_L1_PCIE0_L1_WQ_STATUS_3 |
83562 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30__SHIFT 0x0 |
83563 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31__SHIFT 0x3 |
83564 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status__SHIFT 0x8 |
83565 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30_MASK 0x00000007L |
83566 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31_MASK 0x00000038L |
83567 | #define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status_MASK 0x0000FF00L |
83568 | //IOMMU_L1_PCIE0_L1_FEATURE_CNTRL |
83569 | #define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT 0x0 |
83570 | #define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved__SHIFT 0x8 |
83571 | #define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK 0x000000FFL |
83572 | #define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved_MASK 0xFFFFFF00L |
83573 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5 |
83574 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT 0x0 |
83575 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
83576 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6 |
83577 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT 0x0 |
83578 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
83579 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7 |
83580 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT 0x0 |
83581 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
83582 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8 |
83583 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT 0x0 |
83584 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
83585 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9 |
83586 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT 0x0 |
83587 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
83588 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10 |
83589 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT 0x0 |
83590 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
83591 | //IOMMU_L1_PCIE0_L1_CNTRL_4 |
83592 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT 0x0 |
83593 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT 0x2 |
83594 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED__SHIFT 0x4 |
83595 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT 0x17 |
83596 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT 0x18 |
83597 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en_MASK 0x00000001L |
83598 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En_MASK 0x00000004L |
83599 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED_MASK 0x007FFFF0L |
83600 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK 0x00800000L |
83601 | #define IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val_MASK 0x7F000000L |
83602 | //IOMMU_L1_PCIE0_L1_CLKCNTRL_0 |
83603 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT 0x4 |
83604 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT 0x5 |
83605 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT 0x6 |
83606 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT 0x8 |
83607 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT 0x9 |
83608 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT 0xa |
83609 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT 0xb |
83610 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT 0xc |
83611 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT 0xd |
83612 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT 0xe |
83613 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved__SHIFT 0x16 |
83614 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT 0x1f |
83615 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK 0x00000010L |
83616 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK 0x00000020L |
83617 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK 0x00000040L |
83618 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK 0x00000100L |
83619 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK 0x00000200L |
83620 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK 0x00000400L |
83621 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK 0x00000800L |
83622 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK 0x00001000L |
83623 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK 0x00002000L |
83624 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK 0x003FC000L |
83625 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved_MASK 0x7FC00000L |
83626 | #define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK 0x80000000L |
83627 | //IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL |
83628 | #define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT 0x0 |
83629 | #define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT 0x1 |
83630 | #define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK 0x00000001L |
83631 | #define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK 0x00000002L |
83632 | //IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL |
83633 | #define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT 0x0 |
83634 | #define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved__SHIFT 0x1 |
83635 | #define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT 0x8 |
83636 | #define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK 0x00000001L |
83637 | #define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved_MASK 0x000000FEL |
83638 | #define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK 0xFFFFFF00L |
83639 | //IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL |
83640 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT 0x0 |
83641 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT 0x1 |
83642 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT 0x2 |
83643 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT 0x4 |
83644 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved__SHIFT 0x5 |
83645 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK 0x00000001L |
83646 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK 0x00000002L |
83647 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK 0x0000000CL |
83648 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK 0x00000010L |
83649 | #define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved_MASK 0xFFFFFFE0L |
83650 | //IOMMU_L1_PCIE0_L1_CNTRL_5 |
83651 | #define IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED__SHIFT 0x0 |
83652 | #define IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED_MASK 0xFFFFFFFFL |
83653 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1 |
83654 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT 0x0 |
83655 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT 0x1 |
83656 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT 0x2 |
83657 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT 0x3 |
83658 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN_MASK 0x00000001L |
83659 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN_MASK 0x00000002L |
83660 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN_MASK 0x00000004L |
83661 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK 0x00000008L |
83662 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2 |
83663 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT 0x0 |
83664 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres_MASK 0xFFFFFFFFL |
83665 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3 |
83666 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT 0x0 |
83667 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres_MASK 0xFFFFFFFFL |
83668 | //IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4 |
83669 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT 0x0 |
83670 | #define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres_MASK 0xFFFFFFFFL |
83671 | //IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL |
83672 | #define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
83673 | #define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT 0x5 |
83674 | #define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
83675 | #define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK 0x00000020L |
83676 | //IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0 |
83677 | #define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT 0x0 |
83678 | #define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT 0x8 |
83679 | #define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT 0x1f |
83680 | #define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK 0x000000FFL |
83681 | #define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK 0x0000FF00L |
83682 | #define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK 0x80000000L |
83683 | //IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control |
83684 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
83685 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
83686 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT 0x6 |
83687 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe |
83688 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
83689 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
83690 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK 0x000000C0L |
83691 | #define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L |
83692 | //IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control |
83693 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 |
83694 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT 0x2 |
83695 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT 0x6 |
83696 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT 0xe |
83697 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L |
83698 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL |
83699 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK 0x000000C0L |
83700 | #define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK 0x0000C000L |
83701 | //IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control |
83702 | #define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
83703 | #define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
83704 | #define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
83705 | #define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
83706 | //IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control |
83707 | #define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 |
83708 | #define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT 0x2 |
83709 | #define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L |
83710 | #define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL |
83711 | //IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0 |
83712 | #define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT 0x0 |
83713 | #define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT 0x4 |
83714 | #define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT 0xa |
83715 | #define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK 0x0000000FL |
83716 | #define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK 0x000003F0L |
83717 | #define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK 0x0000FC00L |
83718 | //IOMMU_L1_PCIE0_L1_ECO_CNTRL |
83719 | #define IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO__SHIFT 0x0 |
83720 | #define IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO_MASK 0xFFFFFFFFL |
83721 | |
83722 | |
83723 | // addressBlock: nbio_iohub_iommu_l1shdw_PCIE0_l1shdw |
83724 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0 |
83725 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 |
83726 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL |
83727 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0 |
83728 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 |
83729 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 |
83730 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 |
83731 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 |
83732 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 |
83733 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 |
83734 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 |
83735 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 |
83736 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa |
83737 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb |
83738 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc |
83739 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd |
83740 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf |
83741 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 |
83742 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 |
83743 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 |
83744 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L |
83745 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L |
83746 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L |
83747 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L |
83748 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L |
83749 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L |
83750 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L |
83751 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L |
83752 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L |
83753 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L |
83754 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L |
83755 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L |
83756 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L |
83757 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L |
83758 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L |
83759 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L |
83760 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1 |
83761 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 |
83762 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL |
83763 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0 |
83764 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 |
83765 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 |
83766 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 |
83767 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc |
83768 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L |
83769 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L |
83770 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL |
83771 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L |
83772 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1 |
83773 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 |
83774 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 |
83775 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL |
83776 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L |
83777 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0 |
83778 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 |
83779 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc |
83780 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL |
83781 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L |
83782 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1 |
83783 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 |
83784 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 |
83785 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL |
83786 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L |
83787 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0 |
83788 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 |
83789 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL |
83790 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0 |
83791 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 |
83792 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL |
83793 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0 |
83794 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 |
83795 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL |
83796 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0 |
83797 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 |
83798 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL |
83799 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0 |
83800 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 |
83801 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL |
83802 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0 |
83803 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 |
83804 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL |
83805 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0 |
83806 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 |
83807 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL |
83808 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 |
83809 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 |
83810 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL |
83811 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 |
83812 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 |
83813 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL |
83814 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 |
83815 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 |
83816 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL |
83817 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 |
83818 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 |
83819 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL |
83820 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 |
83821 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 |
83822 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL |
83823 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 |
83824 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 |
83825 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL |
83826 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 |
83827 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 |
83828 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 |
83829 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e |
83830 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f |
83831 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL |
83832 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
83833 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L |
83834 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L |
83835 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 |
83836 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 |
83837 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
83838 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f |
83839 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL |
83840 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
83841 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L |
83842 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 |
83843 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 |
83844 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
83845 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL |
83846 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
83847 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 |
83848 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 |
83849 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
83850 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f |
83851 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL |
83852 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
83853 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L |
83854 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 |
83855 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 |
83856 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
83857 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL |
83858 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
83859 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 |
83860 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 |
83861 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
83862 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f |
83863 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL |
83864 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
83865 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L |
83866 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 |
83867 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 |
83868 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
83869 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL |
83870 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
83871 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 |
83872 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 |
83873 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 |
83874 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e |
83875 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f |
83876 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL |
83877 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
83878 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L |
83879 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L |
83880 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 |
83881 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 |
83882 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
83883 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f |
83884 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL |
83885 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
83886 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L |
83887 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 |
83888 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 |
83889 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
83890 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL |
83891 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
83892 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 |
83893 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 |
83894 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
83895 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f |
83896 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL |
83897 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
83898 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L |
83899 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 |
83900 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 |
83901 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
83902 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL |
83903 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
83904 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 |
83905 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 |
83906 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
83907 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f |
83908 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL |
83909 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
83910 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L |
83911 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 |
83912 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 |
83913 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
83914 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL |
83915 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
83916 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 |
83917 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 |
83918 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 |
83919 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e |
83920 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f |
83921 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL |
83922 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
83923 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L |
83924 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L |
83925 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 |
83926 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 |
83927 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
83928 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f |
83929 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL |
83930 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
83931 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L |
83932 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 |
83933 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 |
83934 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
83935 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL |
83936 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
83937 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 |
83938 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 |
83939 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
83940 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f |
83941 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL |
83942 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
83943 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L |
83944 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 |
83945 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 |
83946 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
83947 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL |
83948 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
83949 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 |
83950 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 |
83951 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
83952 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f |
83953 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL |
83954 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
83955 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L |
83956 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 |
83957 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 |
83958 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
83959 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL |
83960 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
83961 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 |
83962 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 |
83963 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 |
83964 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e |
83965 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f |
83966 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL |
83967 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
83968 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L |
83969 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L |
83970 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 |
83971 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 |
83972 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
83973 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f |
83974 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL |
83975 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
83976 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L |
83977 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 |
83978 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 |
83979 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
83980 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL |
83981 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
83982 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 |
83983 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 |
83984 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
83985 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f |
83986 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL |
83987 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
83988 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L |
83989 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 |
83990 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 |
83991 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
83992 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL |
83993 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
83994 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 |
83995 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 |
83996 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
83997 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f |
83998 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL |
83999 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84000 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L |
84001 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 |
84002 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 |
84003 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
84004 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL |
84005 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84006 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 |
84007 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 |
84008 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 |
84009 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e |
84010 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f |
84011 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL |
84012 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
84013 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L |
84014 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L |
84015 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 |
84016 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 |
84017 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
84018 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f |
84019 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL |
84020 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84021 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L |
84022 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 |
84023 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 |
84024 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
84025 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL |
84026 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84027 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 |
84028 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 |
84029 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
84030 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f |
84031 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL |
84032 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84033 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L |
84034 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 |
84035 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 |
84036 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
84037 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL |
84038 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84039 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 |
84040 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 |
84041 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
84042 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f |
84043 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL |
84044 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84045 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L |
84046 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 |
84047 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 |
84048 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
84049 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL |
84050 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84051 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 |
84052 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 |
84053 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 |
84054 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e |
84055 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f |
84056 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL |
84057 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
84058 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L |
84059 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L |
84060 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 |
84061 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 |
84062 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
84063 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f |
84064 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL |
84065 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84066 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L |
84067 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 |
84068 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 |
84069 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
84070 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL |
84071 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84072 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 |
84073 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 |
84074 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
84075 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f |
84076 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL |
84077 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84078 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L |
84079 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 |
84080 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 |
84081 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
84082 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL |
84083 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84084 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 |
84085 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 |
84086 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
84087 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f |
84088 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL |
84089 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84090 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L |
84091 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 |
84092 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 |
84093 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
84094 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL |
84095 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84096 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 |
84097 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 |
84098 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 |
84099 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e |
84100 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f |
84101 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL |
84102 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
84103 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L |
84104 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L |
84105 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 |
84106 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 |
84107 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
84108 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f |
84109 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL |
84110 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84111 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L |
84112 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 |
84113 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 |
84114 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
84115 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL |
84116 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84117 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 |
84118 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 |
84119 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
84120 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f |
84121 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL |
84122 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84123 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L |
84124 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 |
84125 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 |
84126 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
84127 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL |
84128 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84129 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 |
84130 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 |
84131 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
84132 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f |
84133 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL |
84134 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84135 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L |
84136 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 |
84137 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 |
84138 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
84139 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL |
84140 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84141 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 |
84142 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 |
84143 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 |
84144 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e |
84145 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f |
84146 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL |
84147 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
84148 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L |
84149 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L |
84150 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 |
84151 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 |
84152 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
84153 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f |
84154 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL |
84155 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84156 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L |
84157 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 |
84158 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 |
84159 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
84160 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL |
84161 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84162 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 |
84163 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 |
84164 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
84165 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f |
84166 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL |
84167 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84168 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L |
84169 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 |
84170 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 |
84171 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
84172 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL |
84173 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84174 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 |
84175 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 |
84176 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
84177 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f |
84178 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL |
84179 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84180 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L |
84181 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 |
84182 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 |
84183 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
84184 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL |
84185 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84186 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO |
84187 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
84188 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
84189 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC |
84190 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 |
84191 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L |
84192 | //IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1 |
84193 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 |
84194 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 |
84195 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L |
84196 | #define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L |
84197 | |
84198 | |
84199 | // addressBlock: nbio_iohub_iommu_l1psp_PCIE0_l1psp |
84200 | //IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL |
84201 | #define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT 0x0 |
84202 | #define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT 0x1 |
84203 | #define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK 0x00000001L |
84204 | #define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved_MASK 0xFFFFFFFEL |
84205 | //IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0 |
84206 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV__SHIFT 0x0 |
84207 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO__SHIFT 0x1 |
84208 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved__SHIFT 0x2 |
84209 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT 0x10 |
84210 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV_MASK 0x00000001L |
84211 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO_MASK 0x00000002L |
84212 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved_MASK 0x0000FFFCL |
84213 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK 0xFFFF0000L |
84214 | //IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1 |
84215 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved__SHIFT 0x0 |
84216 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved_MASK 0xFFFFFFFFL |
84217 | //IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0 |
84218 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT 0x0 |
84219 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK 0xFFFFFFFFL |
84220 | //IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1 |
84221 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT 0x0 |
84222 | #define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK 0xFFFFFFFFL |
84223 | //IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL |
84224 | #define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT 0x0 |
84225 | #define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved__SHIFT 0x1 |
84226 | #define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans_MASK 0x00000001L |
84227 | #define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved_MASK 0xFFFFFFFEL |
84228 | |
84229 | |
84230 | // addressBlock: nbio_iohub_iommu_l1_IOAGR_iommul1cfg |
84231 | //IOMMU_L1_IOAGR_L1_PERF_CNTL |
84232 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT 0x0 |
84233 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT 0x8 |
84234 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT 0x10 |
84235 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT 0x18 |
84236 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0_MASK 0x000000FFL |
84237 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1_MASK 0x0000FF00L |
84238 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK 0x00FF0000L |
84239 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK 0xFF000000L |
84240 | //IOMMU_L1_IOAGR_L1_PERF_COUNT_0 |
84241 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT 0x0 |
84242 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK 0xFFFFFFFFL |
84243 | //IOMMU_L1_IOAGR_L1_PERF_COUNT_1 |
84244 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT 0x0 |
84245 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK 0xFFFFFFFFL |
84246 | //IOMMU_L1_IOAGR_L1_PERF_CNTL_B |
84247 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT 0x0 |
84248 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT 0x8 |
84249 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT 0x10 |
84250 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT 0x18 |
84251 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK 0x000000FFL |
84252 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK 0x0000FF00L |
84253 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK 0x00FF0000L |
84254 | #define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK 0xFF000000L |
84255 | //IOMMU_L1_IOAGR_L1_PERF_COUNT_B0 |
84256 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT 0x0 |
84257 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK 0xFFFFFFFFL |
84258 | //IOMMU_L1_IOAGR_L1_PERF_COUNT_B1 |
84259 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT 0x0 |
84260 | #define IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK 0xFFFFFFFFL |
84261 | //IOMMU_L1_IOAGR_L1_SB_LOCATION |
84262 | #define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port__SHIFT 0x0 |
84263 | #define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core__SHIFT 0x10 |
84264 | #define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL |
84265 | #define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L |
84266 | //IOMMU_L1_IOAGR_L1_CNTRL_0 |
84267 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis__SHIFT 0x0 |
84268 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis__SHIFT 0x1 |
84269 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only__SHIFT 0x2 |
84270 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only__SHIFT 0x3 |
84271 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0__SHIFT 0x4 |
84272 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED__SHIFT 0x5 |
84273 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits__SHIFT 0x8 |
84274 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1__SHIFT 0xe |
84275 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks__SHIFT 0x14 |
84276 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries__SHIFT 0x18 |
84277 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT 0x1c |
84278 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT 0x1d |
84279 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT 0x1f |
84280 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis_MASK 0x00000001L |
84281 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis_MASK 0x00000002L |
84282 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only_MASK 0x00000004L |
84283 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only_MASK 0x00000008L |
84284 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0_MASK 0x00000010L |
84285 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED_MASK 0x00000020L |
84286 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits_MASK 0x00003F00L |
84287 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1_MASK 0x000FC000L |
84288 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks_MASK 0x00300000L |
84289 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries_MASK 0x0F000000L |
84290 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis_MASK 0x10000000L |
84291 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK 0x60000000L |
84292 | #define IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis_MASK 0x80000000L |
84293 | //IOMMU_L1_IOAGR_L1_CNTRL_1 |
84294 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED__SHIFT 0x0 |
84295 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass__SHIFT 0x9 |
84296 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn__SHIFT 0xa |
84297 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn__SHIFT 0xb |
84298 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis__SHIFT 0xc |
84299 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis__SHIFT 0xd |
84300 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis__SHIFT 0x14 |
84301 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en__SHIFT 0x15 |
84302 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn__SHIFT 0x16 |
84303 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse__SHIFT 0x17 |
84304 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT 0x1a |
84305 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT 0x1b |
84306 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT 0x1c |
84307 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT 0x1d |
84308 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT 0x1e |
84309 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT 0x1f |
84310 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED_MASK 0x000001FFL |
84311 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass_MASK 0x00000200L |
84312 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn_MASK 0x00000400L |
84313 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn_MASK 0x00000800L |
84314 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis_MASK 0x00001000L |
84315 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis_MASK 0x000FE000L |
84316 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis_MASK 0x00100000L |
84317 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en_MASK 0x00200000L |
84318 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn_MASK 0x00400000L |
84319 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse_MASK 0x03800000L |
84320 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid_MASK 0x04000000L |
84321 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave_MASK 0x08000000L |
84322 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK 0x10000000L |
84323 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn_MASK 0x20000000L |
84324 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En_MASK 0x40000000L |
84325 | #define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En_MASK 0x80000000L |
84326 | //IOMMU_L1_IOAGR_L1_CNTRL_2 |
84327 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable__SHIFT 0x0 |
84328 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT 0x1 |
84329 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT 0x2 |
84330 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT 0x3 |
84331 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED__SHIFT 0x4 |
84332 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE__SHIFT 0x18 |
84333 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT 0x1b |
84334 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT 0x1c |
84335 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn__SHIFT 0x1d |
84336 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT 0x1e |
84337 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT 0x1f |
84338 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable_MASK 0x00000001L |
84339 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK 0x00000002L |
84340 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis_MASK 0x00000004L |
84341 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK 0x00000008L |
84342 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED_MASK 0x00FFFFF0L |
84343 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE_MASK 0x07000000L |
84344 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK 0x08000000L |
84345 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK 0x10000000L |
84346 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn_MASK 0x20000000L |
84347 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK 0x40000000L |
84348 | #define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK 0x80000000L |
84349 | //IOMMU_L1_IOAGR_L1_CNTRL_3 |
84350 | #define IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT 0x0 |
84351 | #define IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK 0xFFFFFFFFL |
84352 | //IOMMU_L1_IOAGR_L1_BANK_SEL_0 |
84353 | #define IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT 0x0 |
84354 | #define IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0_MASK 0x0000FFFFL |
84355 | //IOMMU_L1_IOAGR_L1_BANK_DISABLE_0 |
84356 | #define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT 0x0 |
84357 | #define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT 0x8 |
84358 | #define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK 0x0000003FL |
84359 | #define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK 0x00003F00L |
84360 | //IOMMU_L1_IOAGR_L1_WQ_STATUS_0 |
84361 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0__SHIFT 0x0 |
84362 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1__SHIFT 0x3 |
84363 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2__SHIFT 0x6 |
84364 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3__SHIFT 0x9 |
84365 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4__SHIFT 0xc |
84366 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5__SHIFT 0xf |
84367 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6__SHIFT 0x12 |
84368 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7__SHIFT 0x15 |
84369 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8__SHIFT 0x18 |
84370 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9__SHIFT 0x1b |
84371 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0_MASK 0x00000007L |
84372 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1_MASK 0x00000038L |
84373 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2_MASK 0x000001C0L |
84374 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3_MASK 0x00000E00L |
84375 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4_MASK 0x00007000L |
84376 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5_MASK 0x00038000L |
84377 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6_MASK 0x001C0000L |
84378 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7_MASK 0x00E00000L |
84379 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8_MASK 0x07000000L |
84380 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9_MASK 0x38000000L |
84381 | //IOMMU_L1_IOAGR_L1_WQ_STATUS_1 |
84382 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10__SHIFT 0x0 |
84383 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11__SHIFT 0x3 |
84384 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12__SHIFT 0x6 |
84385 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13__SHIFT 0x9 |
84386 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14__SHIFT 0xc |
84387 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15__SHIFT 0xf |
84388 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16__SHIFT 0x12 |
84389 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17__SHIFT 0x15 |
84390 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18__SHIFT 0x18 |
84391 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19__SHIFT 0x1b |
84392 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10_MASK 0x00000007L |
84393 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11_MASK 0x00000038L |
84394 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12_MASK 0x000001C0L |
84395 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13_MASK 0x00000E00L |
84396 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14_MASK 0x00007000L |
84397 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15_MASK 0x00038000L |
84398 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16_MASK 0x001C0000L |
84399 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17_MASK 0x00E00000L |
84400 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18_MASK 0x07000000L |
84401 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19_MASK 0x38000000L |
84402 | //IOMMU_L1_IOAGR_L1_WQ_STATUS_2 |
84403 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20__SHIFT 0x0 |
84404 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21__SHIFT 0x3 |
84405 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22__SHIFT 0x6 |
84406 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23__SHIFT 0x9 |
84407 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24__SHIFT 0xc |
84408 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25__SHIFT 0xf |
84409 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26__SHIFT 0x12 |
84410 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27__SHIFT 0x15 |
84411 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28__SHIFT 0x18 |
84412 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29__SHIFT 0x1b |
84413 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20_MASK 0x00000007L |
84414 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21_MASK 0x00000038L |
84415 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22_MASK 0x000001C0L |
84416 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23_MASK 0x00000E00L |
84417 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24_MASK 0x00007000L |
84418 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25_MASK 0x00038000L |
84419 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26_MASK 0x001C0000L |
84420 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27_MASK 0x00E00000L |
84421 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28_MASK 0x07000000L |
84422 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29_MASK 0x38000000L |
84423 | //IOMMU_L1_IOAGR_L1_WQ_STATUS_3 |
84424 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30__SHIFT 0x0 |
84425 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31__SHIFT 0x3 |
84426 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status__SHIFT 0x8 |
84427 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30_MASK 0x00000007L |
84428 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31_MASK 0x00000038L |
84429 | #define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status_MASK 0x0000FF00L |
84430 | //IOMMU_L1_IOAGR_L1_FEATURE_CNTRL |
84431 | #define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT 0x0 |
84432 | #define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved__SHIFT 0x8 |
84433 | #define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK 0x000000FFL |
84434 | #define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved_MASK 0xFFFFFF00L |
84435 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5 |
84436 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT 0x0 |
84437 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
84438 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6 |
84439 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT 0x0 |
84440 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
84441 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7 |
84442 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT 0x0 |
84443 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
84444 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8 |
84445 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT 0x0 |
84446 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
84447 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9 |
84448 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT 0x0 |
84449 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
84450 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10 |
84451 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT 0x0 |
84452 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
84453 | //IOMMU_L1_IOAGR_L1_CNTRL_4 |
84454 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT 0x0 |
84455 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT 0x2 |
84456 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED__SHIFT 0x4 |
84457 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT 0x17 |
84458 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT 0x18 |
84459 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en_MASK 0x00000001L |
84460 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En_MASK 0x00000004L |
84461 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED_MASK 0x007FFFF0L |
84462 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK 0x00800000L |
84463 | #define IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val_MASK 0x7F000000L |
84464 | //IOMMU_L1_IOAGR_L1_CLKCNTRL_0 |
84465 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT 0x4 |
84466 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT 0x5 |
84467 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT 0x6 |
84468 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT 0x8 |
84469 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT 0x9 |
84470 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT 0xa |
84471 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT 0xb |
84472 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT 0xc |
84473 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT 0xd |
84474 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT 0xe |
84475 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved__SHIFT 0x16 |
84476 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT 0x1f |
84477 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK 0x00000010L |
84478 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK 0x00000020L |
84479 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK 0x00000040L |
84480 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK 0x00000100L |
84481 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK 0x00000200L |
84482 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK 0x00000400L |
84483 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK 0x00000800L |
84484 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK 0x00001000L |
84485 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK 0x00002000L |
84486 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK 0x003FC000L |
84487 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved_MASK 0x7FC00000L |
84488 | #define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK 0x80000000L |
84489 | //IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL |
84490 | #define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT 0x0 |
84491 | #define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT 0x1 |
84492 | #define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK 0x00000001L |
84493 | #define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK 0x00000002L |
84494 | //IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL |
84495 | #define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT 0x0 |
84496 | #define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved__SHIFT 0x1 |
84497 | #define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT 0x8 |
84498 | #define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK 0x00000001L |
84499 | #define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved_MASK 0x000000FEL |
84500 | #define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK 0xFFFFFF00L |
84501 | //IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL |
84502 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT 0x0 |
84503 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT 0x1 |
84504 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT 0x2 |
84505 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT 0x4 |
84506 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved__SHIFT 0x5 |
84507 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK 0x00000001L |
84508 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK 0x00000002L |
84509 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK 0x0000000CL |
84510 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK 0x00000010L |
84511 | #define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved_MASK 0xFFFFFFE0L |
84512 | //IOMMU_L1_IOAGR_L1_CNTRL_5 |
84513 | #define IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED__SHIFT 0x0 |
84514 | #define IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED_MASK 0xFFFFFFFFL |
84515 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1 |
84516 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT 0x0 |
84517 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT 0x1 |
84518 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT 0x2 |
84519 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT 0x3 |
84520 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN_MASK 0x00000001L |
84521 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN_MASK 0x00000002L |
84522 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN_MASK 0x00000004L |
84523 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK 0x00000008L |
84524 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2 |
84525 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT 0x0 |
84526 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres_MASK 0xFFFFFFFFL |
84527 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3 |
84528 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT 0x0 |
84529 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres_MASK 0xFFFFFFFFL |
84530 | //IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4 |
84531 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT 0x0 |
84532 | #define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres_MASK 0xFFFFFFFFL |
84533 | //IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL |
84534 | #define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
84535 | #define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT 0x5 |
84536 | #define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
84537 | #define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK 0x00000020L |
84538 | //IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0 |
84539 | #define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT 0x0 |
84540 | #define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT 0x8 |
84541 | #define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT 0x1f |
84542 | #define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK 0x000000FFL |
84543 | #define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK 0x0000FF00L |
84544 | #define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK 0x80000000L |
84545 | //IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control |
84546 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
84547 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
84548 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT 0x6 |
84549 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe |
84550 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
84551 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
84552 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK 0x000000C0L |
84553 | #define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L |
84554 | //IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control |
84555 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 |
84556 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT 0x2 |
84557 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT 0x6 |
84558 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT 0xe |
84559 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L |
84560 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL |
84561 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK 0x000000C0L |
84562 | #define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK 0x0000C000L |
84563 | //IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control |
84564 | #define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
84565 | #define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
84566 | #define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
84567 | #define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
84568 | //IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control |
84569 | #define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 |
84570 | #define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT 0x2 |
84571 | #define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L |
84572 | #define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL |
84573 | //IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0 |
84574 | #define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT 0x0 |
84575 | #define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT 0x4 |
84576 | #define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT 0xa |
84577 | #define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK 0x0000000FL |
84578 | #define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK 0x000003F0L |
84579 | #define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK 0x0000FC00L |
84580 | //IOMMU_L1_IOAGR_L1_ECO_CNTRL |
84581 | #define IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO__SHIFT 0x0 |
84582 | #define IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO_MASK 0xFFFFFFFFL |
84583 | |
84584 | |
84585 | // addressBlock: nbio_iohub_iommu_l1shdw_IOAGR_l1shdw |
84586 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0 |
84587 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 |
84588 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL |
84589 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0 |
84590 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 |
84591 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 |
84592 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 |
84593 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 |
84594 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 |
84595 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 |
84596 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 |
84597 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 |
84598 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa |
84599 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb |
84600 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc |
84601 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd |
84602 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf |
84603 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 |
84604 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 |
84605 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 |
84606 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L |
84607 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L |
84608 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L |
84609 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L |
84610 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L |
84611 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L |
84612 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L |
84613 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L |
84614 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L |
84615 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L |
84616 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L |
84617 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L |
84618 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L |
84619 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L |
84620 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L |
84621 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L |
84622 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1 |
84623 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 |
84624 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL |
84625 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0 |
84626 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 |
84627 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 |
84628 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 |
84629 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc |
84630 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L |
84631 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L |
84632 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL |
84633 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L |
84634 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1 |
84635 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 |
84636 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 |
84637 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL |
84638 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L |
84639 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0 |
84640 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 |
84641 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc |
84642 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL |
84643 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L |
84644 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1 |
84645 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 |
84646 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 |
84647 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL |
84648 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L |
84649 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0 |
84650 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 |
84651 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL |
84652 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0 |
84653 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 |
84654 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL |
84655 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0 |
84656 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 |
84657 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL |
84658 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0 |
84659 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 |
84660 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL |
84661 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0 |
84662 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 |
84663 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL |
84664 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0 |
84665 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 |
84666 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL |
84667 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0 |
84668 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 |
84669 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL |
84670 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 |
84671 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 |
84672 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL |
84673 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 |
84674 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 |
84675 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL |
84676 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 |
84677 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 |
84678 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL |
84679 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 |
84680 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 |
84681 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL |
84682 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 |
84683 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 |
84684 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL |
84685 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 |
84686 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 |
84687 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL |
84688 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 |
84689 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 |
84690 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 |
84691 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e |
84692 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f |
84693 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL |
84694 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
84695 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L |
84696 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L |
84697 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 |
84698 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 |
84699 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
84700 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f |
84701 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL |
84702 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84703 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L |
84704 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 |
84705 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 |
84706 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
84707 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL |
84708 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84709 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 |
84710 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 |
84711 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
84712 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f |
84713 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL |
84714 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84715 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L |
84716 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 |
84717 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 |
84718 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
84719 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL |
84720 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84721 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 |
84722 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 |
84723 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
84724 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f |
84725 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL |
84726 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84727 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L |
84728 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 |
84729 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 |
84730 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
84731 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL |
84732 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84733 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 |
84734 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 |
84735 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 |
84736 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e |
84737 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f |
84738 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL |
84739 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
84740 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L |
84741 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L |
84742 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 |
84743 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 |
84744 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
84745 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f |
84746 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL |
84747 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84748 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L |
84749 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 |
84750 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 |
84751 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
84752 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL |
84753 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84754 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 |
84755 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 |
84756 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
84757 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f |
84758 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL |
84759 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84760 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L |
84761 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 |
84762 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 |
84763 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
84764 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL |
84765 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84766 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 |
84767 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 |
84768 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
84769 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f |
84770 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL |
84771 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84772 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L |
84773 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 |
84774 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 |
84775 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
84776 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL |
84777 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84778 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 |
84779 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 |
84780 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 |
84781 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e |
84782 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f |
84783 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL |
84784 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
84785 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L |
84786 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L |
84787 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 |
84788 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 |
84789 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
84790 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f |
84791 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL |
84792 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84793 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L |
84794 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 |
84795 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 |
84796 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
84797 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL |
84798 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84799 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 |
84800 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 |
84801 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
84802 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f |
84803 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL |
84804 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84805 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L |
84806 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 |
84807 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 |
84808 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
84809 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL |
84810 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84811 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 |
84812 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 |
84813 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
84814 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f |
84815 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL |
84816 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84817 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L |
84818 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 |
84819 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 |
84820 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
84821 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL |
84822 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84823 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 |
84824 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 |
84825 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 |
84826 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e |
84827 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f |
84828 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL |
84829 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
84830 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L |
84831 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L |
84832 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 |
84833 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 |
84834 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
84835 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f |
84836 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL |
84837 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84838 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L |
84839 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 |
84840 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 |
84841 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
84842 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL |
84843 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84844 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 |
84845 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 |
84846 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
84847 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f |
84848 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL |
84849 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84850 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L |
84851 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 |
84852 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 |
84853 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
84854 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL |
84855 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84856 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 |
84857 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 |
84858 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
84859 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f |
84860 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL |
84861 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
84862 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L |
84863 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 |
84864 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 |
84865 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
84866 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL |
84867 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
84868 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 |
84869 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 |
84870 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 |
84871 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e |
84872 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f |
84873 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL |
84874 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
84875 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L |
84876 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L |
84877 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 |
84878 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 |
84879 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
84880 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f |
84881 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL |
84882 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84883 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L |
84884 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 |
84885 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 |
84886 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
84887 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL |
84888 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84889 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 |
84890 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 |
84891 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
84892 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f |
84893 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL |
84894 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84895 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L |
84896 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 |
84897 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 |
84898 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
84899 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL |
84900 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84901 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 |
84902 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 |
84903 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
84904 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f |
84905 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL |
84906 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
84907 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L |
84908 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 |
84909 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 |
84910 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
84911 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL |
84912 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
84913 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 |
84914 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 |
84915 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 |
84916 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e |
84917 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f |
84918 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL |
84919 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
84920 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L |
84921 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L |
84922 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 |
84923 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 |
84924 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
84925 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f |
84926 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL |
84927 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84928 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L |
84929 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 |
84930 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 |
84931 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
84932 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL |
84933 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84934 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 |
84935 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 |
84936 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
84937 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f |
84938 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL |
84939 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84940 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L |
84941 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 |
84942 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 |
84943 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
84944 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL |
84945 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84946 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 |
84947 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 |
84948 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
84949 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f |
84950 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL |
84951 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
84952 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L |
84953 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 |
84954 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 |
84955 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
84956 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL |
84957 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
84958 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 |
84959 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 |
84960 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 |
84961 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e |
84962 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f |
84963 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL |
84964 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
84965 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L |
84966 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L |
84967 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 |
84968 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 |
84969 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
84970 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f |
84971 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL |
84972 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84973 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L |
84974 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 |
84975 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 |
84976 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
84977 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL |
84978 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84979 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 |
84980 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 |
84981 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
84982 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f |
84983 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL |
84984 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84985 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L |
84986 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 |
84987 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 |
84988 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
84989 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL |
84990 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
84991 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 |
84992 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 |
84993 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
84994 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f |
84995 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL |
84996 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
84997 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L |
84998 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 |
84999 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 |
85000 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
85001 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL |
85002 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
85003 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 |
85004 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 |
85005 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 |
85006 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e |
85007 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f |
85008 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL |
85009 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
85010 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L |
85011 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L |
85012 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 |
85013 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 |
85014 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
85015 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f |
85016 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL |
85017 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
85018 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L |
85019 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 |
85020 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 |
85021 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
85022 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL |
85023 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
85024 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 |
85025 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 |
85026 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
85027 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f |
85028 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL |
85029 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
85030 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L |
85031 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 |
85032 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 |
85033 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
85034 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL |
85035 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
85036 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 |
85037 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 |
85038 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
85039 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f |
85040 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL |
85041 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
85042 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L |
85043 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 |
85044 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 |
85045 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
85046 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL |
85047 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
85048 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO |
85049 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
85050 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
85051 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC |
85052 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 |
85053 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L |
85054 | //IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1 |
85055 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 |
85056 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 |
85057 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L |
85058 | #define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L |
85059 | |
85060 | |
85061 | // addressBlock: nbio_iohub_iommu_l1psp_IOAGR_l1psp |
85062 | //IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL |
85063 | #define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT 0x0 |
85064 | #define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT 0x1 |
85065 | #define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK 0x00000001L |
85066 | #define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved_MASK 0xFFFFFFFEL |
85067 | //IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0 |
85068 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV__SHIFT 0x0 |
85069 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO__SHIFT 0x1 |
85070 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved__SHIFT 0x2 |
85071 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT 0x10 |
85072 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV_MASK 0x00000001L |
85073 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO_MASK 0x00000002L |
85074 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved_MASK 0x0000FFFCL |
85075 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK 0xFFFF0000L |
85076 | //IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1 |
85077 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved__SHIFT 0x0 |
85078 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved_MASK 0xFFFFFFFFL |
85079 | //IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0 |
85080 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT 0x0 |
85081 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK 0xFFFFFFFFL |
85082 | //IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1 |
85083 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT 0x0 |
85084 | #define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK 0xFFFFFFFFL |
85085 | //IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL |
85086 | #define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT 0x0 |
85087 | #define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved__SHIFT 0x1 |
85088 | #define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans_MASK 0x00000001L |
85089 | #define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved_MASK 0xFFFFFFFEL |
85090 | |
85091 | |
85092 | // addressBlock: nbio_iohub_iommu_l2a_l2acfg |
85093 | //L2_PERF_CNTL_0 |
85094 | #define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT 0x0 |
85095 | #define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT 0x8 |
85096 | #define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT 0x10 |
85097 | #define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT 0x18 |
85098 | #define L2_PERF_CNTL_0__L2PerfEvent0_MASK 0x000000FFL |
85099 | #define L2_PERF_CNTL_0__L2PerfEvent1_MASK 0x0000FF00L |
85100 | #define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK 0x00FF0000L |
85101 | #define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK 0xFF000000L |
85102 | //L2_PERF_COUNT_0 |
85103 | #define L2_PERF_COUNT_0__L2PerfCount0__SHIFT 0x0 |
85104 | #define L2_PERF_COUNT_0__L2PerfCount0_MASK 0xFFFFFFFFL |
85105 | //L2_PERF_COUNT_1 |
85106 | #define L2_PERF_COUNT_1__L2PerfCount1__SHIFT 0x0 |
85107 | #define L2_PERF_COUNT_1__L2PerfCount1_MASK 0xFFFFFFFFL |
85108 | //L2_PERF_CNTL_1 |
85109 | #define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT 0x0 |
85110 | #define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT 0x8 |
85111 | #define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT 0x10 |
85112 | #define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT 0x18 |
85113 | #define L2_PERF_CNTL_1__L2PerfEvent2_MASK 0x000000FFL |
85114 | #define L2_PERF_CNTL_1__L2PerfEvent3_MASK 0x0000FF00L |
85115 | #define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK 0x00FF0000L |
85116 | #define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK 0xFF000000L |
85117 | //L2_PERF_COUNT_2 |
85118 | #define L2_PERF_COUNT_2__L2PerfCount2__SHIFT 0x0 |
85119 | #define L2_PERF_COUNT_2__L2PerfCount2_MASK 0xFFFFFFFFL |
85120 | //L2_PERF_COUNT_3 |
85121 | #define L2_PERF_COUNT_3__L2PerfCount3__SHIFT 0x0 |
85122 | #define L2_PERF_COUNT_3__L2PerfCount3_MASK 0xFFFFFFFFL |
85123 | //L2_STATUS_0 |
85124 | #define L2_STATUS_0__L2STATUS0__SHIFT 0x0 |
85125 | #define L2_STATUS_0__L2STATUS0_MASK 0xFFFFFFFFL |
85126 | //L2_CONTROL_0 |
85127 | #define L2_CONTROL_0__AllowL1CacheVZero__SHIFT 0x1 |
85128 | #define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT 0x2 |
85129 | #define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT 0x3 |
85130 | #define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT 0xa |
85131 | #define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT 0xb |
85132 | #define L2_CONTROL_0__RESERVED__SHIFT 0xc |
85133 | #define L2_CONTROL_0__FLTCMBPriority__SHIFT 0x12 |
85134 | #define L2_CONTROL_0__IFifoBurstLength__SHIFT 0x14 |
85135 | #define L2_CONTROL_0__IFifoClientPriority__SHIFT 0x18 |
85136 | #define L2_CONTROL_0__AllowL1CacheVZero_MASK 0x00000002L |
85137 | #define L2_CONTROL_0__AllowL1CacheATSRsp_MASK 0x00000004L |
85138 | #define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK 0x00000008L |
85139 | #define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK 0x00000400L |
85140 | #define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK 0x00000800L |
85141 | #define L2_CONTROL_0__RESERVED_MASK 0x0003F000L |
85142 | #define L2_CONTROL_0__FLTCMBPriority_MASK 0x00040000L |
85143 | #define L2_CONTROL_0__IFifoBurstLength_MASK 0x00F00000L |
85144 | #define L2_CONTROL_0__IFifoClientPriority_MASK 0xFF000000L |
85145 | //L2_CONTROL_1 |
85146 | #define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT 0x0 |
85147 | #define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT 0x8 |
85148 | #define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT 0x10 |
85149 | #define L2_CONTROL_1__PerfThreshold__SHIFT 0x18 |
85150 | #define L2_CONTROL_1__SeqInvBurstLimitInv_MASK 0x000000FFL |
85151 | #define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK 0x0000FF00L |
85152 | #define L2_CONTROL_1__SeqInvBurstLimitEn_MASK 0x00010000L |
85153 | #define L2_CONTROL_1__PerfThreshold_MASK 0xFF000000L |
85154 | //L2_DTC_CONTROL |
85155 | #define L2_DTC_CONTROL__RESERVED__SHIFT 0x0 |
85156 | #define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT 0x3 |
85157 | #define L2_DTC_CONTROL__DTCParityEn__SHIFT 0x4 |
85158 | #define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT 0x8 |
85159 | #define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT 0xa |
85160 | #define L2_DTC_CONTROL__DTCBypass__SHIFT 0xd |
85161 | #define L2_DTC_CONTROL__DTCParitySupport__SHIFT 0xf |
85162 | #define L2_DTC_CONTROL__DTCWays__SHIFT 0x10 |
85163 | #define L2_DTC_CONTROL__DTCEntries__SHIFT 0x1c |
85164 | #define L2_DTC_CONTROL__RESERVED_MASK 0x00000003L |
85165 | #define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK 0x00000008L |
85166 | #define L2_DTC_CONTROL__DTCParityEn_MASK 0x00000010L |
85167 | #define L2_DTC_CONTROL__DTCInvalidationSel_MASK 0x00000300L |
85168 | #define L2_DTC_CONTROL__DTCSoftInvalidate_MASK 0x00000400L |
85169 | #define L2_DTC_CONTROL__DTCBypass_MASK 0x00002000L |
85170 | #define L2_DTC_CONTROL__DTCParitySupport_MASK 0x00008000L |
85171 | #define L2_DTC_CONTROL__DTCWays_MASK 0x00FF0000L |
85172 | #define L2_DTC_CONTROL__DTCEntries_MASK 0xF0000000L |
85173 | //L2_DTC_HASH_CONTROL |
85174 | #define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT 0x10 |
85175 | #define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK 0xFFFF0000L |
85176 | //L2_DTC_WAY_CONTROL |
85177 | #define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT 0x0 |
85178 | #define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT 0x10 |
85179 | #define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK 0x0000FFFFL |
85180 | #define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK 0xFFFF0000L |
85181 | //L2_ITC_CONTROL |
85182 | #define L2_ITC_CONTROL__RESERVED__SHIFT 0x0 |
85183 | #define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT 0x3 |
85184 | #define L2_ITC_CONTROL__ITCParityEn__SHIFT 0x4 |
85185 | #define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT 0x8 |
85186 | #define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT 0xa |
85187 | #define L2_ITC_CONTROL__ITCBypass__SHIFT 0xd |
85188 | #define L2_ITC_CONTROL__ITCParitySupport__SHIFT 0xf |
85189 | #define L2_ITC_CONTROL__ITCWays__SHIFT 0x10 |
85190 | #define L2_ITC_CONTROL__ITCEntries__SHIFT 0x1c |
85191 | #define L2_ITC_CONTROL__RESERVED_MASK 0x00000003L |
85192 | #define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK 0x00000008L |
85193 | #define L2_ITC_CONTROL__ITCParityEn_MASK 0x00000010L |
85194 | #define L2_ITC_CONTROL__ITCInvalidationSel_MASK 0x00000300L |
85195 | #define L2_ITC_CONTROL__ITCSoftInvalidate_MASK 0x00000400L |
85196 | #define L2_ITC_CONTROL__ITCBypass_MASK 0x00002000L |
85197 | #define L2_ITC_CONTROL__ITCParitySupport_MASK 0x00008000L |
85198 | #define L2_ITC_CONTROL__ITCWays_MASK 0x00FF0000L |
85199 | #define L2_ITC_CONTROL__ITCEntries_MASK 0xF0000000L |
85200 | //L2_ITC_HASH_CONTROL |
85201 | #define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT 0x10 |
85202 | #define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK 0xFFFF0000L |
85203 | //L2_ITC_WAY_CONTROL |
85204 | #define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT 0x0 |
85205 | #define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT 0x10 |
85206 | #define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK 0x0000FFFFL |
85207 | #define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK 0xFFFF0000L |
85208 | //L2_PTC_A_CONTROL |
85209 | #define L2_PTC_A_CONTROL__RESERVED__SHIFT 0x0 |
85210 | #define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT 0x3 |
85211 | #define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT 0x4 |
85212 | #define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT 0x8 |
85213 | #define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT 0xa |
85214 | #define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT 0xb |
85215 | #define L2_PTC_A_CONTROL__PTCABypass__SHIFT 0xd |
85216 | #define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT 0xf |
85217 | #define L2_PTC_A_CONTROL__PTCAWays__SHIFT 0x10 |
85218 | #define L2_PTC_A_CONTROL__PTCAEntries__SHIFT 0x1c |
85219 | #define L2_PTC_A_CONTROL__RESERVED_MASK 0x00000003L |
85220 | #define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK 0x00000008L |
85221 | #define L2_PTC_A_CONTROL__PTCAParityEn_MASK 0x00000010L |
85222 | #define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK 0x00000300L |
85223 | #define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK 0x00000400L |
85224 | #define L2_PTC_A_CONTROL__PTCA2MMode_MASK 0x00000800L |
85225 | #define L2_PTC_A_CONTROL__PTCABypass_MASK 0x00002000L |
85226 | #define L2_PTC_A_CONTROL__PTCAParitySupport_MASK 0x00008000L |
85227 | #define L2_PTC_A_CONTROL__PTCAWays_MASK 0x00FF0000L |
85228 | #define L2_PTC_A_CONTROL__PTCAEntries_MASK 0xF0000000L |
85229 | //L2_PTC_A_HASH_CONTROL |
85230 | #define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT 0x10 |
85231 | #define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK 0xFFFF0000L |
85232 | //L2_PTC_A_WAY_CONTROL |
85233 | #define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT 0x0 |
85234 | #define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT 0x10 |
85235 | #define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK 0x0000FFFFL |
85236 | #define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK 0xFFFF0000L |
85237 | //L2_CREDIT_CONTROL_2 |
85238 | #define L2_CREDIT_CONTROL_2__QUEUECredits__SHIFT 0x0 |
85239 | #define L2_CREDIT_CONTROL_2__QUEUEOverride__SHIFT 0x7 |
85240 | #define L2_CREDIT_CONTROL_2__FLTCMBCredits__SHIFT 0x8 |
85241 | #define L2_CREDIT_CONTROL_2__FLTCMBOverride__SHIFT 0xf |
85242 | #define L2_CREDIT_CONTROL_2__FCELCredits__SHIFT 0x10 |
85243 | #define L2_CREDIT_CONTROL_2__FCELOverride__SHIFT 0x17 |
85244 | #define L2_CREDIT_CONTROL_2__PPR_logger_credits__SHIFT 0x18 |
85245 | #define L2_CREDIT_CONTROL_2__QUEUECredits_MASK 0x0000003FL |
85246 | #define L2_CREDIT_CONTROL_2__QUEUEOverride_MASK 0x00000080L |
85247 | #define L2_CREDIT_CONTROL_2__FLTCMBCredits_MASK 0x00003F00L |
85248 | #define L2_CREDIT_CONTROL_2__FLTCMBOverride_MASK 0x00008000L |
85249 | #define L2_CREDIT_CONTROL_2__FCELCredits_MASK 0x003F0000L |
85250 | #define L2_CREDIT_CONTROL_2__FCELOverride_MASK 0x00800000L |
85251 | #define L2_CREDIT_CONTROL_2__PPR_logger_credits_MASK 0x0F000000L |
85252 | //L2A_UPDATE_FILTER_CNTL |
85253 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT 0x0 |
85254 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT 0x1 |
85255 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK 0x00000001L |
85256 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK 0x0000001EL |
85257 | //L2_ERR_RULE_CONTROL_3 |
85258 | #define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT 0x0 |
85259 | #define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT 0x4 |
85260 | #define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK 0x00000001L |
85261 | #define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK 0xFFFFFFF0L |
85262 | //L2_ERR_RULE_CONTROL_4 |
85263 | #define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT 0x0 |
85264 | #define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK 0xFFFFFFFFL |
85265 | //L2_ERR_RULE_CONTROL_5 |
85266 | #define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT 0x0 |
85267 | #define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK 0xFFFFFFFFL |
85268 | //L2_L2A_CK_GATE_CONTROL |
85269 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT 0x0 |
85270 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT 0x1 |
85271 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT 0x2 |
85272 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ASpare__SHIFT 0x3 |
85273 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT 0x4 |
85274 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT 0x6 |
85275 | #define L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT 0x8 |
85276 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK 0x00000001L |
85277 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK 0x00000002L |
85278 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK 0x00000004L |
85279 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ASpare_MASK 0x00000008L |
85280 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK 0x00000030L |
85281 | #define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK 0x000000C0L |
85282 | #define L2_L2A_CK_GATE_CONTROL__Reserved_MASK 0xFFFFFF00L |
85283 | //L2_L2A_PGSIZE_CONTROL |
85284 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT 0x0 |
85285 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT 0x8 |
85286 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK 0x0000007FL |
85287 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK 0x00007F00L |
85288 | //L2_L2A_MEMPWR_GATE_1 |
85289 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN__SHIFT 0x0 |
85290 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN__SHIFT 0x1 |
85291 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN__SHIFT 0x2 |
85292 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL__SHIFT 0x4 |
85293 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN_MASK 0x00000001L |
85294 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN_MASK 0x00000002L |
85295 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN_MASK 0x00000004L |
85296 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL_MASK 0x00000010L |
85297 | //L2_L2A_MEMPWR_GATE_2 |
85298 | #define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres__SHIFT 0x0 |
85299 | #define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres_MASK 0xFFFFFFFFL |
85300 | //L2_L2A_MEMPWR_GATE_3 |
85301 | #define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres__SHIFT 0x0 |
85302 | #define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres_MASK 0xFFFFFFFFL |
85303 | //L2_L2A_MEMPWR_GATE_4 |
85304 | #define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres__SHIFT 0x0 |
85305 | #define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres_MASK 0xFFFFFFFFL |
85306 | //L2_L2A_MEMPWR_GATE_5 |
85307 | #define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt__SHIFT 0x0 |
85308 | #define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
85309 | //L2_L2A_MEMPWR_GATE_6 |
85310 | #define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt__SHIFT 0x0 |
85311 | #define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
85312 | //L2_L2A_MEMPWR_GATE_7 |
85313 | #define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt__SHIFT 0x0 |
85314 | #define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
85315 | //L2_L2A_MEMPWR_GATE_8 |
85316 | #define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt__SHIFT 0x0 |
85317 | #define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
85318 | //L2_L2A_MEMPWR_GATE_9 |
85319 | #define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt__SHIFT 0x0 |
85320 | #define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
85321 | //L2_PWRGATE_CNTRL_REG_0 |
85322 | #define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT 0x0 |
85323 | #define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK 0xFFFFFFFFL |
85324 | //L2_L2A_MEMPWR_GATE_10 |
85325 | #define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt__SHIFT 0x0 |
85326 | #define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
85327 | //L2_PWRGATE_CNTRL_REG_3 |
85328 | #define L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT 0x0 |
85329 | #define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT 0x1 |
85330 | #define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT 0x2 |
85331 | #define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT 0x3 |
85332 | #define L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK 0x00000001L |
85333 | #define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK 0x00000002L |
85334 | #define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK 0x00000004L |
85335 | #define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK 0x00000018L |
85336 | //L2_ECO_CNTRL_0 |
85337 | #define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT 0x0 |
85338 | #define L2_ECO_CNTRL_0__L2_ECO_0_MASK 0xFFFFFFFFL |
85339 | |
85340 | |
85341 | // addressBlock: nbio_iohub_iommu_l2ashdw_l2ashdw |
85342 | //SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0 |
85343 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 |
85344 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL |
85345 | //SHDWL2A_IOMMU_MMIO_CNTRL_0 |
85346 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 |
85347 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 |
85348 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 |
85349 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16 |
85350 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18 |
85351 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19 |
85352 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L |
85353 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L |
85354 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L |
85355 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L |
85356 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L |
85357 | #define SHDWL2A_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L |
85358 | //SHDWL2A_IOMMU_MMIO_CNTRL_1 |
85359 | #define SHDWL2A_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 |
85360 | #define SHDWL2A_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5 |
85361 | #define SHDWL2A_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd |
85362 | #define SHDWL2A_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL |
85363 | #define SHDWL2A_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L |
85364 | #define SHDWL2A_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L |
85365 | //SHDWL2A_IOMMU_MMIO_EXCL_BASE_0 |
85366 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 |
85367 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 |
85368 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 |
85369 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc |
85370 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L |
85371 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L |
85372 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL |
85373 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L |
85374 | //SHDWL2A_IOMMU_MMIO_EXCL_BASE_1 |
85375 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 |
85376 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 |
85377 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL |
85378 | #define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L |
85379 | //SHDWL2A_IOMMU_MMIO_EXCL_LIM_0 |
85380 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 |
85381 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc |
85382 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL |
85383 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L |
85384 | //SHDWL2A_IOMMU_MMIO_EXCL_LIM_1 |
85385 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 |
85386 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 |
85387 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL |
85388 | #define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L |
85389 | //SHDWL2A_SMI_FILTER_REGISTER_0_0 |
85390 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0 |
85391 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10 |
85392 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11 |
85393 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12 |
85394 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL |
85395 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L |
85396 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L |
85397 | #define SHDWL2A_SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L |
85398 | //SHDWL2A_SMI_FILTER_REGISTER_1_0 |
85399 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0 |
85400 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10 |
85401 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11 |
85402 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12 |
85403 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL |
85404 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L |
85405 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L |
85406 | #define SHDWL2A_SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L |
85407 | //SHDWL2A_SMI_FILTER_REGISTER_2_0 |
85408 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0 |
85409 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10 |
85410 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11 |
85411 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12 |
85412 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL |
85413 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L |
85414 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L |
85415 | #define SHDWL2A_SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L |
85416 | //SHDWL2A_SMI_FILTER_REGISTER_3_0 |
85417 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0 |
85418 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10 |
85419 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11 |
85420 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12 |
85421 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL |
85422 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L |
85423 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L |
85424 | #define SHDWL2A_SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L |
85425 | //SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0 |
85426 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 |
85427 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL |
85428 | //SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0 |
85429 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 |
85430 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL |
85431 | //SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0 |
85432 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 |
85433 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL |
85434 | //SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0 |
85435 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 |
85436 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL |
85437 | //SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0 |
85438 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 |
85439 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL |
85440 | //SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0 |
85441 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 |
85442 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL |
85443 | //SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0 |
85444 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 |
85445 | #define SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL |
85446 | //SHDWL2A_IOMMU_CAP_BASE_LO |
85447 | #define SHDWL2A_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
85448 | #define SHDWL2A_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
85449 | //SHDWL2A_IOMMU_CAP_MISC |
85450 | #define SHDWL2A_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 |
85451 | #define SHDWL2A_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L |
85452 | //SHDWL2A_IOMMU_CAP_MISC_1 |
85453 | #define SHDWL2A_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 |
85454 | #define SHDWL2A_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 |
85455 | #define SHDWL2A_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L |
85456 | #define SHDWL2A_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L |
85457 | //SHDWL2A_IOMMU_CONTROL_W |
85458 | #define SHDWL2A_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 |
85459 | #define SHDWL2A_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 |
85460 | #define SHDWL2A_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L |
85461 | #define SHDWL2A_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L |
85462 | //SHDWL2A_IOMMU_MMIO_CONTROL0_W |
85463 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 |
85464 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 |
85465 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 |
85466 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 |
85467 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 |
85468 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 |
85469 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa |
85470 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc |
85471 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 |
85472 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L |
85473 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L |
85474 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L |
85475 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L |
85476 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L |
85477 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L |
85478 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L |
85479 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L |
85480 | #define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L |
85481 | //SHDWL2A_IOMMU_MMIO_CONTROL1_W |
85482 | #define SHDWL2A_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 |
85483 | #define SHDWL2A_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 |
85484 | #define SHDWL2A_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 |
85485 | #define SHDWL2A_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL |
85486 | #define SHDWL2A_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L |
85487 | #define SHDWL2A_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L |
85488 | |
85489 | |
85490 | // addressBlock: nbio_iohub_smmu_mmio_smmummiocfg |
85491 | //SMMU_IDR0 |
85492 | #define SMMU_IDR0__S2P__SHIFT 0x0 |
85493 | #define SMMU_IDR0__S1P__SHIFT 0x1 |
85494 | #define SMMU_IDR0__TTF__SHIFT 0x2 |
85495 | #define SMMU_IDR0__COHACC__SHIFT 0x4 |
85496 | #define SMMU_IDR0__BTM__SHIFT 0x5 |
85497 | #define SMMU_IDR0__HTTU__SHIFT 0x6 |
85498 | #define SMMU_IDR0__DORMHINT__SHIFT 0x8 |
85499 | #define SMMU_IDR0__Hyp__SHIFT 0x9 |
85500 | #define SMMU_IDR0__ATS__SHIFT 0xa |
85501 | #define SMMU_IDR0__PERFCTRS__SHIFT 0xb |
85502 | #define SMMU_IDR0__ASID16__SHIFT 0xc |
85503 | #define SMMU_IDR0__MSI__SHIFT 0xd |
85504 | #define SMMU_IDR0__SEV__SHIFT 0xe |
85505 | #define SMMU_IDR0__ATOS__SHIFT 0xf |
85506 | #define SMMU_IDR0__PRI__SHIFT 0x10 |
85507 | #define SMMU_IDR0__VMW__SHIFT 0x11 |
85508 | #define SMMU_IDR0__VMID16__SHIFT 0x12 |
85509 | #define SMMU_IDR0__CD2L__SHIFT 0x13 |
85510 | #define SMMU_IDR0__VATOS__SHIFT 0x14 |
85511 | #define SMMU_IDR0__TTENDIAN__SHIFT 0x15 |
85512 | #define SMMU_IDR0__STALL_MODEL__SHIFT 0x18 |
85513 | #define SMMU_IDR0__TERM_MODEL__SHIFT 0x1a |
85514 | #define SMMU_IDR0__ST_LEVEL__SHIFT 0x1b |
85515 | #define SMMU_IDR0__RAS__SHIFT 0x1d |
85516 | #define SMMU_IDR0__S2P_MASK 0x00000001L |
85517 | #define SMMU_IDR0__S1P_MASK 0x00000002L |
85518 | #define SMMU_IDR0__TTF_MASK 0x0000000CL |
85519 | #define SMMU_IDR0__COHACC_MASK 0x00000010L |
85520 | #define SMMU_IDR0__BTM_MASK 0x00000020L |
85521 | #define SMMU_IDR0__HTTU_MASK 0x000000C0L |
85522 | #define SMMU_IDR0__DORMHINT_MASK 0x00000100L |
85523 | #define SMMU_IDR0__Hyp_MASK 0x00000200L |
85524 | #define SMMU_IDR0__ATS_MASK 0x00000400L |
85525 | #define SMMU_IDR0__PERFCTRS_MASK 0x00000800L |
85526 | #define SMMU_IDR0__ASID16_MASK 0x00001000L |
85527 | #define SMMU_IDR0__MSI_MASK 0x00002000L |
85528 | #define SMMU_IDR0__SEV_MASK 0x00004000L |
85529 | #define SMMU_IDR0__ATOS_MASK 0x00008000L |
85530 | #define SMMU_IDR0__PRI_MASK 0x00010000L |
85531 | #define SMMU_IDR0__VMW_MASK 0x00020000L |
85532 | #define SMMU_IDR0__VMID16_MASK 0x00040000L |
85533 | #define SMMU_IDR0__CD2L_MASK 0x00080000L |
85534 | #define SMMU_IDR0__VATOS_MASK 0x00100000L |
85535 | #define SMMU_IDR0__TTENDIAN_MASK 0x00600000L |
85536 | #define SMMU_IDR0__STALL_MODEL_MASK 0x03000000L |
85537 | #define SMMU_IDR0__TERM_MODEL_MASK 0x04000000L |
85538 | #define SMMU_IDR0__ST_LEVEL_MASK 0x18000000L |
85539 | #define SMMU_IDR0__RAS_MASK 0x20000000L |
85540 | //SMMU_IDR1 |
85541 | #define SMMU_IDR1__SIDSIZE__SHIFT 0x0 |
85542 | #define SMMU_IDR1__SSIDSIZE__SHIFT 0x6 |
85543 | #define SMMU_IDR1__PRIQS__SHIFT 0xb |
85544 | #define SMMU_IDR1__EVENTQS__SHIFT 0x10 |
85545 | #define SMMU_IDR1__CMDQS__SHIFT 0x15 |
85546 | #define SMMU_IDR1__ATTR_PERMS_OVR__SHIFT 0x1a |
85547 | #define SMMU_IDR1__ATTR_TYPES_OVR__SHIFT 0x1b |
85548 | #define SMMU_IDR1__REL__SHIFT 0x1c |
85549 | #define SMMU_IDR1__QUEUES_PRESET__SHIFT 0x1d |
85550 | #define SMMU_IDR1__TABLES_PRESET__SHIFT 0x1e |
85551 | #define SMMU_IDR1__SIDSIZE_MASK 0x0000003FL |
85552 | #define SMMU_IDR1__SSIDSIZE_MASK 0x000007C0L |
85553 | #define SMMU_IDR1__PRIQS_MASK 0x0000F800L |
85554 | #define SMMU_IDR1__EVENTQS_MASK 0x001F0000L |
85555 | #define SMMU_IDR1__CMDQS_MASK 0x03E00000L |
85556 | #define SMMU_IDR1__ATTR_PERMS_OVR_MASK 0x04000000L |
85557 | #define SMMU_IDR1__ATTR_TYPES_OVR_MASK 0x08000000L |
85558 | #define SMMU_IDR1__REL_MASK 0x10000000L |
85559 | #define SMMU_IDR1__QUEUES_PRESET_MASK 0x20000000L |
85560 | #define SMMU_IDR1__TABLES_PRESET_MASK 0x40000000L |
85561 | //SMMU_IDR2 |
85562 | #define SMMU_IDR2__BA_VATOS__SHIFT 0x0 |
85563 | #define SMMU_IDR2__BA_RAS__SHIFT 0xa |
85564 | #define SMMU_IDR2__BA_VATOS_MASK 0x000003FFL |
85565 | #define SMMU_IDR2__BA_RAS_MASK 0x000FFC00L |
85566 | //SMMU_IDR3 |
85567 | #define SMMU_IDR3__RESERVED__SHIFT 0x0 |
85568 | #define SMMU_IDR3__HAD__SHIFT 0x2 |
85569 | #define SMMU_IDR3__RESERVED_MASK 0x00000003L |
85570 | #define SMMU_IDR3__HAD_MASK 0x00000004L |
85571 | //SMMU_IDR4 |
85572 | #define SMMU_IDR4__IMPDEF__SHIFT 0x0 |
85573 | #define SMMU_IDR4__IMPDEF_MASK 0xFFFFFFFFL |
85574 | //SMMU_IDR5 |
85575 | #define SMMU_IDR5__OAS__SHIFT 0x0 |
85576 | #define SMMU_IDR5__GRAN4K__SHIFT 0x4 |
85577 | #define SMMU_IDR5__GRAN16K__SHIFT 0x5 |
85578 | #define SMMU_IDR5__GRAN64K__SHIFT 0x6 |
85579 | #define SMMU_IDR5__STALL_MAX__SHIFT 0x10 |
85580 | #define SMMU_IDR5__OAS_MASK 0x00000007L |
85581 | #define SMMU_IDR5__GRAN4K_MASK 0x00000010L |
85582 | #define SMMU_IDR5__GRAN16K_MASK 0x00000020L |
85583 | #define SMMU_IDR5__GRAN64K_MASK 0x00000040L |
85584 | #define SMMU_IDR5__STALL_MAX_MASK 0xFFFF0000L |
85585 | //SMMU_IIDR |
85586 | #define SMMU_IIDR__Implementer__SHIFT 0x0 |
85587 | #define SMMU_IIDR__Revision__SHIFT 0xc |
85588 | #define SMMU_IIDR__Variant__SHIFT 0x10 |
85589 | #define SMMU_IIDR__ProductID__SHIFT 0x14 |
85590 | #define SMMU_IIDR__Implementer_MASK 0x00000FFFL |
85591 | #define SMMU_IIDR__Revision_MASK 0x0000F000L |
85592 | #define SMMU_IIDR__Variant_MASK 0x000F0000L |
85593 | #define SMMU_IIDR__ProductID_MASK 0xFFF00000L |
85594 | //SMMU_AIDR |
85595 | #define SMMU_AIDR__ArchMinorRev__SHIFT 0x0 |
85596 | #define SMMU_AIDR__ArchMajorRev__SHIFT 0x4 |
85597 | #define SMMU_AIDR__ArchMinorRev_MASK 0x0000000FL |
85598 | #define SMMU_AIDR__ArchMajorRev_MASK 0x000000F0L |
85599 | //SMMU_CR0 |
85600 | #define SMMU_CR0__SMMUEN__SHIFT 0x0 |
85601 | #define SMMU_CR0__PRIQEN__SHIFT 0x1 |
85602 | #define SMMU_CR0__EVQEN__SHIFT 0x2 |
85603 | #define SMMU_CR0__CMDEN__SHIFT 0x3 |
85604 | #define SMMU_CR0__ATSCHK__SHIFT 0x4 |
85605 | #define SMMU_CR0__VMW__SHIFT 0x6 |
85606 | #define SMMU_CR0__SMMUEN_MASK 0x00000001L |
85607 | #define SMMU_CR0__PRIQEN_MASK 0x00000002L |
85608 | #define SMMU_CR0__EVQEN_MASK 0x00000004L |
85609 | #define SMMU_CR0__CMDEN_MASK 0x00000008L |
85610 | #define SMMU_CR0__ATSCHK_MASK 0x00000010L |
85611 | #define SMMU_CR0__VMW_MASK 0x000001C0L |
85612 | //SMMU_CR0ACK |
85613 | #define SMMU_CR0ACK__SMMUEN__SHIFT 0x0 |
85614 | #define SMMU_CR0ACK__PRIQEN__SHIFT 0x1 |
85615 | #define SMMU_CR0ACK__EVQEN__SHIFT 0x2 |
85616 | #define SMMU_CR0ACK__CMDEN__SHIFT 0x3 |
85617 | #define SMMU_CR0ACK__ATSCHK__SHIFT 0x4 |
85618 | #define SMMU_CR0ACK__VMW__SHIFT 0x6 |
85619 | #define SMMU_CR0ACK__SMMUEN_MASK 0x00000001L |
85620 | #define SMMU_CR0ACK__PRIQEN_MASK 0x00000002L |
85621 | #define SMMU_CR0ACK__EVQEN_MASK 0x00000004L |
85622 | #define SMMU_CR0ACK__CMDEN_MASK 0x00000008L |
85623 | #define SMMU_CR0ACK__ATSCHK_MASK 0x00000010L |
85624 | #define SMMU_CR0ACK__VMW_MASK 0x000001C0L |
85625 | //SMMU_CR2 |
85626 | #define SMMU_CR2__E2H__SHIFT 0x0 |
85627 | #define SMMU_CR2__RECINVSID__SHIFT 0x1 |
85628 | #define SMMU_CR2__PTM__SHIFT 0x2 |
85629 | #define SMMU_CR2__E2H_MASK 0x00000001L |
85630 | #define SMMU_CR2__RECINVSID_MASK 0x00000002L |
85631 | #define SMMU_CR2__PTM_MASK 0x00000004L |
85632 | //SMMU_GBPA |
85633 | #define SMMU_GBPA__ABORT__SHIFT 0x14 |
85634 | #define SMMU_GBPA__Update__SHIFT 0x1f |
85635 | #define SMMU_GBPA__ABORT_MASK 0x00100000L |
85636 | #define SMMU_GBPA__Update_MASK 0x80000000L |
85637 | //SMMU_STRTAB_BASE_HI |
85638 | #define SMMU_STRTAB_BASE_HI__STRTAB_BASE_ADDR_HI__SHIFT 0x0 |
85639 | #define SMMU_STRTAB_BASE_HI__STRTAB_RA__SHIFT 0x1e |
85640 | #define SMMU_STRTAB_BASE_HI__STRTAB_BASE_ADDR_HI_MASK 0x0000FFFFL |
85641 | #define SMMU_STRTAB_BASE_HI__STRTAB_RA_MASK 0x40000000L |
85642 | //SMMU_STRTAB_BASE_LO |
85643 | #define SMMU_STRTAB_BASE_LO__STRTAB_BASE_ADDR_LO__SHIFT 0x6 |
85644 | #define SMMU_STRTAB_BASE_LO__STRTAB_BASE_ADDR_LO_MASK 0xFFFFFFC0L |
85645 | //SMMU_STRTAB_BASE_CFG |
85646 | #define SMMU_STRTAB_BASE_CFG__STRTAB_LOG2SIZE__SHIFT 0x0 |
85647 | #define SMMU_STRTAB_BASE_CFG__STRTAB_SPLIT__SHIFT 0x6 |
85648 | #define SMMU_STRTAB_BASE_CFG__STRTAB_FMT__SHIFT 0x10 |
85649 | #define SMMU_STRTAB_BASE_CFG__STRTAB_LOG2SIZE_MASK 0x0000003FL |
85650 | #define SMMU_STRTAB_BASE_CFG__STRTAB_SPLIT_MASK 0x000007C0L |
85651 | #define SMMU_STRTAB_BASE_CFG__STRTAB_FMT_MASK 0x00030000L |
85652 | |
85653 | |
85654 | // addressBlock: nbio_iohub_nb_ioagrcfg_ioagr_cfgdec |
85655 | //IOAGR_GLUE_CG_LCLK_CTRL_0 |
85656 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4 |
85657 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16 |
85658 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17 |
85659 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18 |
85660 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19 |
85661 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a |
85662 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b |
85663 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c |
85664 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d |
85665 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e |
85666 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f |
85667 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L |
85668 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L |
85669 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L |
85670 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L |
85671 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L |
85672 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L |
85673 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L |
85674 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L |
85675 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L |
85676 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L |
85677 | #define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L |
85678 | //IOAGR_GLUE_CG_LCLK_CTRL_1 |
85679 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT 0x16 |
85680 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT 0x17 |
85681 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT 0x18 |
85682 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT 0x19 |
85683 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT 0x1a |
85684 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT 0x1b |
85685 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT 0x1c |
85686 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT 0x1d |
85687 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT 0x1e |
85688 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT 0x1f |
85689 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK 0x00400000L |
85690 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK 0x00800000L |
85691 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK 0x01000000L |
85692 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK 0x02000000L |
85693 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK 0x04000000L |
85694 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK 0x08000000L |
85695 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK 0x10000000L |
85696 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK 0x20000000L |
85697 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK 0x40000000L |
85698 | #define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK 0x80000000L |
85699 | //IOAGR_REQDECODE_OVERRIDE |
85700 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT 0x0 |
85701 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT 0x4 |
85702 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT 0x8 |
85703 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT 0xc |
85704 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT 0x10 |
85705 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT 0x14 |
85706 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT 0x18 |
85707 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT 0x1c |
85708 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK 0x0000000FL |
85709 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK 0x000000F0L |
85710 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK 0x00000F00L |
85711 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK 0x0000F000L |
85712 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK 0x000F0000L |
85713 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK 0x00F00000L |
85714 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK 0x0F000000L |
85715 | #define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK 0xF0000000L |
85716 | //IOAGR_RSPDECODE_OVERRIDE |
85717 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT 0x0 |
85718 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT 0x4 |
85719 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT 0x8 |
85720 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT 0xc |
85721 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT 0x10 |
85722 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT 0x14 |
85723 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT 0x18 |
85724 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT 0x1c |
85725 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK 0x0000000FL |
85726 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK 0x000000F0L |
85727 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK 0x00000F00L |
85728 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK 0x0000F000L |
85729 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK 0x000F0000L |
85730 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK 0x00F00000L |
85731 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK 0x0F000000L |
85732 | #define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK 0xF0000000L |
85733 | //IOAGR_USERBIT_BYPASS |
85734 | #define IOAGR_USERBIT_BYPASS__Userbit_Bypass__SHIFT 0x0 |
85735 | #define IOAGR_USERBIT_BYPASS__Userbit_Bypass_MASK 0x00000001L |
85736 | //IOAGR_SDP_PORT_CONTROL |
85737 | #define IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0 |
85738 | #define IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT 0xf |
85739 | #define IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT 0x10 |
85740 | #define IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL |
85741 | #define IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK 0x00008000L |
85742 | #define IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK 0xFFFF0000L |
85743 | //IOAGR_PERF_CNTL |
85744 | #define IOAGR_PERF_CNTL__EVENT0_SEL__SHIFT 0x0 |
85745 | #define IOAGR_PERF_CNTL__EVENT1_SEL__SHIFT 0x8 |
85746 | #define IOAGR_PERF_CNTL__EVENT2_SEL__SHIFT 0x10 |
85747 | #define IOAGR_PERF_CNTL__EVENT3_SEL__SHIFT 0x18 |
85748 | #define IOAGR_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL |
85749 | #define IOAGR_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L |
85750 | #define IOAGR_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L |
85751 | #define IOAGR_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L |
85752 | //IOAGR_PERF_COUNT0 |
85753 | #define IOAGR_PERF_COUNT0__COUNTER0__SHIFT 0x0 |
85754 | #define IOAGR_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL |
85755 | //IOAGR_PERF_COUNT0_UPPER |
85756 | #define IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0 |
85757 | #define IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL |
85758 | //IOAGR_PERF_COUNT1 |
85759 | #define IOAGR_PERF_COUNT1__COUNTER1__SHIFT 0x0 |
85760 | #define IOAGR_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL |
85761 | //IOAGR_PERF_COUNT1_UPPER |
85762 | #define IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0 |
85763 | #define IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL |
85764 | //IOAGR_PERF_COUNT2 |
85765 | #define IOAGR_PERF_COUNT2__COUNTER2__SHIFT 0x0 |
85766 | #define IOAGR_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL |
85767 | //IOAGR_PERF_COUNT2_UPPER |
85768 | #define IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0 |
85769 | #define IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL |
85770 | //IOAGR_PERF_COUNT3 |
85771 | #define IOAGR_PERF_COUNT3__COUNTER3__SHIFT 0x0 |
85772 | #define IOAGR_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL |
85773 | //IOAGR_PERF_COUNT3_UPPER |
85774 | #define IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0 |
85775 | #define IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL |
85776 | //IOAGR_PGMST_CNTL |
85777 | #define IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 |
85778 | #define IOAGR_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 |
85779 | #define IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
85780 | #define IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT 0xe |
85781 | #define IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL |
85782 | #define IOAGR_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L |
85783 | #define IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
85784 | #define IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK 0x0000C000L |
85785 | //IOAGR_PGSLV_CNTL |
85786 | #define IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
85787 | #define IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
85788 | //IOAGR_SION_S0_Client0_Req_BurstTarget_Lower |
85789 | #define IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT 0x0 |
85790 | #define IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85791 | //IOAGR_SION_S0_Client0_Req_BurstTarget_Upper |
85792 | #define IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT 0x0 |
85793 | #define IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85794 | //IOAGR_SION_S0_Client0_Req_TimeSlot_Lower |
85795 | #define IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT 0x0 |
85796 | #define IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85797 | //IOAGR_SION_S0_Client0_Req_TimeSlot_Upper |
85798 | #define IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT 0x0 |
85799 | #define IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85800 | //IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower |
85801 | #define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
85802 | #define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85803 | //IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper |
85804 | #define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
85805 | #define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85806 | //IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower |
85807 | #define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
85808 | #define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85809 | //IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper |
85810 | #define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
85811 | #define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85812 | //IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower |
85813 | #define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
85814 | #define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85815 | //IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper |
85816 | #define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
85817 | #define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85818 | //IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower |
85819 | #define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
85820 | #define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85821 | //IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper |
85822 | #define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
85823 | #define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85824 | //IOAGR_SION_S1_Client0_Req_BurstTarget_Lower |
85825 | #define IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT 0x0 |
85826 | #define IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85827 | //IOAGR_SION_S1_Client0_Req_BurstTarget_Upper |
85828 | #define IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT 0x0 |
85829 | #define IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85830 | //IOAGR_SION_S1_Client0_Req_TimeSlot_Lower |
85831 | #define IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT 0x0 |
85832 | #define IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85833 | //IOAGR_SION_S1_Client0_Req_TimeSlot_Upper |
85834 | #define IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT 0x0 |
85835 | #define IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85836 | //IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower |
85837 | #define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
85838 | #define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85839 | //IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper |
85840 | #define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
85841 | #define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85842 | //IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower |
85843 | #define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
85844 | #define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85845 | //IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper |
85846 | #define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
85847 | #define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85848 | //IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower |
85849 | #define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
85850 | #define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85851 | //IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper |
85852 | #define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
85853 | #define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85854 | //IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower |
85855 | #define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
85856 | #define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85857 | //IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper |
85858 | #define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
85859 | #define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85860 | //IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower |
85861 | #define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
85862 | #define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85863 | //IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper |
85864 | #define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
85865 | #define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85866 | //IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower |
85867 | #define IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
85868 | #define IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85869 | //IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper |
85870 | #define IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
85871 | #define IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85872 | //IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower |
85873 | #define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
85874 | #define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85875 | //IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper |
85876 | #define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
85877 | #define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85878 | //IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower |
85879 | #define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
85880 | #define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85881 | //IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper |
85882 | #define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
85883 | #define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85884 | //IOAGR_SION_S0_Client1_Req_BurstTarget_Lower |
85885 | #define IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT 0x0 |
85886 | #define IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85887 | //IOAGR_SION_S0_Client1_Req_BurstTarget_Upper |
85888 | #define IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT 0x0 |
85889 | #define IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85890 | //IOAGR_SION_S0_Client1_Req_TimeSlot_Lower |
85891 | #define IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT 0x0 |
85892 | #define IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85893 | //IOAGR_SION_S0_Client1_Req_TimeSlot_Upper |
85894 | #define IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT 0x0 |
85895 | #define IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85896 | //IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower |
85897 | #define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
85898 | #define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85899 | //IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper |
85900 | #define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
85901 | #define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85902 | //IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower |
85903 | #define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
85904 | #define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85905 | //IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper |
85906 | #define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
85907 | #define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85908 | //IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower |
85909 | #define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
85910 | #define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85911 | //IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper |
85912 | #define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
85913 | #define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85914 | //IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower |
85915 | #define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
85916 | #define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85917 | //IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper |
85918 | #define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
85919 | #define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85920 | //IOAGR_SION_S1_Client1_Req_BurstTarget_Lower |
85921 | #define IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT 0x0 |
85922 | #define IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85923 | //IOAGR_SION_S1_Client1_Req_BurstTarget_Upper |
85924 | #define IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT 0x0 |
85925 | #define IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85926 | //IOAGR_SION_S1_Client1_Req_TimeSlot_Lower |
85927 | #define IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT 0x0 |
85928 | #define IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85929 | //IOAGR_SION_S1_Client1_Req_TimeSlot_Upper |
85930 | #define IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT 0x0 |
85931 | #define IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85932 | //IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower |
85933 | #define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
85934 | #define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85935 | //IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper |
85936 | #define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
85937 | #define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85938 | //IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower |
85939 | #define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
85940 | #define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85941 | //IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper |
85942 | #define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
85943 | #define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85944 | //IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower |
85945 | #define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
85946 | #define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85947 | //IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper |
85948 | #define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
85949 | #define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85950 | //IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower |
85951 | #define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
85952 | #define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85953 | //IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper |
85954 | #define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
85955 | #define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85956 | //IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower |
85957 | #define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
85958 | #define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85959 | //IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper |
85960 | #define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
85961 | #define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85962 | //IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower |
85963 | #define IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
85964 | #define IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85965 | //IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper |
85966 | #define IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
85967 | #define IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85968 | //IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower |
85969 | #define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
85970 | #define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85971 | //IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper |
85972 | #define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
85973 | #define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85974 | //IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower |
85975 | #define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
85976 | #define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
85977 | //IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper |
85978 | #define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
85979 | #define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
85980 | //IOAGR_SION_S0_Client2_Req_BurstTarget_Lower |
85981 | #define IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT 0x0 |
85982 | #define IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85983 | //IOAGR_SION_S0_Client2_Req_BurstTarget_Upper |
85984 | #define IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT 0x0 |
85985 | #define IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85986 | //IOAGR_SION_S0_Client2_Req_TimeSlot_Lower |
85987 | #define IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT 0x0 |
85988 | #define IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
85989 | //IOAGR_SION_S0_Client2_Req_TimeSlot_Upper |
85990 | #define IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT 0x0 |
85991 | #define IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
85992 | //IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower |
85993 | #define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
85994 | #define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
85995 | //IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper |
85996 | #define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
85997 | #define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
85998 | //IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower |
85999 | #define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
86000 | #define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86001 | //IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper |
86002 | #define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
86003 | #define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86004 | //IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower |
86005 | #define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
86006 | #define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86007 | //IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper |
86008 | #define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
86009 | #define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86010 | //IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower |
86011 | #define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
86012 | #define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86013 | //IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper |
86014 | #define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
86015 | #define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86016 | //IOAGR_SION_S1_Client2_Req_BurstTarget_Lower |
86017 | #define IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT 0x0 |
86018 | #define IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86019 | //IOAGR_SION_S1_Client2_Req_BurstTarget_Upper |
86020 | #define IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT 0x0 |
86021 | #define IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86022 | //IOAGR_SION_S1_Client2_Req_TimeSlot_Lower |
86023 | #define IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT 0x0 |
86024 | #define IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86025 | //IOAGR_SION_S1_Client2_Req_TimeSlot_Upper |
86026 | #define IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT 0x0 |
86027 | #define IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86028 | //IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower |
86029 | #define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
86030 | #define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86031 | //IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper |
86032 | #define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
86033 | #define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86034 | //IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower |
86035 | #define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
86036 | #define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86037 | //IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper |
86038 | #define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
86039 | #define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86040 | //IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower |
86041 | #define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
86042 | #define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86043 | //IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper |
86044 | #define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
86045 | #define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86046 | //IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower |
86047 | #define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
86048 | #define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86049 | //IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper |
86050 | #define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
86051 | #define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86052 | //IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower |
86053 | #define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
86054 | #define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86055 | //IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper |
86056 | #define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
86057 | #define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86058 | //IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower |
86059 | #define IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
86060 | #define IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86061 | //IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper |
86062 | #define IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
86063 | #define IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86064 | //IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower |
86065 | #define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
86066 | #define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86067 | //IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper |
86068 | #define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
86069 | #define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86070 | //IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower |
86071 | #define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
86072 | #define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86073 | //IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper |
86074 | #define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
86075 | #define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86076 | //IOAGR_SION_S0_Client3_Req_BurstTarget_Lower |
86077 | #define IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT 0x0 |
86078 | #define IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86079 | //IOAGR_SION_S0_Client3_Req_BurstTarget_Upper |
86080 | #define IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT 0x0 |
86081 | #define IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86082 | //IOAGR_SION_S0_Client3_Req_TimeSlot_Lower |
86083 | #define IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT 0x0 |
86084 | #define IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86085 | //IOAGR_SION_S0_Client3_Req_TimeSlot_Upper |
86086 | #define IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT 0x0 |
86087 | #define IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86088 | //IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower |
86089 | #define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
86090 | #define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86091 | //IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper |
86092 | #define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
86093 | #define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86094 | //IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower |
86095 | #define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
86096 | #define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86097 | //IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper |
86098 | #define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
86099 | #define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86100 | //IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower |
86101 | #define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
86102 | #define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86103 | //IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper |
86104 | #define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
86105 | #define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86106 | //IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower |
86107 | #define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
86108 | #define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86109 | //IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper |
86110 | #define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
86111 | #define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86112 | //IOAGR_SION_S1_Client3_Req_BurstTarget_Lower |
86113 | #define IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT 0x0 |
86114 | #define IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86115 | //IOAGR_SION_S1_Client3_Req_BurstTarget_Upper |
86116 | #define IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT 0x0 |
86117 | #define IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86118 | //IOAGR_SION_S1_Client3_Req_TimeSlot_Lower |
86119 | #define IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT 0x0 |
86120 | #define IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86121 | //IOAGR_SION_S1_Client3_Req_TimeSlot_Upper |
86122 | #define IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT 0x0 |
86123 | #define IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86124 | //IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower |
86125 | #define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 |
86126 | #define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86127 | //IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper |
86128 | #define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 |
86129 | #define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86130 | //IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower |
86131 | #define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 |
86132 | #define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86133 | //IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper |
86134 | #define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 |
86135 | #define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86136 | //IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower |
86137 | #define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 |
86138 | #define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL |
86139 | //IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper |
86140 | #define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 |
86141 | #define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL |
86142 | //IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower |
86143 | #define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 |
86144 | #define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL |
86145 | //IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper |
86146 | #define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 |
86147 | #define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL |
86148 | //IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower |
86149 | #define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 |
86150 | #define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86151 | //IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper |
86152 | #define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 |
86153 | #define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86154 | //IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower |
86155 | #define IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT 0x0 |
86156 | #define IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86157 | //IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper |
86158 | #define IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT 0x0 |
86159 | #define IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86160 | //IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower |
86161 | #define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
86162 | #define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86163 | //IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper |
86164 | #define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
86165 | #define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86166 | //IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower |
86167 | #define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 |
86168 | #define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL |
86169 | //IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper |
86170 | #define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 |
86171 | #define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL |
86172 | //IOAGR_SION_LiveLock_WatchDog_Threshold |
86173 | #define IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold__SHIFT 0x0 |
86174 | #define IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold_MASK 0x000000FFL |
86175 | |
86176 | |
86177 | // addressBlock: nbio_sst0_sst_core_sstcorecfg |
86178 | //SST_CORE0_SST_CLOCK_CTRL |
86179 | #define SST_CORE0_SST_CLOCK_CTRL__TXCLKGATEEn__SHIFT 0x0 |
86180 | #define SST_CORE0_SST_CLOCK_CTRL__Reserved1__SHIFT 0x1 |
86181 | #define SST_CORE0_SST_CLOCK_CTRL__PCTRL_IDLE_TIME__SHIFT 0x8 |
86182 | #define SST_CORE0_SST_CLOCK_CTRL__RXCLKGATEEn__SHIFT 0x10 |
86183 | #define SST_CORE0_SST_CLOCK_CTRL__Reserved0__SHIFT 0x11 |
86184 | #define SST_CORE0_SST_CLOCK_CTRL__TXCLKGATEEn_MASK 0x00000001L |
86185 | #define SST_CORE0_SST_CLOCK_CTRL__Reserved1_MASK 0x000000FEL |
86186 | #define SST_CORE0_SST_CLOCK_CTRL__PCTRL_IDLE_TIME_MASK 0x0000FF00L |
86187 | #define SST_CORE0_SST_CLOCK_CTRL__RXCLKGATEEn_MASK 0x00010000L |
86188 | #define SST_CORE0_SST_CLOCK_CTRL__Reserved0_MASK 0xFFFE0000L |
86189 | //SST_CORE0_SST_ENABLE_CTRL |
86190 | #define SST_CORE0_SST_ENABLE_CTRL__SST_ENABLE__SHIFT 0x0 |
86191 | #define SST_CORE0_SST_ENABLE_CTRL__Reserved0__SHIFT 0x1 |
86192 | #define SST_CORE0_SST_ENABLE_CTRL__SST_RST_DONE__SHIFT 0x8 |
86193 | #define SST_CORE0_SST_ENABLE_CTRL__Reserved1__SHIFT 0x9 |
86194 | #define SST_CORE0_SST_ENABLE_CTRL__SST_ENABLE_MASK 0x00000001L |
86195 | #define SST_CORE0_SST_ENABLE_CTRL__Reserved0_MASK 0x000000FEL |
86196 | #define SST_CORE0_SST_ENABLE_CTRL__SST_RST_DONE_MASK 0x00000100L |
86197 | #define SST_CORE0_SST_ENABLE_CTRL__Reserved1_MASK 0xFFFFFE00L |
86198 | //SST_CORE0_SST_RSMU_HCID |
86199 | #define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwRev__SHIFT 0x0 |
86200 | #define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMinVer__SHIFT 0x6 |
86201 | #define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMajVer__SHIFT 0xd |
86202 | #define SST_CORE0_SST_RSMU_HCID__RESERVED__SHIFT 0x14 |
86203 | #define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwRev_MASK 0x0000003FL |
86204 | #define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMinVer_MASK 0x00001FC0L |
86205 | #define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMajVer_MASK 0x000FE000L |
86206 | #define SST_CORE0_SST_RSMU_HCID__RESERVED_MASK 0xFFF00000L |
86207 | //SST_CORE0_SST_RSMU_SIID |
86208 | #define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfRev__SHIFT 0x0 |
86209 | #define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer__SHIFT 0x6 |
86210 | #define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer__SHIFT 0xd |
86211 | #define SST_CORE0_SST_RSMU_SIID__RESERVED__SHIFT 0x14 |
86212 | #define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfRev_MASK 0x0000003FL |
86213 | #define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer_MASK 0x00001FC0L |
86214 | #define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer_MASK 0x000FE000L |
86215 | #define SST_CORE0_SST_RSMU_SIID__RESERVED_MASK 0xFFF00000L |
86216 | //SST_CORE0_SST_STATISTIC_0 |
86217 | #define SST_CORE0_SST_STATISTIC_0__RdRspCnt__SHIFT 0x0 |
86218 | #define SST_CORE0_SST_STATISTIC_0__WrRspCnt__SHIFT 0x10 |
86219 | #define SST_CORE0_SST_STATISTIC_0__RdRspCnt_MASK 0x0000FFFFL |
86220 | #define SST_CORE0_SST_STATISTIC_0__WrRspCnt_MASK 0xFFFF0000L |
86221 | //SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO |
86222 | #define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo__SHIFT 0x0 |
86223 | #define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo_MASK 0xFFFFFFFFL |
86224 | //SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI |
86225 | #define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi__SHIFT 0x0 |
86226 | #define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi_MASK 0xFFFFFFFFL |
86227 | //SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO |
86228 | #define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo__SHIFT 0x0 |
86229 | #define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo_MASK 0xFFFFFFFFL |
86230 | //SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI |
86231 | #define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi__SHIFT 0x0 |
86232 | #define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi_MASK 0xFFFFFFFFL |
86233 | //SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO |
86234 | #define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo__SHIFT 0x0 |
86235 | #define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo_MASK 0xFFFFFFFFL |
86236 | //SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI |
86237 | #define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi__SHIFT 0x0 |
86238 | #define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi_MASK 0xFFFFFFFFL |
86239 | //SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO |
86240 | #define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo__SHIFT 0x0 |
86241 | #define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo_MASK 0xFFFFFFFFL |
86242 | //SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI |
86243 | #define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi__SHIFT 0x0 |
86244 | #define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi_MASK 0xFFFFFFFFL |
86245 | //SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO |
86246 | #define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo__SHIFT 0x0 |
86247 | #define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo_MASK 0xFFFFFFFFL |
86248 | //SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI |
86249 | #define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi__SHIFT 0x0 |
86250 | #define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi_MASK 0xFFFFFFFFL |
86251 | //SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO |
86252 | #define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo__SHIFT 0x0 |
86253 | #define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo_MASK 0xFFFFFFFFL |
86254 | //SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI |
86255 | #define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi__SHIFT 0x0 |
86256 | #define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi_MASK 0xFFFFFFFFL |
86257 | //SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS |
86258 | #define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS__SHIFT 0x0 |
86259 | #define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved__SHIFT 0x8 |
86260 | #define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS_MASK 0x000000FFL |
86261 | #define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved_MASK 0xFFFFFF00L |
86262 | //SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK |
86263 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 |
86264 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 |
86265 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 |
86266 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 |
86267 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 |
86268 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 |
86269 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 |
86270 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 |
86271 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 |
86272 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 |
86273 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1__SHIFT 0xa |
86274 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0__SHIFT 0x1a |
86275 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L |
86276 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L |
86277 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L |
86278 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L |
86279 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L |
86280 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L |
86281 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L |
86282 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L |
86283 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L |
86284 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L |
86285 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1_MASK 0x0000FC00L |
86286 | #define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0_MASK 0xFC000000L |
86287 | //SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO |
86288 | #define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO__SHIFT 0x0 |
86289 | #define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86290 | //SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI |
86291 | #define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI__SHIFT 0x0 |
86292 | #define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86293 | //SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO |
86294 | #define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO__SHIFT 0x0 |
86295 | #define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86296 | //SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI |
86297 | #define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI__SHIFT 0x0 |
86298 | #define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86299 | //SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO |
86300 | #define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO__SHIFT 0x0 |
86301 | #define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86302 | //SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI |
86303 | #define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI__SHIFT 0x0 |
86304 | #define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86305 | //SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO |
86306 | #define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO__SHIFT 0x0 |
86307 | #define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86308 | //SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI |
86309 | #define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI__SHIFT 0x0 |
86310 | #define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86311 | //SST_CORE0_SST_BACKDOOR0 |
86312 | #define SST_CORE0_SST_BACKDOOR0__BACKDOOR_CODE__SHIFT 0x0 |
86313 | #define SST_CORE0_SST_BACKDOOR0__BACKDOOR_CODE_MASK 0xFFFFFFFFL |
86314 | //SST_CORE0_SST_BACKDOOR1 |
86315 | #define SST_CORE0_SST_BACKDOOR1__BACKDOOR_CFG0__SHIFT 0x0 |
86316 | #define SST_CORE0_SST_BACKDOOR1__BACKDOOR_CFG0_MASK 0xFFFFFFFFL |
86317 | //SST_CORE0_SST_BACKDOOR2 |
86318 | #define SST_CORE0_SST_BACKDOOR2__BACKDOOR_CHK0__SHIFT 0x0 |
86319 | #define SST_CORE0_SST_BACKDOOR2__BACKDOOR_CHK0_MASK 0xFFFFFFFFL |
86320 | |
86321 | |
86322 | // addressBlock: nbio_sst1_sst_core_sstcorecfg |
86323 | //SST_CORE1_SST_CLOCK_CTRL |
86324 | #define SST_CORE1_SST_CLOCK_CTRL__TXCLKGATEEn__SHIFT 0x0 |
86325 | #define SST_CORE1_SST_CLOCK_CTRL__Reserved1__SHIFT 0x1 |
86326 | #define SST_CORE1_SST_CLOCK_CTRL__PCTRL_IDLE_TIME__SHIFT 0x8 |
86327 | #define SST_CORE1_SST_CLOCK_CTRL__RXCLKGATEEn__SHIFT 0x10 |
86328 | #define SST_CORE1_SST_CLOCK_CTRL__Reserved0__SHIFT 0x11 |
86329 | #define SST_CORE1_SST_CLOCK_CTRL__TXCLKGATEEn_MASK 0x00000001L |
86330 | #define SST_CORE1_SST_CLOCK_CTRL__Reserved1_MASK 0x000000FEL |
86331 | #define SST_CORE1_SST_CLOCK_CTRL__PCTRL_IDLE_TIME_MASK 0x0000FF00L |
86332 | #define SST_CORE1_SST_CLOCK_CTRL__RXCLKGATEEn_MASK 0x00010000L |
86333 | #define SST_CORE1_SST_CLOCK_CTRL__Reserved0_MASK 0xFFFE0000L |
86334 | //SST_CORE1_SST_ENABLE_CTRL |
86335 | #define SST_CORE1_SST_ENABLE_CTRL__SST_ENABLE__SHIFT 0x0 |
86336 | #define SST_CORE1_SST_ENABLE_CTRL__Reserved0__SHIFT 0x1 |
86337 | #define SST_CORE1_SST_ENABLE_CTRL__SST_RST_DONE__SHIFT 0x8 |
86338 | #define SST_CORE1_SST_ENABLE_CTRL__Reserved1__SHIFT 0x9 |
86339 | #define SST_CORE1_SST_ENABLE_CTRL__SST_ENABLE_MASK 0x00000001L |
86340 | #define SST_CORE1_SST_ENABLE_CTRL__Reserved0_MASK 0x000000FEL |
86341 | #define SST_CORE1_SST_ENABLE_CTRL__SST_RST_DONE_MASK 0x00000100L |
86342 | #define SST_CORE1_SST_ENABLE_CTRL__Reserved1_MASK 0xFFFFFE00L |
86343 | //SST_CORE1_SST_RSMU_HCID |
86344 | #define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwRev__SHIFT 0x0 |
86345 | #define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMinVer__SHIFT 0x6 |
86346 | #define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMajVer__SHIFT 0xd |
86347 | #define SST_CORE1_SST_RSMU_HCID__RESERVED__SHIFT 0x14 |
86348 | #define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwRev_MASK 0x0000003FL |
86349 | #define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMinVer_MASK 0x00001FC0L |
86350 | #define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMajVer_MASK 0x000FE000L |
86351 | #define SST_CORE1_SST_RSMU_HCID__RESERVED_MASK 0xFFF00000L |
86352 | //SST_CORE1_SST_RSMU_SIID |
86353 | #define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfRev__SHIFT 0x0 |
86354 | #define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer__SHIFT 0x6 |
86355 | #define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer__SHIFT 0xd |
86356 | #define SST_CORE1_SST_RSMU_SIID__RESERVED__SHIFT 0x14 |
86357 | #define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfRev_MASK 0x0000003FL |
86358 | #define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer_MASK 0x00001FC0L |
86359 | #define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer_MASK 0x000FE000L |
86360 | #define SST_CORE1_SST_RSMU_SIID__RESERVED_MASK 0xFFF00000L |
86361 | //SST_CORE1_SST_STATISTIC_0 |
86362 | #define SST_CORE1_SST_STATISTIC_0__RdRspCnt__SHIFT 0x0 |
86363 | #define SST_CORE1_SST_STATISTIC_0__WrRspCnt__SHIFT 0x10 |
86364 | #define SST_CORE1_SST_STATISTIC_0__RdRspCnt_MASK 0x0000FFFFL |
86365 | #define SST_CORE1_SST_STATISTIC_0__WrRspCnt_MASK 0xFFFF0000L |
86366 | //SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO |
86367 | #define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo__SHIFT 0x0 |
86368 | #define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo_MASK 0xFFFFFFFFL |
86369 | //SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI |
86370 | #define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi__SHIFT 0x0 |
86371 | #define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi_MASK 0xFFFFFFFFL |
86372 | //SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO |
86373 | #define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo__SHIFT 0x0 |
86374 | #define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo_MASK 0xFFFFFFFFL |
86375 | //SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI |
86376 | #define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi__SHIFT 0x0 |
86377 | #define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi_MASK 0xFFFFFFFFL |
86378 | //SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO |
86379 | #define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo__SHIFT 0x0 |
86380 | #define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo_MASK 0xFFFFFFFFL |
86381 | //SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI |
86382 | #define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi__SHIFT 0x0 |
86383 | #define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi_MASK 0xFFFFFFFFL |
86384 | //SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO |
86385 | #define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo__SHIFT 0x0 |
86386 | #define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo_MASK 0xFFFFFFFFL |
86387 | //SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI |
86388 | #define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi__SHIFT 0x0 |
86389 | #define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi_MASK 0xFFFFFFFFL |
86390 | //SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO |
86391 | #define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo__SHIFT 0x0 |
86392 | #define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo_MASK 0xFFFFFFFFL |
86393 | //SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI |
86394 | #define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi__SHIFT 0x0 |
86395 | #define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi_MASK 0xFFFFFFFFL |
86396 | //SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO |
86397 | #define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo__SHIFT 0x0 |
86398 | #define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo_MASK 0xFFFFFFFFL |
86399 | //SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI |
86400 | #define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi__SHIFT 0x0 |
86401 | #define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi_MASK 0xFFFFFFFFL |
86402 | //SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS |
86403 | #define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS__SHIFT 0x0 |
86404 | #define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved__SHIFT 0x8 |
86405 | #define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS_MASK 0x000000FFL |
86406 | #define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved_MASK 0xFFFFFF00L |
86407 | //SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK |
86408 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 |
86409 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 |
86410 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 |
86411 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 |
86412 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 |
86413 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 |
86414 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 |
86415 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 |
86416 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 |
86417 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 |
86418 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1__SHIFT 0xa |
86419 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0__SHIFT 0x1a |
86420 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L |
86421 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L |
86422 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L |
86423 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L |
86424 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L |
86425 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L |
86426 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L |
86427 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L |
86428 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L |
86429 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L |
86430 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1_MASK 0x0000FC00L |
86431 | #define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0_MASK 0xFC000000L |
86432 | //SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO |
86433 | #define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO__SHIFT 0x0 |
86434 | #define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86435 | //SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI |
86436 | #define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI__SHIFT 0x0 |
86437 | #define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86438 | //SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO |
86439 | #define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO__SHIFT 0x0 |
86440 | #define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86441 | //SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI |
86442 | #define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI__SHIFT 0x0 |
86443 | #define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86444 | //SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO |
86445 | #define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO__SHIFT 0x0 |
86446 | #define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86447 | //SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI |
86448 | #define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI__SHIFT 0x0 |
86449 | #define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86450 | //SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO |
86451 | #define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO__SHIFT 0x0 |
86452 | #define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL |
86453 | //SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI |
86454 | #define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI__SHIFT 0x0 |
86455 | #define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL |
86456 | //SST_CORE1_SST_BACKDOOR0 |
86457 | #define SST_CORE1_SST_BACKDOOR0__BACKDOOR_CODE__SHIFT 0x0 |
86458 | #define SST_CORE1_SST_BACKDOOR0__BACKDOOR_CODE_MASK 0xFFFFFFFFL |
86459 | //SST_CORE1_SST_BACKDOOR1 |
86460 | #define SST_CORE1_SST_BACKDOOR1__BACKDOOR_CFG0__SHIFT 0x0 |
86461 | #define SST_CORE1_SST_BACKDOOR1__BACKDOOR_CFG0_MASK 0xFFFFFFFFL |
86462 | //SST_CORE1_SST_BACKDOOR2 |
86463 | #define SST_CORE1_SST_BACKDOOR2__BACKDOOR_CHK0__SHIFT 0x0 |
86464 | #define SST_CORE1_SST_BACKDOOR2__BACKDOOR_CHK0_MASK 0xFFFFFFFFL |
86465 | |
86466 | |
86467 | // addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg |
86468 | //IOMMU_MMIO_DEVTBL_BASE_0 |
86469 | #define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 |
86470 | #define IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT 0x9 |
86471 | #define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT 0xc |
86472 | #define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL |
86473 | #define IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK 0x00000E00L |
86474 | #define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK 0xFFFFF000L |
86475 | //IOMMU_MMIO_DEVTBL_BASE_1 |
86476 | #define IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT 0x0 |
86477 | #define IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT 0x14 |
86478 | #define IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK 0x000FFFFFL |
86479 | #define IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK 0xFFF00000L |
86480 | //IOMMU_MMIO_CMD_BASE_0 |
86481 | #define IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT 0x0 |
86482 | #define IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT 0xc |
86483 | #define IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK 0x00000FFFL |
86484 | #define IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK 0xFFFFF000L |
86485 | //IOMMU_MMIO_CMD_BASE_1 |
86486 | #define IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT 0x0 |
86487 | #define IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT 0x14 |
86488 | #define IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT 0x18 |
86489 | #define IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT 0x1c |
86490 | #define IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK 0x000FFFFFL |
86491 | #define IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK 0x00F00000L |
86492 | #define IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK 0x0F000000L |
86493 | #define IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK 0xF0000000L |
86494 | //IOMMU_MMIO_EVENT_BASE_0 |
86495 | #define IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT 0x0 |
86496 | #define IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT 0xc |
86497 | #define IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK 0x00000FFFL |
86498 | #define IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK 0xFFFFF000L |
86499 | //IOMMU_MMIO_EVENT_BASE_1 |
86500 | #define IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT 0x0 |
86501 | #define IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT 0x14 |
86502 | #define IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT 0x18 |
86503 | #define IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT 0x1c |
86504 | #define IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK 0x000FFFFFL |
86505 | #define IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK 0x00F00000L |
86506 | #define IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK 0x0F000000L |
86507 | #define IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK 0xF0000000L |
86508 | //IOMMU_MMIO_CNTRL_0 |
86509 | #define IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 |
86510 | #define IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 |
86511 | #define IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 |
86512 | #define IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 |
86513 | #define IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 |
86514 | #define IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 |
86515 | #define IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 |
86516 | #define IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 |
86517 | #define IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa |
86518 | #define IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb |
86519 | #define IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc |
86520 | #define IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd |
86521 | #define IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT 0xe |
86522 | #define IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf |
86523 | #define IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 |
86524 | #define IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 |
86525 | #define IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 |
86526 | #define IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16 |
86527 | #define IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18 |
86528 | #define IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19 |
86529 | #define IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT 0x1c |
86530 | #define IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT 0x1d |
86531 | #define IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT 0x1e |
86532 | #define IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L |
86533 | #define IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L |
86534 | #define IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L |
86535 | #define IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L |
86536 | #define IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L |
86537 | #define IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L |
86538 | #define IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L |
86539 | #define IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L |
86540 | #define IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L |
86541 | #define IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L |
86542 | #define IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L |
86543 | #define IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L |
86544 | #define IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK 0x00004000L |
86545 | #define IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L |
86546 | #define IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L |
86547 | #define IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L |
86548 | #define IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L |
86549 | #define IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L |
86550 | #define IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L |
86551 | #define IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L |
86552 | #define IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK 0x10000000L |
86553 | #define IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK 0x20000000L |
86554 | #define IOMMU_MMIO_CNTRL_0__PPRQ_MASK 0xC0000000L |
86555 | //IOMMU_MMIO_CNTRL_1 |
86556 | #define IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT 0x0 |
86557 | #define IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 |
86558 | #define IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT 0x4 |
86559 | #define IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5 |
86560 | #define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT 0x7 |
86561 | #define IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT 0x8 |
86562 | #define IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT 0x9 |
86563 | #define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT 0xa |
86564 | #define IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT 0xb |
86565 | #define IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT 0xc |
86566 | #define IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd |
86567 | #define IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT 0xe |
86568 | #define IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT 0x10 |
86569 | #define IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT 0x11 |
86570 | #define IOMMU_MMIO_CNTRL_1__EVENTQ_MASK 0x00000003L |
86571 | #define IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL |
86572 | #define IOMMU_MMIO_CNTRL_1__Reserved1_MASK 0x00000010L |
86573 | #define IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L |
86574 | #define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK 0x00000080L |
86575 | #define IOMMU_MMIO_CNTRL_1__MARC_en_MASK 0x00000100L |
86576 | #define IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK 0x00000200L |
86577 | #define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK 0x00000400L |
86578 | #define IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK 0x00000800L |
86579 | #define IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK 0x00001000L |
86580 | #define IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L |
86581 | #define IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK 0x0000C000L |
86582 | #define IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK 0x00010000L |
86583 | #define IOMMU_MMIO_CNTRL_1__Reserved0_MASK 0xFFFE0000L |
86584 | //IOMMU_MMIO_EXCL_BASE_0 |
86585 | #define IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 |
86586 | #define IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 |
86587 | #define IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 |
86588 | #define IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc |
86589 | #define IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L |
86590 | #define IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L |
86591 | #define IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL |
86592 | #define IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L |
86593 | //IOMMU_MMIO_EXCL_BASE_1 |
86594 | #define IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 |
86595 | #define IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 |
86596 | #define IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL |
86597 | #define IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L |
86598 | //IOMMU_MMIO_EXCL_LIM_0 |
86599 | #define IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 |
86600 | #define IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc |
86601 | #define IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL |
86602 | #define IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L |
86603 | //IOMMU_MMIO_EXCL_LIM_1 |
86604 | #define IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 |
86605 | #define IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 |
86606 | #define IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL |
86607 | #define IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L |
86608 | //IOMMU_MMIO_EFR_0 |
86609 | #define IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT 0x0 |
86610 | #define IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT 0x1 |
86611 | #define IOMMU_MMIO_EFR_0__XT_SUP__SHIFT 0x2 |
86612 | #define IOMMU_MMIO_EFR_0__NX_SUP__SHIFT 0x3 |
86613 | #define IOMMU_MMIO_EFR_0__GT_SUP__SHIFT 0x4 |
86614 | #define IOMMU_MMIO_EFR_0__Reserved__SHIFT 0x5 |
86615 | #define IOMMU_MMIO_EFR_0__IA_SUP__SHIFT 0x6 |
86616 | #define IOMMU_MMIO_EFR_0__GA_SUP__SHIFT 0x7 |
86617 | #define IOMMU_MMIO_EFR_0__HE_SUP__SHIFT 0x8 |
86618 | #define IOMMU_MMIO_EFR_0__PC_SUP__SHIFT 0x9 |
86619 | #define IOMMU_MMIO_EFR_0__HATS__SHIFT 0xa |
86620 | #define IOMMU_MMIO_EFR_0__GATS__SHIFT 0xc |
86621 | #define IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT 0xe |
86622 | #define IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT 0x10 |
86623 | #define IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT 0x12 |
86624 | #define IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT 0x15 |
86625 | #define IOMMU_MMIO_EFR_0__PPRF__SHIFT 0x18 |
86626 | #define IOMMU_MMIO_EFR_0__GAF__SHIFT 0x1a |
86627 | #define IOMMU_MMIO_EFR_0__EVENTF__SHIFT 0x1c |
86628 | #define IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT 0x1e |
86629 | #define IOMMU_MMIO_EFR_0__Reserved1__SHIFT 0x1f |
86630 | #define IOMMU_MMIO_EFR_0__PREF_SUP_MASK 0x00000001L |
86631 | #define IOMMU_MMIO_EFR_0__PPR_SUP_MASK 0x00000002L |
86632 | #define IOMMU_MMIO_EFR_0__XT_SUP_MASK 0x00000004L |
86633 | #define IOMMU_MMIO_EFR_0__NX_SUP_MASK 0x00000008L |
86634 | #define IOMMU_MMIO_EFR_0__GT_SUP_MASK 0x00000010L |
86635 | #define IOMMU_MMIO_EFR_0__Reserved_MASK 0x00000020L |
86636 | #define IOMMU_MMIO_EFR_0__IA_SUP_MASK 0x00000040L |
86637 | #define IOMMU_MMIO_EFR_0__GA_SUP_MASK 0x00000080L |
86638 | #define IOMMU_MMIO_EFR_0__HE_SUP_MASK 0x00000100L |
86639 | #define IOMMU_MMIO_EFR_0__PC_SUP_MASK 0x00000200L |
86640 | #define IOMMU_MMIO_EFR_0__HATS_MASK 0x00000C00L |
86641 | #define IOMMU_MMIO_EFR_0__GATS_MASK 0x00003000L |
86642 | #define IOMMU_MMIO_EFR_0__GLX_SUP_MASK 0x0000C000L |
86643 | #define IOMMU_MMIO_EFR_0__SMIF_SUP_MASK 0x00030000L |
86644 | #define IOMMU_MMIO_EFR_0__SMIF_RC_MASK 0x001C0000L |
86645 | #define IOMMU_MMIO_EFR_0__GAM_SUP_MASK 0x00E00000L |
86646 | #define IOMMU_MMIO_EFR_0__PPRF_MASK 0x03000000L |
86647 | #define IOMMU_MMIO_EFR_0__GAF_MASK 0x0C000000L |
86648 | #define IOMMU_MMIO_EFR_0__EVENTF_MASK 0x30000000L |
86649 | #define IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK 0x40000000L |
86650 | #define IOMMU_MMIO_EFR_0__Reserved1_MASK 0x80000000L |
86651 | //IOMMU_MMIO_EFR_1 |
86652 | #define IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT 0x0 |
86653 | #define IOMMU_MMIO_EFR_1__Reserved1__SHIFT 0x4 |
86654 | #define IOMMU_MMIO_EFR_1__US_SUP__SHIFT 0x5 |
86655 | #define IOMMU_MMIO_EFR_1__DTE_seg__SHIFT 0x6 |
86656 | #define IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT 0x8 |
86657 | #define IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT 0x9 |
86658 | #define IOMMU_MMIO_EFR_1__MARCnum__SHIFT 0xa |
86659 | #define IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT 0xc |
86660 | #define IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT 0xd |
86661 | #define IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT 0xe |
86662 | #define IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT 0xf |
86663 | #define IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT 0x10 |
86664 | #define IOMMU_MMIO_EFR_1__HA_SUP__SHIFT 0x11 |
86665 | #define IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT 0x12 |
86666 | #define IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT 0x13 |
86667 | #define IOMMU_MMIO_EFR_1__HD_SUP__SHIFT 0x14 |
86668 | #define IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT 0x15 |
86669 | #define IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT 0x16 |
86670 | #define IOMMU_MMIO_EFR_1__Reserved0__SHIFT 0x17 |
86671 | #define IOMMU_MMIO_EFR_1__PAS_MAX_MASK 0x0000000FL |
86672 | #define IOMMU_MMIO_EFR_1__Reserved1_MASK 0x00000010L |
86673 | #define IOMMU_MMIO_EFR_1__US_SUP_MASK 0x00000020L |
86674 | #define IOMMU_MMIO_EFR_1__DTE_seg_MASK 0x000000C0L |
86675 | #define IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK 0x00000100L |
86676 | #define IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK 0x00000200L |
86677 | #define IOMMU_MMIO_EFR_1__MARCnum_MASK 0x00000C00L |
86678 | #define IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK 0x00001000L |
86679 | #define IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK 0x00002000L |
86680 | #define IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK 0x00004000L |
86681 | #define IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK 0x00008000L |
86682 | #define IOMMU_MMIO_EFR_1__GIo_SUP_MASK 0x00010000L |
86683 | #define IOMMU_MMIO_EFR_1__HA_SUP_MASK 0x00020000L |
86684 | #define IOMMU_MMIO_EFR_1__EPH_SUP_MASK 0x00040000L |
86685 | #define IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK 0x00080000L |
86686 | #define IOMMU_MMIO_EFR_1__HD_SUP_MASK 0x00100000L |
86687 | #define IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK 0x00200000L |
86688 | #define IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK 0x00400000L |
86689 | #define IOMMU_MMIO_EFR_1__Reserved0_MASK 0xFF800000L |
86690 | //IOMMU_MMIO_PPR_BASE_0 |
86691 | #define IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT 0x0 |
86692 | #define IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT 0xc |
86693 | #define IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK 0x00000FFFL |
86694 | #define IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK 0xFFFFF000L |
86695 | //IOMMU_MMIO_PPR_BASE_1 |
86696 | #define IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT 0x0 |
86697 | #define IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT 0x14 |
86698 | #define IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT 0x18 |
86699 | #define IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT 0x1c |
86700 | #define IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK 0x000FFFFFL |
86701 | #define IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK 0x00F00000L |
86702 | #define IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK 0x0F000000L |
86703 | #define IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK 0xF0000000L |
86704 | //IOMMU_MMIO_HW_ERR_UPPER_0 |
86705 | #define IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0 |
86706 | #define IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL |
86707 | //IOMMU_MMIO_HW_ERR_UPPER_1 |
86708 | #define IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0 |
86709 | #define IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c |
86710 | #define IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL |
86711 | #define IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L |
86712 | //IOMMU_MMIO_HW_ERR_LOWER_0 |
86713 | #define IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0 |
86714 | #define IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL |
86715 | //IOMMU_MMIO_HW_ERR_LOWER_1 |
86716 | #define IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0 |
86717 | #define IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL |
86718 | //IOMMU_MMIO_HW_ERR_STATUS_0 |
86719 | #define IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT 0x0 |
86720 | #define IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT 0x1 |
86721 | #define IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT 0x2 |
86722 | #define IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK 0x00000001L |
86723 | #define IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK 0x00000002L |
86724 | #define IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFFCL |
86725 | //IOMMU_MMIO_HW_ERR_STATUS_1 |
86726 | #define IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT 0x0 |
86727 | #define IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL |
86728 | //SMI_FILTER_REGISTER_0_0 |
86729 | #define SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0 |
86730 | #define SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10 |
86731 | #define SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11 |
86732 | #define SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12 |
86733 | #define SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL |
86734 | #define SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L |
86735 | #define SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L |
86736 | #define SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L |
86737 | //SMI_FILTER_REGISTER_0_1 |
86738 | #define SMI_FILTER_REGISTER_0_1__Reserved__SHIFT 0x0 |
86739 | #define SMI_FILTER_REGISTER_0_1__Reserved_MASK 0xFFFFFFFFL |
86740 | //SMI_FILTER_REGISTER_1_0 |
86741 | #define SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0 |
86742 | #define SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10 |
86743 | #define SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11 |
86744 | #define SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12 |
86745 | #define SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL |
86746 | #define SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L |
86747 | #define SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L |
86748 | #define SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L |
86749 | //SMI_FILTER_REGISTER_1_1 |
86750 | #define SMI_FILTER_REGISTER_1_1__Reserved__SHIFT 0x0 |
86751 | #define SMI_FILTER_REGISTER_1_1__Reserved_MASK 0xFFFFFFFFL |
86752 | //SMI_FILTER_REGISTER_2_0 |
86753 | #define SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0 |
86754 | #define SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10 |
86755 | #define SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11 |
86756 | #define SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12 |
86757 | #define SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL |
86758 | #define SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L |
86759 | #define SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L |
86760 | #define SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L |
86761 | //SMI_FILTER_REGISTER_2_1 |
86762 | #define SMI_FILTER_REGISTER_2_1__Reserved__SHIFT 0x0 |
86763 | #define SMI_FILTER_REGISTER_2_1__Reserved_MASK 0xFFFFFFFFL |
86764 | //SMI_FILTER_REGISTER_3_0 |
86765 | #define SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0 |
86766 | #define SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10 |
86767 | #define SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11 |
86768 | #define SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12 |
86769 | #define SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL |
86770 | #define SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L |
86771 | #define SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L |
86772 | #define SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L |
86773 | //SMI_FILTER_REGISTER_3_1 |
86774 | #define SMI_FILTER_REGISTER_3_1__Reserved__SHIFT 0x0 |
86775 | #define SMI_FILTER_REGISTER_3_1__Reserved_MASK 0xFFFFFFFFL |
86776 | //IOMMU_MMIO_GA_LOG_BASE_0 |
86777 | #define IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT 0xc |
86778 | #define IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK 0xFFFFF000L |
86779 | //IOMMU_MMIO_GA_LOG_BASE_1 |
86780 | #define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT 0x0 |
86781 | #define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT 0x18 |
86782 | #define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK 0x000FFFFFL |
86783 | #define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK 0x0F000000L |
86784 | //IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 |
86785 | #define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT 0x3 |
86786 | #define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK 0xFFFFFFF8L |
86787 | //IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 |
86788 | #define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT 0x0 |
86789 | #define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK 0x000FFFFFL |
86790 | //IOMMU_MMIO_PPR_B_BASE_0 |
86791 | #define IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT 0x0 |
86792 | #define IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT 0xc |
86793 | #define IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK 0x00000FFFL |
86794 | #define IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK 0xFFFFF000L |
86795 | //IOMMU_MMIO_PPR_B_BASE_1 |
86796 | #define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT 0x0 |
86797 | #define IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT 0x14 |
86798 | #define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT 0x18 |
86799 | #define IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT 0x1c |
86800 | #define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK 0x000FFFFFL |
86801 | #define IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK 0x00F00000L |
86802 | #define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK 0x0F000000L |
86803 | #define IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK 0xF0000000L |
86804 | //IOMMU_MMIO_EVENT_B_BASE_0 |
86805 | #define IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT 0x0 |
86806 | #define IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT 0xc |
86807 | #define IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK 0x00000FFFL |
86808 | #define IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK 0xFFFFF000L |
86809 | //IOMMU_MMIO_EVENT_B_BASE_1 |
86810 | #define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT 0x0 |
86811 | #define IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT 0x14 |
86812 | #define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT 0x18 |
86813 | #define IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT 0x1c |
86814 | #define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK 0x000FFFFFL |
86815 | #define IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK 0x00F00000L |
86816 | #define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK 0x0F000000L |
86817 | #define IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK 0xF0000000L |
86818 | //IOMMU_MMIO_DEVTBL_1_BASE_0 |
86819 | #define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 |
86820 | #define IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT 0x9 |
86821 | #define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT 0xc |
86822 | #define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL |
86823 | #define IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK 0x00000E00L |
86824 | #define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK 0xFFFFF000L |
86825 | //IOMMU_MMIO_DEVTBL_1_BASE_1 |
86826 | #define IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT 0x0 |
86827 | #define IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT 0x14 |
86828 | #define IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK 0x000FFFFFL |
86829 | #define IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK 0xFFF00000L |
86830 | //IOMMU_MMIO_DEVTBL_2_BASE_0 |
86831 | #define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 |
86832 | #define IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT 0x9 |
86833 | #define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT 0xc |
86834 | #define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL |
86835 | #define IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK 0x00000E00L |
86836 | #define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK 0xFFFFF000L |
86837 | //IOMMU_MMIO_DEVTBL_2_BASE_1 |
86838 | #define IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT 0x0 |
86839 | #define IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT 0x14 |
86840 | #define IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK 0x000FFFFFL |
86841 | #define IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK 0xFFF00000L |
86842 | //IOMMU_MMIO_DEVTBL_3_BASE_0 |
86843 | #define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 |
86844 | #define IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT 0x9 |
86845 | #define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT 0xc |
86846 | #define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL |
86847 | #define IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK 0x00000E00L |
86848 | #define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK 0xFFFFF000L |
86849 | //IOMMU_MMIO_DEVTBL_3_BASE_1 |
86850 | #define IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT 0x0 |
86851 | #define IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT 0x14 |
86852 | #define IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK 0x000FFFFFL |
86853 | #define IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK 0xFFF00000L |
86854 | //IOMMU_MMIO_DEVTBL_4_BASE_0 |
86855 | #define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 |
86856 | #define IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT 0x9 |
86857 | #define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT 0xc |
86858 | #define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL |
86859 | #define IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK 0x00000E00L |
86860 | #define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK 0xFFFFF000L |
86861 | //IOMMU_MMIO_DEVTBL_4_BASE_1 |
86862 | #define IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT 0x0 |
86863 | #define IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT 0x14 |
86864 | #define IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK 0x000FFFFFL |
86865 | #define IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK 0xFFF00000L |
86866 | //IOMMU_MMIO_DEVTBL_5_BASE_0 |
86867 | #define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 |
86868 | #define IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT 0x9 |
86869 | #define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT 0xc |
86870 | #define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL |
86871 | #define IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK 0x00000E00L |
86872 | #define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK 0xFFFFF000L |
86873 | //IOMMU_MMIO_DEVTBL_5_BASE_1 |
86874 | #define IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT 0x0 |
86875 | #define IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT 0x14 |
86876 | #define IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK 0x000FFFFFL |
86877 | #define IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK 0xFFF00000L |
86878 | //IOMMU_MMIO_DEVTBL_6_BASE_0 |
86879 | #define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 |
86880 | #define IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT 0x9 |
86881 | #define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT 0xc |
86882 | #define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL |
86883 | #define IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK 0x00000E00L |
86884 | #define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK 0xFFFFF000L |
86885 | //IOMMU_MMIO_DEVTBL_6_BASE_1 |
86886 | #define IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT 0x0 |
86887 | #define IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT 0x14 |
86888 | #define IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK 0x000FFFFFL |
86889 | #define IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK 0xFFF00000L |
86890 | //IOMMU_MMIO_DEVTBL_7_BASE_0 |
86891 | #define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 |
86892 | #define IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT 0x9 |
86893 | #define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT 0xc |
86894 | #define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL |
86895 | #define IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK 0x00000E00L |
86896 | #define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK 0xFFFFF000L |
86897 | //IOMMU_MMIO_DEVTBL_7_BASE_1 |
86898 | #define IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT 0x0 |
86899 | #define IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT 0x14 |
86900 | #define IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK 0x000FFFFFL |
86901 | #define IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK 0xFFF00000L |
86902 | //IOMMU_MMIO_DSFX |
86903 | #define IOMMU_MMIO_DSFX__DSFXSup__SHIFT 0x0 |
86904 | #define IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT 0x18 |
86905 | #define IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT 0x1c |
86906 | #define IOMMU_MMIO_DSFX__DSFXSup_MASK 0x00FFFFFFL |
86907 | #define IOMMU_MMIO_DSFX__REVISION_MINOR_MASK 0x0F000000L |
86908 | #define IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK 0xF0000000L |
86909 | //IOMMU_MMIO_DSCX |
86910 | #define IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT 0x0 |
86911 | #define IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT 0x18 |
86912 | #define IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT 0x1c |
86913 | #define IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK 0x00FFFFFFL |
86914 | #define IOMMU_MMIO_DSCX__REVISION_MINOR_MASK 0x0F000000L |
86915 | #define IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK 0xF0000000L |
86916 | //IOMMU_MMIO_DSSX |
86917 | #define IOMMU_MMIO_DSSX__DSSX_status__SHIFT 0x0 |
86918 | #define IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT 0x18 |
86919 | #define IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT 0x1c |
86920 | #define IOMMU_MMIO_DSSX__DSSX_status_MASK 0x00FFFFFFL |
86921 | #define IOMMU_MMIO_DSSX__REVISION_MINOR_MASK 0x0F000000L |
86922 | #define IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK 0xF0000000L |
86923 | //IOMMU_MMIO_CAP_MISC |
86924 | #define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 |
86925 | #define IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT 0x5 |
86926 | #define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b |
86927 | #define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL |
86928 | #define IOMMU_MMIO_CAP_MISC__Reserved1_MASK 0x07FFFFE0L |
86929 | #define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L |
86930 | //IOMMU_MMIO_CAP_MISC_1 |
86931 | #define IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 |
86932 | #define IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT 0x5 |
86933 | #define IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL |
86934 | #define IOMMU_MMIO_CAP_MISC_1__Reserved_MASK 0xFFFFFFE0L |
86935 | //IOMMU_MMIO_MSI_CAP |
86936 | #define IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 |
86937 | #define IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 |
86938 | #define IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT 0x10 |
86939 | #define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 |
86940 | #define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 |
86941 | #define IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT 0x17 |
86942 | #define IOMMU_MMIO_MSI_CAP__Reserved__SHIFT 0x18 |
86943 | #define IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL |
86944 | #define IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L |
86945 | #define IOMMU_MMIO_MSI_CAP__MSI_EN_MASK 0x00010000L |
86946 | #define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L |
86947 | #define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L |
86948 | #define IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK 0x00800000L |
86949 | #define IOMMU_MMIO_MSI_CAP__Reserved_MASK 0xFF000000L |
86950 | //IOMMU_MMIO_MSI_ADDR_LO |
86951 | #define IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT 0x0 |
86952 | #define IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 |
86953 | #define IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK 0x00000003L |
86954 | #define IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL |
86955 | //IOMMU_MMIO_MSI_ADDR_HI |
86956 | #define IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 |
86957 | #define IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL |
86958 | //IOMMU_MMIO_MSI_DATA |
86959 | #define IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT 0x0 |
86960 | #define IOMMU_MMIO_MSI_DATA__Reserved__SHIFT 0x10 |
86961 | #define IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL |
86962 | #define IOMMU_MMIO_MSI_DATA__Reserved_MASK 0xFFFF0000L |
86963 | //IOMMU_MMIO_MSI_MAPPING_CAP |
86964 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 |
86965 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 |
86966 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 |
86967 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 |
86968 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 |
86969 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b |
86970 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL |
86971 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L |
86972 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L |
86973 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L |
86974 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L |
86975 | #define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L |
86976 | //IOMMU_MMIO_CONTROL_W |
86977 | #define IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT 0x0 |
86978 | #define IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT 0xd |
86979 | #define IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT 0xe |
86980 | #define IOMMU_MMIO_CONTROL_W__Reserved0_MASK 0x00001FFFL |
86981 | #define IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK 0x00002000L |
86982 | #define IOMMU_MMIO_CONTROL_W__Reserved1_MASK 0xFFFFC000L |
86983 | //IOMMU_MARC_BASE_LO_0 |
86984 | #define IOMMU_MARC_BASE_LO_0__Reserved__SHIFT 0x0 |
86985 | #define IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT 0xc |
86986 | #define IOMMU_MARC_BASE_LO_0__Reserved_MASK 0x00000FFFL |
86987 | #define IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK 0xFFFFF000L |
86988 | //IOMMU_MARC_BASE_HI_0 |
86989 | #define IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT 0x0 |
86990 | #define IOMMU_MARC_BASE_HI_0__Reserved__SHIFT 0x14 |
86991 | #define IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK 0x000FFFFFL |
86992 | #define IOMMU_MARC_BASE_HI_0__Reserved_MASK 0xFFF00000L |
86993 | //IOMMU_MARC_RELOC_LO_0 |
86994 | #define IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT 0x0 |
86995 | #define IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT 0x1 |
86996 | #define IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT 0x2 |
86997 | #define IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT 0xc |
86998 | #define IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK 0x00000001L |
86999 | #define IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK 0x00000002L |
87000 | #define IOMMU_MARC_RELOC_LO_0__Reserved_MASK 0x00000FFCL |
87001 | #define IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK 0xFFFFF000L |
87002 | //IOMMU_MARC_RELOC_HI_0 |
87003 | #define IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT 0x0 |
87004 | #define IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT 0x14 |
87005 | #define IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK 0x000FFFFFL |
87006 | #define IOMMU_MARC_RELOC_HI_0__Reserved_MASK 0xFFF00000L |
87007 | //IOMMU_MARC_LEN_LO_0 |
87008 | #define IOMMU_MARC_LEN_LO_0__Reserved__SHIFT 0x0 |
87009 | #define IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT 0xc |
87010 | #define IOMMU_MARC_LEN_LO_0__Reserved_MASK 0x00000FFFL |
87011 | #define IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK 0xFFFFF000L |
87012 | //IOMMU_MARC_LEN_HI_0 |
87013 | #define IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT 0x0 |
87014 | #define IOMMU_MARC_LEN_HI_0__Reserved__SHIFT 0x14 |
87015 | #define IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK 0x000FFFFFL |
87016 | #define IOMMU_MARC_LEN_HI_0__Reserved_MASK 0xFFF00000L |
87017 | //IOMMU_MARC_BASE_LO_1 |
87018 | #define IOMMU_MARC_BASE_LO_1__Reserved__SHIFT 0x0 |
87019 | #define IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT 0xc |
87020 | #define IOMMU_MARC_BASE_LO_1__Reserved_MASK 0x00000FFFL |
87021 | #define IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK 0xFFFFF000L |
87022 | //IOMMU_MARC_BASE_HI_1 |
87023 | #define IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT 0x0 |
87024 | #define IOMMU_MARC_BASE_HI_1__Reserved__SHIFT 0x14 |
87025 | #define IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK 0x000FFFFFL |
87026 | #define IOMMU_MARC_BASE_HI_1__Reserved_MASK 0xFFF00000L |
87027 | //IOMMU_MARC_RELOC_LO_1 |
87028 | #define IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT 0x0 |
87029 | #define IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT 0x1 |
87030 | #define IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT 0x2 |
87031 | #define IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT 0xc |
87032 | #define IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK 0x00000001L |
87033 | #define IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK 0x00000002L |
87034 | #define IOMMU_MARC_RELOC_LO_1__Reserved_MASK 0x00000FFCL |
87035 | #define IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK 0xFFFFF000L |
87036 | //IOMMU_MARC_RELOC_HI_1 |
87037 | #define IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT 0x0 |
87038 | #define IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT 0x14 |
87039 | #define IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK 0x000FFFFFL |
87040 | #define IOMMU_MARC_RELOC_HI_1__Reserved_MASK 0xFFF00000L |
87041 | //IOMMU_MARC_LEN_LO_1 |
87042 | #define IOMMU_MARC_LEN_LO_1__Reserved__SHIFT 0x0 |
87043 | #define IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT 0xc |
87044 | #define IOMMU_MARC_LEN_LO_1__Reserved_MASK 0x00000FFFL |
87045 | #define IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK 0xFFFFF000L |
87046 | //IOMMU_MARC_LEN_HI_1 |
87047 | #define IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT 0x0 |
87048 | #define IOMMU_MARC_LEN_HI_1__Reserved__SHIFT 0x14 |
87049 | #define IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK 0x000FFFFFL |
87050 | #define IOMMU_MARC_LEN_HI_1__Reserved_MASK 0xFFF00000L |
87051 | //IOMMU_MARC_BASE_LO_2 |
87052 | #define IOMMU_MARC_BASE_LO_2__Reserved__SHIFT 0x0 |
87053 | #define IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT 0xc |
87054 | #define IOMMU_MARC_BASE_LO_2__Reserved_MASK 0x00000FFFL |
87055 | #define IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK 0xFFFFF000L |
87056 | //IOMMU_MARC_BASE_HI_2 |
87057 | #define IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT 0x0 |
87058 | #define IOMMU_MARC_BASE_HI_2__Reserved__SHIFT 0x14 |
87059 | #define IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK 0x000FFFFFL |
87060 | #define IOMMU_MARC_BASE_HI_2__Reserved_MASK 0xFFF00000L |
87061 | //IOMMU_MARC_RELOC_LO_2 |
87062 | #define IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT 0x0 |
87063 | #define IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT 0x1 |
87064 | #define IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT 0x2 |
87065 | #define IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT 0xc |
87066 | #define IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK 0x00000001L |
87067 | #define IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK 0x00000002L |
87068 | #define IOMMU_MARC_RELOC_LO_2__Reserved_MASK 0x00000FFCL |
87069 | #define IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK 0xFFFFF000L |
87070 | //IOMMU_MARC_RELOC_HI_2 |
87071 | #define IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT 0x0 |
87072 | #define IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT 0x14 |
87073 | #define IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK 0x000FFFFFL |
87074 | #define IOMMU_MARC_RELOC_HI_2__Reserved_MASK 0xFFF00000L |
87075 | //IOMMU_MARC_LEN_LO_2 |
87076 | #define IOMMU_MARC_LEN_LO_2__Reserved__SHIFT 0x0 |
87077 | #define IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT 0xc |
87078 | #define IOMMU_MARC_LEN_LO_2__Reserved_MASK 0x00000FFFL |
87079 | #define IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK 0xFFFFF000L |
87080 | //IOMMU_MARC_LEN_HI_2 |
87081 | #define IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT 0x0 |
87082 | #define IOMMU_MARC_LEN_HI_2__Reserved__SHIFT 0x14 |
87083 | #define IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK 0x000FFFFFL |
87084 | #define IOMMU_MARC_LEN_HI_2__Reserved_MASK 0xFFF00000L |
87085 | //IOMMU_MARC_BASE_LO_3 |
87086 | #define IOMMU_MARC_BASE_LO_3__Reserved__SHIFT 0x0 |
87087 | #define IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT 0xc |
87088 | #define IOMMU_MARC_BASE_LO_3__Reserved_MASK 0x00000FFFL |
87089 | #define IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK 0xFFFFF000L |
87090 | //IOMMU_MARC_BASE_HI_3 |
87091 | #define IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT 0x0 |
87092 | #define IOMMU_MARC_BASE_HI_3__Reserved__SHIFT 0x14 |
87093 | #define IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK 0x000FFFFFL |
87094 | #define IOMMU_MARC_BASE_HI_3__Reserved_MASK 0xFFF00000L |
87095 | //IOMMU_MARC_RELOC_LO_3 |
87096 | #define IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT 0x0 |
87097 | #define IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT 0x1 |
87098 | #define IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT 0x2 |
87099 | #define IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT 0xc |
87100 | #define IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK 0x00000001L |
87101 | #define IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK 0x00000002L |
87102 | #define IOMMU_MARC_RELOC_LO_3__Reserved_MASK 0x00000FFCL |
87103 | #define IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK 0xFFFFF000L |
87104 | //IOMMU_MARC_RELOC_HI_3 |
87105 | #define IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT 0x0 |
87106 | #define IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT 0x14 |
87107 | #define IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK 0x000FFFFFL |
87108 | #define IOMMU_MARC_RELOC_HI_3__Reserved_MASK 0xFFF00000L |
87109 | //IOMMU_MARC_LEN_LO_3 |
87110 | #define IOMMU_MARC_LEN_LO_3__Reserved__SHIFT 0x0 |
87111 | #define IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT 0xc |
87112 | #define IOMMU_MARC_LEN_LO_3__Reserved_MASK 0x00000FFFL |
87113 | #define IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK 0xFFFFF000L |
87114 | //IOMMU_MARC_LEN_HI_3 |
87115 | #define IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT 0x0 |
87116 | #define IOMMU_MARC_LEN_HI_3__Reserved__SHIFT 0x14 |
87117 | #define IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK 0x000FFFFFL |
87118 | #define IOMMU_MARC_LEN_HI_3__Reserved_MASK 0xFFF00000L |
87119 | //IOMMU_MMIO_CMD_BUF_HDPTR_0 |
87120 | #define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
87121 | #define IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT 0x4 |
87122 | #define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
87123 | #define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
87124 | #define IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK 0x0007FFF0L |
87125 | #define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
87126 | //IOMMU_MMIO_CMD_BUF_HDPTR_1 |
87127 | #define IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
87128 | #define IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87129 | //IOMMU_MMIO_CMD_BUF_TAILPTR_0 |
87130 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
87131 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT 0x4 |
87132 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
87133 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
87134 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK 0x0007FFF0L |
87135 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
87136 | //IOMMU_MMIO_CMD_BUF_TAILPTR_1 |
87137 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
87138 | #define IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87139 | //IOMMU_MMIO_EVENT_BUF_HDPTR_0 |
87140 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
87141 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT 0x4 |
87142 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
87143 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
87144 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK 0x0007FFF0L |
87145 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
87146 | //IOMMU_MMIO_EVENT_BUF_HDPTR_1 |
87147 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
87148 | #define IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87149 | //IOMMU_MMIO_EVENT_BUF_TAILPTR_0 |
87150 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
87151 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT 0x4 |
87152 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
87153 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
87154 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK 0x0007FFF0L |
87155 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
87156 | //IOMMU_MMIO_EVENT_BUF_TAILPTR_1 |
87157 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
87158 | #define IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87159 | //IOMMU_MMIO_STATUS_0 |
87160 | #define IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT 0x0 |
87161 | #define IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT 0x1 |
87162 | #define IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT 0x2 |
87163 | #define IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT 0x3 |
87164 | #define IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT 0x4 |
87165 | #define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT 0x5 |
87166 | #define IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT 0x6 |
87167 | #define IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT 0x7 |
87168 | #define IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT 0x8 |
87169 | #define IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT 0x9 |
87170 | #define IOMMU_MMIO_STATUS_0__GA_INT__SHIFT 0xa |
87171 | #define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT 0xb |
87172 | #define IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT 0xc |
87173 | #define IOMMU_MMIO_STATUS_0__Reserved0__SHIFT 0xd |
87174 | #define IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT 0xf |
87175 | #define IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT 0x10 |
87176 | #define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT 0x11 |
87177 | #define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT 0x12 |
87178 | #define IOMMU_MMIO_STATUS_0__Reserved1__SHIFT 0x13 |
87179 | #define IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK 0x00000001L |
87180 | #define IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK 0x00000002L |
87181 | #define IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK 0x00000004L |
87182 | #define IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK 0x00000008L |
87183 | #define IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK 0x00000010L |
87184 | #define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK 0x00000020L |
87185 | #define IOMMU_MMIO_STATUS_0__PPR_INT_MASK 0x00000040L |
87186 | #define IOMMU_MMIO_STATUS_0__PPR_RUN_MASK 0x00000080L |
87187 | #define IOMMU_MMIO_STATUS_0__GA_RUN_MASK 0x00000100L |
87188 | #define IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK 0x00000200L |
87189 | #define IOMMU_MMIO_STATUS_0__GA_INT_MASK 0x00000400L |
87190 | #define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK 0x00000800L |
87191 | #define IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK 0x00001000L |
87192 | #define IOMMU_MMIO_STATUS_0__Reserved0_MASK 0x00006000L |
87193 | #define IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK 0x00008000L |
87194 | #define IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK 0x00010000L |
87195 | #define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK 0x00020000L |
87196 | #define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK 0x00040000L |
87197 | #define IOMMU_MMIO_STATUS_0__Reserved1_MASK 0xFFF80000L |
87198 | //IOMMU_MMIO_STATUS_1 |
87199 | #define IOMMU_MMIO_STATUS_1__Reserved0__SHIFT 0x0 |
87200 | #define IOMMU_MMIO_STATUS_1__Reserved0_MASK 0xFFFFFFFFL |
87201 | //IOMMU_MMIO_PPR_BUF_HDPTR_0 |
87202 | #define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
87203 | #define IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT 0x4 |
87204 | #define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
87205 | #define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
87206 | #define IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK 0x0007FFF0L |
87207 | #define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
87208 | //IOMMU_MMIO_PPR_BUF_HDPTR_1 |
87209 | #define IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
87210 | #define IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87211 | //IOMMU_MMIO_PPR_BUF_TAILPTR_0 |
87212 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
87213 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT 0x4 |
87214 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
87215 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
87216 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK 0x0007FFF0L |
87217 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
87218 | //IOMMU_MMIO_PPR_BUF_TAILPTR_1 |
87219 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
87220 | #define IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87221 | //IOMMU_MMIO_GA_BUF_HDPTR_0 |
87222 | #define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
87223 | #define IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT 0x3 |
87224 | #define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT 0x10 |
87225 | #define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK 0x00000007L |
87226 | #define IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK 0x0000FFF8L |
87227 | #define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK 0xFFFF0000L |
87228 | //IOMMU_MMIO_GA_BUF_HDPTR_1 |
87229 | #define IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
87230 | #define IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87231 | //IOMMU_MMIO_GA_BUF_TAILPTR_0 |
87232 | #define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
87233 | #define IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT 0x3 |
87234 | #define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT 0x10 |
87235 | #define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK 0x00000007L |
87236 | #define IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK 0x0000FFF8L |
87237 | #define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK 0xFFFF0000L |
87238 | //IOMMU_MMIO_GA_BUF_TAILPTR_1 |
87239 | #define IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
87240 | #define IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87241 | //IOMMU_MMIO_PPR_B_BUF_HDPTR_0 |
87242 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
87243 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT 0x4 |
87244 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
87245 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
87246 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK 0x0007FFF0L |
87247 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
87248 | //IOMMU_MMIO_PPR_B_BUF_HDPTR_1 |
87249 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
87250 | #define IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87251 | //IOMMU_MMIO_PPR_B_BUF_TAILPTR_0 |
87252 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
87253 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT 0x4 |
87254 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
87255 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
87256 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK 0x0007FFF0L |
87257 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
87258 | //IOMMU_MMIO_PPR_B_BUF_TAILPTR_1 |
87259 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
87260 | #define IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87261 | //IOMMU_MMIO_EVENT_B_BUF_HDPTR_0 |
87262 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 |
87263 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT 0x4 |
87264 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 |
87265 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL |
87266 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK 0x0007FFF0L |
87267 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L |
87268 | //IOMMU_MMIO_EVENT_B_BUF_HDPTR_1 |
87269 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 |
87270 | #define IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87271 | //IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 |
87272 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 |
87273 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT 0x4 |
87274 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 |
87275 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL |
87276 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK 0x0007FFF0L |
87277 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L |
87278 | //IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 |
87279 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 |
87280 | #define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL |
87281 | //IOMMU_MMIO_PPR_AUTORESP_0 |
87282 | #define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT 0x0 |
87283 | #define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT 0x4 |
87284 | #define IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT 0x5 |
87285 | #define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK 0x0000000FL |
87286 | #define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK 0x00000010L |
87287 | #define IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK 0xFFFFFFE0L |
87288 | //IOMMU_MMIO_PPR_OVERFLOW_EARLY_0 |
87289 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT 0x0 |
87290 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf |
87291 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT 0x1e |
87292 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT 0x1f |
87293 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK 0x00007FFFL |
87294 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L |
87295 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK 0x40000000L |
87296 | #define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK 0x80000000L |
87297 | //IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 |
87298 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT 0x0 |
87299 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf |
87300 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT 0x1e |
87301 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT 0x1f |
87302 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK 0x00007FFFL |
87303 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L |
87304 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK 0x40000000L |
87305 | #define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK 0x80000000L |
87306 | //IOMMU_MMIO_COUNTER_CONFIG_0 |
87307 | #define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT 0x0 |
87308 | #define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT 0x7 |
87309 | #define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT 0xb |
87310 | #define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT 0xc |
87311 | #define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT 0x12 |
87312 | #define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK 0x0000007FL |
87313 | #define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK 0x00000780L |
87314 | #define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK 0x00000800L |
87315 | #define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK 0x0003F000L |
87316 | #define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK 0xFFFC0000L |
87317 | //IOMMU_MMIO_COUNTER_CONFIG_1 |
87318 | #define IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT 0x0 |
87319 | #define IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK 0xFFFFFFFFL |
87320 | //IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 |
87321 | #define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 |
87322 | #define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL |
87323 | //IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 |
87324 | #define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 |
87325 | #define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL |
87326 | //IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 |
87327 | #define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 |
87328 | #define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL |
87329 | //IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 |
87330 | #define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 |
87331 | #define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL |
87332 | //IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 |
87333 | #define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 |
87334 | #define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL |
87335 | //IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 |
87336 | #define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 |
87337 | #define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL |
87338 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 |
87339 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT 0x0 |
87340 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK 0xFFFFFFFFL |
87341 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 |
87342 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT 0x0 |
87343 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT 0x10 |
87344 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK 0x0000FFFFL |
87345 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK 0xFFFF0000L |
87346 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 |
87347 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 |
87348 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 |
87349 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e |
87350 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f |
87351 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL |
87352 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
87353 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L |
87354 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L |
87355 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 |
87356 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT 0x0 |
87357 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL |
87358 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 |
87359 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 |
87360 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
87361 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f |
87362 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL |
87363 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
87364 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L |
87365 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 |
87366 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 |
87367 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
87368 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL |
87369 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
87370 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 |
87371 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 |
87372 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
87373 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f |
87374 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL |
87375 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
87376 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L |
87377 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 |
87378 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 |
87379 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
87380 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL |
87381 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
87382 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 |
87383 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 |
87384 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 |
87385 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f |
87386 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL |
87387 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
87388 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L |
87389 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 |
87390 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 |
87391 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 |
87392 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL |
87393 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
87394 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 |
87395 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT 0x0 |
87396 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK 0xFFFFFFFFL |
87397 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 |
87398 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT 0x0 |
87399 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT 0x14 |
87400 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT 0x1f |
87401 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK 0x000FFFFFL |
87402 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK 0x7FF00000L |
87403 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK 0x80000000L |
87404 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 |
87405 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT 0x0 |
87406 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK 0xFFFFFFFFL |
87407 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 |
87408 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT 0x0 |
87409 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT 0x10 |
87410 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK 0x0000FFFFL |
87411 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK 0xFFFF0000L |
87412 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 |
87413 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 |
87414 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 |
87415 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e |
87416 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f |
87417 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL |
87418 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
87419 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L |
87420 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L |
87421 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 |
87422 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT 0x0 |
87423 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL |
87424 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 |
87425 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 |
87426 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
87427 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f |
87428 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL |
87429 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
87430 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L |
87431 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 |
87432 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 |
87433 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
87434 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL |
87435 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
87436 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 |
87437 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 |
87438 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
87439 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f |
87440 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL |
87441 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
87442 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L |
87443 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 |
87444 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 |
87445 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
87446 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL |
87447 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
87448 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 |
87449 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 |
87450 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 |
87451 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f |
87452 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL |
87453 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
87454 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L |
87455 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 |
87456 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 |
87457 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 |
87458 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL |
87459 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
87460 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 |
87461 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT 0x0 |
87462 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK 0xFFFFFFFFL |
87463 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 |
87464 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT 0x0 |
87465 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT 0x14 |
87466 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT 0x1f |
87467 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK 0x000FFFFFL |
87468 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK 0x7FF00000L |
87469 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK 0x80000000L |
87470 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 |
87471 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT 0x0 |
87472 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK 0xFFFFFFFFL |
87473 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 |
87474 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT 0x0 |
87475 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT 0x10 |
87476 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK 0x0000FFFFL |
87477 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK 0xFFFF0000L |
87478 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 |
87479 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 |
87480 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 |
87481 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e |
87482 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f |
87483 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL |
87484 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
87485 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L |
87486 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L |
87487 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 |
87488 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT 0x0 |
87489 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL |
87490 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 |
87491 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 |
87492 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
87493 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f |
87494 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL |
87495 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
87496 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L |
87497 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 |
87498 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 |
87499 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
87500 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL |
87501 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
87502 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 |
87503 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 |
87504 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
87505 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f |
87506 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL |
87507 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
87508 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L |
87509 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 |
87510 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 |
87511 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
87512 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL |
87513 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
87514 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 |
87515 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 |
87516 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 |
87517 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f |
87518 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL |
87519 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
87520 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L |
87521 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 |
87522 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 |
87523 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 |
87524 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL |
87525 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
87526 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 |
87527 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT 0x0 |
87528 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK 0xFFFFFFFFL |
87529 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 |
87530 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT 0x0 |
87531 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT 0x14 |
87532 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT 0x1f |
87533 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK 0x000FFFFFL |
87534 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK 0x7FF00000L |
87535 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK 0x80000000L |
87536 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 |
87537 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT 0x0 |
87538 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK 0xFFFFFFFFL |
87539 | //IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 |
87540 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT 0x0 |
87541 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT 0x10 |
87542 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK 0x0000FFFFL |
87543 | #define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK 0xFFFF0000L |
87544 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 |
87545 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 |
87546 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 |
87547 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e |
87548 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f |
87549 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL |
87550 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
87551 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L |
87552 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L |
87553 | //IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 |
87554 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT 0x0 |
87555 | #define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL |
87556 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 |
87557 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 |
87558 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
87559 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f |
87560 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL |
87561 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
87562 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L |
87563 | //IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 |
87564 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 |
87565 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
87566 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL |
87567 | #define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
87568 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 |
87569 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 |
87570 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
87571 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f |
87572 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL |
87573 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
87574 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L |
87575 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 |
87576 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 |
87577 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
87578 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL |
87579 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
87580 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 |
87581 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 |
87582 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 |
87583 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f |
87584 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL |
87585 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
87586 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L |
87587 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 |
87588 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 |
87589 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 |
87590 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL |
87591 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
87592 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 |
87593 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT 0x0 |
87594 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK 0xFFFFFFFFL |
87595 | //IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 |
87596 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT 0x0 |
87597 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT 0x14 |
87598 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT 0x1f |
87599 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK 0x000FFFFFL |
87600 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK 0x7FF00000L |
87601 | #define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK 0x80000000L |
87602 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 |
87603 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT 0x0 |
87604 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK 0xFFFFFFFFL |
87605 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 |
87606 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT 0x0 |
87607 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT 0x10 |
87608 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK 0x0000FFFFL |
87609 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK 0xFFFF0000L |
87610 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 |
87611 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 |
87612 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 |
87613 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e |
87614 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f |
87615 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL |
87616 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L |
87617 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L |
87618 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L |
87619 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 |
87620 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT 0x0 |
87621 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL |
87622 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 |
87623 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 |
87624 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
87625 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f |
87626 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL |
87627 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
87628 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L |
87629 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 |
87630 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 |
87631 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
87632 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL |
87633 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
87634 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 |
87635 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 |
87636 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
87637 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f |
87638 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL |
87639 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
87640 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L |
87641 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 |
87642 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 |
87643 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
87644 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL |
87645 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
87646 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 |
87647 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 |
87648 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 |
87649 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f |
87650 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL |
87651 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L |
87652 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L |
87653 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 |
87654 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 |
87655 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 |
87656 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL |
87657 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L |
87658 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 |
87659 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT 0x0 |
87660 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK 0xFFFFFFFFL |
87661 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 |
87662 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT 0x0 |
87663 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT 0x14 |
87664 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT 0x1f |
87665 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK 0x000FFFFFL |
87666 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK 0x7FF00000L |
87667 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK 0x80000000L |
87668 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 |
87669 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT 0x0 |
87670 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK 0xFFFFFFFFL |
87671 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 |
87672 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT 0x0 |
87673 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT 0x10 |
87674 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK 0x0000FFFFL |
87675 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK 0xFFFF0000L |
87676 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 |
87677 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 |
87678 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 |
87679 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e |
87680 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f |
87681 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL |
87682 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L |
87683 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L |
87684 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L |
87685 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 |
87686 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT 0x0 |
87687 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL |
87688 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 |
87689 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 |
87690 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
87691 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f |
87692 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL |
87693 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
87694 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L |
87695 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 |
87696 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 |
87697 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
87698 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL |
87699 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
87700 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 |
87701 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 |
87702 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
87703 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f |
87704 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL |
87705 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
87706 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L |
87707 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 |
87708 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 |
87709 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
87710 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL |
87711 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
87712 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 |
87713 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 |
87714 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 |
87715 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f |
87716 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL |
87717 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L |
87718 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L |
87719 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 |
87720 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 |
87721 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 |
87722 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL |
87723 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L |
87724 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 |
87725 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT 0x0 |
87726 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK 0xFFFFFFFFL |
87727 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 |
87728 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT 0x0 |
87729 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT 0x14 |
87730 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT 0x1f |
87731 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK 0x000FFFFFL |
87732 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK 0x7FF00000L |
87733 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK 0x80000000L |
87734 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 |
87735 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT 0x0 |
87736 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK 0xFFFFFFFFL |
87737 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 |
87738 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT 0x0 |
87739 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT 0x10 |
87740 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK 0x0000FFFFL |
87741 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK 0xFFFF0000L |
87742 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 |
87743 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 |
87744 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 |
87745 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e |
87746 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f |
87747 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL |
87748 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L |
87749 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L |
87750 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L |
87751 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 |
87752 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT 0x0 |
87753 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL |
87754 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 |
87755 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 |
87756 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
87757 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f |
87758 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL |
87759 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
87760 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L |
87761 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 |
87762 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 |
87763 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
87764 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL |
87765 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
87766 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 |
87767 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 |
87768 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
87769 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f |
87770 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL |
87771 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
87772 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L |
87773 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 |
87774 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 |
87775 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
87776 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL |
87777 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
87778 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 |
87779 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 |
87780 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 |
87781 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f |
87782 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL |
87783 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L |
87784 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L |
87785 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 |
87786 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 |
87787 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 |
87788 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL |
87789 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L |
87790 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 |
87791 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT 0x0 |
87792 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK 0xFFFFFFFFL |
87793 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 |
87794 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT 0x0 |
87795 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT 0x14 |
87796 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT 0x1f |
87797 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK 0x000FFFFFL |
87798 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK 0x7FF00000L |
87799 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK 0x80000000L |
87800 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 |
87801 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT 0x0 |
87802 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK 0xFFFFFFFFL |
87803 | //IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 |
87804 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT 0x0 |
87805 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT 0x10 |
87806 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK 0x0000FFFFL |
87807 | #define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK 0xFFFF0000L |
87808 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 |
87809 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 |
87810 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 |
87811 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e |
87812 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f |
87813 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL |
87814 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L |
87815 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L |
87816 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L |
87817 | //IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 |
87818 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT 0x0 |
87819 | #define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL |
87820 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 |
87821 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 |
87822 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
87823 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f |
87824 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL |
87825 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
87826 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L |
87827 | //IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 |
87828 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 |
87829 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
87830 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL |
87831 | #define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
87832 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 |
87833 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 |
87834 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
87835 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f |
87836 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL |
87837 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
87838 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L |
87839 | //IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 |
87840 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 |
87841 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
87842 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL |
87843 | #define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
87844 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 |
87845 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 |
87846 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 |
87847 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f |
87848 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL |
87849 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L |
87850 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L |
87851 | //IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 |
87852 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 |
87853 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 |
87854 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL |
87855 | #define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L |
87856 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 |
87857 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT 0x0 |
87858 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK 0xFFFFFFFFL |
87859 | //IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 |
87860 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT 0x0 |
87861 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT 0x14 |
87862 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT 0x1f |
87863 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK 0x000FFFFFL |
87864 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK 0x7FF00000L |
87865 | #define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK 0x80000000L |
87866 | |
87867 | |
87868 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
87869 | //NB_NBCFG2_NB_VENDOR_ID |
87870 | #define NB_NBCFG2_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
87871 | #define NB_NBCFG2_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
87872 | //NB_NBCFG2_NB_DEVICE_ID |
87873 | #define NB_NBCFG2_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
87874 | #define NB_NBCFG2_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
87875 | //NB_NBCFG2_NB_COMMAND |
87876 | #define NB_NBCFG2_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
87877 | #define NB_NBCFG2_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
87878 | #define NB_NBCFG2_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
87879 | #define NB_NBCFG2_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
87880 | #define NB_NBCFG2_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
87881 | #define NB_NBCFG2_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
87882 | //NB_NBCFG2_NB_STATUS |
87883 | #define NB_NBCFG2_NB_STATUS__CAP_LIST__SHIFT 0x4 |
87884 | #define NB_NBCFG2_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
87885 | #define NB_NBCFG2_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
87886 | #define NB_NBCFG2_NB_STATUS__CAP_LIST_MASK 0x0010L |
87887 | #define NB_NBCFG2_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
87888 | #define NB_NBCFG2_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
87889 | //NB_NBCFG2_NB_REVISION_ID |
87890 | #define NB_NBCFG2_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
87891 | #define NB_NBCFG2_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
87892 | #define NB_NBCFG2_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
87893 | #define NB_NBCFG2_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
87894 | //NB_NBCFG2_NB_REGPROG_INF |
87895 | #define NB_NBCFG2_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 |
87896 | #define NB_NBCFG2_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL |
87897 | //NB_NBCFG2_NB_SUB_CLASS |
87898 | #define NB_NBCFG2_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
87899 | #define NB_NBCFG2_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
87900 | //NB_NBCFG2_NB_BASE_CODE |
87901 | #define NB_NBCFG2_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
87902 | #define NB_NBCFG2_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
87903 | //NB_NBCFG2_NB_CACHE_LINE |
87904 | #define NB_NBCFG2_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
87905 | #define NB_NBCFG2_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
87906 | //NB_NBCFG2_NB_LATENCY |
87907 | #define NB_NBCFG2_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
87908 | #define NB_NBCFG2_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL |
87909 | //NB_NBCFG2_NB_HEADER |
87910 | #define NB_NBCFG2_NB_HEADER__HEADER_TYPE__SHIFT 0x0 |
87911 | #define NB_NBCFG2_NB_HEADER__DEVICE_TYPE__SHIFT 0x7 |
87912 | #define NB_NBCFG2_NB_HEADER__HEADER_TYPE_MASK 0x7FL |
87913 | #define NB_NBCFG2_NB_HEADER__DEVICE_TYPE_MASK 0x80L |
87914 | //NB_NBCFG2_NB_ADAPTER_ID |
87915 | #define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
87916 | #define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
87917 | #define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
87918 | #define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
87919 | //NB_NBCFG2_NB_CAPABILITIES_PTR |
87920 | #define NB_NBCFG2_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
87921 | #define NB_NBCFG2_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
87922 | //NB_NBCFG2_NB_HEADER_W |
87923 | #define NB_NBCFG2_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7 |
87924 | #define NB_NBCFG2_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L |
87925 | //NB_NBCFG2_NB_PCI_CTRL |
87926 | #define NB_NBCFG2_NB_PCI_CTRL__PMEDis__SHIFT 0x4 |
87927 | #define NB_NBCFG2_NB_PCI_CTRL__SErrDis__SHIFT 0x5 |
87928 | #define NB_NBCFG2_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 |
87929 | #define NB_NBCFG2_NB_PCI_CTRL__HPDis__SHIFT 0x1a |
87930 | #define NB_NBCFG2_NB_PCI_CTRL__PMEDis_MASK 0x00000010L |
87931 | #define NB_NBCFG2_NB_PCI_CTRL__SErrDis_MASK 0x00000020L |
87932 | #define NB_NBCFG2_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L |
87933 | #define NB_NBCFG2_NB_PCI_CTRL__HPDis_MASK 0x04000000L |
87934 | //NB_NBCFG2_NB_ADAPTER_ID_W |
87935 | #define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
87936 | #define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
87937 | #define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
87938 | #define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
87939 | //NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0 |
87940 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0 |
87941 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL |
87942 | //NB_NBCFG2_NB_SMN_INDEX_0 |
87943 | #define NB_NBCFG2_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0 |
87944 | #define NB_NBCFG2_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL |
87945 | //NB_NBCFG2_NB_SMN_DATA_0 |
87946 | #define NB_NBCFG2_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0 |
87947 | #define NB_NBCFG2_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL |
87948 | //NB_NBCFG2_NBCFG_SCRATCH_0 |
87949 | #define NB_NBCFG2_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 |
87950 | #define NB_NBCFG2_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL |
87951 | //NB_NBCFG2_NBCFG_SCRATCH_1 |
87952 | #define NB_NBCFG2_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 |
87953 | #define NB_NBCFG2_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL |
87954 | //NB_NBCFG2_NBCFG_SCRATCH_2 |
87955 | #define NB_NBCFG2_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 |
87956 | #define NB_NBCFG2_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL |
87957 | //NB_NBCFG2_NBCFG_SCRATCH_3 |
87958 | #define NB_NBCFG2_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 |
87959 | #define NB_NBCFG2_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL |
87960 | //NB_NBCFG2_NBCFG_SCRATCH_4 |
87961 | #define NB_NBCFG2_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 |
87962 | #define NB_NBCFG2_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL |
87963 | //NB_NBCFG2_NB_PCI_ARB |
87964 | #define NB_NBCFG2_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
87965 | #define NB_NBCFG2_NB_PCI_ARB__PMEMode__SHIFT 0x8 |
87966 | #define NB_NBCFG2_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 |
87967 | #define NB_NBCFG2_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa |
87968 | #define NB_NBCFG2_NB_PCI_ARB__PMETarget__SHIFT 0x10 |
87969 | #define NB_NBCFG2_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
87970 | #define NB_NBCFG2_NB_PCI_ARB__PMEMode_MASK 0x00000100L |
87971 | #define NB_NBCFG2_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L |
87972 | #define NB_NBCFG2_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L |
87973 | #define NB_NBCFG2_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L |
87974 | //NB_NBCFG2_NB_DRAM_SLOT1_BASE |
87975 | #define NB_NBCFG2_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 |
87976 | #define NB_NBCFG2_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L |
87977 | //NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1 |
87978 | #define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0 |
87979 | #define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
87980 | #define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L |
87981 | #define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
87982 | //NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1 |
87983 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0 |
87984 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL |
87985 | //NB_NBCFG2_NB_SMN_INDEX_1 |
87986 | #define NB_NBCFG2_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0 |
87987 | #define NB_NBCFG2_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL |
87988 | //NB_NBCFG2_NB_SMN_DATA_1 |
87989 | #define NB_NBCFG2_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0 |
87990 | #define NB_NBCFG2_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL |
87991 | //NB_NBCFG2_NB_INDEX_DATA_MUTEX0 |
87992 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 |
87993 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f |
87994 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL |
87995 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L |
87996 | //NB_NBCFG2_NB_INDEX_DATA_MUTEX1 |
87997 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 |
87998 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f |
87999 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL |
88000 | #define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L |
88001 | //NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2 |
88002 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0 |
88003 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL |
88004 | //NB_NBCFG2_NB_SMN_INDEX_2 |
88005 | #define NB_NBCFG2_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0 |
88006 | #define NB_NBCFG2_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL |
88007 | //NB_NBCFG2_NB_SMN_DATA_2 |
88008 | #define NB_NBCFG2_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0 |
88009 | #define NB_NBCFG2_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL |
88010 | //NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3 |
88011 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0 |
88012 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL |
88013 | //NB_NBCFG2_NB_SMN_INDEX_3 |
88014 | #define NB_NBCFG2_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0 |
88015 | #define NB_NBCFG2_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL |
88016 | //NB_NBCFG2_NB_SMN_DATA_3 |
88017 | #define NB_NBCFG2_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0 |
88018 | #define NB_NBCFG2_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL |
88019 | //NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4 |
88020 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0 |
88021 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL |
88022 | //NB_NBCFG2_NB_SMN_INDEX_4 |
88023 | #define NB_NBCFG2_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0 |
88024 | #define NB_NBCFG2_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL |
88025 | //NB_NBCFG2_NB_SMN_DATA_4 |
88026 | #define NB_NBCFG2_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0 |
88027 | #define NB_NBCFG2_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL |
88028 | //NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5 |
88029 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0 |
88030 | #define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL |
88031 | //NB_NBCFG2_NB_SMN_INDEX_5 |
88032 | #define NB_NBCFG2_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0 |
88033 | #define NB_NBCFG2_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL |
88034 | //NB_NBCFG2_NB_SMN_DATA_5 |
88035 | #define NB_NBCFG2_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0 |
88036 | #define NB_NBCFG2_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL |
88037 | //NB_NBCFG2_NB_PERF_CNT_CTRL |
88038 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0 |
88039 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1 |
88040 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2 |
88041 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8 |
88042 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf |
88043 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10 |
88044 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17 |
88045 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L |
88046 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L |
88047 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L |
88048 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L |
88049 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L |
88050 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L |
88051 | #define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L |
88052 | //NB_NBCFG2_NB_SMN_INDEX_6 |
88053 | #define NB_NBCFG2_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0 |
88054 | #define NB_NBCFG2_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL |
88055 | //NB_NBCFG2_NB_SMN_DATA_6 |
88056 | #define NB_NBCFG2_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0 |
88057 | #define NB_NBCFG2_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL |
88058 | |
88059 | |
88060 | // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
88061 | //IOMMU_L2_2_IOMMU_VENDOR_ID |
88062 | #define IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
88063 | #define IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
88064 | //IOMMU_L2_2_IOMMU_DEVICE_ID |
88065 | #define IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
88066 | #define IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
88067 | //IOMMU_L2_2_IOMMU_COMMAND |
88068 | #define IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
88069 | #define IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
88070 | #define IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
88071 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved1__SHIFT 0x3 |
88072 | #define IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6 |
88073 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved0__SHIFT 0x7 |
88074 | #define IOMMU_L2_2_IOMMU_COMMAND__SERR_EN__SHIFT 0x8 |
88075 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved2__SHIFT 0x9 |
88076 | #define IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa |
88077 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved__SHIFT 0xb |
88078 | #define IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
88079 | #define IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
88080 | #define IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
88081 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved1_MASK 0x0038L |
88082 | #define IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L |
88083 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved0_MASK 0x0080L |
88084 | #define IOMMU_L2_2_IOMMU_COMMAND__SERR_EN_MASK 0x0100L |
88085 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved2_MASK 0x0200L |
88086 | #define IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L |
88087 | #define IOMMU_L2_2_IOMMU_COMMAND__Reserved_MASK 0xF800L |
88088 | //IOMMU_L2_2_IOMMU_STATUS |
88089 | #define IOMMU_L2_2_IOMMU_STATUS__Reserved__SHIFT 0x0 |
88090 | #define IOMMU_L2_2_IOMMU_STATUS__INT_Status__SHIFT 0x3 |
88091 | #define IOMMU_L2_2_IOMMU_STATUS__CAP_LIST__SHIFT 0x4 |
88092 | #define IOMMU_L2_2_IOMMU_STATUS__Reserved1__SHIFT 0x5 |
88093 | #define IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8 |
88094 | #define IOMMU_L2_2_IOMMU_STATUS__Reserved2__SHIFT 0x9 |
88095 | #define IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
88096 | #define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
88097 | #define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
88098 | #define IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
88099 | #define IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
88100 | #define IOMMU_L2_2_IOMMU_STATUS__Reserved_MASK 0x0007L |
88101 | #define IOMMU_L2_2_IOMMU_STATUS__INT_Status_MASK 0x0008L |
88102 | #define IOMMU_L2_2_IOMMU_STATUS__CAP_LIST_MASK 0x0010L |
88103 | #define IOMMU_L2_2_IOMMU_STATUS__Reserved1_MASK 0x00E0L |
88104 | #define IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L |
88105 | #define IOMMU_L2_2_IOMMU_STATUS__Reserved2_MASK 0x0600L |
88106 | #define IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
88107 | #define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
88108 | #define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
88109 | #define IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
88110 | #define IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
88111 | //IOMMU_L2_2_IOMMU_REVISION_ID |
88112 | #define IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
88113 | #define IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
88114 | #define IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
88115 | #define IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
88116 | //IOMMU_L2_2_IOMMU_REGPROG_INF |
88117 | #define IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 |
88118 | #define IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL |
88119 | //IOMMU_L2_2_IOMMU_SUB_CLASS |
88120 | #define IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
88121 | #define IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
88122 | //IOMMU_L2_2_IOMMU_BASE_CODE |
88123 | #define IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
88124 | #define IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
88125 | //IOMMU_L2_2_IOMMU_CACHE_LINE |
88126 | #define IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
88127 | #define IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
88128 | //IOMMU_L2_2_IOMMU_LATENCY |
88129 | #define IOMMU_L2_2_IOMMU_LATENCY__LATENCY__SHIFT 0x0 |
88130 | #define IOMMU_L2_2_IOMMU_LATENCY__LATENCY_MASK 0xFFL |
88131 | //IOMMU_L2_2_IOMMU_HEADER |
88132 | #define IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0 |
88133 | #define IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL |
88134 | //IOMMU_L2_2_IOMMU_BIST |
88135 | #define IOMMU_L2_2_IOMMU_BIST__BIST_COMP__SHIFT 0x0 |
88136 | #define IOMMU_L2_2_IOMMU_BIST__BIST_STRT__SHIFT 0x6 |
88137 | #define IOMMU_L2_2_IOMMU_BIST__BIST_CAP__SHIFT 0x7 |
88138 | #define IOMMU_L2_2_IOMMU_BIST__BIST_COMP_MASK 0x0FL |
88139 | #define IOMMU_L2_2_IOMMU_BIST__BIST_STRT_MASK 0x40L |
88140 | #define IOMMU_L2_2_IOMMU_BIST__BIST_CAP_MASK 0x80L |
88141 | //IOMMU_L2_2_IOMMU_ADAPTER_ID |
88142 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
88143 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
88144 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
88145 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
88146 | //IOMMU_L2_2_IOMMU_CAPABILITIES_PTR |
88147 | #define IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
88148 | #define IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
88149 | //IOMMU_L2_2_IOMMU_INTERRUPT_LINE |
88150 | #define IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
88151 | #define IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
88152 | //IOMMU_L2_2_IOMMU_INTERRUPT_PIN |
88153 | #define IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
88154 | #define IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
88155 | //IOMMU_L2_2_IOMMU_CAP_HEADER |
88156 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0 |
88157 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8 |
88158 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10 |
88159 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13 |
88160 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18 |
88161 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19 |
88162 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a |
88163 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b |
88164 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c |
88165 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d |
88166 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL |
88167 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L |
88168 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L |
88169 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L |
88170 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L |
88171 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L |
88172 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L |
88173 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L |
88174 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L |
88175 | #define IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L |
88176 | //IOMMU_L2_2_IOMMU_CAP_BASE_LO |
88177 | #define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 |
88178 | #define IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1 |
88179 | #define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 |
88180 | #define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L |
88181 | #define IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL |
88182 | #define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L |
88183 | //IOMMU_L2_2_IOMMU_CAP_BASE_HI |
88184 | #define IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 |
88185 | #define IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL |
88186 | //IOMMU_L2_2_IOMMU_CAP_RANGE |
88187 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0 |
88188 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5 |
88189 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7 |
88190 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8 |
88191 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10 |
88192 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18 |
88193 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL |
88194 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L |
88195 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L |
88196 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L |
88197 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L |
88198 | #define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L |
88199 | //IOMMU_L2_2_IOMMU_CAP_MISC |
88200 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 |
88201 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5 |
88202 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8 |
88203 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf |
88204 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 |
88205 | #define IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17 |
88206 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b |
88207 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL |
88208 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L |
88209 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L |
88210 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L |
88211 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L |
88212 | #define IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L |
88213 | #define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L |
88214 | //IOMMU_L2_2_IOMMU_CAP_MISC_1 |
88215 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 |
88216 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 |
88217 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 |
88218 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf |
88219 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f |
88220 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL |
88221 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L |
88222 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L |
88223 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L |
88224 | #define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L |
88225 | //IOMMU_L2_2_IOMMU_MSI_CAP |
88226 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 |
88227 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 |
88228 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10 |
88229 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 |
88230 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 |
88231 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17 |
88232 | #define IOMMU_L2_2_IOMMU_MSI_CAP__Reserved__SHIFT 0x18 |
88233 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL |
88234 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L |
88235 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L |
88236 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L |
88237 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L |
88238 | #define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L |
88239 | #define IOMMU_L2_2_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L |
88240 | //IOMMU_L2_2_IOMMU_MSI_ADDR_LO |
88241 | #define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0 |
88242 | #define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 |
88243 | #define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L |
88244 | #define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL |
88245 | //IOMMU_L2_2_IOMMU_MSI_ADDR_HI |
88246 | #define IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 |
88247 | #define IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL |
88248 | //IOMMU_L2_2_IOMMU_MSI_DATA |
88249 | #define IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0 |
88250 | #define IOMMU_L2_2_IOMMU_MSI_DATA__Reserved__SHIFT 0x10 |
88251 | #define IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL |
88252 | #define IOMMU_L2_2_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L |
88253 | //IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP |
88254 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 |
88255 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 |
88256 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 |
88257 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 |
88258 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 |
88259 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b |
88260 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL |
88261 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L |
88262 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L |
88263 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L |
88264 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L |
88265 | #define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L |
88266 | //IOMMU_L2_2_IOMMU_ADAPTER_ID_W |
88267 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0 |
88268 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10 |
88269 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL |
88270 | #define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L |
88271 | //IOMMU_L2_2_IOMMU_CONTROL_W |
88272 | #define IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0 |
88273 | #define IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4 |
88274 | #define IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 |
88275 | #define IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 |
88276 | #define IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa |
88277 | #define IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd |
88278 | #define IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L |
88279 | #define IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L |
88280 | #define IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L |
88281 | #define IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L |
88282 | #define IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L |
88283 | #define IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L |
88284 | //IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W |
88285 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 |
88286 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 |
88287 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2 |
88288 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 |
88289 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 |
88290 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5 |
88291 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6 |
88292 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 |
88293 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8 |
88294 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 |
88295 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa |
88296 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc |
88297 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd |
88298 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 |
88299 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18 |
88300 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a |
88301 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c |
88302 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e |
88303 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L |
88304 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L |
88305 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L |
88306 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L |
88307 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L |
88308 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L |
88309 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L |
88310 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L |
88311 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L |
88312 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L |
88313 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L |
88314 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L |
88315 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L |
88316 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L |
88317 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L |
88318 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L |
88319 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L |
88320 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L |
88321 | //IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W |
88322 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 |
88323 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4 |
88324 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 |
88325 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8 |
88326 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9 |
88327 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa |
88328 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb |
88329 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd |
88330 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe |
88331 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf |
88332 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 |
88333 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11 |
88334 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12 |
88335 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13 |
88336 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14 |
88337 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15 |
88338 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL |
88339 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L |
88340 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L |
88341 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L |
88342 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L |
88343 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L |
88344 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L |
88345 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L |
88346 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L |
88347 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L |
88348 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L |
88349 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L |
88350 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L |
88351 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L |
88352 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L |
88353 | #define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L |
88354 | //IOMMU_L2_2_IOMMU_RANGE_W |
88355 | #define IOMMU_L2_2_IOMMU_RANGE_W__Reserved__SHIFT 0x0 |
88356 | #define IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7 |
88357 | #define IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8 |
88358 | #define IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10 |
88359 | #define IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18 |
88360 | #define IOMMU_L2_2_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL |
88361 | #define IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L |
88362 | #define IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L |
88363 | #define IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L |
88364 | #define IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L |
88365 | //IOMMU_L2_2_IOMMU_DSFX_CONTROL |
88366 | #define IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0 |
88367 | #define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18 |
88368 | #define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c |
88369 | #define IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL |
88370 | #define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L |
88371 | #define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L |
88372 | //IOMMU_L2_2_IOMMU_DSSX_DUMMY_0 |
88373 | #define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0 |
88374 | #define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18 |
88375 | #define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL |
88376 | #define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L |
88377 | //IOMMU_L2_2_IOMMU_DSCX_DUMMY_0 |
88378 | #define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0 |
88379 | #define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18 |
88380 | #define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL |
88381 | #define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L |
88382 | //IOMMU_L2_2_L2B_POISON_DVM_CNTRL |
88383 | #define IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0 |
88384 | #define IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L |
88385 | //IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control |
88386 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 |
88387 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 |
88388 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8 |
88389 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe |
88390 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L |
88391 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL |
88392 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L |
88393 | #define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L |
88394 | //IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control |
88395 | #define IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4 |
88396 | #define IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L |
88397 | //IOMMU_L2_2_SMMU_MMIO_IDR0_W |
88398 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0 |
88399 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1 |
88400 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2 |
88401 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4 |
88402 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5 |
88403 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6 |
88404 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8 |
88405 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9 |
88406 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa |
88407 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb |
88408 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc |
88409 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd |
88410 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe |
88411 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf |
88412 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10 |
88413 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11 |
88414 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12 |
88415 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13 |
88416 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14 |
88417 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15 |
88418 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18 |
88419 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a |
88420 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b |
88421 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d |
88422 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L |
88423 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L |
88424 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL |
88425 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L |
88426 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L |
88427 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L |
88428 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L |
88429 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L |
88430 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L |
88431 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L |
88432 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L |
88433 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L |
88434 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L |
88435 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L |
88436 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L |
88437 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L |
88438 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L |
88439 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L |
88440 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L |
88441 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L |
88442 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L |
88443 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L |
88444 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L |
88445 | #define IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L |
88446 | //IOMMU_L2_2_SMMU_MMIO_IDR1_W |
88447 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0 |
88448 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6 |
88449 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb |
88450 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10 |
88451 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15 |
88452 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a |
88453 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b |
88454 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c |
88455 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d |
88456 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e |
88457 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL |
88458 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L |
88459 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L |
88460 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L |
88461 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L |
88462 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L |
88463 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L |
88464 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L |
88465 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L |
88466 | #define IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L |
88467 | //IOMMU_L2_2_SMMU_MMIO_IDR2_W |
88468 | #define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0 |
88469 | #define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa |
88470 | #define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL |
88471 | #define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L |
88472 | //IOMMU_L2_2_SMMU_MMIO_IDR3_W |
88473 | #define IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2 |
88474 | #define IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L |
88475 | //IOMMU_L2_2_SMMU_MMIO_IDR5_W |
88476 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0 |
88477 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4 |
88478 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5 |
88479 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6 |
88480 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10 |
88481 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L |
88482 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L |
88483 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L |
88484 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L |
88485 | #define IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L |
88486 | //IOMMU_L2_2_SMMU_MMIO_IIDR_W |
88487 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0 |
88488 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc |
88489 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10 |
88490 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14 |
88491 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL |
88492 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L |
88493 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L |
88494 | #define IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L |
88495 | //IOMMU_L2_2_SMMU_AIDR_W |
88496 | #define IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0 |
88497 | #define IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4 |
88498 | #define IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL |
88499 | #define IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L |
88500 | |
88501 | |
88502 | // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
88503 | //NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID |
88504 | #define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
88505 | #define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 |
88506 | #define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL |
88507 | #define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L |
88508 | //NB_PCIEDUMMY0_2_STATUS_COMMAND |
88509 | #define NB_PCIEDUMMY0_2_STATUS_COMMAND__COMMAND__SHIFT 0x0 |
88510 | #define NB_PCIEDUMMY0_2_STATUS_COMMAND__STATUS__SHIFT 0x10 |
88511 | #define NB_PCIEDUMMY0_2_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL |
88512 | #define NB_PCIEDUMMY0_2_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L |
88513 | //NB_PCIEDUMMY0_2_CLASS_CODE_REVID |
88514 | #define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__REVID__SHIFT 0x0 |
88515 | #define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 |
88516 | #define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__REVID_MASK 0x000000FFL |
88517 | #define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L |
88518 | //NB_PCIEDUMMY0_2_HEADER_TYPE |
88519 | #define NB_PCIEDUMMY0_2_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 |
88520 | #define NB_PCIEDUMMY0_2_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 |
88521 | #define NB_PCIEDUMMY0_2_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L |
88522 | #define NB_PCIEDUMMY0_2_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L |
88523 | //NB_PCIEDUMMY0_2_HEADER_TYPE_W |
88524 | #define NB_PCIEDUMMY0_2_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 |
88525 | #define NB_PCIEDUMMY0_2_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L |
88526 | |
88527 | |
88528 | // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
88529 | //BIFPLR0_2_VENDOR_ID |
88530 | #define BIFPLR0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
88531 | #define BIFPLR0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
88532 | //BIFPLR0_2_DEVICE_ID |
88533 | #define BIFPLR0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
88534 | #define BIFPLR0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
88535 | //BIFPLR0_2_COMMAND |
88536 | #define BIFPLR0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
88537 | #define BIFPLR0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
88538 | #define BIFPLR0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
88539 | #define BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
88540 | #define BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
88541 | #define BIFPLR0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
88542 | #define BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
88543 | #define BIFPLR0_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
88544 | #define BIFPLR0_2_COMMAND__SERR_EN__SHIFT 0x8 |
88545 | #define BIFPLR0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
88546 | #define BIFPLR0_2_COMMAND__INT_DIS__SHIFT 0xa |
88547 | #define BIFPLR0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
88548 | #define BIFPLR0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
88549 | #define BIFPLR0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
88550 | #define BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
88551 | #define BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
88552 | #define BIFPLR0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
88553 | #define BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
88554 | #define BIFPLR0_2_COMMAND__AD_STEPPING_MASK 0x0080L |
88555 | #define BIFPLR0_2_COMMAND__SERR_EN_MASK 0x0100L |
88556 | #define BIFPLR0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
88557 | #define BIFPLR0_2_COMMAND__INT_DIS_MASK 0x0400L |
88558 | //BIFPLR0_2_STATUS |
88559 | #define BIFPLR0_2_STATUS__INT_STATUS__SHIFT 0x3 |
88560 | #define BIFPLR0_2_STATUS__CAP_LIST__SHIFT 0x4 |
88561 | #define BIFPLR0_2_STATUS__PCI_66_EN__SHIFT 0x5 |
88562 | #define BIFPLR0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
88563 | #define BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
88564 | #define BIFPLR0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
88565 | #define BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
88566 | #define BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
88567 | #define BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
88568 | #define BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
88569 | #define BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
88570 | #define BIFPLR0_2_STATUS__INT_STATUS_MASK 0x0008L |
88571 | #define BIFPLR0_2_STATUS__CAP_LIST_MASK 0x0010L |
88572 | #define BIFPLR0_2_STATUS__PCI_66_EN_MASK 0x0020L |
88573 | #define BIFPLR0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
88574 | #define BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
88575 | #define BIFPLR0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
88576 | #define BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
88577 | #define BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
88578 | #define BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
88579 | #define BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
88580 | #define BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
88581 | //BIFPLR0_2_REVISION_ID |
88582 | #define BIFPLR0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
88583 | #define BIFPLR0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
88584 | #define BIFPLR0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
88585 | #define BIFPLR0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
88586 | //BIFPLR0_2_PROG_INTERFACE |
88587 | #define BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
88588 | #define BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
88589 | //BIFPLR0_2_SUB_CLASS |
88590 | #define BIFPLR0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
88591 | #define BIFPLR0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
88592 | //BIFPLR0_2_BASE_CLASS |
88593 | #define BIFPLR0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
88594 | #define BIFPLR0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
88595 | //BIFPLR0_2_CACHE_LINE |
88596 | #define BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
88597 | #define BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
88598 | //BIFPLR0_2_LATENCY |
88599 | #define BIFPLR0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
88600 | #define BIFPLR0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
88601 | //BIFPLR0_2_HEADER |
88602 | #define BIFPLR0_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
88603 | #define BIFPLR0_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
88604 | #define BIFPLR0_2_HEADER__HEADER_TYPE_MASK 0x7FL |
88605 | #define BIFPLR0_2_HEADER__DEVICE_TYPE_MASK 0x80L |
88606 | //BIFPLR0_2_BIST |
88607 | #define BIFPLR0_2_BIST__BIST_COMP__SHIFT 0x0 |
88608 | #define BIFPLR0_2_BIST__BIST_STRT__SHIFT 0x6 |
88609 | #define BIFPLR0_2_BIST__BIST_CAP__SHIFT 0x7 |
88610 | #define BIFPLR0_2_BIST__BIST_COMP_MASK 0x0FL |
88611 | #define BIFPLR0_2_BIST__BIST_STRT_MASK 0x40L |
88612 | #define BIFPLR0_2_BIST__BIST_CAP_MASK 0x80L |
88613 | //BIFPLR0_2_SUB_BUS_NUMBER_LATENCY |
88614 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
88615 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
88616 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
88617 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
88618 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
88619 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
88620 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
88621 | #define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
88622 | //BIFPLR0_2_IO_BASE_LIMIT |
88623 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
88624 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
88625 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
88626 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
88627 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
88628 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
88629 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
88630 | #define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
88631 | //BIFPLR0_2_SECONDARY_STATUS |
88632 | #define BIFPLR0_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
88633 | #define BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
88634 | #define BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
88635 | #define BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
88636 | #define BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
88637 | #define BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
88638 | #define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
88639 | #define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
88640 | #define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
88641 | #define BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
88642 | #define BIFPLR0_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
88643 | #define BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
88644 | #define BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
88645 | #define BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
88646 | #define BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
88647 | #define BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
88648 | #define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
88649 | #define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
88650 | #define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
88651 | #define BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
88652 | //BIFPLR0_2_MEM_BASE_LIMIT |
88653 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
88654 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
88655 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
88656 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
88657 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
88658 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
88659 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
88660 | #define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
88661 | //BIFPLR0_2_PREF_BASE_LIMIT |
88662 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
88663 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
88664 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
88665 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
88666 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
88667 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
88668 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
88669 | #define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
88670 | //BIFPLR0_2_PREF_BASE_UPPER |
88671 | #define BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
88672 | #define BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
88673 | //BIFPLR0_2_PREF_LIMIT_UPPER |
88674 | #define BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
88675 | #define BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
88676 | //BIFPLR0_2_IO_BASE_LIMIT_HI |
88677 | #define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
88678 | #define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
88679 | #define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
88680 | #define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
88681 | //BIFPLR0_2_CAP_PTR |
88682 | #define BIFPLR0_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
88683 | #define BIFPLR0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
88684 | //BIFPLR0_2_INTERRUPT_LINE |
88685 | #define BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
88686 | #define BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
88687 | //BIFPLR0_2_INTERRUPT_PIN |
88688 | #define BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
88689 | #define BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
88690 | //BIFPLR0_2_IRQ_BRIDGE_CNTL |
88691 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
88692 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
88693 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
88694 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
88695 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
88696 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
88697 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
88698 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
88699 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
88700 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
88701 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
88702 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
88703 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
88704 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
88705 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
88706 | #define BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
88707 | //BIFPLR0_2_EXT_BRIDGE_CNTL |
88708 | #define BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
88709 | #define BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
88710 | //BIFPLR0_2_PMI_CAP_LIST |
88711 | #define BIFPLR0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
88712 | #define BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
88713 | #define BIFPLR0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
88714 | #define BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
88715 | //BIFPLR0_2_PMI_CAP |
88716 | #define BIFPLR0_2_PMI_CAP__VERSION__SHIFT 0x0 |
88717 | #define BIFPLR0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
88718 | #define BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
88719 | #define BIFPLR0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
88720 | #define BIFPLR0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
88721 | #define BIFPLR0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
88722 | #define BIFPLR0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
88723 | #define BIFPLR0_2_PMI_CAP__VERSION_MASK 0x0007L |
88724 | #define BIFPLR0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
88725 | #define BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
88726 | #define BIFPLR0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
88727 | #define BIFPLR0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
88728 | #define BIFPLR0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
88729 | #define BIFPLR0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
88730 | //BIFPLR0_2_PMI_STATUS_CNTL |
88731 | #define BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
88732 | #define BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
88733 | #define BIFPLR0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
88734 | #define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
88735 | #define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
88736 | #define BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
88737 | #define BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
88738 | #define BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
88739 | #define BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
88740 | #define BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
88741 | #define BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
88742 | #define BIFPLR0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
88743 | #define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
88744 | #define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
88745 | #define BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
88746 | #define BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
88747 | #define BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
88748 | #define BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
88749 | //BIFPLR0_2_PCIE_CAP_LIST |
88750 | #define BIFPLR0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
88751 | #define BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
88752 | #define BIFPLR0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
88753 | #define BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
88754 | //BIFPLR0_2_PCIE_CAP |
88755 | #define BIFPLR0_2_PCIE_CAP__VERSION__SHIFT 0x0 |
88756 | #define BIFPLR0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
88757 | #define BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
88758 | #define BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
88759 | #define BIFPLR0_2_PCIE_CAP__VERSION_MASK 0x000FL |
88760 | #define BIFPLR0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
88761 | #define BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
88762 | #define BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
88763 | //BIFPLR0_2_DEVICE_CAP |
88764 | #define BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
88765 | #define BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
88766 | #define BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
88767 | #define BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
88768 | #define BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
88769 | #define BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
88770 | #define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
88771 | #define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
88772 | #define BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
88773 | #define BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
88774 | #define BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
88775 | #define BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
88776 | #define BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
88777 | #define BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
88778 | #define BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
88779 | #define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
88780 | #define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
88781 | #define BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
88782 | //BIFPLR0_2_DEVICE_CNTL |
88783 | #define BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
88784 | #define BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
88785 | #define BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
88786 | #define BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
88787 | #define BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
88788 | #define BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
88789 | #define BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
88790 | #define BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
88791 | #define BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
88792 | #define BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
88793 | #define BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
88794 | #define BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
88795 | #define BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
88796 | #define BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
88797 | #define BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
88798 | #define BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
88799 | #define BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
88800 | #define BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
88801 | #define BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
88802 | #define BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
88803 | #define BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
88804 | #define BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
88805 | #define BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
88806 | #define BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
88807 | //BIFPLR0_2_DEVICE_STATUS |
88808 | #define BIFPLR0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
88809 | #define BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
88810 | #define BIFPLR0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
88811 | #define BIFPLR0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
88812 | #define BIFPLR0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
88813 | #define BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
88814 | #define BIFPLR0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
88815 | #define BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
88816 | #define BIFPLR0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
88817 | #define BIFPLR0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
88818 | #define BIFPLR0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
88819 | #define BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
88820 | //BIFPLR0_2_LINK_CAP |
88821 | #define BIFPLR0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
88822 | #define BIFPLR0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
88823 | #define BIFPLR0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
88824 | #define BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
88825 | #define BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
88826 | #define BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
88827 | #define BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
88828 | #define BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
88829 | #define BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
88830 | #define BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
88831 | #define BIFPLR0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
88832 | #define BIFPLR0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
88833 | #define BIFPLR0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
88834 | #define BIFPLR0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
88835 | #define BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
88836 | #define BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
88837 | #define BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
88838 | #define BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
88839 | #define BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
88840 | #define BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
88841 | #define BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
88842 | #define BIFPLR0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
88843 | //BIFPLR0_2_LINK_CNTL |
88844 | #define BIFPLR0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
88845 | #define BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
88846 | #define BIFPLR0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
88847 | #define BIFPLR0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
88848 | #define BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
88849 | #define BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
88850 | #define BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
88851 | #define BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
88852 | #define BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
88853 | #define BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
88854 | #define BIFPLR0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
88855 | #define BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
88856 | #define BIFPLR0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
88857 | #define BIFPLR0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
88858 | #define BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
88859 | #define BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
88860 | #define BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
88861 | #define BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
88862 | #define BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
88863 | #define BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
88864 | //BIFPLR0_2_LINK_STATUS |
88865 | #define BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
88866 | #define BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
88867 | #define BIFPLR0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
88868 | #define BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
88869 | #define BIFPLR0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
88870 | #define BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
88871 | #define BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
88872 | #define BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
88873 | #define BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
88874 | #define BIFPLR0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
88875 | #define BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
88876 | #define BIFPLR0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
88877 | #define BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
88878 | #define BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
88879 | //BIFPLR0_2_SLOT_CAP |
88880 | #define BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
88881 | #define BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
88882 | #define BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
88883 | #define BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
88884 | #define BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
88885 | #define BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
88886 | #define BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
88887 | #define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
88888 | #define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
88889 | #define BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
88890 | #define BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
88891 | #define BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
88892 | #define BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
88893 | #define BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
88894 | #define BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
88895 | #define BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
88896 | #define BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
88897 | #define BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
88898 | #define BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
88899 | #define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
88900 | #define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
88901 | #define BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
88902 | #define BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
88903 | #define BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
88904 | //BIFPLR0_2_SLOT_CNTL |
88905 | #define BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
88906 | #define BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
88907 | #define BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
88908 | #define BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
88909 | #define BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
88910 | #define BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
88911 | #define BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
88912 | #define BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
88913 | #define BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
88914 | #define BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
88915 | #define BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
88916 | #define BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
88917 | #define BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
88918 | #define BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
88919 | #define BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
88920 | #define BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
88921 | #define BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
88922 | #define BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
88923 | #define BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
88924 | #define BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
88925 | #define BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
88926 | #define BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
88927 | #define BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
88928 | #define BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
88929 | //BIFPLR0_2_SLOT_STATUS |
88930 | #define BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
88931 | #define BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
88932 | #define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
88933 | #define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
88934 | #define BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
88935 | #define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
88936 | #define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
88937 | #define BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
88938 | #define BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
88939 | #define BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
88940 | #define BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
88941 | #define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
88942 | #define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
88943 | #define BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
88944 | #define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
88945 | #define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
88946 | #define BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
88947 | #define BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
88948 | //BIFPLR0_2_ROOT_CNTL |
88949 | #define BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
88950 | #define BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
88951 | #define BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
88952 | #define BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
88953 | #define BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
88954 | #define BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
88955 | #define BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
88956 | #define BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
88957 | #define BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
88958 | #define BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
88959 | //BIFPLR0_2_ROOT_CAP |
88960 | #define BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
88961 | #define BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
88962 | //BIFPLR0_2_ROOT_STATUS |
88963 | #define BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
88964 | #define BIFPLR0_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
88965 | #define BIFPLR0_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
88966 | #define BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
88967 | #define BIFPLR0_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
88968 | #define BIFPLR0_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
88969 | //BIFPLR0_2_DEVICE_CAP2 |
88970 | #define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
88971 | #define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
88972 | #define BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
88973 | #define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
88974 | #define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
88975 | #define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
88976 | #define BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
88977 | #define BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
88978 | #define BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
88979 | #define BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
88980 | #define BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
88981 | #define BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
88982 | #define BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
88983 | #define BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
88984 | #define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
88985 | #define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
88986 | #define BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
88987 | #define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
88988 | #define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
88989 | #define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
88990 | #define BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
88991 | #define BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
88992 | #define BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
88993 | #define BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
88994 | #define BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
88995 | #define BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
88996 | #define BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
88997 | #define BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
88998 | //BIFPLR0_2_DEVICE_CNTL2 |
88999 | #define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
89000 | #define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
89001 | #define BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
89002 | #define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
89003 | #define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
89004 | #define BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
89005 | #define BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
89006 | #define BIFPLR0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
89007 | #define BIFPLR0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
89008 | #define BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
89009 | #define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
89010 | #define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
89011 | #define BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
89012 | #define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
89013 | #define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
89014 | #define BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
89015 | #define BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
89016 | #define BIFPLR0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
89017 | #define BIFPLR0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
89018 | #define BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
89019 | //BIFPLR0_2_DEVICE_STATUS2 |
89020 | #define BIFPLR0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
89021 | #define BIFPLR0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
89022 | //BIFPLR0_2_LINK_CAP2 |
89023 | #define BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
89024 | #define BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
89025 | #define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
89026 | #define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
89027 | #define BIFPLR0_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
89028 | #define BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
89029 | #define BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
89030 | #define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
89031 | #define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
89032 | #define BIFPLR0_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
89033 | //BIFPLR0_2_LINK_CNTL2 |
89034 | #define BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
89035 | #define BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
89036 | #define BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
89037 | #define BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
89038 | #define BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
89039 | #define BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
89040 | #define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
89041 | #define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
89042 | #define BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
89043 | #define BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
89044 | #define BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
89045 | #define BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
89046 | #define BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
89047 | #define BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
89048 | #define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
89049 | #define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
89050 | //BIFPLR0_2_LINK_STATUS2 |
89051 | #define BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
89052 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
89053 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
89054 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
89055 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
89056 | #define BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
89057 | #define BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
89058 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
89059 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
89060 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
89061 | #define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
89062 | #define BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
89063 | //BIFPLR0_2_SLOT_CAP2 |
89064 | #define BIFPLR0_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
89065 | #define BIFPLR0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
89066 | //BIFPLR0_2_SLOT_CNTL2 |
89067 | #define BIFPLR0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
89068 | #define BIFPLR0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
89069 | //BIFPLR0_2_SLOT_STATUS2 |
89070 | #define BIFPLR0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
89071 | #define BIFPLR0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
89072 | //BIFPLR0_2_MSI_CAP_LIST |
89073 | #define BIFPLR0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
89074 | #define BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
89075 | #define BIFPLR0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
89076 | #define BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
89077 | //BIFPLR0_2_MSI_MSG_CNTL |
89078 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
89079 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
89080 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
89081 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
89082 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
89083 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
89084 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
89085 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
89086 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
89087 | #define BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
89088 | //BIFPLR0_2_MSI_MSG_ADDR_LO |
89089 | #define BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
89090 | #define BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
89091 | //BIFPLR0_2_MSI_MSG_ADDR_HI |
89092 | #define BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
89093 | #define BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
89094 | //BIFPLR0_2_MSI_MSG_DATA |
89095 | #define BIFPLR0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
89096 | #define BIFPLR0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
89097 | //BIFPLR0_2_MSI_MSG_DATA_64 |
89098 | #define BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
89099 | #define BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
89100 | //BIFPLR0_2_SSID_CAP_LIST |
89101 | #define BIFPLR0_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
89102 | #define BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
89103 | #define BIFPLR0_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
89104 | #define BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
89105 | //BIFPLR0_2_SSID_CAP |
89106 | #define BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
89107 | #define BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
89108 | #define BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
89109 | #define BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
89110 | //BIFPLR0_2_MSI_MAP_CAP_LIST |
89111 | #define BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
89112 | #define BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
89113 | #define BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
89114 | #define BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
89115 | //BIFPLR0_2_MSI_MAP_CAP |
89116 | #define BIFPLR0_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
89117 | #define BIFPLR0_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
89118 | #define BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
89119 | #define BIFPLR0_2_MSI_MAP_CAP__EN_MASK 0x0001L |
89120 | #define BIFPLR0_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
89121 | #define BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
89122 | //BIFPLR0_2_MSI_MAP_ADDR_LO |
89123 | #define BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
89124 | #define BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
89125 | //BIFPLR0_2_MSI_MAP_ADDR_HI |
89126 | #define BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
89127 | #define BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
89128 | //BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
89129 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89130 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89131 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89132 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89133 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89134 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89135 | //BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR |
89136 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
89137 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
89138 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
89139 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
89140 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
89141 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
89142 | //BIFPLR0_2_PCIE_VENDOR_SPECIFIC1 |
89143 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
89144 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
89145 | //BIFPLR0_2_PCIE_VENDOR_SPECIFIC2 |
89146 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
89147 | #define BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
89148 | //BIFPLR0_2_PCIE_VC_ENH_CAP_LIST |
89149 | #define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89150 | #define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89151 | #define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89152 | #define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89153 | #define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89154 | #define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89155 | //BIFPLR0_2_PCIE_PORT_VC_CAP_REG1 |
89156 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
89157 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
89158 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
89159 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
89160 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
89161 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
89162 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
89163 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
89164 | //BIFPLR0_2_PCIE_PORT_VC_CAP_REG2 |
89165 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
89166 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
89167 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
89168 | #define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
89169 | //BIFPLR0_2_PCIE_PORT_VC_CNTL |
89170 | #define BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
89171 | #define BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
89172 | #define BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
89173 | #define BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
89174 | //BIFPLR0_2_PCIE_PORT_VC_STATUS |
89175 | #define BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
89176 | #define BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
89177 | //BIFPLR0_2_PCIE_VC0_RESOURCE_CAP |
89178 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
89179 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
89180 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
89181 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
89182 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
89183 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
89184 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
89185 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
89186 | //BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL |
89187 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
89188 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
89189 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
89190 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
89191 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
89192 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
89193 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
89194 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
89195 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
89196 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
89197 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
89198 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
89199 | //BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS |
89200 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
89201 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
89202 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
89203 | #define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
89204 | //BIFPLR0_2_PCIE_VC1_RESOURCE_CAP |
89205 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
89206 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
89207 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
89208 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
89209 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
89210 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
89211 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
89212 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
89213 | //BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL |
89214 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
89215 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
89216 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
89217 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
89218 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
89219 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
89220 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
89221 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
89222 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
89223 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
89224 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
89225 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
89226 | //BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS |
89227 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
89228 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
89229 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
89230 | #define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
89231 | //BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
89232 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89233 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89234 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89235 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89236 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89237 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89238 | //BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1 |
89239 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
89240 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
89241 | //BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2 |
89242 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
89243 | #define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
89244 | //BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
89245 | #define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89246 | #define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89247 | #define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89248 | #define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89249 | #define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89250 | #define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89251 | //BIFPLR0_2_PCIE_UNCORR_ERR_STATUS |
89252 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
89253 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
89254 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
89255 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
89256 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
89257 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
89258 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
89259 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
89260 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
89261 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
89262 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
89263 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
89264 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
89265 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
89266 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
89267 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
89268 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
89269 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
89270 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
89271 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
89272 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
89273 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
89274 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
89275 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
89276 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
89277 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
89278 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
89279 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
89280 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
89281 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
89282 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
89283 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
89284 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
89285 | #define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
89286 | //BIFPLR0_2_PCIE_UNCORR_ERR_MASK |
89287 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
89288 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
89289 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
89290 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
89291 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
89292 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
89293 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
89294 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
89295 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
89296 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
89297 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
89298 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
89299 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
89300 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
89301 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
89302 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
89303 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
89304 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
89305 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
89306 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
89307 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
89308 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
89309 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
89310 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
89311 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
89312 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
89313 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
89314 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
89315 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
89316 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
89317 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
89318 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
89319 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
89320 | #define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
89321 | //BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY |
89322 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
89323 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
89324 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
89325 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
89326 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
89327 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
89328 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
89329 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
89330 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
89331 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
89332 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
89333 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
89334 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
89335 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
89336 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
89337 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
89338 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
89339 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
89340 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
89341 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
89342 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
89343 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
89344 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
89345 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
89346 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
89347 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
89348 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
89349 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
89350 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
89351 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
89352 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
89353 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
89354 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
89355 | #define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
89356 | //BIFPLR0_2_PCIE_CORR_ERR_STATUS |
89357 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
89358 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
89359 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
89360 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
89361 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
89362 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
89363 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
89364 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
89365 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
89366 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
89367 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
89368 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
89369 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
89370 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
89371 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
89372 | #define BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
89373 | //BIFPLR0_2_PCIE_CORR_ERR_MASK |
89374 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
89375 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
89376 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
89377 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
89378 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
89379 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
89380 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
89381 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
89382 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
89383 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
89384 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
89385 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
89386 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
89387 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
89388 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
89389 | #define BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
89390 | //BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL |
89391 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
89392 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
89393 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
89394 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
89395 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
89396 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
89397 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
89398 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
89399 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
89400 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
89401 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
89402 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
89403 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
89404 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
89405 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
89406 | #define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
89407 | //BIFPLR0_2_PCIE_HDR_LOG0 |
89408 | #define BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
89409 | #define BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
89410 | //BIFPLR0_2_PCIE_HDR_LOG1 |
89411 | #define BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
89412 | #define BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
89413 | //BIFPLR0_2_PCIE_HDR_LOG2 |
89414 | #define BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
89415 | #define BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
89416 | //BIFPLR0_2_PCIE_HDR_LOG3 |
89417 | #define BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
89418 | #define BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
89419 | //BIFPLR0_2_PCIE_ROOT_ERR_CMD |
89420 | #define BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
89421 | #define BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
89422 | #define BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
89423 | #define BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
89424 | #define BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
89425 | #define BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
89426 | //BIFPLR0_2_PCIE_ROOT_ERR_STATUS |
89427 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
89428 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
89429 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
89430 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
89431 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
89432 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
89433 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
89434 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
89435 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
89436 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
89437 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
89438 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
89439 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
89440 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
89441 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
89442 | #define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
89443 | //BIFPLR0_2_PCIE_ERR_SRC_ID |
89444 | #define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
89445 | #define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
89446 | #define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
89447 | #define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
89448 | //BIFPLR0_2_PCIE_TLP_PREFIX_LOG0 |
89449 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
89450 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
89451 | //BIFPLR0_2_PCIE_TLP_PREFIX_LOG1 |
89452 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
89453 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
89454 | //BIFPLR0_2_PCIE_TLP_PREFIX_LOG2 |
89455 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
89456 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
89457 | //BIFPLR0_2_PCIE_TLP_PREFIX_LOG3 |
89458 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
89459 | #define BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
89460 | //BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST |
89461 | #define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89462 | #define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89463 | #define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89464 | #define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89465 | #define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89466 | #define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89467 | //BIFPLR0_2_PCIE_LINK_CNTL3 |
89468 | #define BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
89469 | #define BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
89470 | #define BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
89471 | #define BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
89472 | #define BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
89473 | #define BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
89474 | #define BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
89475 | #define BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
89476 | //BIFPLR0_2_PCIE_LANE_ERROR_STATUS |
89477 | #define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
89478 | #define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
89479 | #define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
89480 | #define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
89481 | //BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL |
89482 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89483 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89484 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89485 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89486 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89487 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89488 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89489 | #define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89490 | //BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL |
89491 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89492 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89493 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89494 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89495 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89496 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89497 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89498 | #define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89499 | //BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL |
89500 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89501 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89502 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89503 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89504 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89505 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89506 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89507 | #define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89508 | //BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL |
89509 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89510 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89511 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89512 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89513 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89514 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89515 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89516 | #define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89517 | //BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL |
89518 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89519 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89520 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89521 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89522 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89523 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89524 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89525 | #define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89526 | //BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL |
89527 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89528 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89529 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89530 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89531 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89532 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89533 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89534 | #define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89535 | //BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL |
89536 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89537 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89538 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89539 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89540 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89541 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89542 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89543 | #define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89544 | //BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL |
89545 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89546 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89547 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89548 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89549 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89550 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89551 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89552 | #define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89553 | //BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL |
89554 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89555 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89556 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89557 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89558 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89559 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89560 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89561 | #define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89562 | //BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL |
89563 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89564 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89565 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89566 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89567 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89568 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89569 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89570 | #define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89571 | //BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL |
89572 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89573 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89574 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89575 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89576 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89577 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89578 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89579 | #define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89580 | //BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL |
89581 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89582 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89583 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89584 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89585 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89586 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89587 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89588 | #define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89589 | //BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL |
89590 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89591 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89592 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89593 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89594 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89595 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89596 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89597 | #define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89598 | //BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL |
89599 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89600 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89601 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89602 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89603 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89604 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89605 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89606 | #define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89607 | //BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL |
89608 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89609 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89610 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89611 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89612 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89613 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89614 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89615 | #define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89616 | //BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL |
89617 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
89618 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
89619 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
89620 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
89621 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
89622 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
89623 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
89624 | #define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
89625 | //BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST |
89626 | #define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89627 | #define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89628 | #define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89629 | #define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89630 | #define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89631 | #define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89632 | //BIFPLR0_2_PCIE_ACS_CAP |
89633 | #define BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
89634 | #define BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
89635 | #define BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
89636 | #define BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
89637 | #define BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
89638 | #define BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
89639 | #define BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
89640 | #define BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
89641 | #define BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
89642 | #define BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
89643 | #define BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
89644 | #define BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
89645 | #define BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
89646 | #define BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
89647 | #define BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
89648 | #define BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
89649 | //BIFPLR0_2_PCIE_ACS_CNTL |
89650 | #define BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
89651 | #define BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
89652 | #define BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
89653 | #define BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
89654 | #define BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
89655 | #define BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
89656 | #define BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
89657 | #define BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
89658 | #define BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
89659 | #define BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
89660 | #define BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
89661 | #define BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
89662 | #define BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
89663 | #define BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
89664 | //BIFPLR0_2_PCIE_MC_ENH_CAP_LIST |
89665 | #define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89666 | #define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89667 | #define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89668 | #define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89669 | #define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89670 | #define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89671 | //BIFPLR0_2_PCIE_MC_CAP |
89672 | #define BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
89673 | #define BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
89674 | #define BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
89675 | #define BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
89676 | //BIFPLR0_2_PCIE_MC_CNTL |
89677 | #define BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
89678 | #define BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
89679 | #define BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
89680 | #define BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
89681 | //BIFPLR0_2_PCIE_MC_ADDR0 |
89682 | #define BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
89683 | #define BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
89684 | #define BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
89685 | #define BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
89686 | //BIFPLR0_2_PCIE_MC_ADDR1 |
89687 | #define BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
89688 | #define BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
89689 | //BIFPLR0_2_PCIE_MC_RCV0 |
89690 | #define BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
89691 | #define BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
89692 | //BIFPLR0_2_PCIE_MC_RCV1 |
89693 | #define BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
89694 | #define BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
89695 | //BIFPLR0_2_PCIE_MC_BLOCK_ALL0 |
89696 | #define BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
89697 | #define BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
89698 | //BIFPLR0_2_PCIE_MC_BLOCK_ALL1 |
89699 | #define BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
89700 | #define BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
89701 | //BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
89702 | #define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
89703 | #define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
89704 | //BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
89705 | #define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
89706 | #define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
89707 | //BIFPLR0_2_PCIE_MC_OVERLAY_BAR0 |
89708 | #define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
89709 | #define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
89710 | #define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
89711 | #define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
89712 | //BIFPLR0_2_PCIE_MC_OVERLAY_BAR1 |
89713 | #define BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
89714 | #define BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
89715 | //BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST |
89716 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
89717 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
89718 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89719 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89720 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89721 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89722 | //BIFPLR0_2_PCIE_L1_PM_SUB_CAP |
89723 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
89724 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
89725 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
89726 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
89727 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
89728 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
89729 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
89730 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
89731 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
89732 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
89733 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
89734 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
89735 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
89736 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
89737 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
89738 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
89739 | //BIFPLR0_2_PCIE_L1_PM_SUB_CNTL |
89740 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
89741 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
89742 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
89743 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
89744 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
89745 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
89746 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
89747 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
89748 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
89749 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
89750 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
89751 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
89752 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
89753 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
89754 | //BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2 |
89755 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
89756 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
89757 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
89758 | #define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
89759 | //BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST |
89760 | #define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
89761 | #define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
89762 | #define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89763 | #define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89764 | #define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89765 | #define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89766 | //BIFPLR0_2_PCIE_DPC_CAP_LIST |
89767 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
89768 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
89769 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
89770 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
89771 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
89772 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
89773 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
89774 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
89775 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
89776 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
89777 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
89778 | #define BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
89779 | //BIFPLR0_2_PCIE_DPC_CNTL |
89780 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
89781 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
89782 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
89783 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
89784 | #define BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
89785 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
89786 | #define BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
89787 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
89788 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
89789 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
89790 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
89791 | #define BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
89792 | #define BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
89793 | #define BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
89794 | //BIFPLR0_2_PCIE_DPC_STATUS |
89795 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
89796 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
89797 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
89798 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
89799 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
89800 | #define BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
89801 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
89802 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
89803 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
89804 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
89805 | #define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
89806 | #define BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
89807 | //BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID |
89808 | #define BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
89809 | #define BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
89810 | //BIFPLR0_2_PCIE_RP_PIO_STATUS |
89811 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
89812 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
89813 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
89814 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
89815 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
89816 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
89817 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
89818 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
89819 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
89820 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
89821 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
89822 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
89823 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
89824 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
89825 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
89826 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
89827 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
89828 | #define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
89829 | //BIFPLR0_2_PCIE_RP_PIO_MASK |
89830 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
89831 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
89832 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
89833 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
89834 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
89835 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
89836 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
89837 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
89838 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
89839 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
89840 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
89841 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
89842 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
89843 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
89844 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
89845 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
89846 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
89847 | #define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
89848 | //BIFPLR0_2_PCIE_RP_PIO_SEVERITY |
89849 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
89850 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
89851 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
89852 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
89853 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
89854 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
89855 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
89856 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
89857 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
89858 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
89859 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
89860 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
89861 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
89862 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
89863 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
89864 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
89865 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
89866 | #define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
89867 | //BIFPLR0_2_PCIE_RP_PIO_SYSERROR |
89868 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
89869 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
89870 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
89871 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
89872 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
89873 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
89874 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
89875 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
89876 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
89877 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
89878 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
89879 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
89880 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
89881 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
89882 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
89883 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
89884 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
89885 | #define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
89886 | //BIFPLR0_2_PCIE_RP_PIO_EXCEPTION |
89887 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
89888 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
89889 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
89890 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
89891 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
89892 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
89893 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
89894 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
89895 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
89896 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
89897 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
89898 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
89899 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
89900 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
89901 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
89902 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
89903 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
89904 | #define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
89905 | //BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0 |
89906 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
89907 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
89908 | //BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1 |
89909 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
89910 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
89911 | //BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2 |
89912 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
89913 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
89914 | //BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3 |
89915 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
89916 | #define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
89917 | //BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG |
89918 | #define BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
89919 | #define BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
89920 | //BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0 |
89921 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
89922 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
89923 | //BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1 |
89924 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
89925 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
89926 | //BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2 |
89927 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
89928 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
89929 | //BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3 |
89930 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
89931 | #define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
89932 | //BIFPLR0_2_PCIE_ESM_CAP_LIST |
89933 | #define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
89934 | #define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
89935 | #define BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
89936 | #define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
89937 | #define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
89938 | #define BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
89939 | //BIFPLR0_2_PCIE_ESM_HEADER_1 |
89940 | #define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
89941 | #define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
89942 | #define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
89943 | #define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
89944 | #define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
89945 | #define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
89946 | //BIFPLR0_2_PCIE_ESM_HEADER_2 |
89947 | #define BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
89948 | #define BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
89949 | //BIFPLR0_2_PCIE_ESM_STATUS |
89950 | #define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
89951 | #define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
89952 | #define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
89953 | #define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
89954 | //BIFPLR0_2_PCIE_ESM_CTRL |
89955 | #define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
89956 | #define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
89957 | #define BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
89958 | #define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
89959 | #define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
89960 | #define BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
89961 | //BIFPLR0_2_PCIE_ESM_CAP_1 |
89962 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
89963 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
89964 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
89965 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
89966 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
89967 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
89968 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
89969 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
89970 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
89971 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
89972 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
89973 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
89974 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
89975 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
89976 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
89977 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
89978 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
89979 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
89980 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
89981 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
89982 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
89983 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
89984 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
89985 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
89986 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
89987 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
89988 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
89989 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
89990 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
89991 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
89992 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
89993 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
89994 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
89995 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
89996 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
89997 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
89998 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
89999 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
90000 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
90001 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
90002 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
90003 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
90004 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
90005 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
90006 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
90007 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
90008 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
90009 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
90010 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
90011 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
90012 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
90013 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
90014 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
90015 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
90016 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
90017 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
90018 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
90019 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
90020 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
90021 | #define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
90022 | //BIFPLR0_2_PCIE_ESM_CAP_2 |
90023 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
90024 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
90025 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
90026 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
90027 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
90028 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
90029 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
90030 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
90031 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
90032 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
90033 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
90034 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
90035 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
90036 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
90037 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
90038 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
90039 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
90040 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
90041 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
90042 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
90043 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
90044 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
90045 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
90046 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
90047 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
90048 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
90049 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
90050 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
90051 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
90052 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
90053 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
90054 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
90055 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
90056 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
90057 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
90058 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
90059 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
90060 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
90061 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
90062 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
90063 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
90064 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
90065 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
90066 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
90067 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
90068 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
90069 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
90070 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
90071 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
90072 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
90073 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
90074 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
90075 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
90076 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
90077 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
90078 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
90079 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
90080 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
90081 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
90082 | #define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
90083 | //BIFPLR0_2_PCIE_ESM_CAP_3 |
90084 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
90085 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
90086 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
90087 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
90088 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
90089 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
90090 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
90091 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
90092 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
90093 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
90094 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
90095 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
90096 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
90097 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
90098 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
90099 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
90100 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
90101 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
90102 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
90103 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
90104 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
90105 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
90106 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
90107 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
90108 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
90109 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
90110 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
90111 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
90112 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
90113 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
90114 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
90115 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
90116 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
90117 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
90118 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
90119 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
90120 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
90121 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
90122 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
90123 | #define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
90124 | //BIFPLR0_2_PCIE_ESM_CAP_4 |
90125 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
90126 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
90127 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
90128 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
90129 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
90130 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
90131 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
90132 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
90133 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
90134 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
90135 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
90136 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
90137 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
90138 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
90139 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
90140 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
90141 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
90142 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
90143 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
90144 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
90145 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
90146 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
90147 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
90148 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
90149 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
90150 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
90151 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
90152 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
90153 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
90154 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
90155 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
90156 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
90157 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
90158 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
90159 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
90160 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
90161 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
90162 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
90163 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
90164 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
90165 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
90166 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
90167 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
90168 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
90169 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
90170 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
90171 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
90172 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
90173 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
90174 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
90175 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
90176 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
90177 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
90178 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
90179 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
90180 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
90181 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
90182 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
90183 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
90184 | #define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
90185 | //BIFPLR0_2_PCIE_ESM_CAP_5 |
90186 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
90187 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
90188 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
90189 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
90190 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
90191 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
90192 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
90193 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
90194 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
90195 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
90196 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
90197 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
90198 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
90199 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
90200 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
90201 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
90202 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
90203 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
90204 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
90205 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
90206 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
90207 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
90208 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
90209 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
90210 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
90211 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
90212 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
90213 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
90214 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
90215 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
90216 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
90217 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
90218 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
90219 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
90220 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
90221 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
90222 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
90223 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
90224 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
90225 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
90226 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
90227 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
90228 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
90229 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
90230 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
90231 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
90232 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
90233 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
90234 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
90235 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
90236 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
90237 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
90238 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
90239 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
90240 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
90241 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
90242 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
90243 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
90244 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
90245 | #define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
90246 | //BIFPLR0_2_PCIE_ESM_CAP_6 |
90247 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
90248 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
90249 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
90250 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
90251 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
90252 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
90253 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
90254 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
90255 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
90256 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
90257 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
90258 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
90259 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
90260 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
90261 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
90262 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
90263 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
90264 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
90265 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
90266 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
90267 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
90268 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
90269 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
90270 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
90271 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
90272 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
90273 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
90274 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
90275 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
90276 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
90277 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
90278 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
90279 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
90280 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
90281 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
90282 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
90283 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
90284 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
90285 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
90286 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
90287 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
90288 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
90289 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
90290 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
90291 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
90292 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
90293 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
90294 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
90295 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
90296 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
90297 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
90298 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
90299 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
90300 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
90301 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
90302 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
90303 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
90304 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
90305 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
90306 | #define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
90307 | //BIFPLR0_2_PCIE_ESM_CAP_7 |
90308 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
90309 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
90310 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
90311 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
90312 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
90313 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
90314 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
90315 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
90316 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
90317 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
90318 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
90319 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
90320 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
90321 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
90322 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
90323 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
90324 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
90325 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
90326 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
90327 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
90328 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
90329 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
90330 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
90331 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
90332 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
90333 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
90334 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
90335 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
90336 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
90337 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
90338 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
90339 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
90340 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
90341 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
90342 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
90343 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
90344 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
90345 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
90346 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
90347 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
90348 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
90349 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
90350 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
90351 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
90352 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
90353 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
90354 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
90355 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
90356 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
90357 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
90358 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
90359 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
90360 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
90361 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
90362 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
90363 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
90364 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
90365 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
90366 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
90367 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
90368 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
90369 | #define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
90370 | |
90371 | |
90372 | // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
90373 | //BIFPLR1_2_VENDOR_ID |
90374 | #define BIFPLR1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
90375 | #define BIFPLR1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
90376 | //BIFPLR1_2_DEVICE_ID |
90377 | #define BIFPLR1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
90378 | #define BIFPLR1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
90379 | //BIFPLR1_2_COMMAND |
90380 | #define BIFPLR1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
90381 | #define BIFPLR1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
90382 | #define BIFPLR1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
90383 | #define BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
90384 | #define BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
90385 | #define BIFPLR1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
90386 | #define BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
90387 | #define BIFPLR1_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
90388 | #define BIFPLR1_2_COMMAND__SERR_EN__SHIFT 0x8 |
90389 | #define BIFPLR1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
90390 | #define BIFPLR1_2_COMMAND__INT_DIS__SHIFT 0xa |
90391 | #define BIFPLR1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
90392 | #define BIFPLR1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
90393 | #define BIFPLR1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
90394 | #define BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
90395 | #define BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
90396 | #define BIFPLR1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
90397 | #define BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
90398 | #define BIFPLR1_2_COMMAND__AD_STEPPING_MASK 0x0080L |
90399 | #define BIFPLR1_2_COMMAND__SERR_EN_MASK 0x0100L |
90400 | #define BIFPLR1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
90401 | #define BIFPLR1_2_COMMAND__INT_DIS_MASK 0x0400L |
90402 | //BIFPLR1_2_STATUS |
90403 | #define BIFPLR1_2_STATUS__INT_STATUS__SHIFT 0x3 |
90404 | #define BIFPLR1_2_STATUS__CAP_LIST__SHIFT 0x4 |
90405 | #define BIFPLR1_2_STATUS__PCI_66_EN__SHIFT 0x5 |
90406 | #define BIFPLR1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
90407 | #define BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
90408 | #define BIFPLR1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
90409 | #define BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
90410 | #define BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
90411 | #define BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
90412 | #define BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
90413 | #define BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
90414 | #define BIFPLR1_2_STATUS__INT_STATUS_MASK 0x0008L |
90415 | #define BIFPLR1_2_STATUS__CAP_LIST_MASK 0x0010L |
90416 | #define BIFPLR1_2_STATUS__PCI_66_EN_MASK 0x0020L |
90417 | #define BIFPLR1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
90418 | #define BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
90419 | #define BIFPLR1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
90420 | #define BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
90421 | #define BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
90422 | #define BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
90423 | #define BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
90424 | #define BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
90425 | //BIFPLR1_2_REVISION_ID |
90426 | #define BIFPLR1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
90427 | #define BIFPLR1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
90428 | #define BIFPLR1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
90429 | #define BIFPLR1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
90430 | //BIFPLR1_2_PROG_INTERFACE |
90431 | #define BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
90432 | #define BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
90433 | //BIFPLR1_2_SUB_CLASS |
90434 | #define BIFPLR1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
90435 | #define BIFPLR1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
90436 | //BIFPLR1_2_BASE_CLASS |
90437 | #define BIFPLR1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
90438 | #define BIFPLR1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
90439 | //BIFPLR1_2_CACHE_LINE |
90440 | #define BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
90441 | #define BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
90442 | //BIFPLR1_2_LATENCY |
90443 | #define BIFPLR1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
90444 | #define BIFPLR1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
90445 | //BIFPLR1_2_HEADER |
90446 | #define BIFPLR1_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
90447 | #define BIFPLR1_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
90448 | #define BIFPLR1_2_HEADER__HEADER_TYPE_MASK 0x7FL |
90449 | #define BIFPLR1_2_HEADER__DEVICE_TYPE_MASK 0x80L |
90450 | //BIFPLR1_2_BIST |
90451 | #define BIFPLR1_2_BIST__BIST_COMP__SHIFT 0x0 |
90452 | #define BIFPLR1_2_BIST__BIST_STRT__SHIFT 0x6 |
90453 | #define BIFPLR1_2_BIST__BIST_CAP__SHIFT 0x7 |
90454 | #define BIFPLR1_2_BIST__BIST_COMP_MASK 0x0FL |
90455 | #define BIFPLR1_2_BIST__BIST_STRT_MASK 0x40L |
90456 | #define BIFPLR1_2_BIST__BIST_CAP_MASK 0x80L |
90457 | //BIFPLR1_2_SUB_BUS_NUMBER_LATENCY |
90458 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
90459 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
90460 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
90461 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
90462 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
90463 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
90464 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
90465 | #define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
90466 | //BIFPLR1_2_IO_BASE_LIMIT |
90467 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
90468 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
90469 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
90470 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
90471 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
90472 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
90473 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
90474 | #define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
90475 | //BIFPLR1_2_SECONDARY_STATUS |
90476 | #define BIFPLR1_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
90477 | #define BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
90478 | #define BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
90479 | #define BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
90480 | #define BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
90481 | #define BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
90482 | #define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
90483 | #define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
90484 | #define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
90485 | #define BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
90486 | #define BIFPLR1_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
90487 | #define BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
90488 | #define BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
90489 | #define BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
90490 | #define BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
90491 | #define BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
90492 | #define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
90493 | #define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
90494 | #define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
90495 | #define BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
90496 | //BIFPLR1_2_MEM_BASE_LIMIT |
90497 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
90498 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
90499 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
90500 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
90501 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
90502 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
90503 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
90504 | #define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
90505 | //BIFPLR1_2_PREF_BASE_LIMIT |
90506 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
90507 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
90508 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
90509 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
90510 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
90511 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
90512 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
90513 | #define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
90514 | //BIFPLR1_2_PREF_BASE_UPPER |
90515 | #define BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
90516 | #define BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
90517 | //BIFPLR1_2_PREF_LIMIT_UPPER |
90518 | #define BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
90519 | #define BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
90520 | //BIFPLR1_2_IO_BASE_LIMIT_HI |
90521 | #define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
90522 | #define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
90523 | #define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
90524 | #define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
90525 | //BIFPLR1_2_CAP_PTR |
90526 | #define BIFPLR1_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
90527 | #define BIFPLR1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
90528 | //BIFPLR1_2_INTERRUPT_LINE |
90529 | #define BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
90530 | #define BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
90531 | //BIFPLR1_2_INTERRUPT_PIN |
90532 | #define BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
90533 | #define BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
90534 | //BIFPLR1_2_IRQ_BRIDGE_CNTL |
90535 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
90536 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
90537 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
90538 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
90539 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
90540 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
90541 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
90542 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
90543 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
90544 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
90545 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
90546 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
90547 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
90548 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
90549 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
90550 | #define BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
90551 | //BIFPLR1_2_EXT_BRIDGE_CNTL |
90552 | #define BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
90553 | #define BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
90554 | //BIFPLR1_2_PMI_CAP_LIST |
90555 | #define BIFPLR1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
90556 | #define BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
90557 | #define BIFPLR1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
90558 | #define BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
90559 | //BIFPLR1_2_PMI_CAP |
90560 | #define BIFPLR1_2_PMI_CAP__VERSION__SHIFT 0x0 |
90561 | #define BIFPLR1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
90562 | #define BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
90563 | #define BIFPLR1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
90564 | #define BIFPLR1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
90565 | #define BIFPLR1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
90566 | #define BIFPLR1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
90567 | #define BIFPLR1_2_PMI_CAP__VERSION_MASK 0x0007L |
90568 | #define BIFPLR1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
90569 | #define BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
90570 | #define BIFPLR1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
90571 | #define BIFPLR1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
90572 | #define BIFPLR1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
90573 | #define BIFPLR1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
90574 | //BIFPLR1_2_PMI_STATUS_CNTL |
90575 | #define BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
90576 | #define BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
90577 | #define BIFPLR1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
90578 | #define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
90579 | #define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
90580 | #define BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
90581 | #define BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
90582 | #define BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
90583 | #define BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
90584 | #define BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
90585 | #define BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
90586 | #define BIFPLR1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
90587 | #define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
90588 | #define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
90589 | #define BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
90590 | #define BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
90591 | #define BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
90592 | #define BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
90593 | //BIFPLR1_2_PCIE_CAP_LIST |
90594 | #define BIFPLR1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
90595 | #define BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
90596 | #define BIFPLR1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
90597 | #define BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
90598 | //BIFPLR1_2_PCIE_CAP |
90599 | #define BIFPLR1_2_PCIE_CAP__VERSION__SHIFT 0x0 |
90600 | #define BIFPLR1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
90601 | #define BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
90602 | #define BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
90603 | #define BIFPLR1_2_PCIE_CAP__VERSION_MASK 0x000FL |
90604 | #define BIFPLR1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
90605 | #define BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
90606 | #define BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
90607 | //BIFPLR1_2_DEVICE_CAP |
90608 | #define BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
90609 | #define BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
90610 | #define BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
90611 | #define BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
90612 | #define BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
90613 | #define BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
90614 | #define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
90615 | #define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
90616 | #define BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
90617 | #define BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
90618 | #define BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
90619 | #define BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
90620 | #define BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
90621 | #define BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
90622 | #define BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
90623 | #define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
90624 | #define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
90625 | #define BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
90626 | //BIFPLR1_2_DEVICE_CNTL |
90627 | #define BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
90628 | #define BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
90629 | #define BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
90630 | #define BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
90631 | #define BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
90632 | #define BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
90633 | #define BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
90634 | #define BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
90635 | #define BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
90636 | #define BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
90637 | #define BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
90638 | #define BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
90639 | #define BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
90640 | #define BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
90641 | #define BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
90642 | #define BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
90643 | #define BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
90644 | #define BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
90645 | #define BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
90646 | #define BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
90647 | #define BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
90648 | #define BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
90649 | #define BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
90650 | #define BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
90651 | //BIFPLR1_2_DEVICE_STATUS |
90652 | #define BIFPLR1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
90653 | #define BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
90654 | #define BIFPLR1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
90655 | #define BIFPLR1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
90656 | #define BIFPLR1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
90657 | #define BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
90658 | #define BIFPLR1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
90659 | #define BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
90660 | #define BIFPLR1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
90661 | #define BIFPLR1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
90662 | #define BIFPLR1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
90663 | #define BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
90664 | //BIFPLR1_2_LINK_CAP |
90665 | #define BIFPLR1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
90666 | #define BIFPLR1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
90667 | #define BIFPLR1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
90668 | #define BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
90669 | #define BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
90670 | #define BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
90671 | #define BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
90672 | #define BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
90673 | #define BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
90674 | #define BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
90675 | #define BIFPLR1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
90676 | #define BIFPLR1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
90677 | #define BIFPLR1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
90678 | #define BIFPLR1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
90679 | #define BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
90680 | #define BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
90681 | #define BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
90682 | #define BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
90683 | #define BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
90684 | #define BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
90685 | #define BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
90686 | #define BIFPLR1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
90687 | //BIFPLR1_2_LINK_CNTL |
90688 | #define BIFPLR1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
90689 | #define BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
90690 | #define BIFPLR1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
90691 | #define BIFPLR1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
90692 | #define BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
90693 | #define BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
90694 | #define BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
90695 | #define BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
90696 | #define BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
90697 | #define BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
90698 | #define BIFPLR1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
90699 | #define BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
90700 | #define BIFPLR1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
90701 | #define BIFPLR1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
90702 | #define BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
90703 | #define BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
90704 | #define BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
90705 | #define BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
90706 | #define BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
90707 | #define BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
90708 | //BIFPLR1_2_LINK_STATUS |
90709 | #define BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
90710 | #define BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
90711 | #define BIFPLR1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
90712 | #define BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
90713 | #define BIFPLR1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
90714 | #define BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
90715 | #define BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
90716 | #define BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
90717 | #define BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
90718 | #define BIFPLR1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
90719 | #define BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
90720 | #define BIFPLR1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
90721 | #define BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
90722 | #define BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
90723 | //BIFPLR1_2_SLOT_CAP |
90724 | #define BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
90725 | #define BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
90726 | #define BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
90727 | #define BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
90728 | #define BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
90729 | #define BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
90730 | #define BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
90731 | #define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
90732 | #define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
90733 | #define BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
90734 | #define BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
90735 | #define BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
90736 | #define BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
90737 | #define BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
90738 | #define BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
90739 | #define BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
90740 | #define BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
90741 | #define BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
90742 | #define BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
90743 | #define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
90744 | #define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
90745 | #define BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
90746 | #define BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
90747 | #define BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
90748 | //BIFPLR1_2_SLOT_CNTL |
90749 | #define BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
90750 | #define BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
90751 | #define BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
90752 | #define BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
90753 | #define BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
90754 | #define BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
90755 | #define BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
90756 | #define BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
90757 | #define BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
90758 | #define BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
90759 | #define BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
90760 | #define BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
90761 | #define BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
90762 | #define BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
90763 | #define BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
90764 | #define BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
90765 | #define BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
90766 | #define BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
90767 | #define BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
90768 | #define BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
90769 | #define BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
90770 | #define BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
90771 | #define BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
90772 | #define BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
90773 | //BIFPLR1_2_SLOT_STATUS |
90774 | #define BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
90775 | #define BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
90776 | #define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
90777 | #define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
90778 | #define BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
90779 | #define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
90780 | #define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
90781 | #define BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
90782 | #define BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
90783 | #define BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
90784 | #define BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
90785 | #define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
90786 | #define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
90787 | #define BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
90788 | #define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
90789 | #define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
90790 | #define BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
90791 | #define BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
90792 | //BIFPLR1_2_ROOT_CNTL |
90793 | #define BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
90794 | #define BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
90795 | #define BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
90796 | #define BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
90797 | #define BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
90798 | #define BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
90799 | #define BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
90800 | #define BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
90801 | #define BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
90802 | #define BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
90803 | //BIFPLR1_2_ROOT_CAP |
90804 | #define BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
90805 | #define BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
90806 | //BIFPLR1_2_ROOT_STATUS |
90807 | #define BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
90808 | #define BIFPLR1_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
90809 | #define BIFPLR1_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
90810 | #define BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
90811 | #define BIFPLR1_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
90812 | #define BIFPLR1_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
90813 | //BIFPLR1_2_DEVICE_CAP2 |
90814 | #define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
90815 | #define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
90816 | #define BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
90817 | #define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
90818 | #define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
90819 | #define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
90820 | #define BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
90821 | #define BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
90822 | #define BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
90823 | #define BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
90824 | #define BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
90825 | #define BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
90826 | #define BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
90827 | #define BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
90828 | #define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
90829 | #define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
90830 | #define BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
90831 | #define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
90832 | #define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
90833 | #define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
90834 | #define BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
90835 | #define BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
90836 | #define BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
90837 | #define BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
90838 | #define BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
90839 | #define BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
90840 | #define BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
90841 | #define BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
90842 | //BIFPLR1_2_DEVICE_CNTL2 |
90843 | #define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
90844 | #define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
90845 | #define BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
90846 | #define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
90847 | #define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
90848 | #define BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
90849 | #define BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
90850 | #define BIFPLR1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
90851 | #define BIFPLR1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
90852 | #define BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
90853 | #define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
90854 | #define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
90855 | #define BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
90856 | #define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
90857 | #define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
90858 | #define BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
90859 | #define BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
90860 | #define BIFPLR1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
90861 | #define BIFPLR1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
90862 | #define BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
90863 | //BIFPLR1_2_DEVICE_STATUS2 |
90864 | #define BIFPLR1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
90865 | #define BIFPLR1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
90866 | //BIFPLR1_2_LINK_CAP2 |
90867 | #define BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
90868 | #define BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
90869 | #define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
90870 | #define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
90871 | #define BIFPLR1_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
90872 | #define BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
90873 | #define BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
90874 | #define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
90875 | #define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
90876 | #define BIFPLR1_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
90877 | //BIFPLR1_2_LINK_CNTL2 |
90878 | #define BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
90879 | #define BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
90880 | #define BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
90881 | #define BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
90882 | #define BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
90883 | #define BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
90884 | #define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
90885 | #define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
90886 | #define BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
90887 | #define BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
90888 | #define BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
90889 | #define BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
90890 | #define BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
90891 | #define BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
90892 | #define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
90893 | #define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
90894 | //BIFPLR1_2_LINK_STATUS2 |
90895 | #define BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
90896 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
90897 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
90898 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
90899 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
90900 | #define BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
90901 | #define BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
90902 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
90903 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
90904 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
90905 | #define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
90906 | #define BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
90907 | //BIFPLR1_2_SLOT_CAP2 |
90908 | #define BIFPLR1_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
90909 | #define BIFPLR1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
90910 | //BIFPLR1_2_SLOT_CNTL2 |
90911 | #define BIFPLR1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
90912 | #define BIFPLR1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
90913 | //BIFPLR1_2_SLOT_STATUS2 |
90914 | #define BIFPLR1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
90915 | #define BIFPLR1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
90916 | //BIFPLR1_2_MSI_CAP_LIST |
90917 | #define BIFPLR1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
90918 | #define BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
90919 | #define BIFPLR1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
90920 | #define BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
90921 | //BIFPLR1_2_MSI_MSG_CNTL |
90922 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
90923 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
90924 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
90925 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
90926 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
90927 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
90928 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
90929 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
90930 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
90931 | #define BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
90932 | //BIFPLR1_2_MSI_MSG_ADDR_LO |
90933 | #define BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
90934 | #define BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
90935 | //BIFPLR1_2_MSI_MSG_ADDR_HI |
90936 | #define BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
90937 | #define BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
90938 | //BIFPLR1_2_MSI_MSG_DATA |
90939 | #define BIFPLR1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
90940 | #define BIFPLR1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
90941 | //BIFPLR1_2_MSI_MSG_DATA_64 |
90942 | #define BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
90943 | #define BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
90944 | //BIFPLR1_2_SSID_CAP_LIST |
90945 | #define BIFPLR1_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
90946 | #define BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
90947 | #define BIFPLR1_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
90948 | #define BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
90949 | //BIFPLR1_2_SSID_CAP |
90950 | #define BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
90951 | #define BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
90952 | #define BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
90953 | #define BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
90954 | //BIFPLR1_2_MSI_MAP_CAP_LIST |
90955 | #define BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
90956 | #define BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
90957 | #define BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
90958 | #define BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
90959 | //BIFPLR1_2_MSI_MAP_CAP |
90960 | #define BIFPLR1_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
90961 | #define BIFPLR1_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
90962 | #define BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
90963 | #define BIFPLR1_2_MSI_MAP_CAP__EN_MASK 0x0001L |
90964 | #define BIFPLR1_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
90965 | #define BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
90966 | //BIFPLR1_2_MSI_MAP_ADDR_LO |
90967 | #define BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
90968 | #define BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
90969 | //BIFPLR1_2_MSI_MAP_ADDR_HI |
90970 | #define BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
90971 | #define BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
90972 | //BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
90973 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
90974 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
90975 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
90976 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
90977 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
90978 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
90979 | //BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR |
90980 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
90981 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
90982 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
90983 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
90984 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
90985 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
90986 | //BIFPLR1_2_PCIE_VENDOR_SPECIFIC1 |
90987 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
90988 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
90989 | //BIFPLR1_2_PCIE_VENDOR_SPECIFIC2 |
90990 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
90991 | #define BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
90992 | //BIFPLR1_2_PCIE_VC_ENH_CAP_LIST |
90993 | #define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
90994 | #define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
90995 | #define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
90996 | #define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
90997 | #define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
90998 | #define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
90999 | //BIFPLR1_2_PCIE_PORT_VC_CAP_REG1 |
91000 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
91001 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
91002 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
91003 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
91004 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
91005 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
91006 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
91007 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
91008 | //BIFPLR1_2_PCIE_PORT_VC_CAP_REG2 |
91009 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
91010 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
91011 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
91012 | #define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
91013 | //BIFPLR1_2_PCIE_PORT_VC_CNTL |
91014 | #define BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
91015 | #define BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
91016 | #define BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
91017 | #define BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
91018 | //BIFPLR1_2_PCIE_PORT_VC_STATUS |
91019 | #define BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
91020 | #define BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
91021 | //BIFPLR1_2_PCIE_VC0_RESOURCE_CAP |
91022 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
91023 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
91024 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
91025 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
91026 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
91027 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
91028 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
91029 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
91030 | //BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL |
91031 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
91032 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
91033 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
91034 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
91035 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
91036 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
91037 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
91038 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
91039 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
91040 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
91041 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
91042 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
91043 | //BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS |
91044 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
91045 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
91046 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
91047 | #define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
91048 | //BIFPLR1_2_PCIE_VC1_RESOURCE_CAP |
91049 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
91050 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
91051 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
91052 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
91053 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
91054 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
91055 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
91056 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
91057 | //BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL |
91058 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
91059 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
91060 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
91061 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
91062 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
91063 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
91064 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
91065 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
91066 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
91067 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
91068 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
91069 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
91070 | //BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS |
91071 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
91072 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
91073 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
91074 | #define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
91075 | //BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
91076 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
91077 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
91078 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91079 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91080 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91081 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91082 | //BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1 |
91083 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
91084 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
91085 | //BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2 |
91086 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
91087 | #define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
91088 | //BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
91089 | #define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
91090 | #define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
91091 | #define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91092 | #define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91093 | #define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91094 | #define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91095 | //BIFPLR1_2_PCIE_UNCORR_ERR_STATUS |
91096 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
91097 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
91098 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
91099 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
91100 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
91101 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
91102 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
91103 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
91104 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
91105 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
91106 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
91107 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
91108 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
91109 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
91110 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
91111 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
91112 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
91113 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
91114 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
91115 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
91116 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
91117 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
91118 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
91119 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
91120 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
91121 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
91122 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
91123 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
91124 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
91125 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
91126 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
91127 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
91128 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
91129 | #define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
91130 | //BIFPLR1_2_PCIE_UNCORR_ERR_MASK |
91131 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
91132 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
91133 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
91134 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
91135 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
91136 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
91137 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
91138 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
91139 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
91140 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
91141 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
91142 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
91143 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
91144 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
91145 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
91146 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
91147 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
91148 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
91149 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
91150 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
91151 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
91152 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
91153 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
91154 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
91155 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
91156 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
91157 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
91158 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
91159 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
91160 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
91161 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
91162 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
91163 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
91164 | #define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
91165 | //BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY |
91166 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
91167 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
91168 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
91169 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
91170 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
91171 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
91172 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
91173 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
91174 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
91175 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
91176 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
91177 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
91178 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
91179 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
91180 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
91181 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
91182 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
91183 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
91184 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
91185 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
91186 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
91187 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
91188 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
91189 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
91190 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
91191 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
91192 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
91193 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
91194 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
91195 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
91196 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
91197 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
91198 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
91199 | #define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
91200 | //BIFPLR1_2_PCIE_CORR_ERR_STATUS |
91201 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
91202 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
91203 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
91204 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
91205 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
91206 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
91207 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
91208 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
91209 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
91210 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
91211 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
91212 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
91213 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
91214 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
91215 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
91216 | #define BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
91217 | //BIFPLR1_2_PCIE_CORR_ERR_MASK |
91218 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
91219 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
91220 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
91221 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
91222 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
91223 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
91224 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
91225 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
91226 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
91227 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
91228 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
91229 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
91230 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
91231 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
91232 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
91233 | #define BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
91234 | //BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL |
91235 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
91236 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
91237 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
91238 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
91239 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
91240 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
91241 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
91242 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
91243 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
91244 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
91245 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
91246 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
91247 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
91248 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
91249 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
91250 | #define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
91251 | //BIFPLR1_2_PCIE_HDR_LOG0 |
91252 | #define BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
91253 | #define BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
91254 | //BIFPLR1_2_PCIE_HDR_LOG1 |
91255 | #define BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
91256 | #define BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
91257 | //BIFPLR1_2_PCIE_HDR_LOG2 |
91258 | #define BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
91259 | #define BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
91260 | //BIFPLR1_2_PCIE_HDR_LOG3 |
91261 | #define BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
91262 | #define BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
91263 | //BIFPLR1_2_PCIE_ROOT_ERR_CMD |
91264 | #define BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
91265 | #define BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
91266 | #define BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
91267 | #define BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
91268 | #define BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
91269 | #define BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
91270 | //BIFPLR1_2_PCIE_ROOT_ERR_STATUS |
91271 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
91272 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
91273 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
91274 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
91275 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
91276 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
91277 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
91278 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
91279 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
91280 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
91281 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
91282 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
91283 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
91284 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
91285 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
91286 | #define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
91287 | //BIFPLR1_2_PCIE_ERR_SRC_ID |
91288 | #define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
91289 | #define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
91290 | #define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
91291 | #define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
91292 | //BIFPLR1_2_PCIE_TLP_PREFIX_LOG0 |
91293 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
91294 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
91295 | //BIFPLR1_2_PCIE_TLP_PREFIX_LOG1 |
91296 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
91297 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
91298 | //BIFPLR1_2_PCIE_TLP_PREFIX_LOG2 |
91299 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
91300 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
91301 | //BIFPLR1_2_PCIE_TLP_PREFIX_LOG3 |
91302 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
91303 | #define BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
91304 | //BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST |
91305 | #define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
91306 | #define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
91307 | #define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91308 | #define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91309 | #define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91310 | #define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91311 | //BIFPLR1_2_PCIE_LINK_CNTL3 |
91312 | #define BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
91313 | #define BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
91314 | #define BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
91315 | #define BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
91316 | #define BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
91317 | #define BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
91318 | #define BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
91319 | #define BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
91320 | //BIFPLR1_2_PCIE_LANE_ERROR_STATUS |
91321 | #define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
91322 | #define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
91323 | #define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
91324 | #define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
91325 | //BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL |
91326 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91327 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91328 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91329 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91330 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91331 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91332 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91333 | #define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91334 | //BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL |
91335 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91336 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91337 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91338 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91339 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91340 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91341 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91342 | #define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91343 | //BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL |
91344 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91345 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91346 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91347 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91348 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91349 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91350 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91351 | #define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91352 | //BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL |
91353 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91354 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91355 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91356 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91357 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91358 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91359 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91360 | #define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91361 | //BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL |
91362 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91363 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91364 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91365 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91366 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91367 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91368 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91369 | #define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91370 | //BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL |
91371 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91372 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91373 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91374 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91375 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91376 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91377 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91378 | #define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91379 | //BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL |
91380 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91381 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91382 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91383 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91384 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91385 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91386 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91387 | #define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91388 | //BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL |
91389 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91390 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91391 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91392 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91393 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91394 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91395 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91396 | #define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91397 | //BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL |
91398 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91399 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91400 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91401 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91402 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91403 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91404 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91405 | #define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91406 | //BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL |
91407 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91408 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91409 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91410 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91411 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91412 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91413 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91414 | #define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91415 | //BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL |
91416 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91417 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91418 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91419 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91420 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91421 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91422 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91423 | #define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91424 | //BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL |
91425 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91426 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91427 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91428 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91429 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91430 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91431 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91432 | #define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91433 | //BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL |
91434 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91435 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91436 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91437 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91438 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91439 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91440 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91441 | #define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91442 | //BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL |
91443 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91444 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91445 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91446 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91447 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91448 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91449 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91450 | #define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91451 | //BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL |
91452 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91453 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91454 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91455 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91456 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91457 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91458 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91459 | #define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91460 | //BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL |
91461 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
91462 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
91463 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
91464 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
91465 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
91466 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
91467 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
91468 | #define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
91469 | //BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST |
91470 | #define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
91471 | #define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
91472 | #define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91473 | #define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91474 | #define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91475 | #define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91476 | //BIFPLR1_2_PCIE_ACS_CAP |
91477 | #define BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
91478 | #define BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
91479 | #define BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
91480 | #define BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
91481 | #define BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
91482 | #define BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
91483 | #define BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
91484 | #define BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
91485 | #define BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
91486 | #define BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
91487 | #define BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
91488 | #define BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
91489 | #define BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
91490 | #define BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
91491 | #define BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
91492 | #define BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
91493 | //BIFPLR1_2_PCIE_ACS_CNTL |
91494 | #define BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
91495 | #define BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
91496 | #define BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
91497 | #define BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
91498 | #define BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
91499 | #define BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
91500 | #define BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
91501 | #define BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
91502 | #define BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
91503 | #define BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
91504 | #define BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
91505 | #define BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
91506 | #define BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
91507 | #define BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
91508 | //BIFPLR1_2_PCIE_MC_ENH_CAP_LIST |
91509 | #define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
91510 | #define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
91511 | #define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91512 | #define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91513 | #define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91514 | #define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91515 | //BIFPLR1_2_PCIE_MC_CAP |
91516 | #define BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
91517 | #define BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
91518 | #define BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
91519 | #define BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
91520 | //BIFPLR1_2_PCIE_MC_CNTL |
91521 | #define BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
91522 | #define BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
91523 | #define BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
91524 | #define BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
91525 | //BIFPLR1_2_PCIE_MC_ADDR0 |
91526 | #define BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
91527 | #define BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
91528 | #define BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
91529 | #define BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
91530 | //BIFPLR1_2_PCIE_MC_ADDR1 |
91531 | #define BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
91532 | #define BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
91533 | //BIFPLR1_2_PCIE_MC_RCV0 |
91534 | #define BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
91535 | #define BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
91536 | //BIFPLR1_2_PCIE_MC_RCV1 |
91537 | #define BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
91538 | #define BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
91539 | //BIFPLR1_2_PCIE_MC_BLOCK_ALL0 |
91540 | #define BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
91541 | #define BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
91542 | //BIFPLR1_2_PCIE_MC_BLOCK_ALL1 |
91543 | #define BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
91544 | #define BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
91545 | //BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
91546 | #define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
91547 | #define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
91548 | //BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
91549 | #define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
91550 | #define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
91551 | //BIFPLR1_2_PCIE_MC_OVERLAY_BAR0 |
91552 | #define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
91553 | #define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
91554 | #define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
91555 | #define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
91556 | //BIFPLR1_2_PCIE_MC_OVERLAY_BAR1 |
91557 | #define BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
91558 | #define BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
91559 | //BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST |
91560 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
91561 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
91562 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91563 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91564 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91565 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91566 | //BIFPLR1_2_PCIE_L1_PM_SUB_CAP |
91567 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
91568 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
91569 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
91570 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
91571 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
91572 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
91573 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
91574 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
91575 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
91576 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
91577 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
91578 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
91579 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
91580 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
91581 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
91582 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
91583 | //BIFPLR1_2_PCIE_L1_PM_SUB_CNTL |
91584 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
91585 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
91586 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
91587 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
91588 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
91589 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
91590 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
91591 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
91592 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
91593 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
91594 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
91595 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
91596 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
91597 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
91598 | //BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2 |
91599 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
91600 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
91601 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
91602 | #define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
91603 | //BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST |
91604 | #define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
91605 | #define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
91606 | #define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91607 | #define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91608 | #define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91609 | #define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91610 | //BIFPLR1_2_PCIE_DPC_CAP_LIST |
91611 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
91612 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
91613 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
91614 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
91615 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
91616 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
91617 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
91618 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
91619 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
91620 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
91621 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
91622 | #define BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
91623 | //BIFPLR1_2_PCIE_DPC_CNTL |
91624 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
91625 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
91626 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
91627 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
91628 | #define BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
91629 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
91630 | #define BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
91631 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
91632 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
91633 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
91634 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
91635 | #define BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
91636 | #define BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
91637 | #define BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
91638 | //BIFPLR1_2_PCIE_DPC_STATUS |
91639 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
91640 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
91641 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
91642 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
91643 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
91644 | #define BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
91645 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
91646 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
91647 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
91648 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
91649 | #define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
91650 | #define BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
91651 | //BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID |
91652 | #define BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
91653 | #define BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
91654 | //BIFPLR1_2_PCIE_RP_PIO_STATUS |
91655 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
91656 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
91657 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
91658 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
91659 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
91660 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
91661 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
91662 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
91663 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
91664 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
91665 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
91666 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
91667 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
91668 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
91669 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
91670 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
91671 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
91672 | #define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
91673 | //BIFPLR1_2_PCIE_RP_PIO_MASK |
91674 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
91675 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
91676 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
91677 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
91678 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
91679 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
91680 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
91681 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
91682 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
91683 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
91684 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
91685 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
91686 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
91687 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
91688 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
91689 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
91690 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
91691 | #define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
91692 | //BIFPLR1_2_PCIE_RP_PIO_SEVERITY |
91693 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
91694 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
91695 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
91696 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
91697 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
91698 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
91699 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
91700 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
91701 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
91702 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
91703 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
91704 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
91705 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
91706 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
91707 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
91708 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
91709 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
91710 | #define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
91711 | //BIFPLR1_2_PCIE_RP_PIO_SYSERROR |
91712 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
91713 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
91714 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
91715 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
91716 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
91717 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
91718 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
91719 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
91720 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
91721 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
91722 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
91723 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
91724 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
91725 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
91726 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
91727 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
91728 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
91729 | #define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
91730 | //BIFPLR1_2_PCIE_RP_PIO_EXCEPTION |
91731 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
91732 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
91733 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
91734 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
91735 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
91736 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
91737 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
91738 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
91739 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
91740 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
91741 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
91742 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
91743 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
91744 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
91745 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
91746 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
91747 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
91748 | #define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
91749 | //BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0 |
91750 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
91751 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
91752 | //BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1 |
91753 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
91754 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
91755 | //BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2 |
91756 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
91757 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
91758 | //BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3 |
91759 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
91760 | #define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
91761 | //BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG |
91762 | #define BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
91763 | #define BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
91764 | //BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0 |
91765 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
91766 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
91767 | //BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1 |
91768 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
91769 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
91770 | //BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2 |
91771 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
91772 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
91773 | //BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3 |
91774 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
91775 | #define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
91776 | //BIFPLR1_2_PCIE_ESM_CAP_LIST |
91777 | #define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
91778 | #define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
91779 | #define BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
91780 | #define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
91781 | #define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
91782 | #define BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
91783 | //BIFPLR1_2_PCIE_ESM_HEADER_1 |
91784 | #define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
91785 | #define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
91786 | #define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
91787 | #define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
91788 | #define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
91789 | #define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
91790 | //BIFPLR1_2_PCIE_ESM_HEADER_2 |
91791 | #define BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
91792 | #define BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
91793 | //BIFPLR1_2_PCIE_ESM_STATUS |
91794 | #define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
91795 | #define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
91796 | #define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
91797 | #define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
91798 | //BIFPLR1_2_PCIE_ESM_CTRL |
91799 | #define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
91800 | #define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
91801 | #define BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
91802 | #define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
91803 | #define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
91804 | #define BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
91805 | //BIFPLR1_2_PCIE_ESM_CAP_1 |
91806 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
91807 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
91808 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
91809 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
91810 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
91811 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
91812 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
91813 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
91814 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
91815 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
91816 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
91817 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
91818 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
91819 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
91820 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
91821 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
91822 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
91823 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
91824 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
91825 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
91826 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
91827 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
91828 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
91829 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
91830 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
91831 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
91832 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
91833 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
91834 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
91835 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
91836 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
91837 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
91838 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
91839 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
91840 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
91841 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
91842 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
91843 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
91844 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
91845 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
91846 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
91847 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
91848 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
91849 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
91850 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
91851 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
91852 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
91853 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
91854 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
91855 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
91856 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
91857 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
91858 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
91859 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
91860 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
91861 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
91862 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
91863 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
91864 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
91865 | #define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
91866 | //BIFPLR1_2_PCIE_ESM_CAP_2 |
91867 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
91868 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
91869 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
91870 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
91871 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
91872 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
91873 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
91874 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
91875 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
91876 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
91877 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
91878 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
91879 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
91880 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
91881 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
91882 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
91883 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
91884 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
91885 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
91886 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
91887 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
91888 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
91889 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
91890 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
91891 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
91892 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
91893 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
91894 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
91895 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
91896 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
91897 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
91898 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
91899 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
91900 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
91901 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
91902 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
91903 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
91904 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
91905 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
91906 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
91907 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
91908 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
91909 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
91910 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
91911 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
91912 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
91913 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
91914 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
91915 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
91916 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
91917 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
91918 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
91919 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
91920 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
91921 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
91922 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
91923 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
91924 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
91925 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
91926 | #define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
91927 | //BIFPLR1_2_PCIE_ESM_CAP_3 |
91928 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
91929 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
91930 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
91931 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
91932 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
91933 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
91934 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
91935 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
91936 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
91937 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
91938 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
91939 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
91940 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
91941 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
91942 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
91943 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
91944 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
91945 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
91946 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
91947 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
91948 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
91949 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
91950 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
91951 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
91952 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
91953 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
91954 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
91955 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
91956 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
91957 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
91958 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
91959 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
91960 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
91961 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
91962 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
91963 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
91964 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
91965 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
91966 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
91967 | #define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
91968 | //BIFPLR1_2_PCIE_ESM_CAP_4 |
91969 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
91970 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
91971 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
91972 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
91973 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
91974 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
91975 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
91976 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
91977 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
91978 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
91979 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
91980 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
91981 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
91982 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
91983 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
91984 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
91985 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
91986 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
91987 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
91988 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
91989 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
91990 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
91991 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
91992 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
91993 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
91994 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
91995 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
91996 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
91997 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
91998 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
91999 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
92000 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
92001 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
92002 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
92003 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
92004 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
92005 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
92006 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
92007 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
92008 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
92009 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
92010 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
92011 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
92012 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
92013 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
92014 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
92015 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
92016 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
92017 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
92018 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
92019 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
92020 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
92021 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
92022 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
92023 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
92024 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
92025 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
92026 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
92027 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
92028 | #define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
92029 | //BIFPLR1_2_PCIE_ESM_CAP_5 |
92030 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
92031 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
92032 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
92033 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
92034 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
92035 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
92036 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
92037 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
92038 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
92039 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
92040 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
92041 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
92042 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
92043 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
92044 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
92045 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
92046 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
92047 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
92048 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
92049 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
92050 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
92051 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
92052 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
92053 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
92054 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
92055 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
92056 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
92057 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
92058 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
92059 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
92060 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
92061 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
92062 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
92063 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
92064 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
92065 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
92066 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
92067 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
92068 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
92069 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
92070 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
92071 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
92072 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
92073 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
92074 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
92075 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
92076 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
92077 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
92078 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
92079 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
92080 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
92081 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
92082 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
92083 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
92084 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
92085 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
92086 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
92087 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
92088 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
92089 | #define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
92090 | //BIFPLR1_2_PCIE_ESM_CAP_6 |
92091 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
92092 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
92093 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
92094 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
92095 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
92096 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
92097 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
92098 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
92099 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
92100 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
92101 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
92102 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
92103 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
92104 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
92105 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
92106 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
92107 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
92108 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
92109 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
92110 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
92111 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
92112 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
92113 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
92114 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
92115 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
92116 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
92117 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
92118 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
92119 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
92120 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
92121 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
92122 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
92123 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
92124 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
92125 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
92126 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
92127 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
92128 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
92129 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
92130 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
92131 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
92132 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
92133 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
92134 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
92135 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
92136 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
92137 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
92138 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
92139 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
92140 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
92141 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
92142 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
92143 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
92144 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
92145 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
92146 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
92147 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
92148 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
92149 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
92150 | #define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
92151 | //BIFPLR1_2_PCIE_ESM_CAP_7 |
92152 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
92153 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
92154 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
92155 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
92156 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
92157 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
92158 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
92159 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
92160 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
92161 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
92162 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
92163 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
92164 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
92165 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
92166 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
92167 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
92168 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
92169 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
92170 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
92171 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
92172 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
92173 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
92174 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
92175 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
92176 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
92177 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
92178 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
92179 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
92180 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
92181 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
92182 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
92183 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
92184 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
92185 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
92186 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
92187 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
92188 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
92189 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
92190 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
92191 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
92192 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
92193 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
92194 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
92195 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
92196 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
92197 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
92198 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
92199 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
92200 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
92201 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
92202 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
92203 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
92204 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
92205 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
92206 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
92207 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
92208 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
92209 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
92210 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
92211 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
92212 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
92213 | #define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
92214 | |
92215 | |
92216 | // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
92217 | //BIFPLR2_2_VENDOR_ID |
92218 | #define BIFPLR2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
92219 | #define BIFPLR2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
92220 | //BIFPLR2_2_DEVICE_ID |
92221 | #define BIFPLR2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
92222 | #define BIFPLR2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
92223 | //BIFPLR2_2_COMMAND |
92224 | #define BIFPLR2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
92225 | #define BIFPLR2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
92226 | #define BIFPLR2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
92227 | #define BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
92228 | #define BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
92229 | #define BIFPLR2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
92230 | #define BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
92231 | #define BIFPLR2_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
92232 | #define BIFPLR2_2_COMMAND__SERR_EN__SHIFT 0x8 |
92233 | #define BIFPLR2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
92234 | #define BIFPLR2_2_COMMAND__INT_DIS__SHIFT 0xa |
92235 | #define BIFPLR2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
92236 | #define BIFPLR2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
92237 | #define BIFPLR2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
92238 | #define BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
92239 | #define BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
92240 | #define BIFPLR2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
92241 | #define BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
92242 | #define BIFPLR2_2_COMMAND__AD_STEPPING_MASK 0x0080L |
92243 | #define BIFPLR2_2_COMMAND__SERR_EN_MASK 0x0100L |
92244 | #define BIFPLR2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
92245 | #define BIFPLR2_2_COMMAND__INT_DIS_MASK 0x0400L |
92246 | //BIFPLR2_2_STATUS |
92247 | #define BIFPLR2_2_STATUS__INT_STATUS__SHIFT 0x3 |
92248 | #define BIFPLR2_2_STATUS__CAP_LIST__SHIFT 0x4 |
92249 | #define BIFPLR2_2_STATUS__PCI_66_EN__SHIFT 0x5 |
92250 | #define BIFPLR2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
92251 | #define BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
92252 | #define BIFPLR2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
92253 | #define BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
92254 | #define BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
92255 | #define BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
92256 | #define BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
92257 | #define BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
92258 | #define BIFPLR2_2_STATUS__INT_STATUS_MASK 0x0008L |
92259 | #define BIFPLR2_2_STATUS__CAP_LIST_MASK 0x0010L |
92260 | #define BIFPLR2_2_STATUS__PCI_66_EN_MASK 0x0020L |
92261 | #define BIFPLR2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
92262 | #define BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
92263 | #define BIFPLR2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
92264 | #define BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
92265 | #define BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
92266 | #define BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
92267 | #define BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
92268 | #define BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
92269 | //BIFPLR2_2_REVISION_ID |
92270 | #define BIFPLR2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
92271 | #define BIFPLR2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
92272 | #define BIFPLR2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
92273 | #define BIFPLR2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
92274 | //BIFPLR2_2_PROG_INTERFACE |
92275 | #define BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
92276 | #define BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
92277 | //BIFPLR2_2_SUB_CLASS |
92278 | #define BIFPLR2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
92279 | #define BIFPLR2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
92280 | //BIFPLR2_2_BASE_CLASS |
92281 | #define BIFPLR2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
92282 | #define BIFPLR2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
92283 | //BIFPLR2_2_CACHE_LINE |
92284 | #define BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
92285 | #define BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
92286 | //BIFPLR2_2_LATENCY |
92287 | #define BIFPLR2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
92288 | #define BIFPLR2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
92289 | //BIFPLR2_2_HEADER |
92290 | #define BIFPLR2_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
92291 | #define BIFPLR2_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
92292 | #define BIFPLR2_2_HEADER__HEADER_TYPE_MASK 0x7FL |
92293 | #define BIFPLR2_2_HEADER__DEVICE_TYPE_MASK 0x80L |
92294 | //BIFPLR2_2_BIST |
92295 | #define BIFPLR2_2_BIST__BIST_COMP__SHIFT 0x0 |
92296 | #define BIFPLR2_2_BIST__BIST_STRT__SHIFT 0x6 |
92297 | #define BIFPLR2_2_BIST__BIST_CAP__SHIFT 0x7 |
92298 | #define BIFPLR2_2_BIST__BIST_COMP_MASK 0x0FL |
92299 | #define BIFPLR2_2_BIST__BIST_STRT_MASK 0x40L |
92300 | #define BIFPLR2_2_BIST__BIST_CAP_MASK 0x80L |
92301 | //BIFPLR2_2_SUB_BUS_NUMBER_LATENCY |
92302 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
92303 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
92304 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
92305 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
92306 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
92307 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
92308 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
92309 | #define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
92310 | //BIFPLR2_2_IO_BASE_LIMIT |
92311 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
92312 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
92313 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
92314 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
92315 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
92316 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
92317 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
92318 | #define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
92319 | //BIFPLR2_2_SECONDARY_STATUS |
92320 | #define BIFPLR2_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
92321 | #define BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
92322 | #define BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
92323 | #define BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
92324 | #define BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
92325 | #define BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
92326 | #define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
92327 | #define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
92328 | #define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
92329 | #define BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
92330 | #define BIFPLR2_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
92331 | #define BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
92332 | #define BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
92333 | #define BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
92334 | #define BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
92335 | #define BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
92336 | #define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
92337 | #define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
92338 | #define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
92339 | #define BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
92340 | //BIFPLR2_2_MEM_BASE_LIMIT |
92341 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
92342 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
92343 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
92344 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
92345 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
92346 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
92347 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
92348 | #define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
92349 | //BIFPLR2_2_PREF_BASE_LIMIT |
92350 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
92351 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
92352 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
92353 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
92354 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
92355 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
92356 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
92357 | #define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
92358 | //BIFPLR2_2_PREF_BASE_UPPER |
92359 | #define BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
92360 | #define BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
92361 | //BIFPLR2_2_PREF_LIMIT_UPPER |
92362 | #define BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
92363 | #define BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
92364 | //BIFPLR2_2_IO_BASE_LIMIT_HI |
92365 | #define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
92366 | #define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
92367 | #define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
92368 | #define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
92369 | //BIFPLR2_2_CAP_PTR |
92370 | #define BIFPLR2_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
92371 | #define BIFPLR2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
92372 | //BIFPLR2_2_INTERRUPT_LINE |
92373 | #define BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
92374 | #define BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
92375 | //BIFPLR2_2_INTERRUPT_PIN |
92376 | #define BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
92377 | #define BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
92378 | //BIFPLR2_2_IRQ_BRIDGE_CNTL |
92379 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
92380 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
92381 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
92382 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
92383 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
92384 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
92385 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
92386 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
92387 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
92388 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
92389 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
92390 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
92391 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
92392 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
92393 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
92394 | #define BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
92395 | //BIFPLR2_2_EXT_BRIDGE_CNTL |
92396 | #define BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
92397 | #define BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
92398 | //BIFPLR2_2_PMI_CAP_LIST |
92399 | #define BIFPLR2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
92400 | #define BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
92401 | #define BIFPLR2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
92402 | #define BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
92403 | //BIFPLR2_2_PMI_CAP |
92404 | #define BIFPLR2_2_PMI_CAP__VERSION__SHIFT 0x0 |
92405 | #define BIFPLR2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
92406 | #define BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
92407 | #define BIFPLR2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
92408 | #define BIFPLR2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
92409 | #define BIFPLR2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
92410 | #define BIFPLR2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
92411 | #define BIFPLR2_2_PMI_CAP__VERSION_MASK 0x0007L |
92412 | #define BIFPLR2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
92413 | #define BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
92414 | #define BIFPLR2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
92415 | #define BIFPLR2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
92416 | #define BIFPLR2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
92417 | #define BIFPLR2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
92418 | //BIFPLR2_2_PMI_STATUS_CNTL |
92419 | #define BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
92420 | #define BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
92421 | #define BIFPLR2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
92422 | #define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
92423 | #define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
92424 | #define BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
92425 | #define BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
92426 | #define BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
92427 | #define BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
92428 | #define BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
92429 | #define BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
92430 | #define BIFPLR2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
92431 | #define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
92432 | #define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
92433 | #define BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
92434 | #define BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
92435 | #define BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
92436 | #define BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
92437 | //BIFPLR2_2_PCIE_CAP_LIST |
92438 | #define BIFPLR2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
92439 | #define BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
92440 | #define BIFPLR2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
92441 | #define BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
92442 | //BIFPLR2_2_PCIE_CAP |
92443 | #define BIFPLR2_2_PCIE_CAP__VERSION__SHIFT 0x0 |
92444 | #define BIFPLR2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
92445 | #define BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
92446 | #define BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
92447 | #define BIFPLR2_2_PCIE_CAP__VERSION_MASK 0x000FL |
92448 | #define BIFPLR2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
92449 | #define BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
92450 | #define BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
92451 | //BIFPLR2_2_DEVICE_CAP |
92452 | #define BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
92453 | #define BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
92454 | #define BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
92455 | #define BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
92456 | #define BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
92457 | #define BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
92458 | #define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
92459 | #define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
92460 | #define BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
92461 | #define BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
92462 | #define BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
92463 | #define BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
92464 | #define BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
92465 | #define BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
92466 | #define BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
92467 | #define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
92468 | #define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
92469 | #define BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
92470 | //BIFPLR2_2_DEVICE_CNTL |
92471 | #define BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
92472 | #define BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
92473 | #define BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
92474 | #define BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
92475 | #define BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
92476 | #define BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
92477 | #define BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
92478 | #define BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
92479 | #define BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
92480 | #define BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
92481 | #define BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
92482 | #define BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
92483 | #define BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
92484 | #define BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
92485 | #define BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
92486 | #define BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
92487 | #define BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
92488 | #define BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
92489 | #define BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
92490 | #define BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
92491 | #define BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
92492 | #define BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
92493 | #define BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
92494 | #define BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
92495 | //BIFPLR2_2_DEVICE_STATUS |
92496 | #define BIFPLR2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
92497 | #define BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
92498 | #define BIFPLR2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
92499 | #define BIFPLR2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
92500 | #define BIFPLR2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
92501 | #define BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
92502 | #define BIFPLR2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
92503 | #define BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
92504 | #define BIFPLR2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
92505 | #define BIFPLR2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
92506 | #define BIFPLR2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
92507 | #define BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
92508 | //BIFPLR2_2_LINK_CAP |
92509 | #define BIFPLR2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
92510 | #define BIFPLR2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
92511 | #define BIFPLR2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
92512 | #define BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
92513 | #define BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
92514 | #define BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
92515 | #define BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
92516 | #define BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
92517 | #define BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
92518 | #define BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
92519 | #define BIFPLR2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
92520 | #define BIFPLR2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
92521 | #define BIFPLR2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
92522 | #define BIFPLR2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
92523 | #define BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
92524 | #define BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
92525 | #define BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
92526 | #define BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
92527 | #define BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
92528 | #define BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
92529 | #define BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
92530 | #define BIFPLR2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
92531 | //BIFPLR2_2_LINK_CNTL |
92532 | #define BIFPLR2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
92533 | #define BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
92534 | #define BIFPLR2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
92535 | #define BIFPLR2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
92536 | #define BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
92537 | #define BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
92538 | #define BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
92539 | #define BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
92540 | #define BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
92541 | #define BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
92542 | #define BIFPLR2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
92543 | #define BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
92544 | #define BIFPLR2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
92545 | #define BIFPLR2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
92546 | #define BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
92547 | #define BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
92548 | #define BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
92549 | #define BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
92550 | #define BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
92551 | #define BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
92552 | //BIFPLR2_2_LINK_STATUS |
92553 | #define BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
92554 | #define BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
92555 | #define BIFPLR2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
92556 | #define BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
92557 | #define BIFPLR2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
92558 | #define BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
92559 | #define BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
92560 | #define BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
92561 | #define BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
92562 | #define BIFPLR2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
92563 | #define BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
92564 | #define BIFPLR2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
92565 | #define BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
92566 | #define BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
92567 | //BIFPLR2_2_SLOT_CAP |
92568 | #define BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
92569 | #define BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
92570 | #define BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
92571 | #define BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
92572 | #define BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
92573 | #define BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
92574 | #define BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
92575 | #define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
92576 | #define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
92577 | #define BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
92578 | #define BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
92579 | #define BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
92580 | #define BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
92581 | #define BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
92582 | #define BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
92583 | #define BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
92584 | #define BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
92585 | #define BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
92586 | #define BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
92587 | #define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
92588 | #define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
92589 | #define BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
92590 | #define BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
92591 | #define BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
92592 | //BIFPLR2_2_SLOT_CNTL |
92593 | #define BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
92594 | #define BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
92595 | #define BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
92596 | #define BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
92597 | #define BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
92598 | #define BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
92599 | #define BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
92600 | #define BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
92601 | #define BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
92602 | #define BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
92603 | #define BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
92604 | #define BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
92605 | #define BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
92606 | #define BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
92607 | #define BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
92608 | #define BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
92609 | #define BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
92610 | #define BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
92611 | #define BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
92612 | #define BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
92613 | #define BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
92614 | #define BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
92615 | #define BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
92616 | #define BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
92617 | //BIFPLR2_2_SLOT_STATUS |
92618 | #define BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
92619 | #define BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
92620 | #define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
92621 | #define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
92622 | #define BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
92623 | #define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
92624 | #define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
92625 | #define BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
92626 | #define BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
92627 | #define BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
92628 | #define BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
92629 | #define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
92630 | #define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
92631 | #define BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
92632 | #define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
92633 | #define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
92634 | #define BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
92635 | #define BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
92636 | //BIFPLR2_2_ROOT_CNTL |
92637 | #define BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
92638 | #define BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
92639 | #define BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
92640 | #define BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
92641 | #define BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
92642 | #define BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
92643 | #define BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
92644 | #define BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
92645 | #define BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
92646 | #define BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
92647 | //BIFPLR2_2_ROOT_CAP |
92648 | #define BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
92649 | #define BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
92650 | //BIFPLR2_2_ROOT_STATUS |
92651 | #define BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
92652 | #define BIFPLR2_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
92653 | #define BIFPLR2_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
92654 | #define BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
92655 | #define BIFPLR2_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
92656 | #define BIFPLR2_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
92657 | //BIFPLR2_2_DEVICE_CAP2 |
92658 | #define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
92659 | #define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
92660 | #define BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
92661 | #define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
92662 | #define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
92663 | #define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
92664 | #define BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
92665 | #define BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
92666 | #define BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
92667 | #define BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
92668 | #define BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
92669 | #define BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
92670 | #define BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
92671 | #define BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
92672 | #define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
92673 | #define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
92674 | #define BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
92675 | #define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
92676 | #define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
92677 | #define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
92678 | #define BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
92679 | #define BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
92680 | #define BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
92681 | #define BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
92682 | #define BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
92683 | #define BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
92684 | #define BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
92685 | #define BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
92686 | //BIFPLR2_2_DEVICE_CNTL2 |
92687 | #define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
92688 | #define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
92689 | #define BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
92690 | #define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
92691 | #define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
92692 | #define BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
92693 | #define BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
92694 | #define BIFPLR2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
92695 | #define BIFPLR2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
92696 | #define BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
92697 | #define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
92698 | #define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
92699 | #define BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
92700 | #define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
92701 | #define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
92702 | #define BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
92703 | #define BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
92704 | #define BIFPLR2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
92705 | #define BIFPLR2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
92706 | #define BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
92707 | //BIFPLR2_2_DEVICE_STATUS2 |
92708 | #define BIFPLR2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
92709 | #define BIFPLR2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
92710 | //BIFPLR2_2_LINK_CAP2 |
92711 | #define BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
92712 | #define BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
92713 | #define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
92714 | #define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
92715 | #define BIFPLR2_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
92716 | #define BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
92717 | #define BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
92718 | #define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
92719 | #define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
92720 | #define BIFPLR2_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
92721 | //BIFPLR2_2_LINK_CNTL2 |
92722 | #define BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
92723 | #define BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
92724 | #define BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
92725 | #define BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
92726 | #define BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
92727 | #define BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
92728 | #define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
92729 | #define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
92730 | #define BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
92731 | #define BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
92732 | #define BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
92733 | #define BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
92734 | #define BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
92735 | #define BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
92736 | #define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
92737 | #define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
92738 | //BIFPLR2_2_LINK_STATUS2 |
92739 | #define BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
92740 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
92741 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
92742 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
92743 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
92744 | #define BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
92745 | #define BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
92746 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
92747 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
92748 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
92749 | #define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
92750 | #define BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
92751 | //BIFPLR2_2_SLOT_CAP2 |
92752 | #define BIFPLR2_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
92753 | #define BIFPLR2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
92754 | //BIFPLR2_2_SLOT_CNTL2 |
92755 | #define BIFPLR2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
92756 | #define BIFPLR2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
92757 | //BIFPLR2_2_SLOT_STATUS2 |
92758 | #define BIFPLR2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
92759 | #define BIFPLR2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
92760 | //BIFPLR2_2_MSI_CAP_LIST |
92761 | #define BIFPLR2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
92762 | #define BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
92763 | #define BIFPLR2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
92764 | #define BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
92765 | //BIFPLR2_2_MSI_MSG_CNTL |
92766 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
92767 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
92768 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
92769 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
92770 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
92771 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
92772 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
92773 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
92774 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
92775 | #define BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
92776 | //BIFPLR2_2_MSI_MSG_ADDR_LO |
92777 | #define BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
92778 | #define BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
92779 | //BIFPLR2_2_MSI_MSG_ADDR_HI |
92780 | #define BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
92781 | #define BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
92782 | //BIFPLR2_2_MSI_MSG_DATA |
92783 | #define BIFPLR2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
92784 | #define BIFPLR2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
92785 | //BIFPLR2_2_MSI_MSG_DATA_64 |
92786 | #define BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
92787 | #define BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
92788 | //BIFPLR2_2_SSID_CAP_LIST |
92789 | #define BIFPLR2_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
92790 | #define BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
92791 | #define BIFPLR2_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
92792 | #define BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
92793 | //BIFPLR2_2_SSID_CAP |
92794 | #define BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
92795 | #define BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
92796 | #define BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
92797 | #define BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
92798 | //BIFPLR2_2_MSI_MAP_CAP_LIST |
92799 | #define BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
92800 | #define BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
92801 | #define BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
92802 | #define BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
92803 | //BIFPLR2_2_MSI_MAP_CAP |
92804 | #define BIFPLR2_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
92805 | #define BIFPLR2_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
92806 | #define BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
92807 | #define BIFPLR2_2_MSI_MAP_CAP__EN_MASK 0x0001L |
92808 | #define BIFPLR2_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
92809 | #define BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
92810 | //BIFPLR2_2_MSI_MAP_ADDR_LO |
92811 | #define BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
92812 | #define BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
92813 | //BIFPLR2_2_MSI_MAP_ADDR_HI |
92814 | #define BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
92815 | #define BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
92816 | //BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
92817 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
92818 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
92819 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
92820 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
92821 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
92822 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
92823 | //BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR |
92824 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
92825 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
92826 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
92827 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
92828 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
92829 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
92830 | //BIFPLR2_2_PCIE_VENDOR_SPECIFIC1 |
92831 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
92832 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
92833 | //BIFPLR2_2_PCIE_VENDOR_SPECIFIC2 |
92834 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
92835 | #define BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
92836 | //BIFPLR2_2_PCIE_VC_ENH_CAP_LIST |
92837 | #define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
92838 | #define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
92839 | #define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
92840 | #define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
92841 | #define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
92842 | #define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
92843 | //BIFPLR2_2_PCIE_PORT_VC_CAP_REG1 |
92844 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
92845 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
92846 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
92847 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
92848 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
92849 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
92850 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
92851 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
92852 | //BIFPLR2_2_PCIE_PORT_VC_CAP_REG2 |
92853 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
92854 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
92855 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
92856 | #define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
92857 | //BIFPLR2_2_PCIE_PORT_VC_CNTL |
92858 | #define BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
92859 | #define BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
92860 | #define BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
92861 | #define BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
92862 | //BIFPLR2_2_PCIE_PORT_VC_STATUS |
92863 | #define BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
92864 | #define BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
92865 | //BIFPLR2_2_PCIE_VC0_RESOURCE_CAP |
92866 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
92867 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
92868 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
92869 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
92870 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
92871 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
92872 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
92873 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
92874 | //BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL |
92875 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
92876 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
92877 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
92878 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
92879 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
92880 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
92881 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
92882 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
92883 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
92884 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
92885 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
92886 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
92887 | //BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS |
92888 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
92889 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
92890 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
92891 | #define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
92892 | //BIFPLR2_2_PCIE_VC1_RESOURCE_CAP |
92893 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
92894 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
92895 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
92896 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
92897 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
92898 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
92899 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
92900 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
92901 | //BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL |
92902 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
92903 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
92904 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
92905 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
92906 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
92907 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
92908 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
92909 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
92910 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
92911 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
92912 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
92913 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
92914 | //BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS |
92915 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
92916 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
92917 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
92918 | #define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
92919 | //BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
92920 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
92921 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
92922 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
92923 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
92924 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
92925 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
92926 | //BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1 |
92927 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
92928 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
92929 | //BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2 |
92930 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
92931 | #define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
92932 | //BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
92933 | #define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
92934 | #define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
92935 | #define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
92936 | #define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
92937 | #define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
92938 | #define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
92939 | //BIFPLR2_2_PCIE_UNCORR_ERR_STATUS |
92940 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
92941 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
92942 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
92943 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
92944 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
92945 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
92946 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
92947 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
92948 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
92949 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
92950 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
92951 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
92952 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
92953 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
92954 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
92955 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
92956 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
92957 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
92958 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
92959 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
92960 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
92961 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
92962 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
92963 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
92964 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
92965 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
92966 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
92967 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
92968 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
92969 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
92970 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
92971 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
92972 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
92973 | #define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
92974 | //BIFPLR2_2_PCIE_UNCORR_ERR_MASK |
92975 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
92976 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
92977 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
92978 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
92979 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
92980 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
92981 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
92982 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
92983 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
92984 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
92985 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
92986 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
92987 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
92988 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
92989 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
92990 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
92991 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
92992 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
92993 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
92994 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
92995 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
92996 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
92997 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
92998 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
92999 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
93000 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
93001 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
93002 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
93003 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
93004 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
93005 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
93006 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
93007 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
93008 | #define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
93009 | //BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY |
93010 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
93011 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
93012 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
93013 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
93014 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
93015 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
93016 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
93017 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
93018 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
93019 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
93020 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
93021 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
93022 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
93023 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
93024 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
93025 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
93026 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
93027 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
93028 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
93029 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
93030 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
93031 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
93032 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
93033 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
93034 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
93035 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
93036 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
93037 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
93038 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
93039 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
93040 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
93041 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
93042 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
93043 | #define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
93044 | //BIFPLR2_2_PCIE_CORR_ERR_STATUS |
93045 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
93046 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
93047 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
93048 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
93049 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
93050 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
93051 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
93052 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
93053 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
93054 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
93055 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
93056 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
93057 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
93058 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
93059 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
93060 | #define BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
93061 | //BIFPLR2_2_PCIE_CORR_ERR_MASK |
93062 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
93063 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
93064 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
93065 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
93066 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
93067 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
93068 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
93069 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
93070 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
93071 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
93072 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
93073 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
93074 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
93075 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
93076 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
93077 | #define BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
93078 | //BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL |
93079 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
93080 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
93081 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
93082 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
93083 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
93084 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
93085 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
93086 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
93087 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
93088 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
93089 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
93090 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
93091 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
93092 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
93093 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
93094 | #define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
93095 | //BIFPLR2_2_PCIE_HDR_LOG0 |
93096 | #define BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
93097 | #define BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
93098 | //BIFPLR2_2_PCIE_HDR_LOG1 |
93099 | #define BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
93100 | #define BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
93101 | //BIFPLR2_2_PCIE_HDR_LOG2 |
93102 | #define BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
93103 | #define BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
93104 | //BIFPLR2_2_PCIE_HDR_LOG3 |
93105 | #define BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
93106 | #define BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
93107 | //BIFPLR2_2_PCIE_ROOT_ERR_CMD |
93108 | #define BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
93109 | #define BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
93110 | #define BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
93111 | #define BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
93112 | #define BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
93113 | #define BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
93114 | //BIFPLR2_2_PCIE_ROOT_ERR_STATUS |
93115 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
93116 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
93117 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
93118 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
93119 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
93120 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
93121 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
93122 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
93123 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
93124 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
93125 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
93126 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
93127 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
93128 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
93129 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
93130 | #define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
93131 | //BIFPLR2_2_PCIE_ERR_SRC_ID |
93132 | #define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
93133 | #define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
93134 | #define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
93135 | #define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
93136 | //BIFPLR2_2_PCIE_TLP_PREFIX_LOG0 |
93137 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
93138 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
93139 | //BIFPLR2_2_PCIE_TLP_PREFIX_LOG1 |
93140 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
93141 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
93142 | //BIFPLR2_2_PCIE_TLP_PREFIX_LOG2 |
93143 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
93144 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
93145 | //BIFPLR2_2_PCIE_TLP_PREFIX_LOG3 |
93146 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
93147 | #define BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
93148 | //BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST |
93149 | #define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
93150 | #define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
93151 | #define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
93152 | #define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
93153 | #define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
93154 | #define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
93155 | //BIFPLR2_2_PCIE_LINK_CNTL3 |
93156 | #define BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
93157 | #define BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
93158 | #define BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
93159 | #define BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
93160 | #define BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
93161 | #define BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
93162 | #define BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
93163 | #define BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
93164 | //BIFPLR2_2_PCIE_LANE_ERROR_STATUS |
93165 | #define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
93166 | #define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
93167 | #define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
93168 | #define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
93169 | //BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL |
93170 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93171 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93172 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93173 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93174 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93175 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93176 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93177 | #define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93178 | //BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL |
93179 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93180 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93181 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93182 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93183 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93184 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93185 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93186 | #define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93187 | //BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL |
93188 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93189 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93190 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93191 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93192 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93193 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93194 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93195 | #define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93196 | //BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL |
93197 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93198 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93199 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93200 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93201 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93202 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93203 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93204 | #define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93205 | //BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL |
93206 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93207 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93208 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93209 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93210 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93211 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93212 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93213 | #define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93214 | //BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL |
93215 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93216 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93217 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93218 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93219 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93220 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93221 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93222 | #define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93223 | //BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL |
93224 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93225 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93226 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93227 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93228 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93229 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93230 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93231 | #define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93232 | //BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL |
93233 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93234 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93235 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93236 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93237 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93238 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93239 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93240 | #define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93241 | //BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL |
93242 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93243 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93244 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93245 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93246 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93247 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93248 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93249 | #define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93250 | //BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL |
93251 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93252 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93253 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93254 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93255 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93256 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93257 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93258 | #define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93259 | //BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL |
93260 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93261 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93262 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93263 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93264 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93265 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93266 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93267 | #define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93268 | //BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL |
93269 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93270 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93271 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93272 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93273 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93274 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93275 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93276 | #define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93277 | //BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL |
93278 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93279 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93280 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93281 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93282 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93283 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93284 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93285 | #define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93286 | //BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL |
93287 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93288 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93289 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93290 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93291 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93292 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93293 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93294 | #define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93295 | //BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL |
93296 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93297 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93298 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93299 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93300 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93301 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93302 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93303 | #define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93304 | //BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL |
93305 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
93306 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
93307 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
93308 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
93309 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
93310 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
93311 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
93312 | #define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
93313 | //BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST |
93314 | #define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
93315 | #define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
93316 | #define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
93317 | #define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
93318 | #define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
93319 | #define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
93320 | //BIFPLR2_2_PCIE_ACS_CAP |
93321 | #define BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
93322 | #define BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
93323 | #define BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
93324 | #define BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
93325 | #define BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
93326 | #define BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
93327 | #define BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
93328 | #define BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
93329 | #define BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
93330 | #define BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
93331 | #define BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
93332 | #define BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
93333 | #define BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
93334 | #define BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
93335 | #define BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
93336 | #define BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
93337 | //BIFPLR2_2_PCIE_ACS_CNTL |
93338 | #define BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
93339 | #define BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
93340 | #define BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
93341 | #define BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
93342 | #define BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
93343 | #define BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
93344 | #define BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
93345 | #define BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
93346 | #define BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
93347 | #define BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
93348 | #define BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
93349 | #define BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
93350 | #define BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
93351 | #define BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
93352 | //BIFPLR2_2_PCIE_MC_ENH_CAP_LIST |
93353 | #define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
93354 | #define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
93355 | #define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
93356 | #define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
93357 | #define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
93358 | #define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
93359 | //BIFPLR2_2_PCIE_MC_CAP |
93360 | #define BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
93361 | #define BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
93362 | #define BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
93363 | #define BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
93364 | //BIFPLR2_2_PCIE_MC_CNTL |
93365 | #define BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
93366 | #define BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
93367 | #define BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
93368 | #define BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
93369 | //BIFPLR2_2_PCIE_MC_ADDR0 |
93370 | #define BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
93371 | #define BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
93372 | #define BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
93373 | #define BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
93374 | //BIFPLR2_2_PCIE_MC_ADDR1 |
93375 | #define BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
93376 | #define BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
93377 | //BIFPLR2_2_PCIE_MC_RCV0 |
93378 | #define BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
93379 | #define BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
93380 | //BIFPLR2_2_PCIE_MC_RCV1 |
93381 | #define BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
93382 | #define BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
93383 | //BIFPLR2_2_PCIE_MC_BLOCK_ALL0 |
93384 | #define BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
93385 | #define BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
93386 | //BIFPLR2_2_PCIE_MC_BLOCK_ALL1 |
93387 | #define BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
93388 | #define BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
93389 | //BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
93390 | #define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
93391 | #define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
93392 | //BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
93393 | #define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
93394 | #define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
93395 | //BIFPLR2_2_PCIE_MC_OVERLAY_BAR0 |
93396 | #define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
93397 | #define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
93398 | #define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
93399 | #define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
93400 | //BIFPLR2_2_PCIE_MC_OVERLAY_BAR1 |
93401 | #define BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
93402 | #define BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
93403 | //BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST |
93404 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
93405 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
93406 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
93407 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
93408 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
93409 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
93410 | //BIFPLR2_2_PCIE_L1_PM_SUB_CAP |
93411 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
93412 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
93413 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
93414 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
93415 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
93416 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
93417 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
93418 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
93419 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
93420 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
93421 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
93422 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
93423 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
93424 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
93425 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
93426 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
93427 | //BIFPLR2_2_PCIE_L1_PM_SUB_CNTL |
93428 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
93429 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
93430 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
93431 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
93432 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
93433 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
93434 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
93435 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
93436 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
93437 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
93438 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
93439 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
93440 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
93441 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
93442 | //BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2 |
93443 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
93444 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
93445 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
93446 | #define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
93447 | //BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST |
93448 | #define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
93449 | #define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
93450 | #define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
93451 | #define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
93452 | #define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
93453 | #define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
93454 | //BIFPLR2_2_PCIE_DPC_CAP_LIST |
93455 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
93456 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
93457 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
93458 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
93459 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
93460 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
93461 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
93462 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
93463 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
93464 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
93465 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
93466 | #define BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
93467 | //BIFPLR2_2_PCIE_DPC_CNTL |
93468 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
93469 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
93470 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
93471 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
93472 | #define BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
93473 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
93474 | #define BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
93475 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
93476 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
93477 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
93478 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
93479 | #define BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
93480 | #define BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
93481 | #define BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
93482 | //BIFPLR2_2_PCIE_DPC_STATUS |
93483 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
93484 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
93485 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
93486 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
93487 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
93488 | #define BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
93489 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
93490 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
93491 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
93492 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
93493 | #define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
93494 | #define BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
93495 | //BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID |
93496 | #define BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
93497 | #define BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
93498 | //BIFPLR2_2_PCIE_RP_PIO_STATUS |
93499 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
93500 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
93501 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
93502 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
93503 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
93504 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
93505 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
93506 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
93507 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
93508 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
93509 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
93510 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
93511 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
93512 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
93513 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
93514 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
93515 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
93516 | #define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
93517 | //BIFPLR2_2_PCIE_RP_PIO_MASK |
93518 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
93519 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
93520 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
93521 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
93522 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
93523 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
93524 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
93525 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
93526 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
93527 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
93528 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
93529 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
93530 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
93531 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
93532 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
93533 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
93534 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
93535 | #define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
93536 | //BIFPLR2_2_PCIE_RP_PIO_SEVERITY |
93537 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
93538 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
93539 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
93540 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
93541 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
93542 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
93543 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
93544 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
93545 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
93546 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
93547 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
93548 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
93549 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
93550 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
93551 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
93552 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
93553 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
93554 | #define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
93555 | //BIFPLR2_2_PCIE_RP_PIO_SYSERROR |
93556 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
93557 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
93558 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
93559 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
93560 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
93561 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
93562 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
93563 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
93564 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
93565 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
93566 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
93567 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
93568 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
93569 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
93570 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
93571 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
93572 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
93573 | #define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
93574 | //BIFPLR2_2_PCIE_RP_PIO_EXCEPTION |
93575 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
93576 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
93577 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
93578 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
93579 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
93580 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
93581 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
93582 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
93583 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
93584 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
93585 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
93586 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
93587 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
93588 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
93589 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
93590 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
93591 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
93592 | #define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
93593 | //BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0 |
93594 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
93595 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
93596 | //BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1 |
93597 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
93598 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
93599 | //BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2 |
93600 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
93601 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
93602 | //BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3 |
93603 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
93604 | #define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
93605 | //BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG |
93606 | #define BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
93607 | #define BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
93608 | //BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0 |
93609 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
93610 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
93611 | //BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1 |
93612 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
93613 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
93614 | //BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2 |
93615 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
93616 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
93617 | //BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3 |
93618 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
93619 | #define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
93620 | //BIFPLR2_2_PCIE_ESM_CAP_LIST |
93621 | #define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
93622 | #define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
93623 | #define BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
93624 | #define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
93625 | #define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
93626 | #define BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
93627 | //BIFPLR2_2_PCIE_ESM_HEADER_1 |
93628 | #define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
93629 | #define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
93630 | #define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
93631 | #define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
93632 | #define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
93633 | #define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
93634 | //BIFPLR2_2_PCIE_ESM_HEADER_2 |
93635 | #define BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
93636 | #define BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
93637 | //BIFPLR2_2_PCIE_ESM_STATUS |
93638 | #define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
93639 | #define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
93640 | #define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
93641 | #define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
93642 | //BIFPLR2_2_PCIE_ESM_CTRL |
93643 | #define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
93644 | #define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
93645 | #define BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
93646 | #define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
93647 | #define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
93648 | #define BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
93649 | //BIFPLR2_2_PCIE_ESM_CAP_1 |
93650 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
93651 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
93652 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
93653 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
93654 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
93655 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
93656 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
93657 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
93658 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
93659 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
93660 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
93661 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
93662 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
93663 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
93664 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
93665 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
93666 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
93667 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
93668 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
93669 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
93670 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
93671 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
93672 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
93673 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
93674 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
93675 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
93676 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
93677 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
93678 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
93679 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
93680 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
93681 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
93682 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
93683 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
93684 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
93685 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
93686 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
93687 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
93688 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
93689 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
93690 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
93691 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
93692 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
93693 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
93694 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
93695 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
93696 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
93697 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
93698 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
93699 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
93700 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
93701 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
93702 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
93703 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
93704 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
93705 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
93706 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
93707 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
93708 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
93709 | #define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
93710 | //BIFPLR2_2_PCIE_ESM_CAP_2 |
93711 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
93712 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
93713 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
93714 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
93715 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
93716 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
93717 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
93718 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
93719 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
93720 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
93721 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
93722 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
93723 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
93724 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
93725 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
93726 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
93727 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
93728 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
93729 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
93730 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
93731 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
93732 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
93733 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
93734 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
93735 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
93736 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
93737 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
93738 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
93739 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
93740 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
93741 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
93742 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
93743 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
93744 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
93745 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
93746 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
93747 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
93748 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
93749 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
93750 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
93751 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
93752 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
93753 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
93754 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
93755 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
93756 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
93757 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
93758 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
93759 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
93760 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
93761 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
93762 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
93763 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
93764 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
93765 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
93766 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
93767 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
93768 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
93769 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
93770 | #define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
93771 | //BIFPLR2_2_PCIE_ESM_CAP_3 |
93772 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
93773 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
93774 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
93775 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
93776 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
93777 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
93778 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
93779 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
93780 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
93781 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
93782 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
93783 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
93784 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
93785 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
93786 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
93787 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
93788 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
93789 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
93790 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
93791 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
93792 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
93793 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
93794 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
93795 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
93796 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
93797 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
93798 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
93799 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
93800 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
93801 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
93802 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
93803 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
93804 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
93805 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
93806 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
93807 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
93808 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
93809 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
93810 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
93811 | #define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
93812 | //BIFPLR2_2_PCIE_ESM_CAP_4 |
93813 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
93814 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
93815 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
93816 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
93817 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
93818 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
93819 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
93820 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
93821 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
93822 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
93823 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
93824 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
93825 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
93826 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
93827 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
93828 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
93829 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
93830 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
93831 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
93832 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
93833 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
93834 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
93835 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
93836 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
93837 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
93838 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
93839 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
93840 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
93841 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
93842 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
93843 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
93844 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
93845 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
93846 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
93847 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
93848 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
93849 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
93850 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
93851 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
93852 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
93853 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
93854 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
93855 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
93856 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
93857 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
93858 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
93859 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
93860 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
93861 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
93862 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
93863 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
93864 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
93865 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
93866 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
93867 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
93868 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
93869 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
93870 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
93871 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
93872 | #define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
93873 | //BIFPLR2_2_PCIE_ESM_CAP_5 |
93874 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
93875 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
93876 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
93877 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
93878 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
93879 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
93880 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
93881 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
93882 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
93883 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
93884 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
93885 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
93886 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
93887 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
93888 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
93889 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
93890 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
93891 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
93892 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
93893 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
93894 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
93895 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
93896 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
93897 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
93898 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
93899 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
93900 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
93901 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
93902 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
93903 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
93904 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
93905 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
93906 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
93907 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
93908 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
93909 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
93910 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
93911 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
93912 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
93913 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
93914 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
93915 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
93916 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
93917 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
93918 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
93919 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
93920 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
93921 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
93922 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
93923 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
93924 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
93925 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
93926 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
93927 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
93928 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
93929 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
93930 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
93931 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
93932 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
93933 | #define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
93934 | //BIFPLR2_2_PCIE_ESM_CAP_6 |
93935 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
93936 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
93937 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
93938 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
93939 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
93940 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
93941 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
93942 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
93943 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
93944 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
93945 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
93946 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
93947 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
93948 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
93949 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
93950 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
93951 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
93952 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
93953 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
93954 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
93955 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
93956 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
93957 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
93958 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
93959 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
93960 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
93961 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
93962 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
93963 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
93964 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
93965 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
93966 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
93967 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
93968 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
93969 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
93970 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
93971 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
93972 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
93973 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
93974 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
93975 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
93976 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
93977 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
93978 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
93979 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
93980 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
93981 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
93982 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
93983 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
93984 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
93985 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
93986 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
93987 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
93988 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
93989 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
93990 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
93991 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
93992 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
93993 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
93994 | #define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
93995 | //BIFPLR2_2_PCIE_ESM_CAP_7 |
93996 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
93997 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
93998 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
93999 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
94000 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
94001 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
94002 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
94003 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
94004 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
94005 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
94006 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
94007 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
94008 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
94009 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
94010 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
94011 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
94012 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
94013 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
94014 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
94015 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
94016 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
94017 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
94018 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
94019 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
94020 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
94021 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
94022 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
94023 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
94024 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
94025 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
94026 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
94027 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
94028 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
94029 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
94030 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
94031 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
94032 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
94033 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
94034 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
94035 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
94036 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
94037 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
94038 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
94039 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
94040 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
94041 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
94042 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
94043 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
94044 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
94045 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
94046 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
94047 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
94048 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
94049 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
94050 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
94051 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
94052 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
94053 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
94054 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
94055 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
94056 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
94057 | #define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
94058 | |
94059 | |
94060 | // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
94061 | //BIFPLR3_2_VENDOR_ID |
94062 | #define BIFPLR3_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
94063 | #define BIFPLR3_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
94064 | //BIFPLR3_2_DEVICE_ID |
94065 | #define BIFPLR3_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
94066 | #define BIFPLR3_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
94067 | //BIFPLR3_2_COMMAND |
94068 | #define BIFPLR3_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
94069 | #define BIFPLR3_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
94070 | #define BIFPLR3_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
94071 | #define BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
94072 | #define BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
94073 | #define BIFPLR3_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
94074 | #define BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
94075 | #define BIFPLR3_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
94076 | #define BIFPLR3_2_COMMAND__SERR_EN__SHIFT 0x8 |
94077 | #define BIFPLR3_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
94078 | #define BIFPLR3_2_COMMAND__INT_DIS__SHIFT 0xa |
94079 | #define BIFPLR3_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
94080 | #define BIFPLR3_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
94081 | #define BIFPLR3_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
94082 | #define BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
94083 | #define BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
94084 | #define BIFPLR3_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
94085 | #define BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
94086 | #define BIFPLR3_2_COMMAND__AD_STEPPING_MASK 0x0080L |
94087 | #define BIFPLR3_2_COMMAND__SERR_EN_MASK 0x0100L |
94088 | #define BIFPLR3_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
94089 | #define BIFPLR3_2_COMMAND__INT_DIS_MASK 0x0400L |
94090 | //BIFPLR3_2_STATUS |
94091 | #define BIFPLR3_2_STATUS__INT_STATUS__SHIFT 0x3 |
94092 | #define BIFPLR3_2_STATUS__CAP_LIST__SHIFT 0x4 |
94093 | #define BIFPLR3_2_STATUS__PCI_66_EN__SHIFT 0x5 |
94094 | #define BIFPLR3_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
94095 | #define BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
94096 | #define BIFPLR3_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
94097 | #define BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
94098 | #define BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
94099 | #define BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
94100 | #define BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
94101 | #define BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
94102 | #define BIFPLR3_2_STATUS__INT_STATUS_MASK 0x0008L |
94103 | #define BIFPLR3_2_STATUS__CAP_LIST_MASK 0x0010L |
94104 | #define BIFPLR3_2_STATUS__PCI_66_EN_MASK 0x0020L |
94105 | #define BIFPLR3_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
94106 | #define BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
94107 | #define BIFPLR3_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
94108 | #define BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
94109 | #define BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
94110 | #define BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
94111 | #define BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
94112 | #define BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
94113 | //BIFPLR3_2_REVISION_ID |
94114 | #define BIFPLR3_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
94115 | #define BIFPLR3_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
94116 | #define BIFPLR3_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
94117 | #define BIFPLR3_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
94118 | //BIFPLR3_2_PROG_INTERFACE |
94119 | #define BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
94120 | #define BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
94121 | //BIFPLR3_2_SUB_CLASS |
94122 | #define BIFPLR3_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
94123 | #define BIFPLR3_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
94124 | //BIFPLR3_2_BASE_CLASS |
94125 | #define BIFPLR3_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
94126 | #define BIFPLR3_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
94127 | //BIFPLR3_2_CACHE_LINE |
94128 | #define BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
94129 | #define BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
94130 | //BIFPLR3_2_LATENCY |
94131 | #define BIFPLR3_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
94132 | #define BIFPLR3_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
94133 | //BIFPLR3_2_HEADER |
94134 | #define BIFPLR3_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
94135 | #define BIFPLR3_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
94136 | #define BIFPLR3_2_HEADER__HEADER_TYPE_MASK 0x7FL |
94137 | #define BIFPLR3_2_HEADER__DEVICE_TYPE_MASK 0x80L |
94138 | //BIFPLR3_2_BIST |
94139 | #define BIFPLR3_2_BIST__BIST_COMP__SHIFT 0x0 |
94140 | #define BIFPLR3_2_BIST__BIST_STRT__SHIFT 0x6 |
94141 | #define BIFPLR3_2_BIST__BIST_CAP__SHIFT 0x7 |
94142 | #define BIFPLR3_2_BIST__BIST_COMP_MASK 0x0FL |
94143 | #define BIFPLR3_2_BIST__BIST_STRT_MASK 0x40L |
94144 | #define BIFPLR3_2_BIST__BIST_CAP_MASK 0x80L |
94145 | //BIFPLR3_2_SUB_BUS_NUMBER_LATENCY |
94146 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
94147 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
94148 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
94149 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
94150 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
94151 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
94152 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
94153 | #define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
94154 | //BIFPLR3_2_IO_BASE_LIMIT |
94155 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
94156 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
94157 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
94158 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
94159 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
94160 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
94161 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
94162 | #define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
94163 | //BIFPLR3_2_SECONDARY_STATUS |
94164 | #define BIFPLR3_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
94165 | #define BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
94166 | #define BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
94167 | #define BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
94168 | #define BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
94169 | #define BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
94170 | #define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
94171 | #define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
94172 | #define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
94173 | #define BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
94174 | #define BIFPLR3_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
94175 | #define BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
94176 | #define BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
94177 | #define BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
94178 | #define BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
94179 | #define BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
94180 | #define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
94181 | #define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
94182 | #define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
94183 | #define BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
94184 | //BIFPLR3_2_MEM_BASE_LIMIT |
94185 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
94186 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
94187 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
94188 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
94189 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
94190 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
94191 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
94192 | #define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
94193 | //BIFPLR3_2_PREF_BASE_LIMIT |
94194 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
94195 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
94196 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
94197 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
94198 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
94199 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
94200 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
94201 | #define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
94202 | //BIFPLR3_2_PREF_BASE_UPPER |
94203 | #define BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
94204 | #define BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
94205 | //BIFPLR3_2_PREF_LIMIT_UPPER |
94206 | #define BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
94207 | #define BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
94208 | //BIFPLR3_2_IO_BASE_LIMIT_HI |
94209 | #define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
94210 | #define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
94211 | #define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
94212 | #define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
94213 | //BIFPLR3_2_CAP_PTR |
94214 | #define BIFPLR3_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
94215 | #define BIFPLR3_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
94216 | //BIFPLR3_2_INTERRUPT_LINE |
94217 | #define BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
94218 | #define BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
94219 | //BIFPLR3_2_INTERRUPT_PIN |
94220 | #define BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
94221 | #define BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
94222 | //BIFPLR3_2_IRQ_BRIDGE_CNTL |
94223 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
94224 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
94225 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
94226 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
94227 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
94228 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
94229 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
94230 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
94231 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
94232 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
94233 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
94234 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
94235 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
94236 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
94237 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
94238 | #define BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
94239 | //BIFPLR3_2_EXT_BRIDGE_CNTL |
94240 | #define BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
94241 | #define BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
94242 | //BIFPLR3_2_PMI_CAP_LIST |
94243 | #define BIFPLR3_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
94244 | #define BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
94245 | #define BIFPLR3_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
94246 | #define BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
94247 | //BIFPLR3_2_PMI_CAP |
94248 | #define BIFPLR3_2_PMI_CAP__VERSION__SHIFT 0x0 |
94249 | #define BIFPLR3_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
94250 | #define BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
94251 | #define BIFPLR3_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
94252 | #define BIFPLR3_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
94253 | #define BIFPLR3_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
94254 | #define BIFPLR3_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
94255 | #define BIFPLR3_2_PMI_CAP__VERSION_MASK 0x0007L |
94256 | #define BIFPLR3_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
94257 | #define BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
94258 | #define BIFPLR3_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
94259 | #define BIFPLR3_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
94260 | #define BIFPLR3_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
94261 | #define BIFPLR3_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
94262 | //BIFPLR3_2_PMI_STATUS_CNTL |
94263 | #define BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
94264 | #define BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
94265 | #define BIFPLR3_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
94266 | #define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
94267 | #define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
94268 | #define BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
94269 | #define BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
94270 | #define BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
94271 | #define BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
94272 | #define BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
94273 | #define BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
94274 | #define BIFPLR3_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
94275 | #define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
94276 | #define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
94277 | #define BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
94278 | #define BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
94279 | #define BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
94280 | #define BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
94281 | //BIFPLR3_2_PCIE_CAP_LIST |
94282 | #define BIFPLR3_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
94283 | #define BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
94284 | #define BIFPLR3_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
94285 | #define BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
94286 | //BIFPLR3_2_PCIE_CAP |
94287 | #define BIFPLR3_2_PCIE_CAP__VERSION__SHIFT 0x0 |
94288 | #define BIFPLR3_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
94289 | #define BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
94290 | #define BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
94291 | #define BIFPLR3_2_PCIE_CAP__VERSION_MASK 0x000FL |
94292 | #define BIFPLR3_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
94293 | #define BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
94294 | #define BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
94295 | //BIFPLR3_2_DEVICE_CAP |
94296 | #define BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
94297 | #define BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
94298 | #define BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
94299 | #define BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
94300 | #define BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
94301 | #define BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
94302 | #define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
94303 | #define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
94304 | #define BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
94305 | #define BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
94306 | #define BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
94307 | #define BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
94308 | #define BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
94309 | #define BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
94310 | #define BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
94311 | #define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
94312 | #define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
94313 | #define BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
94314 | //BIFPLR3_2_DEVICE_CNTL |
94315 | #define BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
94316 | #define BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
94317 | #define BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
94318 | #define BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
94319 | #define BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
94320 | #define BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
94321 | #define BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
94322 | #define BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
94323 | #define BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
94324 | #define BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
94325 | #define BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
94326 | #define BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
94327 | #define BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
94328 | #define BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
94329 | #define BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
94330 | #define BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
94331 | #define BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
94332 | #define BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
94333 | #define BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
94334 | #define BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
94335 | #define BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
94336 | #define BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
94337 | #define BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
94338 | #define BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
94339 | //BIFPLR3_2_DEVICE_STATUS |
94340 | #define BIFPLR3_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
94341 | #define BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
94342 | #define BIFPLR3_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
94343 | #define BIFPLR3_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
94344 | #define BIFPLR3_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
94345 | #define BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
94346 | #define BIFPLR3_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
94347 | #define BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
94348 | #define BIFPLR3_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
94349 | #define BIFPLR3_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
94350 | #define BIFPLR3_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
94351 | #define BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
94352 | //BIFPLR3_2_LINK_CAP |
94353 | #define BIFPLR3_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
94354 | #define BIFPLR3_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
94355 | #define BIFPLR3_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
94356 | #define BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
94357 | #define BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
94358 | #define BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
94359 | #define BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
94360 | #define BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
94361 | #define BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
94362 | #define BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
94363 | #define BIFPLR3_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
94364 | #define BIFPLR3_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
94365 | #define BIFPLR3_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
94366 | #define BIFPLR3_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
94367 | #define BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
94368 | #define BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
94369 | #define BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
94370 | #define BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
94371 | #define BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
94372 | #define BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
94373 | #define BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
94374 | #define BIFPLR3_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
94375 | //BIFPLR3_2_LINK_CNTL |
94376 | #define BIFPLR3_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
94377 | #define BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
94378 | #define BIFPLR3_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
94379 | #define BIFPLR3_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
94380 | #define BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
94381 | #define BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
94382 | #define BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
94383 | #define BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
94384 | #define BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
94385 | #define BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
94386 | #define BIFPLR3_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
94387 | #define BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
94388 | #define BIFPLR3_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
94389 | #define BIFPLR3_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
94390 | #define BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
94391 | #define BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
94392 | #define BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
94393 | #define BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
94394 | #define BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
94395 | #define BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
94396 | //BIFPLR3_2_LINK_STATUS |
94397 | #define BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
94398 | #define BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
94399 | #define BIFPLR3_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
94400 | #define BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
94401 | #define BIFPLR3_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
94402 | #define BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
94403 | #define BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
94404 | #define BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
94405 | #define BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
94406 | #define BIFPLR3_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
94407 | #define BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
94408 | #define BIFPLR3_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
94409 | #define BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
94410 | #define BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
94411 | //BIFPLR3_2_SLOT_CAP |
94412 | #define BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
94413 | #define BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
94414 | #define BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
94415 | #define BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
94416 | #define BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
94417 | #define BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
94418 | #define BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
94419 | #define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
94420 | #define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
94421 | #define BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
94422 | #define BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
94423 | #define BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
94424 | #define BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
94425 | #define BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
94426 | #define BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
94427 | #define BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
94428 | #define BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
94429 | #define BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
94430 | #define BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
94431 | #define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
94432 | #define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
94433 | #define BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
94434 | #define BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
94435 | #define BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
94436 | //BIFPLR3_2_SLOT_CNTL |
94437 | #define BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
94438 | #define BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
94439 | #define BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
94440 | #define BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
94441 | #define BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
94442 | #define BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
94443 | #define BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
94444 | #define BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
94445 | #define BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
94446 | #define BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
94447 | #define BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
94448 | #define BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
94449 | #define BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
94450 | #define BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
94451 | #define BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
94452 | #define BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
94453 | #define BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
94454 | #define BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
94455 | #define BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
94456 | #define BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
94457 | #define BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
94458 | #define BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
94459 | #define BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
94460 | #define BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
94461 | //BIFPLR3_2_SLOT_STATUS |
94462 | #define BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
94463 | #define BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
94464 | #define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
94465 | #define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
94466 | #define BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
94467 | #define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
94468 | #define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
94469 | #define BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
94470 | #define BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
94471 | #define BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
94472 | #define BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
94473 | #define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
94474 | #define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
94475 | #define BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
94476 | #define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
94477 | #define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
94478 | #define BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
94479 | #define BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
94480 | //BIFPLR3_2_ROOT_CNTL |
94481 | #define BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
94482 | #define BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
94483 | #define BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
94484 | #define BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
94485 | #define BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
94486 | #define BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
94487 | #define BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
94488 | #define BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
94489 | #define BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
94490 | #define BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
94491 | //BIFPLR3_2_ROOT_CAP |
94492 | #define BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
94493 | #define BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
94494 | //BIFPLR3_2_ROOT_STATUS |
94495 | #define BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
94496 | #define BIFPLR3_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
94497 | #define BIFPLR3_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
94498 | #define BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
94499 | #define BIFPLR3_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
94500 | #define BIFPLR3_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
94501 | //BIFPLR3_2_DEVICE_CAP2 |
94502 | #define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
94503 | #define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
94504 | #define BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
94505 | #define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
94506 | #define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
94507 | #define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
94508 | #define BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
94509 | #define BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
94510 | #define BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
94511 | #define BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
94512 | #define BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
94513 | #define BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
94514 | #define BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
94515 | #define BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
94516 | #define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
94517 | #define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
94518 | #define BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
94519 | #define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
94520 | #define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
94521 | #define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
94522 | #define BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
94523 | #define BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
94524 | #define BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
94525 | #define BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
94526 | #define BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
94527 | #define BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
94528 | #define BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
94529 | #define BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
94530 | //BIFPLR3_2_DEVICE_CNTL2 |
94531 | #define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
94532 | #define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
94533 | #define BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
94534 | #define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
94535 | #define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
94536 | #define BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
94537 | #define BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
94538 | #define BIFPLR3_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
94539 | #define BIFPLR3_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
94540 | #define BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
94541 | #define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
94542 | #define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
94543 | #define BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
94544 | #define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
94545 | #define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
94546 | #define BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
94547 | #define BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
94548 | #define BIFPLR3_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
94549 | #define BIFPLR3_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
94550 | #define BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
94551 | //BIFPLR3_2_DEVICE_STATUS2 |
94552 | #define BIFPLR3_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
94553 | #define BIFPLR3_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
94554 | //BIFPLR3_2_LINK_CAP2 |
94555 | #define BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
94556 | #define BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
94557 | #define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
94558 | #define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
94559 | #define BIFPLR3_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
94560 | #define BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
94561 | #define BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
94562 | #define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
94563 | #define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
94564 | #define BIFPLR3_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
94565 | //BIFPLR3_2_LINK_CNTL2 |
94566 | #define BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
94567 | #define BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
94568 | #define BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
94569 | #define BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
94570 | #define BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
94571 | #define BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
94572 | #define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
94573 | #define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
94574 | #define BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
94575 | #define BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
94576 | #define BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
94577 | #define BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
94578 | #define BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
94579 | #define BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
94580 | #define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
94581 | #define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
94582 | //BIFPLR3_2_LINK_STATUS2 |
94583 | #define BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
94584 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
94585 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
94586 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
94587 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
94588 | #define BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
94589 | #define BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
94590 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
94591 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
94592 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
94593 | #define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
94594 | #define BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
94595 | //BIFPLR3_2_SLOT_CAP2 |
94596 | #define BIFPLR3_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
94597 | #define BIFPLR3_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
94598 | //BIFPLR3_2_SLOT_CNTL2 |
94599 | #define BIFPLR3_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
94600 | #define BIFPLR3_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
94601 | //BIFPLR3_2_SLOT_STATUS2 |
94602 | #define BIFPLR3_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
94603 | #define BIFPLR3_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
94604 | //BIFPLR3_2_MSI_CAP_LIST |
94605 | #define BIFPLR3_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
94606 | #define BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
94607 | #define BIFPLR3_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
94608 | #define BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
94609 | //BIFPLR3_2_MSI_MSG_CNTL |
94610 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
94611 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
94612 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
94613 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
94614 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
94615 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
94616 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
94617 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
94618 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
94619 | #define BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
94620 | //BIFPLR3_2_MSI_MSG_ADDR_LO |
94621 | #define BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
94622 | #define BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
94623 | //BIFPLR3_2_MSI_MSG_ADDR_HI |
94624 | #define BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
94625 | #define BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
94626 | //BIFPLR3_2_MSI_MSG_DATA |
94627 | #define BIFPLR3_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
94628 | #define BIFPLR3_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
94629 | //BIFPLR3_2_MSI_MSG_DATA_64 |
94630 | #define BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
94631 | #define BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
94632 | //BIFPLR3_2_SSID_CAP_LIST |
94633 | #define BIFPLR3_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
94634 | #define BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
94635 | #define BIFPLR3_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
94636 | #define BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
94637 | //BIFPLR3_2_SSID_CAP |
94638 | #define BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
94639 | #define BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
94640 | #define BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
94641 | #define BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
94642 | //BIFPLR3_2_MSI_MAP_CAP_LIST |
94643 | #define BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
94644 | #define BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
94645 | #define BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
94646 | #define BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
94647 | //BIFPLR3_2_MSI_MAP_CAP |
94648 | #define BIFPLR3_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
94649 | #define BIFPLR3_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
94650 | #define BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
94651 | #define BIFPLR3_2_MSI_MAP_CAP__EN_MASK 0x0001L |
94652 | #define BIFPLR3_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
94653 | #define BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
94654 | //BIFPLR3_2_MSI_MAP_ADDR_LO |
94655 | #define BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
94656 | #define BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
94657 | //BIFPLR3_2_MSI_MAP_ADDR_HI |
94658 | #define BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
94659 | #define BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
94660 | //BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
94661 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
94662 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
94663 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
94664 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
94665 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
94666 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
94667 | //BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR |
94668 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
94669 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
94670 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
94671 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
94672 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
94673 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
94674 | //BIFPLR3_2_PCIE_VENDOR_SPECIFIC1 |
94675 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
94676 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
94677 | //BIFPLR3_2_PCIE_VENDOR_SPECIFIC2 |
94678 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
94679 | #define BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
94680 | //BIFPLR3_2_PCIE_VC_ENH_CAP_LIST |
94681 | #define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
94682 | #define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
94683 | #define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
94684 | #define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
94685 | #define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
94686 | #define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
94687 | //BIFPLR3_2_PCIE_PORT_VC_CAP_REG1 |
94688 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
94689 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
94690 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
94691 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
94692 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
94693 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
94694 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
94695 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
94696 | //BIFPLR3_2_PCIE_PORT_VC_CAP_REG2 |
94697 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
94698 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
94699 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
94700 | #define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
94701 | //BIFPLR3_2_PCIE_PORT_VC_CNTL |
94702 | #define BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
94703 | #define BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
94704 | #define BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
94705 | #define BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
94706 | //BIFPLR3_2_PCIE_PORT_VC_STATUS |
94707 | #define BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
94708 | #define BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
94709 | //BIFPLR3_2_PCIE_VC0_RESOURCE_CAP |
94710 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
94711 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
94712 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
94713 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
94714 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
94715 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
94716 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
94717 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
94718 | //BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL |
94719 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
94720 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
94721 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
94722 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
94723 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
94724 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
94725 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
94726 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
94727 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
94728 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
94729 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
94730 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
94731 | //BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS |
94732 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
94733 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
94734 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
94735 | #define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
94736 | //BIFPLR3_2_PCIE_VC1_RESOURCE_CAP |
94737 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
94738 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
94739 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
94740 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
94741 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
94742 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
94743 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
94744 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
94745 | //BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL |
94746 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
94747 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
94748 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
94749 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
94750 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
94751 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
94752 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
94753 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
94754 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
94755 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
94756 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
94757 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
94758 | //BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS |
94759 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
94760 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
94761 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
94762 | #define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
94763 | //BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
94764 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
94765 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
94766 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
94767 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
94768 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
94769 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
94770 | //BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1 |
94771 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
94772 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
94773 | //BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2 |
94774 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
94775 | #define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
94776 | //BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
94777 | #define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
94778 | #define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
94779 | #define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
94780 | #define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
94781 | #define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
94782 | #define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
94783 | //BIFPLR3_2_PCIE_UNCORR_ERR_STATUS |
94784 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
94785 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
94786 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
94787 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
94788 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
94789 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
94790 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
94791 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
94792 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
94793 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
94794 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
94795 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
94796 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
94797 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
94798 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
94799 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
94800 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
94801 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
94802 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
94803 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
94804 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
94805 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
94806 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
94807 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
94808 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
94809 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
94810 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
94811 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
94812 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
94813 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
94814 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
94815 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
94816 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
94817 | #define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
94818 | //BIFPLR3_2_PCIE_UNCORR_ERR_MASK |
94819 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
94820 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
94821 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
94822 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
94823 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
94824 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
94825 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
94826 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
94827 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
94828 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
94829 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
94830 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
94831 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
94832 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
94833 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
94834 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
94835 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
94836 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
94837 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
94838 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
94839 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
94840 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
94841 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
94842 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
94843 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
94844 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
94845 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
94846 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
94847 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
94848 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
94849 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
94850 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
94851 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
94852 | #define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
94853 | //BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY |
94854 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
94855 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
94856 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
94857 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
94858 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
94859 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
94860 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
94861 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
94862 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
94863 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
94864 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
94865 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
94866 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
94867 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
94868 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
94869 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
94870 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
94871 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
94872 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
94873 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
94874 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
94875 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
94876 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
94877 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
94878 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
94879 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
94880 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
94881 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
94882 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
94883 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
94884 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
94885 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
94886 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
94887 | #define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
94888 | //BIFPLR3_2_PCIE_CORR_ERR_STATUS |
94889 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
94890 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
94891 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
94892 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
94893 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
94894 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
94895 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
94896 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
94897 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
94898 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
94899 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
94900 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
94901 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
94902 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
94903 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
94904 | #define BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
94905 | //BIFPLR3_2_PCIE_CORR_ERR_MASK |
94906 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
94907 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
94908 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
94909 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
94910 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
94911 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
94912 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
94913 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
94914 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
94915 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
94916 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
94917 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
94918 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
94919 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
94920 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
94921 | #define BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
94922 | //BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL |
94923 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
94924 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
94925 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
94926 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
94927 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
94928 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
94929 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
94930 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
94931 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
94932 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
94933 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
94934 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
94935 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
94936 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
94937 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
94938 | #define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
94939 | //BIFPLR3_2_PCIE_HDR_LOG0 |
94940 | #define BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
94941 | #define BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
94942 | //BIFPLR3_2_PCIE_HDR_LOG1 |
94943 | #define BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
94944 | #define BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
94945 | //BIFPLR3_2_PCIE_HDR_LOG2 |
94946 | #define BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
94947 | #define BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
94948 | //BIFPLR3_2_PCIE_HDR_LOG3 |
94949 | #define BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
94950 | #define BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
94951 | //BIFPLR3_2_PCIE_ROOT_ERR_CMD |
94952 | #define BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
94953 | #define BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
94954 | #define BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
94955 | #define BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
94956 | #define BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
94957 | #define BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
94958 | //BIFPLR3_2_PCIE_ROOT_ERR_STATUS |
94959 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
94960 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
94961 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
94962 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
94963 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
94964 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
94965 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
94966 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
94967 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
94968 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
94969 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
94970 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
94971 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
94972 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
94973 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
94974 | #define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
94975 | //BIFPLR3_2_PCIE_ERR_SRC_ID |
94976 | #define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
94977 | #define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
94978 | #define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
94979 | #define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
94980 | //BIFPLR3_2_PCIE_TLP_PREFIX_LOG0 |
94981 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
94982 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
94983 | //BIFPLR3_2_PCIE_TLP_PREFIX_LOG1 |
94984 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
94985 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
94986 | //BIFPLR3_2_PCIE_TLP_PREFIX_LOG2 |
94987 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
94988 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
94989 | //BIFPLR3_2_PCIE_TLP_PREFIX_LOG3 |
94990 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
94991 | #define BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
94992 | //BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST |
94993 | #define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
94994 | #define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
94995 | #define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
94996 | #define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
94997 | #define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
94998 | #define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
94999 | //BIFPLR3_2_PCIE_LINK_CNTL3 |
95000 | #define BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
95001 | #define BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
95002 | #define BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
95003 | #define BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
95004 | #define BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
95005 | #define BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
95006 | #define BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
95007 | #define BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
95008 | //BIFPLR3_2_PCIE_LANE_ERROR_STATUS |
95009 | #define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
95010 | #define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
95011 | #define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
95012 | #define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
95013 | //BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL |
95014 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95015 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95016 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95017 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95018 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95019 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95020 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95021 | #define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95022 | //BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL |
95023 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95024 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95025 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95026 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95027 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95028 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95029 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95030 | #define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95031 | //BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL |
95032 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95033 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95034 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95035 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95036 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95037 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95038 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95039 | #define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95040 | //BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL |
95041 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95042 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95043 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95044 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95045 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95046 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95047 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95048 | #define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95049 | //BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL |
95050 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95051 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95052 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95053 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95054 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95055 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95056 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95057 | #define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95058 | //BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL |
95059 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95060 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95061 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95062 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95063 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95064 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95065 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95066 | #define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95067 | //BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL |
95068 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95069 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95070 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95071 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95072 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95073 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95074 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95075 | #define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95076 | //BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL |
95077 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95078 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95079 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95080 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95081 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95082 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95083 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95084 | #define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95085 | //BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL |
95086 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95087 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95088 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95089 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95090 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95091 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95092 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95093 | #define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95094 | //BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL |
95095 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95096 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95097 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95098 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95099 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95100 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95101 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95102 | #define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95103 | //BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL |
95104 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95105 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95106 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95107 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95108 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95109 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95110 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95111 | #define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95112 | //BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL |
95113 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95114 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95115 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95116 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95117 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95118 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95119 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95120 | #define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95121 | //BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL |
95122 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95123 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95124 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95125 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95126 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95127 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95128 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95129 | #define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95130 | //BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL |
95131 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95132 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95133 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95134 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95135 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95136 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95137 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95138 | #define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95139 | //BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL |
95140 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95141 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95142 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95143 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95144 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95145 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95146 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95147 | #define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95148 | //BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL |
95149 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
95150 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
95151 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
95152 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
95153 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
95154 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
95155 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
95156 | #define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
95157 | //BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST |
95158 | #define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
95159 | #define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
95160 | #define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
95161 | #define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
95162 | #define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
95163 | #define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
95164 | //BIFPLR3_2_PCIE_ACS_CAP |
95165 | #define BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
95166 | #define BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
95167 | #define BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
95168 | #define BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
95169 | #define BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
95170 | #define BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
95171 | #define BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
95172 | #define BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
95173 | #define BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
95174 | #define BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
95175 | #define BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
95176 | #define BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
95177 | #define BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
95178 | #define BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
95179 | #define BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
95180 | #define BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
95181 | //BIFPLR3_2_PCIE_ACS_CNTL |
95182 | #define BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
95183 | #define BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
95184 | #define BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
95185 | #define BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
95186 | #define BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
95187 | #define BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
95188 | #define BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
95189 | #define BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
95190 | #define BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
95191 | #define BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
95192 | #define BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
95193 | #define BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
95194 | #define BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
95195 | #define BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
95196 | //BIFPLR3_2_PCIE_MC_ENH_CAP_LIST |
95197 | #define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
95198 | #define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
95199 | #define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
95200 | #define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
95201 | #define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
95202 | #define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
95203 | //BIFPLR3_2_PCIE_MC_CAP |
95204 | #define BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
95205 | #define BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
95206 | #define BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
95207 | #define BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
95208 | //BIFPLR3_2_PCIE_MC_CNTL |
95209 | #define BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
95210 | #define BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
95211 | #define BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
95212 | #define BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
95213 | //BIFPLR3_2_PCIE_MC_ADDR0 |
95214 | #define BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
95215 | #define BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
95216 | #define BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
95217 | #define BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
95218 | //BIFPLR3_2_PCIE_MC_ADDR1 |
95219 | #define BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
95220 | #define BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
95221 | //BIFPLR3_2_PCIE_MC_RCV0 |
95222 | #define BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
95223 | #define BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
95224 | //BIFPLR3_2_PCIE_MC_RCV1 |
95225 | #define BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
95226 | #define BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
95227 | //BIFPLR3_2_PCIE_MC_BLOCK_ALL0 |
95228 | #define BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
95229 | #define BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
95230 | //BIFPLR3_2_PCIE_MC_BLOCK_ALL1 |
95231 | #define BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
95232 | #define BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
95233 | //BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
95234 | #define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
95235 | #define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
95236 | //BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
95237 | #define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
95238 | #define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
95239 | //BIFPLR3_2_PCIE_MC_OVERLAY_BAR0 |
95240 | #define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
95241 | #define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
95242 | #define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
95243 | #define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
95244 | //BIFPLR3_2_PCIE_MC_OVERLAY_BAR1 |
95245 | #define BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
95246 | #define BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
95247 | //BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST |
95248 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
95249 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
95250 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
95251 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
95252 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
95253 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
95254 | //BIFPLR3_2_PCIE_L1_PM_SUB_CAP |
95255 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
95256 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
95257 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
95258 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
95259 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
95260 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
95261 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
95262 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
95263 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
95264 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
95265 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
95266 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
95267 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
95268 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
95269 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
95270 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
95271 | //BIFPLR3_2_PCIE_L1_PM_SUB_CNTL |
95272 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
95273 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
95274 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
95275 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
95276 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
95277 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
95278 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
95279 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
95280 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
95281 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
95282 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
95283 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
95284 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
95285 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
95286 | //BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2 |
95287 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
95288 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
95289 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
95290 | #define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
95291 | //BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST |
95292 | #define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
95293 | #define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
95294 | #define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
95295 | #define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
95296 | #define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
95297 | #define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
95298 | //BIFPLR3_2_PCIE_DPC_CAP_LIST |
95299 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
95300 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
95301 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
95302 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
95303 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
95304 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
95305 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
95306 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
95307 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
95308 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
95309 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
95310 | #define BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
95311 | //BIFPLR3_2_PCIE_DPC_CNTL |
95312 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
95313 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
95314 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
95315 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
95316 | #define BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
95317 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
95318 | #define BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
95319 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
95320 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
95321 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
95322 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
95323 | #define BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
95324 | #define BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
95325 | #define BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
95326 | //BIFPLR3_2_PCIE_DPC_STATUS |
95327 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
95328 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
95329 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
95330 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
95331 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
95332 | #define BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
95333 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
95334 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
95335 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
95336 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
95337 | #define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
95338 | #define BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
95339 | //BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID |
95340 | #define BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
95341 | #define BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
95342 | //BIFPLR3_2_PCIE_RP_PIO_STATUS |
95343 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
95344 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
95345 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
95346 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
95347 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
95348 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
95349 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
95350 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
95351 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
95352 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
95353 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
95354 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
95355 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
95356 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
95357 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
95358 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
95359 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
95360 | #define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
95361 | //BIFPLR3_2_PCIE_RP_PIO_MASK |
95362 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
95363 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
95364 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
95365 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
95366 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
95367 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
95368 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
95369 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
95370 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
95371 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
95372 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
95373 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
95374 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
95375 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
95376 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
95377 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
95378 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
95379 | #define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
95380 | //BIFPLR3_2_PCIE_RP_PIO_SEVERITY |
95381 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
95382 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
95383 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
95384 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
95385 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
95386 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
95387 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
95388 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
95389 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
95390 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
95391 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
95392 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
95393 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
95394 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
95395 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
95396 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
95397 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
95398 | #define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
95399 | //BIFPLR3_2_PCIE_RP_PIO_SYSERROR |
95400 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
95401 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
95402 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
95403 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
95404 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
95405 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
95406 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
95407 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
95408 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
95409 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
95410 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
95411 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
95412 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
95413 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
95414 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
95415 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
95416 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
95417 | #define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
95418 | //BIFPLR3_2_PCIE_RP_PIO_EXCEPTION |
95419 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
95420 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
95421 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
95422 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
95423 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
95424 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
95425 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
95426 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
95427 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
95428 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
95429 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
95430 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
95431 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
95432 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
95433 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
95434 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
95435 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
95436 | #define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
95437 | //BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0 |
95438 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
95439 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
95440 | //BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1 |
95441 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
95442 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
95443 | //BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2 |
95444 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
95445 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
95446 | //BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3 |
95447 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
95448 | #define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
95449 | //BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG |
95450 | #define BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
95451 | #define BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
95452 | //BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0 |
95453 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
95454 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
95455 | //BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1 |
95456 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
95457 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
95458 | //BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2 |
95459 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
95460 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
95461 | //BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3 |
95462 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
95463 | #define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
95464 | //BIFPLR3_2_PCIE_ESM_CAP_LIST |
95465 | #define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
95466 | #define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
95467 | #define BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
95468 | #define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
95469 | #define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
95470 | #define BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
95471 | //BIFPLR3_2_PCIE_ESM_HEADER_1 |
95472 | #define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
95473 | #define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
95474 | #define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
95475 | #define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
95476 | #define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
95477 | #define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
95478 | //BIFPLR3_2_PCIE_ESM_HEADER_2 |
95479 | #define BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
95480 | #define BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
95481 | //BIFPLR3_2_PCIE_ESM_STATUS |
95482 | #define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
95483 | #define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
95484 | #define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
95485 | #define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
95486 | //BIFPLR3_2_PCIE_ESM_CTRL |
95487 | #define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
95488 | #define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
95489 | #define BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
95490 | #define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
95491 | #define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
95492 | #define BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
95493 | //BIFPLR3_2_PCIE_ESM_CAP_1 |
95494 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
95495 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
95496 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
95497 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
95498 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
95499 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
95500 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
95501 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
95502 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
95503 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
95504 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
95505 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
95506 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
95507 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
95508 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
95509 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
95510 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
95511 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
95512 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
95513 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
95514 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
95515 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
95516 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
95517 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
95518 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
95519 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
95520 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
95521 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
95522 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
95523 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
95524 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
95525 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
95526 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
95527 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
95528 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
95529 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
95530 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
95531 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
95532 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
95533 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
95534 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
95535 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
95536 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
95537 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
95538 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
95539 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
95540 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
95541 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
95542 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
95543 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
95544 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
95545 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
95546 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
95547 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
95548 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
95549 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
95550 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
95551 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
95552 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
95553 | #define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
95554 | //BIFPLR3_2_PCIE_ESM_CAP_2 |
95555 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
95556 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
95557 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
95558 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
95559 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
95560 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
95561 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
95562 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
95563 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
95564 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
95565 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
95566 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
95567 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
95568 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
95569 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
95570 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
95571 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
95572 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
95573 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
95574 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
95575 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
95576 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
95577 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
95578 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
95579 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
95580 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
95581 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
95582 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
95583 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
95584 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
95585 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
95586 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
95587 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
95588 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
95589 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
95590 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
95591 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
95592 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
95593 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
95594 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
95595 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
95596 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
95597 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
95598 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
95599 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
95600 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
95601 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
95602 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
95603 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
95604 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
95605 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
95606 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
95607 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
95608 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
95609 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
95610 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
95611 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
95612 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
95613 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
95614 | #define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
95615 | //BIFPLR3_2_PCIE_ESM_CAP_3 |
95616 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
95617 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
95618 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
95619 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
95620 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
95621 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
95622 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
95623 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
95624 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
95625 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
95626 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
95627 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
95628 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
95629 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
95630 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
95631 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
95632 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
95633 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
95634 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
95635 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
95636 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
95637 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
95638 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
95639 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
95640 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
95641 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
95642 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
95643 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
95644 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
95645 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
95646 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
95647 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
95648 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
95649 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
95650 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
95651 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
95652 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
95653 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
95654 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
95655 | #define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
95656 | //BIFPLR3_2_PCIE_ESM_CAP_4 |
95657 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
95658 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
95659 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
95660 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
95661 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
95662 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
95663 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
95664 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
95665 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
95666 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
95667 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
95668 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
95669 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
95670 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
95671 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
95672 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
95673 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
95674 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
95675 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
95676 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
95677 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
95678 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
95679 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
95680 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
95681 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
95682 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
95683 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
95684 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
95685 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
95686 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
95687 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
95688 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
95689 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
95690 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
95691 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
95692 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
95693 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
95694 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
95695 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
95696 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
95697 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
95698 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
95699 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
95700 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
95701 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
95702 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
95703 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
95704 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
95705 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
95706 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
95707 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
95708 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
95709 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
95710 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
95711 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
95712 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
95713 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
95714 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
95715 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
95716 | #define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
95717 | //BIFPLR3_2_PCIE_ESM_CAP_5 |
95718 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
95719 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
95720 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
95721 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
95722 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
95723 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
95724 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
95725 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
95726 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
95727 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
95728 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
95729 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
95730 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
95731 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
95732 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
95733 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
95734 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
95735 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
95736 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
95737 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
95738 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
95739 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
95740 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
95741 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
95742 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
95743 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
95744 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
95745 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
95746 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
95747 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
95748 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
95749 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
95750 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
95751 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
95752 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
95753 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
95754 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
95755 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
95756 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
95757 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
95758 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
95759 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
95760 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
95761 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
95762 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
95763 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
95764 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
95765 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
95766 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
95767 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
95768 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
95769 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
95770 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
95771 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
95772 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
95773 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
95774 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
95775 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
95776 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
95777 | #define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
95778 | //BIFPLR3_2_PCIE_ESM_CAP_6 |
95779 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
95780 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
95781 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
95782 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
95783 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
95784 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
95785 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
95786 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
95787 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
95788 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
95789 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
95790 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
95791 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
95792 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
95793 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
95794 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
95795 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
95796 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
95797 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
95798 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
95799 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
95800 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
95801 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
95802 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
95803 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
95804 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
95805 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
95806 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
95807 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
95808 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
95809 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
95810 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
95811 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
95812 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
95813 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
95814 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
95815 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
95816 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
95817 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
95818 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
95819 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
95820 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
95821 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
95822 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
95823 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
95824 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
95825 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
95826 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
95827 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
95828 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
95829 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
95830 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
95831 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
95832 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
95833 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
95834 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
95835 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
95836 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
95837 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
95838 | #define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
95839 | //BIFPLR3_2_PCIE_ESM_CAP_7 |
95840 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
95841 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
95842 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
95843 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
95844 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
95845 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
95846 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
95847 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
95848 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
95849 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
95850 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
95851 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
95852 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
95853 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
95854 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
95855 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
95856 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
95857 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
95858 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
95859 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
95860 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
95861 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
95862 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
95863 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
95864 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
95865 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
95866 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
95867 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
95868 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
95869 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
95870 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
95871 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
95872 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
95873 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
95874 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
95875 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
95876 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
95877 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
95878 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
95879 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
95880 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
95881 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
95882 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
95883 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
95884 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
95885 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
95886 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
95887 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
95888 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
95889 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
95890 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
95891 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
95892 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
95893 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
95894 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
95895 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
95896 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
95897 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
95898 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
95899 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
95900 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
95901 | #define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
95902 | |
95903 | |
95904 | // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
95905 | //BIFPLR4_2_VENDOR_ID |
95906 | #define BIFPLR4_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
95907 | #define BIFPLR4_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
95908 | //BIFPLR4_2_DEVICE_ID |
95909 | #define BIFPLR4_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
95910 | #define BIFPLR4_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
95911 | //BIFPLR4_2_COMMAND |
95912 | #define BIFPLR4_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
95913 | #define BIFPLR4_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
95914 | #define BIFPLR4_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
95915 | #define BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
95916 | #define BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
95917 | #define BIFPLR4_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
95918 | #define BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
95919 | #define BIFPLR4_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
95920 | #define BIFPLR4_2_COMMAND__SERR_EN__SHIFT 0x8 |
95921 | #define BIFPLR4_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
95922 | #define BIFPLR4_2_COMMAND__INT_DIS__SHIFT 0xa |
95923 | #define BIFPLR4_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
95924 | #define BIFPLR4_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
95925 | #define BIFPLR4_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
95926 | #define BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
95927 | #define BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
95928 | #define BIFPLR4_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
95929 | #define BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
95930 | #define BIFPLR4_2_COMMAND__AD_STEPPING_MASK 0x0080L |
95931 | #define BIFPLR4_2_COMMAND__SERR_EN_MASK 0x0100L |
95932 | #define BIFPLR4_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
95933 | #define BIFPLR4_2_COMMAND__INT_DIS_MASK 0x0400L |
95934 | //BIFPLR4_2_STATUS |
95935 | #define BIFPLR4_2_STATUS__INT_STATUS__SHIFT 0x3 |
95936 | #define BIFPLR4_2_STATUS__CAP_LIST__SHIFT 0x4 |
95937 | #define BIFPLR4_2_STATUS__PCI_66_EN__SHIFT 0x5 |
95938 | #define BIFPLR4_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
95939 | #define BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
95940 | #define BIFPLR4_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
95941 | #define BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
95942 | #define BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
95943 | #define BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
95944 | #define BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
95945 | #define BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
95946 | #define BIFPLR4_2_STATUS__INT_STATUS_MASK 0x0008L |
95947 | #define BIFPLR4_2_STATUS__CAP_LIST_MASK 0x0010L |
95948 | #define BIFPLR4_2_STATUS__PCI_66_EN_MASK 0x0020L |
95949 | #define BIFPLR4_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
95950 | #define BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
95951 | #define BIFPLR4_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
95952 | #define BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
95953 | #define BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
95954 | #define BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
95955 | #define BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
95956 | #define BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
95957 | //BIFPLR4_2_REVISION_ID |
95958 | #define BIFPLR4_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
95959 | #define BIFPLR4_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
95960 | #define BIFPLR4_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
95961 | #define BIFPLR4_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
95962 | //BIFPLR4_2_PROG_INTERFACE |
95963 | #define BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
95964 | #define BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
95965 | //BIFPLR4_2_SUB_CLASS |
95966 | #define BIFPLR4_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
95967 | #define BIFPLR4_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
95968 | //BIFPLR4_2_BASE_CLASS |
95969 | #define BIFPLR4_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
95970 | #define BIFPLR4_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
95971 | //BIFPLR4_2_CACHE_LINE |
95972 | #define BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
95973 | #define BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
95974 | //BIFPLR4_2_LATENCY |
95975 | #define BIFPLR4_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
95976 | #define BIFPLR4_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
95977 | //BIFPLR4_2_HEADER |
95978 | #define BIFPLR4_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
95979 | #define BIFPLR4_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
95980 | #define BIFPLR4_2_HEADER__HEADER_TYPE_MASK 0x7FL |
95981 | #define BIFPLR4_2_HEADER__DEVICE_TYPE_MASK 0x80L |
95982 | //BIFPLR4_2_BIST |
95983 | #define BIFPLR4_2_BIST__BIST_COMP__SHIFT 0x0 |
95984 | #define BIFPLR4_2_BIST__BIST_STRT__SHIFT 0x6 |
95985 | #define BIFPLR4_2_BIST__BIST_CAP__SHIFT 0x7 |
95986 | #define BIFPLR4_2_BIST__BIST_COMP_MASK 0x0FL |
95987 | #define BIFPLR4_2_BIST__BIST_STRT_MASK 0x40L |
95988 | #define BIFPLR4_2_BIST__BIST_CAP_MASK 0x80L |
95989 | //BIFPLR4_2_SUB_BUS_NUMBER_LATENCY |
95990 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
95991 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
95992 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
95993 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
95994 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
95995 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
95996 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
95997 | #define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
95998 | //BIFPLR4_2_IO_BASE_LIMIT |
95999 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
96000 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
96001 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
96002 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
96003 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
96004 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
96005 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
96006 | #define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
96007 | //BIFPLR4_2_SECONDARY_STATUS |
96008 | #define BIFPLR4_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
96009 | #define BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
96010 | #define BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
96011 | #define BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
96012 | #define BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
96013 | #define BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
96014 | #define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
96015 | #define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
96016 | #define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
96017 | #define BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
96018 | #define BIFPLR4_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
96019 | #define BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
96020 | #define BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
96021 | #define BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
96022 | #define BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
96023 | #define BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
96024 | #define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
96025 | #define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
96026 | #define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
96027 | #define BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
96028 | //BIFPLR4_2_MEM_BASE_LIMIT |
96029 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
96030 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
96031 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
96032 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
96033 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
96034 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
96035 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
96036 | #define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
96037 | //BIFPLR4_2_PREF_BASE_LIMIT |
96038 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
96039 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
96040 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
96041 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
96042 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
96043 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
96044 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
96045 | #define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
96046 | //BIFPLR4_2_PREF_BASE_UPPER |
96047 | #define BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
96048 | #define BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
96049 | //BIFPLR4_2_PREF_LIMIT_UPPER |
96050 | #define BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
96051 | #define BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
96052 | //BIFPLR4_2_IO_BASE_LIMIT_HI |
96053 | #define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
96054 | #define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
96055 | #define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
96056 | #define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
96057 | //BIFPLR4_2_CAP_PTR |
96058 | #define BIFPLR4_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
96059 | #define BIFPLR4_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
96060 | //BIFPLR4_2_INTERRUPT_LINE |
96061 | #define BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
96062 | #define BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
96063 | //BIFPLR4_2_INTERRUPT_PIN |
96064 | #define BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
96065 | #define BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
96066 | //BIFPLR4_2_IRQ_BRIDGE_CNTL |
96067 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
96068 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
96069 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
96070 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
96071 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
96072 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
96073 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
96074 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
96075 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
96076 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
96077 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
96078 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
96079 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
96080 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
96081 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
96082 | #define BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
96083 | //BIFPLR4_2_EXT_BRIDGE_CNTL |
96084 | #define BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
96085 | #define BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
96086 | //BIFPLR4_2_PMI_CAP_LIST |
96087 | #define BIFPLR4_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
96088 | #define BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
96089 | #define BIFPLR4_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
96090 | #define BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
96091 | //BIFPLR4_2_PMI_CAP |
96092 | #define BIFPLR4_2_PMI_CAP__VERSION__SHIFT 0x0 |
96093 | #define BIFPLR4_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
96094 | #define BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
96095 | #define BIFPLR4_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
96096 | #define BIFPLR4_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
96097 | #define BIFPLR4_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
96098 | #define BIFPLR4_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
96099 | #define BIFPLR4_2_PMI_CAP__VERSION_MASK 0x0007L |
96100 | #define BIFPLR4_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
96101 | #define BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
96102 | #define BIFPLR4_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
96103 | #define BIFPLR4_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
96104 | #define BIFPLR4_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
96105 | #define BIFPLR4_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
96106 | //BIFPLR4_2_PMI_STATUS_CNTL |
96107 | #define BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
96108 | #define BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
96109 | #define BIFPLR4_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
96110 | #define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
96111 | #define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
96112 | #define BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
96113 | #define BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
96114 | #define BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
96115 | #define BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
96116 | #define BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
96117 | #define BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
96118 | #define BIFPLR4_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
96119 | #define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
96120 | #define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
96121 | #define BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
96122 | #define BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
96123 | #define BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
96124 | #define BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
96125 | //BIFPLR4_2_PCIE_CAP_LIST |
96126 | #define BIFPLR4_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
96127 | #define BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
96128 | #define BIFPLR4_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
96129 | #define BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
96130 | //BIFPLR4_2_PCIE_CAP |
96131 | #define BIFPLR4_2_PCIE_CAP__VERSION__SHIFT 0x0 |
96132 | #define BIFPLR4_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
96133 | #define BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
96134 | #define BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
96135 | #define BIFPLR4_2_PCIE_CAP__VERSION_MASK 0x000FL |
96136 | #define BIFPLR4_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
96137 | #define BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
96138 | #define BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
96139 | //BIFPLR4_2_DEVICE_CAP |
96140 | #define BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
96141 | #define BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
96142 | #define BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
96143 | #define BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
96144 | #define BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
96145 | #define BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
96146 | #define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
96147 | #define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
96148 | #define BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
96149 | #define BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
96150 | #define BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
96151 | #define BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
96152 | #define BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
96153 | #define BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
96154 | #define BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
96155 | #define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
96156 | #define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
96157 | #define BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
96158 | //BIFPLR4_2_DEVICE_CNTL |
96159 | #define BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
96160 | #define BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
96161 | #define BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
96162 | #define BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
96163 | #define BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
96164 | #define BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
96165 | #define BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
96166 | #define BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
96167 | #define BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
96168 | #define BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
96169 | #define BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
96170 | #define BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
96171 | #define BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
96172 | #define BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
96173 | #define BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
96174 | #define BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
96175 | #define BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
96176 | #define BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
96177 | #define BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
96178 | #define BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
96179 | #define BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
96180 | #define BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
96181 | #define BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
96182 | #define BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
96183 | //BIFPLR4_2_DEVICE_STATUS |
96184 | #define BIFPLR4_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
96185 | #define BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
96186 | #define BIFPLR4_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
96187 | #define BIFPLR4_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
96188 | #define BIFPLR4_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
96189 | #define BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
96190 | #define BIFPLR4_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
96191 | #define BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
96192 | #define BIFPLR4_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
96193 | #define BIFPLR4_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
96194 | #define BIFPLR4_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
96195 | #define BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
96196 | //BIFPLR4_2_LINK_CAP |
96197 | #define BIFPLR4_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
96198 | #define BIFPLR4_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
96199 | #define BIFPLR4_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
96200 | #define BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
96201 | #define BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
96202 | #define BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
96203 | #define BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
96204 | #define BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
96205 | #define BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
96206 | #define BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
96207 | #define BIFPLR4_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
96208 | #define BIFPLR4_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
96209 | #define BIFPLR4_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
96210 | #define BIFPLR4_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
96211 | #define BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
96212 | #define BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
96213 | #define BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
96214 | #define BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
96215 | #define BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
96216 | #define BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
96217 | #define BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
96218 | #define BIFPLR4_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
96219 | //BIFPLR4_2_LINK_CNTL |
96220 | #define BIFPLR4_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
96221 | #define BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
96222 | #define BIFPLR4_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
96223 | #define BIFPLR4_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
96224 | #define BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
96225 | #define BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
96226 | #define BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
96227 | #define BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
96228 | #define BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
96229 | #define BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
96230 | #define BIFPLR4_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
96231 | #define BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
96232 | #define BIFPLR4_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
96233 | #define BIFPLR4_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
96234 | #define BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
96235 | #define BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
96236 | #define BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
96237 | #define BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
96238 | #define BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
96239 | #define BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
96240 | //BIFPLR4_2_LINK_STATUS |
96241 | #define BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
96242 | #define BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
96243 | #define BIFPLR4_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
96244 | #define BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
96245 | #define BIFPLR4_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
96246 | #define BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
96247 | #define BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
96248 | #define BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
96249 | #define BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
96250 | #define BIFPLR4_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
96251 | #define BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
96252 | #define BIFPLR4_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
96253 | #define BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
96254 | #define BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
96255 | //BIFPLR4_2_SLOT_CAP |
96256 | #define BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
96257 | #define BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
96258 | #define BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
96259 | #define BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
96260 | #define BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
96261 | #define BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
96262 | #define BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
96263 | #define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
96264 | #define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
96265 | #define BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
96266 | #define BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
96267 | #define BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
96268 | #define BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
96269 | #define BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
96270 | #define BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
96271 | #define BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
96272 | #define BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
96273 | #define BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
96274 | #define BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
96275 | #define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
96276 | #define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
96277 | #define BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
96278 | #define BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
96279 | #define BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
96280 | //BIFPLR4_2_SLOT_CNTL |
96281 | #define BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
96282 | #define BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
96283 | #define BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
96284 | #define BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
96285 | #define BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
96286 | #define BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
96287 | #define BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
96288 | #define BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
96289 | #define BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
96290 | #define BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
96291 | #define BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
96292 | #define BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
96293 | #define BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
96294 | #define BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
96295 | #define BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
96296 | #define BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
96297 | #define BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
96298 | #define BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
96299 | #define BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
96300 | #define BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
96301 | #define BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
96302 | #define BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
96303 | #define BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
96304 | #define BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
96305 | //BIFPLR4_2_SLOT_STATUS |
96306 | #define BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
96307 | #define BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
96308 | #define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
96309 | #define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
96310 | #define BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
96311 | #define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
96312 | #define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
96313 | #define BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
96314 | #define BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
96315 | #define BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
96316 | #define BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
96317 | #define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
96318 | #define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
96319 | #define BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
96320 | #define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
96321 | #define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
96322 | #define BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
96323 | #define BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
96324 | //BIFPLR4_2_ROOT_CNTL |
96325 | #define BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
96326 | #define BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
96327 | #define BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
96328 | #define BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
96329 | #define BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
96330 | #define BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
96331 | #define BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
96332 | #define BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
96333 | #define BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
96334 | #define BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
96335 | //BIFPLR4_2_ROOT_CAP |
96336 | #define BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
96337 | #define BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
96338 | //BIFPLR4_2_ROOT_STATUS |
96339 | #define BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
96340 | #define BIFPLR4_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
96341 | #define BIFPLR4_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
96342 | #define BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
96343 | #define BIFPLR4_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
96344 | #define BIFPLR4_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
96345 | //BIFPLR4_2_DEVICE_CAP2 |
96346 | #define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
96347 | #define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
96348 | #define BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
96349 | #define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
96350 | #define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
96351 | #define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
96352 | #define BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
96353 | #define BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
96354 | #define BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
96355 | #define BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
96356 | #define BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
96357 | #define BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
96358 | #define BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
96359 | #define BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
96360 | #define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
96361 | #define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
96362 | #define BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
96363 | #define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
96364 | #define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
96365 | #define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
96366 | #define BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
96367 | #define BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
96368 | #define BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
96369 | #define BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
96370 | #define BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
96371 | #define BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
96372 | #define BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
96373 | #define BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
96374 | //BIFPLR4_2_DEVICE_CNTL2 |
96375 | #define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
96376 | #define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
96377 | #define BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
96378 | #define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
96379 | #define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
96380 | #define BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
96381 | #define BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
96382 | #define BIFPLR4_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
96383 | #define BIFPLR4_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
96384 | #define BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
96385 | #define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
96386 | #define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
96387 | #define BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
96388 | #define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
96389 | #define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
96390 | #define BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
96391 | #define BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
96392 | #define BIFPLR4_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
96393 | #define BIFPLR4_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
96394 | #define BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
96395 | //BIFPLR4_2_DEVICE_STATUS2 |
96396 | #define BIFPLR4_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
96397 | #define BIFPLR4_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
96398 | //BIFPLR4_2_LINK_CAP2 |
96399 | #define BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
96400 | #define BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
96401 | #define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
96402 | #define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
96403 | #define BIFPLR4_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
96404 | #define BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
96405 | #define BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
96406 | #define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
96407 | #define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
96408 | #define BIFPLR4_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
96409 | //BIFPLR4_2_LINK_CNTL2 |
96410 | #define BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
96411 | #define BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
96412 | #define BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
96413 | #define BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
96414 | #define BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
96415 | #define BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
96416 | #define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
96417 | #define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
96418 | #define BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
96419 | #define BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
96420 | #define BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
96421 | #define BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
96422 | #define BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
96423 | #define BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
96424 | #define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
96425 | #define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
96426 | //BIFPLR4_2_LINK_STATUS2 |
96427 | #define BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
96428 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
96429 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
96430 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
96431 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
96432 | #define BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
96433 | #define BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
96434 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
96435 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
96436 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
96437 | #define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
96438 | #define BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
96439 | //BIFPLR4_2_SLOT_CAP2 |
96440 | #define BIFPLR4_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
96441 | #define BIFPLR4_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
96442 | //BIFPLR4_2_SLOT_CNTL2 |
96443 | #define BIFPLR4_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
96444 | #define BIFPLR4_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
96445 | //BIFPLR4_2_SLOT_STATUS2 |
96446 | #define BIFPLR4_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
96447 | #define BIFPLR4_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
96448 | //BIFPLR4_2_MSI_CAP_LIST |
96449 | #define BIFPLR4_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
96450 | #define BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
96451 | #define BIFPLR4_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
96452 | #define BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
96453 | //BIFPLR4_2_MSI_MSG_CNTL |
96454 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
96455 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
96456 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
96457 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
96458 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
96459 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
96460 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
96461 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
96462 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
96463 | #define BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
96464 | //BIFPLR4_2_MSI_MSG_ADDR_LO |
96465 | #define BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
96466 | #define BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
96467 | //BIFPLR4_2_MSI_MSG_ADDR_HI |
96468 | #define BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
96469 | #define BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
96470 | //BIFPLR4_2_MSI_MSG_DATA |
96471 | #define BIFPLR4_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
96472 | #define BIFPLR4_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
96473 | //BIFPLR4_2_MSI_MSG_DATA_64 |
96474 | #define BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
96475 | #define BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
96476 | //BIFPLR4_2_SSID_CAP_LIST |
96477 | #define BIFPLR4_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
96478 | #define BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
96479 | #define BIFPLR4_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
96480 | #define BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
96481 | //BIFPLR4_2_SSID_CAP |
96482 | #define BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
96483 | #define BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
96484 | #define BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
96485 | #define BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
96486 | //BIFPLR4_2_MSI_MAP_CAP_LIST |
96487 | #define BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
96488 | #define BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
96489 | #define BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
96490 | #define BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
96491 | //BIFPLR4_2_MSI_MAP_CAP |
96492 | #define BIFPLR4_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
96493 | #define BIFPLR4_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
96494 | #define BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
96495 | #define BIFPLR4_2_MSI_MAP_CAP__EN_MASK 0x0001L |
96496 | #define BIFPLR4_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
96497 | #define BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
96498 | //BIFPLR4_2_MSI_MAP_ADDR_LO |
96499 | #define BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
96500 | #define BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
96501 | //BIFPLR4_2_MSI_MAP_ADDR_HI |
96502 | #define BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
96503 | #define BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
96504 | //BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
96505 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
96506 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
96507 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
96508 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
96509 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
96510 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
96511 | //BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR |
96512 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
96513 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
96514 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
96515 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
96516 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
96517 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
96518 | //BIFPLR4_2_PCIE_VENDOR_SPECIFIC1 |
96519 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
96520 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
96521 | //BIFPLR4_2_PCIE_VENDOR_SPECIFIC2 |
96522 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
96523 | #define BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
96524 | //BIFPLR4_2_PCIE_VC_ENH_CAP_LIST |
96525 | #define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
96526 | #define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
96527 | #define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
96528 | #define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
96529 | #define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
96530 | #define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
96531 | //BIFPLR4_2_PCIE_PORT_VC_CAP_REG1 |
96532 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
96533 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
96534 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
96535 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
96536 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
96537 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
96538 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
96539 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
96540 | //BIFPLR4_2_PCIE_PORT_VC_CAP_REG2 |
96541 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
96542 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
96543 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
96544 | #define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
96545 | //BIFPLR4_2_PCIE_PORT_VC_CNTL |
96546 | #define BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
96547 | #define BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
96548 | #define BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
96549 | #define BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
96550 | //BIFPLR4_2_PCIE_PORT_VC_STATUS |
96551 | #define BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
96552 | #define BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
96553 | //BIFPLR4_2_PCIE_VC0_RESOURCE_CAP |
96554 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
96555 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
96556 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
96557 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
96558 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
96559 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
96560 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
96561 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
96562 | //BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL |
96563 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
96564 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
96565 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
96566 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
96567 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
96568 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
96569 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
96570 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
96571 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
96572 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
96573 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
96574 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
96575 | //BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS |
96576 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
96577 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
96578 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
96579 | #define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
96580 | //BIFPLR4_2_PCIE_VC1_RESOURCE_CAP |
96581 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
96582 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
96583 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
96584 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
96585 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
96586 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
96587 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
96588 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
96589 | //BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL |
96590 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
96591 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
96592 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
96593 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
96594 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
96595 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
96596 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
96597 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
96598 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
96599 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
96600 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
96601 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
96602 | //BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS |
96603 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
96604 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
96605 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
96606 | #define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
96607 | //BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
96608 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
96609 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
96610 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
96611 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
96612 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
96613 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
96614 | //BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1 |
96615 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
96616 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
96617 | //BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2 |
96618 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
96619 | #define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
96620 | //BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
96621 | #define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
96622 | #define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
96623 | #define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
96624 | #define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
96625 | #define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
96626 | #define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
96627 | //BIFPLR4_2_PCIE_UNCORR_ERR_STATUS |
96628 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
96629 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
96630 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
96631 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
96632 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
96633 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
96634 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
96635 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
96636 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
96637 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
96638 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
96639 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
96640 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
96641 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
96642 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
96643 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
96644 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
96645 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
96646 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
96647 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
96648 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
96649 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
96650 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
96651 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
96652 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
96653 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
96654 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
96655 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
96656 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
96657 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
96658 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
96659 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
96660 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
96661 | #define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
96662 | //BIFPLR4_2_PCIE_UNCORR_ERR_MASK |
96663 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
96664 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
96665 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
96666 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
96667 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
96668 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
96669 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
96670 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
96671 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
96672 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
96673 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
96674 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
96675 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
96676 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
96677 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
96678 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
96679 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
96680 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
96681 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
96682 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
96683 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
96684 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
96685 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
96686 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
96687 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
96688 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
96689 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
96690 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
96691 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
96692 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
96693 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
96694 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
96695 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
96696 | #define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
96697 | //BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY |
96698 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
96699 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
96700 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
96701 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
96702 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
96703 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
96704 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
96705 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
96706 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
96707 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
96708 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
96709 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
96710 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
96711 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
96712 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
96713 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
96714 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
96715 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
96716 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
96717 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
96718 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
96719 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
96720 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
96721 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
96722 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
96723 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
96724 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
96725 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
96726 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
96727 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
96728 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
96729 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
96730 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
96731 | #define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
96732 | //BIFPLR4_2_PCIE_CORR_ERR_STATUS |
96733 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
96734 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
96735 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
96736 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
96737 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
96738 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
96739 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
96740 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
96741 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
96742 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
96743 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
96744 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
96745 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
96746 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
96747 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
96748 | #define BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
96749 | //BIFPLR4_2_PCIE_CORR_ERR_MASK |
96750 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
96751 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
96752 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
96753 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
96754 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
96755 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
96756 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
96757 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
96758 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
96759 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
96760 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
96761 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
96762 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
96763 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
96764 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
96765 | #define BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
96766 | //BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL |
96767 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
96768 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
96769 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
96770 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
96771 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
96772 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
96773 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
96774 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
96775 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
96776 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
96777 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
96778 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
96779 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
96780 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
96781 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
96782 | #define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
96783 | //BIFPLR4_2_PCIE_HDR_LOG0 |
96784 | #define BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
96785 | #define BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
96786 | //BIFPLR4_2_PCIE_HDR_LOG1 |
96787 | #define BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
96788 | #define BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
96789 | //BIFPLR4_2_PCIE_HDR_LOG2 |
96790 | #define BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
96791 | #define BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
96792 | //BIFPLR4_2_PCIE_HDR_LOG3 |
96793 | #define BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
96794 | #define BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
96795 | //BIFPLR4_2_PCIE_ROOT_ERR_CMD |
96796 | #define BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
96797 | #define BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
96798 | #define BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
96799 | #define BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
96800 | #define BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
96801 | #define BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
96802 | //BIFPLR4_2_PCIE_ROOT_ERR_STATUS |
96803 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
96804 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
96805 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
96806 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
96807 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
96808 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
96809 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
96810 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
96811 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
96812 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
96813 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
96814 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
96815 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
96816 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
96817 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
96818 | #define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
96819 | //BIFPLR4_2_PCIE_ERR_SRC_ID |
96820 | #define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
96821 | #define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
96822 | #define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
96823 | #define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
96824 | //BIFPLR4_2_PCIE_TLP_PREFIX_LOG0 |
96825 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
96826 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
96827 | //BIFPLR4_2_PCIE_TLP_PREFIX_LOG1 |
96828 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
96829 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
96830 | //BIFPLR4_2_PCIE_TLP_PREFIX_LOG2 |
96831 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
96832 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
96833 | //BIFPLR4_2_PCIE_TLP_PREFIX_LOG3 |
96834 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
96835 | #define BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
96836 | //BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST |
96837 | #define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
96838 | #define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
96839 | #define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
96840 | #define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
96841 | #define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
96842 | #define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
96843 | //BIFPLR4_2_PCIE_LINK_CNTL3 |
96844 | #define BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
96845 | #define BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
96846 | #define BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
96847 | #define BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
96848 | #define BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
96849 | #define BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
96850 | #define BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
96851 | #define BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
96852 | //BIFPLR4_2_PCIE_LANE_ERROR_STATUS |
96853 | #define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
96854 | #define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
96855 | #define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
96856 | #define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
96857 | //BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL |
96858 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96859 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96860 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96861 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96862 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96863 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96864 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96865 | #define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96866 | //BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL |
96867 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96868 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96869 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96870 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96871 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96872 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96873 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96874 | #define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96875 | //BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL |
96876 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96877 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96878 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96879 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96880 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96881 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96882 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96883 | #define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96884 | //BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL |
96885 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96886 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96887 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96888 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96889 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96890 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96891 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96892 | #define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96893 | //BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL |
96894 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96895 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96896 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96897 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96898 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96899 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96900 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96901 | #define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96902 | //BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL |
96903 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96904 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96905 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96906 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96907 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96908 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96909 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96910 | #define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96911 | //BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL |
96912 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96913 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96914 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96915 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96916 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96917 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96918 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96919 | #define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96920 | //BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL |
96921 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96922 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96923 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96924 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96925 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96926 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96927 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96928 | #define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96929 | //BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL |
96930 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96931 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96932 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96933 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96934 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96935 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96936 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96937 | #define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96938 | //BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL |
96939 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96940 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96941 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96942 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96943 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96944 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96945 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96946 | #define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96947 | //BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL |
96948 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96949 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96950 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96951 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96952 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96953 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96954 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96955 | #define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96956 | //BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL |
96957 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96958 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96959 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96960 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96961 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96962 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96963 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96964 | #define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96965 | //BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL |
96966 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96967 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96968 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96969 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96970 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96971 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96972 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96973 | #define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96974 | //BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL |
96975 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96976 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96977 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96978 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96979 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96980 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96981 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96982 | #define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96983 | //BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL |
96984 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96985 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96986 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96987 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96988 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96989 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96990 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
96991 | #define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
96992 | //BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL |
96993 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
96994 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
96995 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
96996 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
96997 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
96998 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
96999 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
97000 | #define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
97001 | //BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST |
97002 | #define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
97003 | #define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
97004 | #define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
97005 | #define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
97006 | #define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
97007 | #define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
97008 | //BIFPLR4_2_PCIE_ACS_CAP |
97009 | #define BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
97010 | #define BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
97011 | #define BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
97012 | #define BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
97013 | #define BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
97014 | #define BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
97015 | #define BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
97016 | #define BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
97017 | #define BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
97018 | #define BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
97019 | #define BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
97020 | #define BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
97021 | #define BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
97022 | #define BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
97023 | #define BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
97024 | #define BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
97025 | //BIFPLR4_2_PCIE_ACS_CNTL |
97026 | #define BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
97027 | #define BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
97028 | #define BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
97029 | #define BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
97030 | #define BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
97031 | #define BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
97032 | #define BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
97033 | #define BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
97034 | #define BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
97035 | #define BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
97036 | #define BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
97037 | #define BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
97038 | #define BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
97039 | #define BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
97040 | //BIFPLR4_2_PCIE_MC_ENH_CAP_LIST |
97041 | #define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
97042 | #define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
97043 | #define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
97044 | #define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
97045 | #define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
97046 | #define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
97047 | //BIFPLR4_2_PCIE_MC_CAP |
97048 | #define BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
97049 | #define BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
97050 | #define BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
97051 | #define BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
97052 | //BIFPLR4_2_PCIE_MC_CNTL |
97053 | #define BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
97054 | #define BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
97055 | #define BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
97056 | #define BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
97057 | //BIFPLR4_2_PCIE_MC_ADDR0 |
97058 | #define BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
97059 | #define BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
97060 | #define BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
97061 | #define BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
97062 | //BIFPLR4_2_PCIE_MC_ADDR1 |
97063 | #define BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
97064 | #define BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
97065 | //BIFPLR4_2_PCIE_MC_RCV0 |
97066 | #define BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
97067 | #define BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
97068 | //BIFPLR4_2_PCIE_MC_RCV1 |
97069 | #define BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
97070 | #define BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
97071 | //BIFPLR4_2_PCIE_MC_BLOCK_ALL0 |
97072 | #define BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
97073 | #define BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
97074 | //BIFPLR4_2_PCIE_MC_BLOCK_ALL1 |
97075 | #define BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
97076 | #define BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
97077 | //BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
97078 | #define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
97079 | #define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
97080 | //BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
97081 | #define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
97082 | #define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
97083 | //BIFPLR4_2_PCIE_MC_OVERLAY_BAR0 |
97084 | #define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
97085 | #define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
97086 | #define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
97087 | #define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
97088 | //BIFPLR4_2_PCIE_MC_OVERLAY_BAR1 |
97089 | #define BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
97090 | #define BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
97091 | //BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST |
97092 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
97093 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
97094 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
97095 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
97096 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
97097 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
97098 | //BIFPLR4_2_PCIE_L1_PM_SUB_CAP |
97099 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
97100 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
97101 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
97102 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
97103 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
97104 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
97105 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
97106 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
97107 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
97108 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
97109 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
97110 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
97111 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
97112 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
97113 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
97114 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
97115 | //BIFPLR4_2_PCIE_L1_PM_SUB_CNTL |
97116 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
97117 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
97118 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
97119 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
97120 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
97121 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
97122 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
97123 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
97124 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
97125 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
97126 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
97127 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
97128 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
97129 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
97130 | //BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2 |
97131 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
97132 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
97133 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
97134 | #define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
97135 | //BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST |
97136 | #define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
97137 | #define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
97138 | #define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
97139 | #define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
97140 | #define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
97141 | #define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
97142 | //BIFPLR4_2_PCIE_DPC_CAP_LIST |
97143 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
97144 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
97145 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
97146 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
97147 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
97148 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
97149 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
97150 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
97151 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
97152 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
97153 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
97154 | #define BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
97155 | //BIFPLR4_2_PCIE_DPC_CNTL |
97156 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
97157 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
97158 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
97159 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
97160 | #define BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
97161 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
97162 | #define BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
97163 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
97164 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
97165 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
97166 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
97167 | #define BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
97168 | #define BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
97169 | #define BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
97170 | //BIFPLR4_2_PCIE_DPC_STATUS |
97171 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
97172 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
97173 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
97174 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
97175 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
97176 | #define BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
97177 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
97178 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
97179 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
97180 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
97181 | #define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
97182 | #define BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
97183 | //BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID |
97184 | #define BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
97185 | #define BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
97186 | //BIFPLR4_2_PCIE_RP_PIO_STATUS |
97187 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
97188 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
97189 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
97190 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
97191 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
97192 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
97193 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
97194 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
97195 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
97196 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
97197 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
97198 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
97199 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
97200 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
97201 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
97202 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
97203 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
97204 | #define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
97205 | //BIFPLR4_2_PCIE_RP_PIO_MASK |
97206 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
97207 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
97208 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
97209 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
97210 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
97211 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
97212 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
97213 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
97214 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
97215 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
97216 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
97217 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
97218 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
97219 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
97220 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
97221 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
97222 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
97223 | #define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
97224 | //BIFPLR4_2_PCIE_RP_PIO_SEVERITY |
97225 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
97226 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
97227 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
97228 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
97229 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
97230 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
97231 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
97232 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
97233 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
97234 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
97235 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
97236 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
97237 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
97238 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
97239 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
97240 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
97241 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
97242 | #define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
97243 | //BIFPLR4_2_PCIE_RP_PIO_SYSERROR |
97244 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
97245 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
97246 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
97247 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
97248 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
97249 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
97250 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
97251 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
97252 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
97253 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
97254 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
97255 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
97256 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
97257 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
97258 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
97259 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
97260 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
97261 | #define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
97262 | //BIFPLR4_2_PCIE_RP_PIO_EXCEPTION |
97263 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
97264 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
97265 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
97266 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
97267 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
97268 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
97269 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
97270 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
97271 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
97272 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
97273 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
97274 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
97275 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
97276 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
97277 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
97278 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
97279 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
97280 | #define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
97281 | //BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0 |
97282 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
97283 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
97284 | //BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1 |
97285 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
97286 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
97287 | //BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2 |
97288 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
97289 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
97290 | //BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3 |
97291 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
97292 | #define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
97293 | //BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG |
97294 | #define BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
97295 | #define BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
97296 | //BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0 |
97297 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
97298 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
97299 | //BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1 |
97300 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
97301 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
97302 | //BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2 |
97303 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
97304 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
97305 | //BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3 |
97306 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
97307 | #define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
97308 | //BIFPLR4_2_PCIE_ESM_CAP_LIST |
97309 | #define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
97310 | #define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
97311 | #define BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
97312 | #define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
97313 | #define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
97314 | #define BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
97315 | //BIFPLR4_2_PCIE_ESM_HEADER_1 |
97316 | #define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
97317 | #define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
97318 | #define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
97319 | #define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
97320 | #define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
97321 | #define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
97322 | //BIFPLR4_2_PCIE_ESM_HEADER_2 |
97323 | #define BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
97324 | #define BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
97325 | //BIFPLR4_2_PCIE_ESM_STATUS |
97326 | #define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
97327 | #define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
97328 | #define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
97329 | #define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
97330 | //BIFPLR4_2_PCIE_ESM_CTRL |
97331 | #define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
97332 | #define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
97333 | #define BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
97334 | #define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
97335 | #define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
97336 | #define BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
97337 | //BIFPLR4_2_PCIE_ESM_CAP_1 |
97338 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
97339 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
97340 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
97341 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
97342 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
97343 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
97344 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
97345 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
97346 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
97347 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
97348 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
97349 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
97350 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
97351 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
97352 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
97353 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
97354 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
97355 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
97356 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
97357 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
97358 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
97359 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
97360 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
97361 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
97362 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
97363 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
97364 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
97365 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
97366 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
97367 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
97368 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
97369 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
97370 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
97371 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
97372 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
97373 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
97374 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
97375 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
97376 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
97377 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
97378 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
97379 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
97380 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
97381 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
97382 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
97383 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
97384 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
97385 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
97386 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
97387 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
97388 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
97389 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
97390 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
97391 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
97392 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
97393 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
97394 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
97395 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
97396 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
97397 | #define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
97398 | //BIFPLR4_2_PCIE_ESM_CAP_2 |
97399 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
97400 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
97401 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
97402 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
97403 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
97404 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
97405 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
97406 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
97407 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
97408 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
97409 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
97410 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
97411 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
97412 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
97413 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
97414 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
97415 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
97416 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
97417 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
97418 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
97419 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
97420 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
97421 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
97422 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
97423 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
97424 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
97425 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
97426 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
97427 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
97428 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
97429 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
97430 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
97431 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
97432 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
97433 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
97434 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
97435 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
97436 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
97437 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
97438 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
97439 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
97440 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
97441 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
97442 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
97443 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
97444 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
97445 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
97446 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
97447 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
97448 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
97449 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
97450 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
97451 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
97452 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
97453 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
97454 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
97455 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
97456 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
97457 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
97458 | #define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
97459 | //BIFPLR4_2_PCIE_ESM_CAP_3 |
97460 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
97461 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
97462 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
97463 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
97464 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
97465 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
97466 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
97467 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
97468 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
97469 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
97470 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
97471 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
97472 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
97473 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
97474 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
97475 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
97476 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
97477 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
97478 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
97479 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
97480 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
97481 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
97482 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
97483 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
97484 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
97485 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
97486 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
97487 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
97488 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
97489 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
97490 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
97491 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
97492 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
97493 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
97494 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
97495 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
97496 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
97497 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
97498 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
97499 | #define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
97500 | //BIFPLR4_2_PCIE_ESM_CAP_4 |
97501 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
97502 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
97503 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
97504 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
97505 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
97506 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
97507 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
97508 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
97509 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
97510 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
97511 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
97512 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
97513 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
97514 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
97515 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
97516 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
97517 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
97518 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
97519 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
97520 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
97521 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
97522 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
97523 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
97524 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
97525 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
97526 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
97527 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
97528 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
97529 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
97530 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
97531 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
97532 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
97533 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
97534 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
97535 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
97536 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
97537 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
97538 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
97539 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
97540 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
97541 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
97542 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
97543 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
97544 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
97545 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
97546 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
97547 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
97548 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
97549 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
97550 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
97551 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
97552 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
97553 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
97554 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
97555 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
97556 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
97557 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
97558 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
97559 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
97560 | #define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
97561 | //BIFPLR4_2_PCIE_ESM_CAP_5 |
97562 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
97563 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
97564 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
97565 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
97566 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
97567 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
97568 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
97569 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
97570 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
97571 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
97572 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
97573 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
97574 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
97575 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
97576 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
97577 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
97578 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
97579 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
97580 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
97581 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
97582 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
97583 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
97584 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
97585 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
97586 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
97587 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
97588 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
97589 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
97590 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
97591 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
97592 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
97593 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
97594 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
97595 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
97596 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
97597 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
97598 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
97599 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
97600 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
97601 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
97602 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
97603 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
97604 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
97605 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
97606 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
97607 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
97608 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
97609 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
97610 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
97611 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
97612 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
97613 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
97614 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
97615 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
97616 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
97617 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
97618 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
97619 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
97620 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
97621 | #define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
97622 | //BIFPLR4_2_PCIE_ESM_CAP_6 |
97623 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
97624 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
97625 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
97626 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
97627 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
97628 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
97629 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
97630 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
97631 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
97632 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
97633 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
97634 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
97635 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
97636 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
97637 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
97638 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
97639 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
97640 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
97641 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
97642 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
97643 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
97644 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
97645 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
97646 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
97647 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
97648 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
97649 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
97650 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
97651 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
97652 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
97653 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
97654 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
97655 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
97656 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
97657 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
97658 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
97659 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
97660 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
97661 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
97662 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
97663 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
97664 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
97665 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
97666 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
97667 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
97668 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
97669 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
97670 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
97671 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
97672 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
97673 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
97674 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
97675 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
97676 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
97677 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
97678 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
97679 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
97680 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
97681 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
97682 | #define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
97683 | //BIFPLR4_2_PCIE_ESM_CAP_7 |
97684 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
97685 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
97686 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
97687 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
97688 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
97689 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
97690 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
97691 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
97692 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
97693 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
97694 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
97695 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
97696 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
97697 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
97698 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
97699 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
97700 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
97701 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
97702 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
97703 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
97704 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
97705 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
97706 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
97707 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
97708 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
97709 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
97710 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
97711 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
97712 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
97713 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
97714 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
97715 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
97716 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
97717 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
97718 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
97719 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
97720 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
97721 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
97722 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
97723 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
97724 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
97725 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
97726 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
97727 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
97728 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
97729 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
97730 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
97731 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
97732 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
97733 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
97734 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
97735 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
97736 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
97737 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
97738 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
97739 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
97740 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
97741 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
97742 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
97743 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
97744 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
97745 | #define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
97746 | |
97747 | |
97748 | // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
97749 | //BIFPLR5_2_VENDOR_ID |
97750 | #define BIFPLR5_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
97751 | #define BIFPLR5_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
97752 | //BIFPLR5_2_DEVICE_ID |
97753 | #define BIFPLR5_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
97754 | #define BIFPLR5_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
97755 | //BIFPLR5_2_COMMAND |
97756 | #define BIFPLR5_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
97757 | #define BIFPLR5_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
97758 | #define BIFPLR5_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
97759 | #define BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
97760 | #define BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
97761 | #define BIFPLR5_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
97762 | #define BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
97763 | #define BIFPLR5_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
97764 | #define BIFPLR5_2_COMMAND__SERR_EN__SHIFT 0x8 |
97765 | #define BIFPLR5_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
97766 | #define BIFPLR5_2_COMMAND__INT_DIS__SHIFT 0xa |
97767 | #define BIFPLR5_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
97768 | #define BIFPLR5_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
97769 | #define BIFPLR5_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
97770 | #define BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
97771 | #define BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
97772 | #define BIFPLR5_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
97773 | #define BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
97774 | #define BIFPLR5_2_COMMAND__AD_STEPPING_MASK 0x0080L |
97775 | #define BIFPLR5_2_COMMAND__SERR_EN_MASK 0x0100L |
97776 | #define BIFPLR5_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
97777 | #define BIFPLR5_2_COMMAND__INT_DIS_MASK 0x0400L |
97778 | //BIFPLR5_2_STATUS |
97779 | #define BIFPLR5_2_STATUS__INT_STATUS__SHIFT 0x3 |
97780 | #define BIFPLR5_2_STATUS__CAP_LIST__SHIFT 0x4 |
97781 | #define BIFPLR5_2_STATUS__PCI_66_EN__SHIFT 0x5 |
97782 | #define BIFPLR5_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
97783 | #define BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
97784 | #define BIFPLR5_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
97785 | #define BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
97786 | #define BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
97787 | #define BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
97788 | #define BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
97789 | #define BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
97790 | #define BIFPLR5_2_STATUS__INT_STATUS_MASK 0x0008L |
97791 | #define BIFPLR5_2_STATUS__CAP_LIST_MASK 0x0010L |
97792 | #define BIFPLR5_2_STATUS__PCI_66_EN_MASK 0x0020L |
97793 | #define BIFPLR5_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
97794 | #define BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
97795 | #define BIFPLR5_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
97796 | #define BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
97797 | #define BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
97798 | #define BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
97799 | #define BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
97800 | #define BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
97801 | //BIFPLR5_2_REVISION_ID |
97802 | #define BIFPLR5_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
97803 | #define BIFPLR5_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
97804 | #define BIFPLR5_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
97805 | #define BIFPLR5_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
97806 | //BIFPLR5_2_PROG_INTERFACE |
97807 | #define BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
97808 | #define BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
97809 | //BIFPLR5_2_SUB_CLASS |
97810 | #define BIFPLR5_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
97811 | #define BIFPLR5_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
97812 | //BIFPLR5_2_BASE_CLASS |
97813 | #define BIFPLR5_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
97814 | #define BIFPLR5_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
97815 | //BIFPLR5_2_CACHE_LINE |
97816 | #define BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
97817 | #define BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
97818 | //BIFPLR5_2_LATENCY |
97819 | #define BIFPLR5_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
97820 | #define BIFPLR5_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
97821 | //BIFPLR5_2_HEADER |
97822 | #define BIFPLR5_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
97823 | #define BIFPLR5_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
97824 | #define BIFPLR5_2_HEADER__HEADER_TYPE_MASK 0x7FL |
97825 | #define BIFPLR5_2_HEADER__DEVICE_TYPE_MASK 0x80L |
97826 | //BIFPLR5_2_BIST |
97827 | #define BIFPLR5_2_BIST__BIST_COMP__SHIFT 0x0 |
97828 | #define BIFPLR5_2_BIST__BIST_STRT__SHIFT 0x6 |
97829 | #define BIFPLR5_2_BIST__BIST_CAP__SHIFT 0x7 |
97830 | #define BIFPLR5_2_BIST__BIST_COMP_MASK 0x0FL |
97831 | #define BIFPLR5_2_BIST__BIST_STRT_MASK 0x40L |
97832 | #define BIFPLR5_2_BIST__BIST_CAP_MASK 0x80L |
97833 | //BIFPLR5_2_SUB_BUS_NUMBER_LATENCY |
97834 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
97835 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
97836 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
97837 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
97838 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
97839 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
97840 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
97841 | #define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
97842 | //BIFPLR5_2_IO_BASE_LIMIT |
97843 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
97844 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
97845 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
97846 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
97847 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
97848 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
97849 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
97850 | #define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
97851 | //BIFPLR5_2_SECONDARY_STATUS |
97852 | #define BIFPLR5_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
97853 | #define BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
97854 | #define BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
97855 | #define BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
97856 | #define BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
97857 | #define BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
97858 | #define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
97859 | #define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
97860 | #define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
97861 | #define BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
97862 | #define BIFPLR5_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
97863 | #define BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
97864 | #define BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
97865 | #define BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
97866 | #define BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
97867 | #define BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
97868 | #define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
97869 | #define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
97870 | #define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
97871 | #define BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
97872 | //BIFPLR5_2_MEM_BASE_LIMIT |
97873 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
97874 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
97875 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
97876 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
97877 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
97878 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
97879 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
97880 | #define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
97881 | //BIFPLR5_2_PREF_BASE_LIMIT |
97882 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
97883 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
97884 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
97885 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
97886 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
97887 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
97888 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
97889 | #define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
97890 | //BIFPLR5_2_PREF_BASE_UPPER |
97891 | #define BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
97892 | #define BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
97893 | //BIFPLR5_2_PREF_LIMIT_UPPER |
97894 | #define BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
97895 | #define BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
97896 | //BIFPLR5_2_IO_BASE_LIMIT_HI |
97897 | #define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
97898 | #define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
97899 | #define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
97900 | #define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
97901 | //BIFPLR5_2_CAP_PTR |
97902 | #define BIFPLR5_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
97903 | #define BIFPLR5_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
97904 | //BIFPLR5_2_INTERRUPT_LINE |
97905 | #define BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
97906 | #define BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
97907 | //BIFPLR5_2_INTERRUPT_PIN |
97908 | #define BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
97909 | #define BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
97910 | //BIFPLR5_2_IRQ_BRIDGE_CNTL |
97911 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
97912 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
97913 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
97914 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
97915 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
97916 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
97917 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
97918 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
97919 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
97920 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
97921 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
97922 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
97923 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
97924 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
97925 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
97926 | #define BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
97927 | //BIFPLR5_2_EXT_BRIDGE_CNTL |
97928 | #define BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
97929 | #define BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
97930 | //BIFPLR5_2_PMI_CAP_LIST |
97931 | #define BIFPLR5_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
97932 | #define BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
97933 | #define BIFPLR5_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
97934 | #define BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
97935 | //BIFPLR5_2_PMI_CAP |
97936 | #define BIFPLR5_2_PMI_CAP__VERSION__SHIFT 0x0 |
97937 | #define BIFPLR5_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
97938 | #define BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
97939 | #define BIFPLR5_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
97940 | #define BIFPLR5_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
97941 | #define BIFPLR5_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
97942 | #define BIFPLR5_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
97943 | #define BIFPLR5_2_PMI_CAP__VERSION_MASK 0x0007L |
97944 | #define BIFPLR5_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
97945 | #define BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
97946 | #define BIFPLR5_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
97947 | #define BIFPLR5_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
97948 | #define BIFPLR5_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
97949 | #define BIFPLR5_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
97950 | //BIFPLR5_2_PMI_STATUS_CNTL |
97951 | #define BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
97952 | #define BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
97953 | #define BIFPLR5_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
97954 | #define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
97955 | #define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
97956 | #define BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
97957 | #define BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
97958 | #define BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
97959 | #define BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
97960 | #define BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
97961 | #define BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
97962 | #define BIFPLR5_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
97963 | #define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
97964 | #define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
97965 | #define BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
97966 | #define BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
97967 | #define BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
97968 | #define BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
97969 | //BIFPLR5_2_PCIE_CAP_LIST |
97970 | #define BIFPLR5_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
97971 | #define BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
97972 | #define BIFPLR5_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
97973 | #define BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
97974 | //BIFPLR5_2_PCIE_CAP |
97975 | #define BIFPLR5_2_PCIE_CAP__VERSION__SHIFT 0x0 |
97976 | #define BIFPLR5_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
97977 | #define BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
97978 | #define BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
97979 | #define BIFPLR5_2_PCIE_CAP__VERSION_MASK 0x000FL |
97980 | #define BIFPLR5_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
97981 | #define BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
97982 | #define BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
97983 | //BIFPLR5_2_DEVICE_CAP |
97984 | #define BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
97985 | #define BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
97986 | #define BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
97987 | #define BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
97988 | #define BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
97989 | #define BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
97990 | #define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
97991 | #define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
97992 | #define BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
97993 | #define BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
97994 | #define BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
97995 | #define BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
97996 | #define BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
97997 | #define BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
97998 | #define BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
97999 | #define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
98000 | #define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
98001 | #define BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
98002 | //BIFPLR5_2_DEVICE_CNTL |
98003 | #define BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
98004 | #define BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
98005 | #define BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
98006 | #define BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
98007 | #define BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
98008 | #define BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
98009 | #define BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
98010 | #define BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
98011 | #define BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
98012 | #define BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
98013 | #define BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
98014 | #define BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
98015 | #define BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
98016 | #define BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
98017 | #define BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
98018 | #define BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
98019 | #define BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
98020 | #define BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
98021 | #define BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
98022 | #define BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
98023 | #define BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
98024 | #define BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
98025 | #define BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
98026 | #define BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
98027 | //BIFPLR5_2_DEVICE_STATUS |
98028 | #define BIFPLR5_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
98029 | #define BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
98030 | #define BIFPLR5_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
98031 | #define BIFPLR5_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
98032 | #define BIFPLR5_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
98033 | #define BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
98034 | #define BIFPLR5_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
98035 | #define BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
98036 | #define BIFPLR5_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
98037 | #define BIFPLR5_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
98038 | #define BIFPLR5_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
98039 | #define BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
98040 | //BIFPLR5_2_LINK_CAP |
98041 | #define BIFPLR5_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
98042 | #define BIFPLR5_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
98043 | #define BIFPLR5_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
98044 | #define BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
98045 | #define BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
98046 | #define BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
98047 | #define BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
98048 | #define BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
98049 | #define BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
98050 | #define BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
98051 | #define BIFPLR5_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
98052 | #define BIFPLR5_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
98053 | #define BIFPLR5_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
98054 | #define BIFPLR5_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
98055 | #define BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
98056 | #define BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
98057 | #define BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
98058 | #define BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
98059 | #define BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
98060 | #define BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
98061 | #define BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
98062 | #define BIFPLR5_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
98063 | //BIFPLR5_2_LINK_CNTL |
98064 | #define BIFPLR5_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
98065 | #define BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
98066 | #define BIFPLR5_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
98067 | #define BIFPLR5_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
98068 | #define BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
98069 | #define BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
98070 | #define BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
98071 | #define BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
98072 | #define BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
98073 | #define BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
98074 | #define BIFPLR5_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
98075 | #define BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
98076 | #define BIFPLR5_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
98077 | #define BIFPLR5_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
98078 | #define BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
98079 | #define BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
98080 | #define BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
98081 | #define BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
98082 | #define BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
98083 | #define BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
98084 | //BIFPLR5_2_LINK_STATUS |
98085 | #define BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
98086 | #define BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
98087 | #define BIFPLR5_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
98088 | #define BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
98089 | #define BIFPLR5_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
98090 | #define BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
98091 | #define BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
98092 | #define BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
98093 | #define BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
98094 | #define BIFPLR5_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
98095 | #define BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
98096 | #define BIFPLR5_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
98097 | #define BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
98098 | #define BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
98099 | //BIFPLR5_2_SLOT_CAP |
98100 | #define BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
98101 | #define BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
98102 | #define BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
98103 | #define BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
98104 | #define BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
98105 | #define BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
98106 | #define BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
98107 | #define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
98108 | #define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
98109 | #define BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
98110 | #define BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
98111 | #define BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
98112 | #define BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
98113 | #define BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
98114 | #define BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
98115 | #define BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
98116 | #define BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
98117 | #define BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
98118 | #define BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
98119 | #define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
98120 | #define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
98121 | #define BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
98122 | #define BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
98123 | #define BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
98124 | //BIFPLR5_2_SLOT_CNTL |
98125 | #define BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
98126 | #define BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
98127 | #define BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
98128 | #define BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
98129 | #define BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
98130 | #define BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
98131 | #define BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
98132 | #define BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
98133 | #define BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
98134 | #define BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
98135 | #define BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
98136 | #define BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
98137 | #define BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
98138 | #define BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
98139 | #define BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
98140 | #define BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
98141 | #define BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
98142 | #define BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
98143 | #define BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
98144 | #define BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
98145 | #define BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
98146 | #define BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
98147 | #define BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
98148 | #define BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
98149 | //BIFPLR5_2_SLOT_STATUS |
98150 | #define BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
98151 | #define BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
98152 | #define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
98153 | #define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
98154 | #define BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
98155 | #define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
98156 | #define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
98157 | #define BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
98158 | #define BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
98159 | #define BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
98160 | #define BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
98161 | #define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
98162 | #define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
98163 | #define BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
98164 | #define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
98165 | #define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
98166 | #define BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
98167 | #define BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
98168 | //BIFPLR5_2_ROOT_CNTL |
98169 | #define BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
98170 | #define BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
98171 | #define BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
98172 | #define BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
98173 | #define BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
98174 | #define BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
98175 | #define BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
98176 | #define BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
98177 | #define BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
98178 | #define BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
98179 | //BIFPLR5_2_ROOT_CAP |
98180 | #define BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
98181 | #define BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
98182 | //BIFPLR5_2_ROOT_STATUS |
98183 | #define BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
98184 | #define BIFPLR5_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
98185 | #define BIFPLR5_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
98186 | #define BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
98187 | #define BIFPLR5_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
98188 | #define BIFPLR5_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
98189 | //BIFPLR5_2_DEVICE_CAP2 |
98190 | #define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
98191 | #define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
98192 | #define BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
98193 | #define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
98194 | #define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
98195 | #define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
98196 | #define BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
98197 | #define BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
98198 | #define BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
98199 | #define BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
98200 | #define BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
98201 | #define BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
98202 | #define BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
98203 | #define BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
98204 | #define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
98205 | #define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
98206 | #define BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
98207 | #define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
98208 | #define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
98209 | #define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
98210 | #define BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
98211 | #define BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
98212 | #define BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
98213 | #define BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
98214 | #define BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
98215 | #define BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
98216 | #define BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
98217 | #define BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
98218 | //BIFPLR5_2_DEVICE_CNTL2 |
98219 | #define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
98220 | #define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
98221 | #define BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
98222 | #define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
98223 | #define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
98224 | #define BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
98225 | #define BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
98226 | #define BIFPLR5_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
98227 | #define BIFPLR5_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
98228 | #define BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
98229 | #define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
98230 | #define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
98231 | #define BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
98232 | #define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
98233 | #define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
98234 | #define BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
98235 | #define BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
98236 | #define BIFPLR5_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
98237 | #define BIFPLR5_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
98238 | #define BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
98239 | //BIFPLR5_2_DEVICE_STATUS2 |
98240 | #define BIFPLR5_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
98241 | #define BIFPLR5_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
98242 | //BIFPLR5_2_LINK_CAP2 |
98243 | #define BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
98244 | #define BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
98245 | #define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
98246 | #define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
98247 | #define BIFPLR5_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
98248 | #define BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
98249 | #define BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
98250 | #define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
98251 | #define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
98252 | #define BIFPLR5_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
98253 | //BIFPLR5_2_LINK_CNTL2 |
98254 | #define BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
98255 | #define BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
98256 | #define BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
98257 | #define BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
98258 | #define BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
98259 | #define BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
98260 | #define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
98261 | #define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
98262 | #define BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
98263 | #define BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
98264 | #define BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
98265 | #define BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
98266 | #define BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
98267 | #define BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
98268 | #define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
98269 | #define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
98270 | //BIFPLR5_2_LINK_STATUS2 |
98271 | #define BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
98272 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
98273 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
98274 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
98275 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
98276 | #define BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
98277 | #define BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
98278 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
98279 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
98280 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
98281 | #define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
98282 | #define BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
98283 | //BIFPLR5_2_SLOT_CAP2 |
98284 | #define BIFPLR5_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
98285 | #define BIFPLR5_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
98286 | //BIFPLR5_2_SLOT_CNTL2 |
98287 | #define BIFPLR5_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
98288 | #define BIFPLR5_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
98289 | //BIFPLR5_2_SLOT_STATUS2 |
98290 | #define BIFPLR5_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
98291 | #define BIFPLR5_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
98292 | //BIFPLR5_2_MSI_CAP_LIST |
98293 | #define BIFPLR5_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
98294 | #define BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
98295 | #define BIFPLR5_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
98296 | #define BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
98297 | //BIFPLR5_2_MSI_MSG_CNTL |
98298 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
98299 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
98300 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
98301 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
98302 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
98303 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
98304 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
98305 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
98306 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
98307 | #define BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
98308 | //BIFPLR5_2_MSI_MSG_ADDR_LO |
98309 | #define BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
98310 | #define BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
98311 | //BIFPLR5_2_MSI_MSG_ADDR_HI |
98312 | #define BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
98313 | #define BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
98314 | //BIFPLR5_2_MSI_MSG_DATA |
98315 | #define BIFPLR5_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
98316 | #define BIFPLR5_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
98317 | //BIFPLR5_2_MSI_MSG_DATA_64 |
98318 | #define BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
98319 | #define BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
98320 | //BIFPLR5_2_SSID_CAP_LIST |
98321 | #define BIFPLR5_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
98322 | #define BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
98323 | #define BIFPLR5_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
98324 | #define BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
98325 | //BIFPLR5_2_SSID_CAP |
98326 | #define BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
98327 | #define BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
98328 | #define BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
98329 | #define BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
98330 | //BIFPLR5_2_MSI_MAP_CAP_LIST |
98331 | #define BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
98332 | #define BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
98333 | #define BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
98334 | #define BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
98335 | //BIFPLR5_2_MSI_MAP_CAP |
98336 | #define BIFPLR5_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
98337 | #define BIFPLR5_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
98338 | #define BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
98339 | #define BIFPLR5_2_MSI_MAP_CAP__EN_MASK 0x0001L |
98340 | #define BIFPLR5_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
98341 | #define BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
98342 | //BIFPLR5_2_MSI_MAP_ADDR_LO |
98343 | #define BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
98344 | #define BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
98345 | //BIFPLR5_2_MSI_MAP_ADDR_HI |
98346 | #define BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
98347 | #define BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
98348 | //BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
98349 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98350 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98351 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98352 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98353 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98354 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98355 | //BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR |
98356 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
98357 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
98358 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
98359 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
98360 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
98361 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
98362 | //BIFPLR5_2_PCIE_VENDOR_SPECIFIC1 |
98363 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
98364 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
98365 | //BIFPLR5_2_PCIE_VENDOR_SPECIFIC2 |
98366 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
98367 | #define BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
98368 | //BIFPLR5_2_PCIE_VC_ENH_CAP_LIST |
98369 | #define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98370 | #define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98371 | #define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98372 | #define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98373 | #define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98374 | #define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98375 | //BIFPLR5_2_PCIE_PORT_VC_CAP_REG1 |
98376 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
98377 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
98378 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
98379 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
98380 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
98381 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
98382 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
98383 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
98384 | //BIFPLR5_2_PCIE_PORT_VC_CAP_REG2 |
98385 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
98386 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
98387 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
98388 | #define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
98389 | //BIFPLR5_2_PCIE_PORT_VC_CNTL |
98390 | #define BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
98391 | #define BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
98392 | #define BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
98393 | #define BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
98394 | //BIFPLR5_2_PCIE_PORT_VC_STATUS |
98395 | #define BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
98396 | #define BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
98397 | //BIFPLR5_2_PCIE_VC0_RESOURCE_CAP |
98398 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
98399 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
98400 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
98401 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
98402 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
98403 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
98404 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
98405 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
98406 | //BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL |
98407 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
98408 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
98409 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
98410 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
98411 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
98412 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
98413 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
98414 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
98415 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
98416 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
98417 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
98418 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
98419 | //BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS |
98420 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
98421 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
98422 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
98423 | #define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
98424 | //BIFPLR5_2_PCIE_VC1_RESOURCE_CAP |
98425 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
98426 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
98427 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
98428 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
98429 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
98430 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
98431 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
98432 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
98433 | //BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL |
98434 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
98435 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
98436 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
98437 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
98438 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
98439 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
98440 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
98441 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
98442 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
98443 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
98444 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
98445 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
98446 | //BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS |
98447 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
98448 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
98449 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
98450 | #define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
98451 | //BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
98452 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98453 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98454 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98455 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98456 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98457 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98458 | //BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1 |
98459 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
98460 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
98461 | //BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2 |
98462 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
98463 | #define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
98464 | //BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
98465 | #define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98466 | #define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98467 | #define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98468 | #define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98469 | #define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98470 | #define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98471 | //BIFPLR5_2_PCIE_UNCORR_ERR_STATUS |
98472 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
98473 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
98474 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
98475 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
98476 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
98477 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
98478 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
98479 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
98480 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
98481 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
98482 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
98483 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
98484 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
98485 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
98486 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
98487 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
98488 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
98489 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
98490 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
98491 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
98492 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
98493 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
98494 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
98495 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
98496 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
98497 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
98498 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
98499 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
98500 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
98501 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
98502 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
98503 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
98504 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
98505 | #define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
98506 | //BIFPLR5_2_PCIE_UNCORR_ERR_MASK |
98507 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
98508 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
98509 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
98510 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
98511 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
98512 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
98513 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
98514 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
98515 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
98516 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
98517 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
98518 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
98519 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
98520 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
98521 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
98522 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
98523 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
98524 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
98525 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
98526 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
98527 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
98528 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
98529 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
98530 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
98531 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
98532 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
98533 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
98534 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
98535 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
98536 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
98537 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
98538 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
98539 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
98540 | #define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
98541 | //BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY |
98542 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
98543 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
98544 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
98545 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
98546 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
98547 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
98548 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
98549 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
98550 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
98551 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
98552 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
98553 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
98554 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
98555 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
98556 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
98557 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
98558 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
98559 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
98560 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
98561 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
98562 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
98563 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
98564 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
98565 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
98566 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
98567 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
98568 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
98569 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
98570 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
98571 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
98572 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
98573 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
98574 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
98575 | #define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
98576 | //BIFPLR5_2_PCIE_CORR_ERR_STATUS |
98577 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
98578 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
98579 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
98580 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
98581 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
98582 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
98583 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
98584 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
98585 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
98586 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
98587 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
98588 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
98589 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
98590 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
98591 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
98592 | #define BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
98593 | //BIFPLR5_2_PCIE_CORR_ERR_MASK |
98594 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
98595 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
98596 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
98597 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
98598 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
98599 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
98600 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
98601 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
98602 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
98603 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
98604 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
98605 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
98606 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
98607 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
98608 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
98609 | #define BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
98610 | //BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL |
98611 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
98612 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
98613 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
98614 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
98615 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
98616 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
98617 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
98618 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
98619 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
98620 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
98621 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
98622 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
98623 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
98624 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
98625 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
98626 | #define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
98627 | //BIFPLR5_2_PCIE_HDR_LOG0 |
98628 | #define BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
98629 | #define BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
98630 | //BIFPLR5_2_PCIE_HDR_LOG1 |
98631 | #define BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
98632 | #define BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
98633 | //BIFPLR5_2_PCIE_HDR_LOG2 |
98634 | #define BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
98635 | #define BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
98636 | //BIFPLR5_2_PCIE_HDR_LOG3 |
98637 | #define BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
98638 | #define BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
98639 | //BIFPLR5_2_PCIE_ROOT_ERR_CMD |
98640 | #define BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
98641 | #define BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
98642 | #define BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
98643 | #define BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
98644 | #define BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
98645 | #define BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
98646 | //BIFPLR5_2_PCIE_ROOT_ERR_STATUS |
98647 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
98648 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
98649 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
98650 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
98651 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
98652 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
98653 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
98654 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
98655 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
98656 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
98657 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
98658 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
98659 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
98660 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
98661 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
98662 | #define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
98663 | //BIFPLR5_2_PCIE_ERR_SRC_ID |
98664 | #define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
98665 | #define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
98666 | #define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
98667 | #define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
98668 | //BIFPLR5_2_PCIE_TLP_PREFIX_LOG0 |
98669 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
98670 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
98671 | //BIFPLR5_2_PCIE_TLP_PREFIX_LOG1 |
98672 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
98673 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
98674 | //BIFPLR5_2_PCIE_TLP_PREFIX_LOG2 |
98675 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
98676 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
98677 | //BIFPLR5_2_PCIE_TLP_PREFIX_LOG3 |
98678 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
98679 | #define BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
98680 | //BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST |
98681 | #define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98682 | #define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98683 | #define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98684 | #define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98685 | #define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98686 | #define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98687 | //BIFPLR5_2_PCIE_LINK_CNTL3 |
98688 | #define BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
98689 | #define BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
98690 | #define BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
98691 | #define BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
98692 | #define BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
98693 | #define BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
98694 | #define BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
98695 | #define BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
98696 | //BIFPLR5_2_PCIE_LANE_ERROR_STATUS |
98697 | #define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
98698 | #define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
98699 | #define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
98700 | #define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
98701 | //BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL |
98702 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98703 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98704 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98705 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98706 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98707 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98708 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98709 | #define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98710 | //BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL |
98711 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98712 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98713 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98714 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98715 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98716 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98717 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98718 | #define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98719 | //BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL |
98720 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98721 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98722 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98723 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98724 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98725 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98726 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98727 | #define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98728 | //BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL |
98729 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98730 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98731 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98732 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98733 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98734 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98735 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98736 | #define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98737 | //BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL |
98738 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98739 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98740 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98741 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98742 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98743 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98744 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98745 | #define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98746 | //BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL |
98747 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98748 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98749 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98750 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98751 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98752 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98753 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98754 | #define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98755 | //BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL |
98756 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98757 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98758 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98759 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98760 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98761 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98762 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98763 | #define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98764 | //BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL |
98765 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98766 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98767 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98768 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98769 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98770 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98771 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98772 | #define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98773 | //BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL |
98774 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98775 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98776 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98777 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98778 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98779 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98780 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98781 | #define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98782 | //BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL |
98783 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98784 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98785 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98786 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98787 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98788 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98789 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98790 | #define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98791 | //BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL |
98792 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98793 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98794 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98795 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98796 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98797 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98798 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98799 | #define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98800 | //BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL |
98801 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98802 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98803 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98804 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98805 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98806 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98807 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98808 | #define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98809 | //BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL |
98810 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98811 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98812 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98813 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98814 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98815 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98816 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98817 | #define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98818 | //BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL |
98819 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98820 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98821 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98822 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98823 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98824 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98825 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98826 | #define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98827 | //BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL |
98828 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98829 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98830 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98831 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98832 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98833 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98834 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98835 | #define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98836 | //BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL |
98837 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
98838 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
98839 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
98840 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
98841 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
98842 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
98843 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
98844 | #define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
98845 | //BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST |
98846 | #define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98847 | #define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98848 | #define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98849 | #define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98850 | #define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98851 | #define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98852 | //BIFPLR5_2_PCIE_ACS_CAP |
98853 | #define BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
98854 | #define BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
98855 | #define BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
98856 | #define BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
98857 | #define BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
98858 | #define BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
98859 | #define BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
98860 | #define BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
98861 | #define BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
98862 | #define BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
98863 | #define BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
98864 | #define BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
98865 | #define BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
98866 | #define BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
98867 | #define BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
98868 | #define BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
98869 | //BIFPLR5_2_PCIE_ACS_CNTL |
98870 | #define BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
98871 | #define BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
98872 | #define BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
98873 | #define BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
98874 | #define BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
98875 | #define BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
98876 | #define BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
98877 | #define BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
98878 | #define BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
98879 | #define BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
98880 | #define BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
98881 | #define BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
98882 | #define BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
98883 | #define BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
98884 | //BIFPLR5_2_PCIE_MC_ENH_CAP_LIST |
98885 | #define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98886 | #define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98887 | #define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98888 | #define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98889 | #define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98890 | #define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98891 | //BIFPLR5_2_PCIE_MC_CAP |
98892 | #define BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
98893 | #define BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
98894 | #define BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
98895 | #define BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
98896 | //BIFPLR5_2_PCIE_MC_CNTL |
98897 | #define BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
98898 | #define BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
98899 | #define BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
98900 | #define BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
98901 | //BIFPLR5_2_PCIE_MC_ADDR0 |
98902 | #define BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
98903 | #define BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
98904 | #define BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
98905 | #define BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
98906 | //BIFPLR5_2_PCIE_MC_ADDR1 |
98907 | #define BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
98908 | #define BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
98909 | //BIFPLR5_2_PCIE_MC_RCV0 |
98910 | #define BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
98911 | #define BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
98912 | //BIFPLR5_2_PCIE_MC_RCV1 |
98913 | #define BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
98914 | #define BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
98915 | //BIFPLR5_2_PCIE_MC_BLOCK_ALL0 |
98916 | #define BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
98917 | #define BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
98918 | //BIFPLR5_2_PCIE_MC_BLOCK_ALL1 |
98919 | #define BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
98920 | #define BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
98921 | //BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
98922 | #define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
98923 | #define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
98924 | //BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
98925 | #define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
98926 | #define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
98927 | //BIFPLR5_2_PCIE_MC_OVERLAY_BAR0 |
98928 | #define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
98929 | #define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
98930 | #define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
98931 | #define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
98932 | //BIFPLR5_2_PCIE_MC_OVERLAY_BAR1 |
98933 | #define BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
98934 | #define BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
98935 | //BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST |
98936 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
98937 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
98938 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98939 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98940 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98941 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98942 | //BIFPLR5_2_PCIE_L1_PM_SUB_CAP |
98943 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
98944 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
98945 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
98946 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
98947 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
98948 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
98949 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
98950 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
98951 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
98952 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
98953 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
98954 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
98955 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
98956 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
98957 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
98958 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
98959 | //BIFPLR5_2_PCIE_L1_PM_SUB_CNTL |
98960 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
98961 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
98962 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
98963 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
98964 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
98965 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
98966 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
98967 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
98968 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
98969 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
98970 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
98971 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
98972 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
98973 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
98974 | //BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2 |
98975 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
98976 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
98977 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
98978 | #define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
98979 | //BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST |
98980 | #define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
98981 | #define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
98982 | #define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
98983 | #define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
98984 | #define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
98985 | #define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
98986 | //BIFPLR5_2_PCIE_DPC_CAP_LIST |
98987 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
98988 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
98989 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
98990 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
98991 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
98992 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
98993 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
98994 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
98995 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
98996 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
98997 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
98998 | #define BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
98999 | //BIFPLR5_2_PCIE_DPC_CNTL |
99000 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
99001 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
99002 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
99003 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
99004 | #define BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
99005 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
99006 | #define BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
99007 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
99008 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
99009 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
99010 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
99011 | #define BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
99012 | #define BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
99013 | #define BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
99014 | //BIFPLR5_2_PCIE_DPC_STATUS |
99015 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
99016 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
99017 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
99018 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
99019 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
99020 | #define BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
99021 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
99022 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
99023 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
99024 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
99025 | #define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
99026 | #define BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
99027 | //BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID |
99028 | #define BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
99029 | #define BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
99030 | //BIFPLR5_2_PCIE_RP_PIO_STATUS |
99031 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
99032 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
99033 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
99034 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
99035 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
99036 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
99037 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
99038 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
99039 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
99040 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
99041 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
99042 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
99043 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
99044 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
99045 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
99046 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
99047 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
99048 | #define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
99049 | //BIFPLR5_2_PCIE_RP_PIO_MASK |
99050 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
99051 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
99052 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
99053 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
99054 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
99055 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
99056 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
99057 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
99058 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
99059 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
99060 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
99061 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
99062 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
99063 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
99064 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
99065 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
99066 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
99067 | #define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
99068 | //BIFPLR5_2_PCIE_RP_PIO_SEVERITY |
99069 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
99070 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
99071 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
99072 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
99073 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
99074 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
99075 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
99076 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
99077 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
99078 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
99079 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
99080 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
99081 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
99082 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
99083 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
99084 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
99085 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
99086 | #define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
99087 | //BIFPLR5_2_PCIE_RP_PIO_SYSERROR |
99088 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
99089 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
99090 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
99091 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
99092 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
99093 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
99094 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
99095 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
99096 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
99097 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
99098 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
99099 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
99100 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
99101 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
99102 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
99103 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
99104 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
99105 | #define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
99106 | //BIFPLR5_2_PCIE_RP_PIO_EXCEPTION |
99107 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
99108 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
99109 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
99110 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
99111 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
99112 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
99113 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
99114 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
99115 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
99116 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
99117 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
99118 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
99119 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
99120 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
99121 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
99122 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
99123 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
99124 | #define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
99125 | //BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0 |
99126 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
99127 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
99128 | //BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1 |
99129 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
99130 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
99131 | //BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2 |
99132 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
99133 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
99134 | //BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3 |
99135 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
99136 | #define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
99137 | //BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG |
99138 | #define BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
99139 | #define BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
99140 | //BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0 |
99141 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
99142 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
99143 | //BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1 |
99144 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
99145 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
99146 | //BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2 |
99147 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
99148 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
99149 | //BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3 |
99150 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
99151 | #define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
99152 | //BIFPLR5_2_PCIE_ESM_CAP_LIST |
99153 | #define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
99154 | #define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
99155 | #define BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
99156 | #define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
99157 | #define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
99158 | #define BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
99159 | //BIFPLR5_2_PCIE_ESM_HEADER_1 |
99160 | #define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
99161 | #define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
99162 | #define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
99163 | #define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
99164 | #define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
99165 | #define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
99166 | //BIFPLR5_2_PCIE_ESM_HEADER_2 |
99167 | #define BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
99168 | #define BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
99169 | //BIFPLR5_2_PCIE_ESM_STATUS |
99170 | #define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
99171 | #define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
99172 | #define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
99173 | #define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
99174 | //BIFPLR5_2_PCIE_ESM_CTRL |
99175 | #define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
99176 | #define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
99177 | #define BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
99178 | #define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
99179 | #define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
99180 | #define BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
99181 | //BIFPLR5_2_PCIE_ESM_CAP_1 |
99182 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
99183 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
99184 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
99185 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
99186 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
99187 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
99188 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
99189 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
99190 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
99191 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
99192 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
99193 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
99194 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
99195 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
99196 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
99197 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
99198 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
99199 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
99200 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
99201 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
99202 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
99203 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
99204 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
99205 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
99206 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
99207 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
99208 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
99209 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
99210 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
99211 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
99212 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
99213 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
99214 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
99215 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
99216 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
99217 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
99218 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
99219 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
99220 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
99221 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
99222 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
99223 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
99224 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
99225 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
99226 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
99227 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
99228 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
99229 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
99230 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
99231 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
99232 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
99233 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
99234 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
99235 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
99236 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
99237 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
99238 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
99239 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
99240 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
99241 | #define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
99242 | //BIFPLR5_2_PCIE_ESM_CAP_2 |
99243 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
99244 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
99245 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
99246 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
99247 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
99248 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
99249 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
99250 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
99251 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
99252 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
99253 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
99254 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
99255 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
99256 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
99257 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
99258 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
99259 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
99260 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
99261 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
99262 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
99263 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
99264 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
99265 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
99266 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
99267 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
99268 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
99269 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
99270 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
99271 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
99272 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
99273 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
99274 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
99275 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
99276 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
99277 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
99278 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
99279 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
99280 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
99281 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
99282 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
99283 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
99284 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
99285 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
99286 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
99287 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
99288 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
99289 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
99290 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
99291 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
99292 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
99293 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
99294 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
99295 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
99296 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
99297 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
99298 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
99299 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
99300 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
99301 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
99302 | #define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
99303 | //BIFPLR5_2_PCIE_ESM_CAP_3 |
99304 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
99305 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
99306 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
99307 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
99308 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
99309 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
99310 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
99311 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
99312 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
99313 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
99314 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
99315 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
99316 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
99317 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
99318 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
99319 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
99320 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
99321 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
99322 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
99323 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
99324 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
99325 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
99326 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
99327 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
99328 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
99329 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
99330 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
99331 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
99332 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
99333 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
99334 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
99335 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
99336 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
99337 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
99338 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
99339 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
99340 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
99341 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
99342 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
99343 | #define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
99344 | //BIFPLR5_2_PCIE_ESM_CAP_4 |
99345 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
99346 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
99347 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
99348 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
99349 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
99350 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
99351 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
99352 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
99353 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
99354 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
99355 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
99356 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
99357 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
99358 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
99359 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
99360 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
99361 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
99362 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
99363 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
99364 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
99365 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
99366 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
99367 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
99368 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
99369 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
99370 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
99371 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
99372 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
99373 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
99374 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
99375 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
99376 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
99377 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
99378 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
99379 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
99380 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
99381 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
99382 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
99383 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
99384 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
99385 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
99386 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
99387 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
99388 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
99389 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
99390 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
99391 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
99392 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
99393 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
99394 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
99395 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
99396 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
99397 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
99398 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
99399 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
99400 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
99401 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
99402 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
99403 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
99404 | #define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
99405 | //BIFPLR5_2_PCIE_ESM_CAP_5 |
99406 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
99407 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
99408 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
99409 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
99410 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
99411 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
99412 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
99413 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
99414 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
99415 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
99416 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
99417 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
99418 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
99419 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
99420 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
99421 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
99422 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
99423 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
99424 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
99425 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
99426 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
99427 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
99428 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
99429 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
99430 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
99431 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
99432 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
99433 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
99434 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
99435 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
99436 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
99437 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
99438 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
99439 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
99440 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
99441 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
99442 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
99443 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
99444 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
99445 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
99446 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
99447 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
99448 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
99449 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
99450 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
99451 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
99452 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
99453 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
99454 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
99455 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
99456 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
99457 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
99458 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
99459 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
99460 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
99461 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
99462 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
99463 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
99464 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
99465 | #define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
99466 | //BIFPLR5_2_PCIE_ESM_CAP_6 |
99467 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
99468 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
99469 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
99470 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
99471 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
99472 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
99473 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
99474 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
99475 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
99476 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
99477 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
99478 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
99479 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
99480 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
99481 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
99482 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
99483 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
99484 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
99485 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
99486 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
99487 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
99488 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
99489 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
99490 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
99491 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
99492 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
99493 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
99494 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
99495 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
99496 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
99497 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
99498 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
99499 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
99500 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
99501 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
99502 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
99503 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
99504 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
99505 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
99506 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
99507 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
99508 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
99509 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
99510 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
99511 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
99512 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
99513 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
99514 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
99515 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
99516 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
99517 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
99518 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
99519 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
99520 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
99521 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
99522 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
99523 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
99524 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
99525 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
99526 | #define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
99527 | //BIFPLR5_2_PCIE_ESM_CAP_7 |
99528 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
99529 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
99530 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
99531 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
99532 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
99533 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
99534 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
99535 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
99536 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
99537 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
99538 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
99539 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
99540 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
99541 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
99542 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
99543 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
99544 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
99545 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
99546 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
99547 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
99548 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
99549 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
99550 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
99551 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
99552 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
99553 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
99554 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
99555 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
99556 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
99557 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
99558 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
99559 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
99560 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
99561 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
99562 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
99563 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
99564 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
99565 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
99566 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
99567 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
99568 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
99569 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
99570 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
99571 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
99572 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
99573 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
99574 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
99575 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
99576 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
99577 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
99578 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
99579 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
99580 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
99581 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
99582 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
99583 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
99584 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
99585 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
99586 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
99587 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
99588 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
99589 | #define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
99590 | |
99591 | |
99592 | // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
99593 | //BIFPLR6_2_VENDOR_ID |
99594 | #define BIFPLR6_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
99595 | #define BIFPLR6_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
99596 | //BIFPLR6_2_DEVICE_ID |
99597 | #define BIFPLR6_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
99598 | #define BIFPLR6_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
99599 | //BIFPLR6_2_COMMAND |
99600 | #define BIFPLR6_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
99601 | #define BIFPLR6_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
99602 | #define BIFPLR6_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
99603 | #define BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
99604 | #define BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
99605 | #define BIFPLR6_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
99606 | #define BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
99607 | #define BIFPLR6_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
99608 | #define BIFPLR6_2_COMMAND__SERR_EN__SHIFT 0x8 |
99609 | #define BIFPLR6_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
99610 | #define BIFPLR6_2_COMMAND__INT_DIS__SHIFT 0xa |
99611 | #define BIFPLR6_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
99612 | #define BIFPLR6_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
99613 | #define BIFPLR6_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
99614 | #define BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
99615 | #define BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
99616 | #define BIFPLR6_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
99617 | #define BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
99618 | #define BIFPLR6_2_COMMAND__AD_STEPPING_MASK 0x0080L |
99619 | #define BIFPLR6_2_COMMAND__SERR_EN_MASK 0x0100L |
99620 | #define BIFPLR6_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
99621 | #define BIFPLR6_2_COMMAND__INT_DIS_MASK 0x0400L |
99622 | //BIFPLR6_2_STATUS |
99623 | #define BIFPLR6_2_STATUS__INT_STATUS__SHIFT 0x3 |
99624 | #define BIFPLR6_2_STATUS__CAP_LIST__SHIFT 0x4 |
99625 | #define BIFPLR6_2_STATUS__PCI_66_EN__SHIFT 0x5 |
99626 | #define BIFPLR6_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
99627 | #define BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
99628 | #define BIFPLR6_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
99629 | #define BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
99630 | #define BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
99631 | #define BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
99632 | #define BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
99633 | #define BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
99634 | #define BIFPLR6_2_STATUS__INT_STATUS_MASK 0x0008L |
99635 | #define BIFPLR6_2_STATUS__CAP_LIST_MASK 0x0010L |
99636 | #define BIFPLR6_2_STATUS__PCI_66_EN_MASK 0x0020L |
99637 | #define BIFPLR6_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
99638 | #define BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
99639 | #define BIFPLR6_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
99640 | #define BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
99641 | #define BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
99642 | #define BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
99643 | #define BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
99644 | #define BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
99645 | //BIFPLR6_2_REVISION_ID |
99646 | #define BIFPLR6_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
99647 | #define BIFPLR6_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
99648 | #define BIFPLR6_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
99649 | #define BIFPLR6_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
99650 | //BIFPLR6_2_PROG_INTERFACE |
99651 | #define BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
99652 | #define BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
99653 | //BIFPLR6_2_SUB_CLASS |
99654 | #define BIFPLR6_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
99655 | #define BIFPLR6_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
99656 | //BIFPLR6_2_BASE_CLASS |
99657 | #define BIFPLR6_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
99658 | #define BIFPLR6_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
99659 | //BIFPLR6_2_CACHE_LINE |
99660 | #define BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
99661 | #define BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
99662 | //BIFPLR6_2_LATENCY |
99663 | #define BIFPLR6_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
99664 | #define BIFPLR6_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
99665 | //BIFPLR6_2_HEADER |
99666 | #define BIFPLR6_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
99667 | #define BIFPLR6_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
99668 | #define BIFPLR6_2_HEADER__HEADER_TYPE_MASK 0x7FL |
99669 | #define BIFPLR6_2_HEADER__DEVICE_TYPE_MASK 0x80L |
99670 | //BIFPLR6_2_BIST |
99671 | #define BIFPLR6_2_BIST__BIST_COMP__SHIFT 0x0 |
99672 | #define BIFPLR6_2_BIST__BIST_STRT__SHIFT 0x6 |
99673 | #define BIFPLR6_2_BIST__BIST_CAP__SHIFT 0x7 |
99674 | #define BIFPLR6_2_BIST__BIST_COMP_MASK 0x0FL |
99675 | #define BIFPLR6_2_BIST__BIST_STRT_MASK 0x40L |
99676 | #define BIFPLR6_2_BIST__BIST_CAP_MASK 0x80L |
99677 | //BIFPLR6_2_SUB_BUS_NUMBER_LATENCY |
99678 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
99679 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
99680 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
99681 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
99682 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
99683 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
99684 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
99685 | #define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
99686 | //BIFPLR6_2_IO_BASE_LIMIT |
99687 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
99688 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
99689 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
99690 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
99691 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
99692 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
99693 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
99694 | #define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
99695 | //BIFPLR6_2_SECONDARY_STATUS |
99696 | #define BIFPLR6_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
99697 | #define BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
99698 | #define BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
99699 | #define BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
99700 | #define BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
99701 | #define BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
99702 | #define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
99703 | #define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
99704 | #define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
99705 | #define BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
99706 | #define BIFPLR6_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
99707 | #define BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
99708 | #define BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
99709 | #define BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
99710 | #define BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
99711 | #define BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
99712 | #define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
99713 | #define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
99714 | #define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
99715 | #define BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
99716 | //BIFPLR6_2_MEM_BASE_LIMIT |
99717 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
99718 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
99719 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
99720 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
99721 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
99722 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
99723 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
99724 | #define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
99725 | //BIFPLR6_2_PREF_BASE_LIMIT |
99726 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
99727 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
99728 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
99729 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
99730 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
99731 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
99732 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
99733 | #define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
99734 | //BIFPLR6_2_PREF_BASE_UPPER |
99735 | #define BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
99736 | #define BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
99737 | //BIFPLR6_2_PREF_LIMIT_UPPER |
99738 | #define BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
99739 | #define BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
99740 | //BIFPLR6_2_IO_BASE_LIMIT_HI |
99741 | #define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
99742 | #define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
99743 | #define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
99744 | #define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
99745 | //BIFPLR6_2_CAP_PTR |
99746 | #define BIFPLR6_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
99747 | #define BIFPLR6_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
99748 | //BIFPLR6_2_INTERRUPT_LINE |
99749 | #define BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
99750 | #define BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
99751 | //BIFPLR6_2_INTERRUPT_PIN |
99752 | #define BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
99753 | #define BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
99754 | //BIFPLR6_2_IRQ_BRIDGE_CNTL |
99755 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
99756 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
99757 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
99758 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
99759 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
99760 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
99761 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
99762 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
99763 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
99764 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
99765 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
99766 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
99767 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
99768 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
99769 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
99770 | #define BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
99771 | //BIFPLR6_2_EXT_BRIDGE_CNTL |
99772 | #define BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
99773 | #define BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
99774 | //BIFPLR6_2_PMI_CAP_LIST |
99775 | #define BIFPLR6_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
99776 | #define BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
99777 | #define BIFPLR6_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
99778 | #define BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
99779 | //BIFPLR6_2_PMI_CAP |
99780 | #define BIFPLR6_2_PMI_CAP__VERSION__SHIFT 0x0 |
99781 | #define BIFPLR6_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
99782 | #define BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
99783 | #define BIFPLR6_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
99784 | #define BIFPLR6_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
99785 | #define BIFPLR6_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
99786 | #define BIFPLR6_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
99787 | #define BIFPLR6_2_PMI_CAP__VERSION_MASK 0x0007L |
99788 | #define BIFPLR6_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
99789 | #define BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
99790 | #define BIFPLR6_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
99791 | #define BIFPLR6_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
99792 | #define BIFPLR6_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
99793 | #define BIFPLR6_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
99794 | //BIFPLR6_2_PMI_STATUS_CNTL |
99795 | #define BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
99796 | #define BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
99797 | #define BIFPLR6_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
99798 | #define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
99799 | #define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
99800 | #define BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
99801 | #define BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
99802 | #define BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
99803 | #define BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
99804 | #define BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
99805 | #define BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
99806 | #define BIFPLR6_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
99807 | #define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
99808 | #define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
99809 | #define BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
99810 | #define BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
99811 | #define BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
99812 | #define BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
99813 | //BIFPLR6_2_PCIE_CAP_LIST |
99814 | #define BIFPLR6_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
99815 | #define BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
99816 | #define BIFPLR6_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
99817 | #define BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
99818 | //BIFPLR6_2_PCIE_CAP |
99819 | #define BIFPLR6_2_PCIE_CAP__VERSION__SHIFT 0x0 |
99820 | #define BIFPLR6_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
99821 | #define BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
99822 | #define BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
99823 | #define BIFPLR6_2_PCIE_CAP__VERSION_MASK 0x000FL |
99824 | #define BIFPLR6_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
99825 | #define BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
99826 | #define BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
99827 | //BIFPLR6_2_DEVICE_CAP |
99828 | #define BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
99829 | #define BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
99830 | #define BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
99831 | #define BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
99832 | #define BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
99833 | #define BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
99834 | #define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
99835 | #define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
99836 | #define BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
99837 | #define BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
99838 | #define BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
99839 | #define BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
99840 | #define BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
99841 | #define BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
99842 | #define BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
99843 | #define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
99844 | #define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
99845 | #define BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
99846 | //BIFPLR6_2_DEVICE_CNTL |
99847 | #define BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
99848 | #define BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
99849 | #define BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
99850 | #define BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
99851 | #define BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
99852 | #define BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
99853 | #define BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
99854 | #define BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
99855 | #define BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
99856 | #define BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
99857 | #define BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
99858 | #define BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
99859 | #define BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
99860 | #define BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
99861 | #define BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
99862 | #define BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
99863 | #define BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
99864 | #define BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
99865 | #define BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
99866 | #define BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
99867 | #define BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
99868 | #define BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
99869 | #define BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
99870 | #define BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
99871 | //BIFPLR6_2_DEVICE_STATUS |
99872 | #define BIFPLR6_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
99873 | #define BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
99874 | #define BIFPLR6_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
99875 | #define BIFPLR6_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
99876 | #define BIFPLR6_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
99877 | #define BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
99878 | #define BIFPLR6_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
99879 | #define BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
99880 | #define BIFPLR6_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
99881 | #define BIFPLR6_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
99882 | #define BIFPLR6_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
99883 | #define BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
99884 | //BIFPLR6_2_LINK_CAP |
99885 | #define BIFPLR6_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
99886 | #define BIFPLR6_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
99887 | #define BIFPLR6_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
99888 | #define BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
99889 | #define BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
99890 | #define BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
99891 | #define BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
99892 | #define BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
99893 | #define BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
99894 | #define BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
99895 | #define BIFPLR6_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
99896 | #define BIFPLR6_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
99897 | #define BIFPLR6_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
99898 | #define BIFPLR6_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
99899 | #define BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
99900 | #define BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
99901 | #define BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
99902 | #define BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
99903 | #define BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
99904 | #define BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
99905 | #define BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
99906 | #define BIFPLR6_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
99907 | //BIFPLR6_2_LINK_CNTL |
99908 | #define BIFPLR6_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
99909 | #define BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
99910 | #define BIFPLR6_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
99911 | #define BIFPLR6_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
99912 | #define BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
99913 | #define BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
99914 | #define BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
99915 | #define BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
99916 | #define BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
99917 | #define BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
99918 | #define BIFPLR6_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
99919 | #define BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
99920 | #define BIFPLR6_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
99921 | #define BIFPLR6_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
99922 | #define BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
99923 | #define BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
99924 | #define BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
99925 | #define BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
99926 | #define BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
99927 | #define BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
99928 | //BIFPLR6_2_LINK_STATUS |
99929 | #define BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
99930 | #define BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
99931 | #define BIFPLR6_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
99932 | #define BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
99933 | #define BIFPLR6_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
99934 | #define BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
99935 | #define BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
99936 | #define BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
99937 | #define BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
99938 | #define BIFPLR6_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
99939 | #define BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
99940 | #define BIFPLR6_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
99941 | #define BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
99942 | #define BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
99943 | //BIFPLR6_2_SLOT_CAP |
99944 | #define BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
99945 | #define BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
99946 | #define BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
99947 | #define BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
99948 | #define BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
99949 | #define BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
99950 | #define BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
99951 | #define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
99952 | #define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
99953 | #define BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
99954 | #define BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
99955 | #define BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
99956 | #define BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
99957 | #define BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
99958 | #define BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
99959 | #define BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
99960 | #define BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
99961 | #define BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
99962 | #define BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
99963 | #define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
99964 | #define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
99965 | #define BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
99966 | #define BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
99967 | #define BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
99968 | //BIFPLR6_2_SLOT_CNTL |
99969 | #define BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
99970 | #define BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
99971 | #define BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
99972 | #define BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
99973 | #define BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
99974 | #define BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
99975 | #define BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
99976 | #define BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
99977 | #define BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
99978 | #define BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
99979 | #define BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
99980 | #define BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
99981 | #define BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
99982 | #define BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
99983 | #define BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
99984 | #define BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
99985 | #define BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
99986 | #define BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
99987 | #define BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
99988 | #define BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
99989 | #define BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
99990 | #define BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
99991 | #define BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
99992 | #define BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
99993 | //BIFPLR6_2_SLOT_STATUS |
99994 | #define BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
99995 | #define BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
99996 | #define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
99997 | #define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
99998 | #define BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
99999 | #define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
100000 | #define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
100001 | #define BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
100002 | #define BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
100003 | #define BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
100004 | #define BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
100005 | #define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
100006 | #define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
100007 | #define BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
100008 | #define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
100009 | #define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
100010 | #define BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
100011 | #define BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
100012 | //BIFPLR6_2_ROOT_CNTL |
100013 | #define BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
100014 | #define BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
100015 | #define BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
100016 | #define BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
100017 | #define BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
100018 | #define BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
100019 | #define BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
100020 | #define BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
100021 | #define BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
100022 | #define BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
100023 | //BIFPLR6_2_ROOT_CAP |
100024 | #define BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
100025 | #define BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
100026 | //BIFPLR6_2_ROOT_STATUS |
100027 | #define BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
100028 | #define BIFPLR6_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
100029 | #define BIFPLR6_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
100030 | #define BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
100031 | #define BIFPLR6_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
100032 | #define BIFPLR6_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
100033 | //BIFPLR6_2_DEVICE_CAP2 |
100034 | #define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
100035 | #define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
100036 | #define BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
100037 | #define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
100038 | #define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
100039 | #define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
100040 | #define BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
100041 | #define BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
100042 | #define BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
100043 | #define BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
100044 | #define BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
100045 | #define BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
100046 | #define BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
100047 | #define BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
100048 | #define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
100049 | #define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
100050 | #define BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
100051 | #define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
100052 | #define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
100053 | #define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
100054 | #define BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
100055 | #define BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
100056 | #define BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
100057 | #define BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
100058 | #define BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
100059 | #define BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
100060 | #define BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
100061 | #define BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
100062 | //BIFPLR6_2_DEVICE_CNTL2 |
100063 | #define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
100064 | #define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
100065 | #define BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
100066 | #define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
100067 | #define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
100068 | #define BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
100069 | #define BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
100070 | #define BIFPLR6_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
100071 | #define BIFPLR6_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
100072 | #define BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
100073 | #define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
100074 | #define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
100075 | #define BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
100076 | #define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
100077 | #define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
100078 | #define BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
100079 | #define BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
100080 | #define BIFPLR6_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
100081 | #define BIFPLR6_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
100082 | #define BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
100083 | //BIFPLR6_2_DEVICE_STATUS2 |
100084 | #define BIFPLR6_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
100085 | #define BIFPLR6_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
100086 | //BIFPLR6_2_LINK_CAP2 |
100087 | #define BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
100088 | #define BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
100089 | #define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
100090 | #define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
100091 | #define BIFPLR6_2_LINK_CAP2__RESERVED__SHIFT 0x13 |
100092 | #define BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
100093 | #define BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
100094 | #define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
100095 | #define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
100096 | #define BIFPLR6_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
100097 | //BIFPLR6_2_LINK_CNTL2 |
100098 | #define BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
100099 | #define BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
100100 | #define BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
100101 | #define BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
100102 | #define BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
100103 | #define BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
100104 | #define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
100105 | #define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
100106 | #define BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
100107 | #define BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
100108 | #define BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
100109 | #define BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
100110 | #define BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
100111 | #define BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
100112 | #define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
100113 | #define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
100114 | //BIFPLR6_2_LINK_STATUS2 |
100115 | #define BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
100116 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
100117 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
100118 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
100119 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
100120 | #define BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
100121 | #define BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
100122 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
100123 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
100124 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
100125 | #define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
100126 | #define BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
100127 | //BIFPLR6_2_SLOT_CAP2 |
100128 | #define BIFPLR6_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
100129 | #define BIFPLR6_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
100130 | //BIFPLR6_2_SLOT_CNTL2 |
100131 | #define BIFPLR6_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
100132 | #define BIFPLR6_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
100133 | //BIFPLR6_2_SLOT_STATUS2 |
100134 | #define BIFPLR6_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
100135 | #define BIFPLR6_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
100136 | //BIFPLR6_2_MSI_CAP_LIST |
100137 | #define BIFPLR6_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
100138 | #define BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
100139 | #define BIFPLR6_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
100140 | #define BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
100141 | //BIFPLR6_2_MSI_MSG_CNTL |
100142 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
100143 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
100144 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
100145 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
100146 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
100147 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
100148 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
100149 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
100150 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
100151 | #define BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
100152 | //BIFPLR6_2_MSI_MSG_ADDR_LO |
100153 | #define BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
100154 | #define BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
100155 | //BIFPLR6_2_MSI_MSG_ADDR_HI |
100156 | #define BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
100157 | #define BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
100158 | //BIFPLR6_2_MSI_MSG_DATA |
100159 | #define BIFPLR6_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
100160 | #define BIFPLR6_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
100161 | //BIFPLR6_2_MSI_MSG_DATA_64 |
100162 | #define BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
100163 | #define BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
100164 | //BIFPLR6_2_SSID_CAP_LIST |
100165 | #define BIFPLR6_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
100166 | #define BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
100167 | #define BIFPLR6_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
100168 | #define BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
100169 | //BIFPLR6_2_SSID_CAP |
100170 | #define BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
100171 | #define BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
100172 | #define BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
100173 | #define BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
100174 | //BIFPLR6_2_MSI_MAP_CAP_LIST |
100175 | #define BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
100176 | #define BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
100177 | #define BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
100178 | #define BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
100179 | //BIFPLR6_2_MSI_MAP_CAP |
100180 | #define BIFPLR6_2_MSI_MAP_CAP__EN__SHIFT 0x0 |
100181 | #define BIFPLR6_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
100182 | #define BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
100183 | #define BIFPLR6_2_MSI_MAP_CAP__EN_MASK 0x0001L |
100184 | #define BIFPLR6_2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
100185 | #define BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
100186 | //BIFPLR6_2_MSI_MAP_ADDR_LO |
100187 | #define BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
100188 | #define BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
100189 | //BIFPLR6_2_MSI_MAP_ADDR_HI |
100190 | #define BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
100191 | #define BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
100192 | //BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
100193 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100194 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100195 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100196 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100197 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100198 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100199 | //BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR |
100200 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
100201 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
100202 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
100203 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
100204 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
100205 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
100206 | //BIFPLR6_2_PCIE_VENDOR_SPECIFIC1 |
100207 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
100208 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
100209 | //BIFPLR6_2_PCIE_VENDOR_SPECIFIC2 |
100210 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
100211 | #define BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
100212 | //BIFPLR6_2_PCIE_VC_ENH_CAP_LIST |
100213 | #define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100214 | #define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100215 | #define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100216 | #define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100217 | #define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100218 | #define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100219 | //BIFPLR6_2_PCIE_PORT_VC_CAP_REG1 |
100220 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
100221 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
100222 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
100223 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
100224 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
100225 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
100226 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
100227 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
100228 | //BIFPLR6_2_PCIE_PORT_VC_CAP_REG2 |
100229 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
100230 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
100231 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
100232 | #define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
100233 | //BIFPLR6_2_PCIE_PORT_VC_CNTL |
100234 | #define BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
100235 | #define BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
100236 | #define BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
100237 | #define BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
100238 | //BIFPLR6_2_PCIE_PORT_VC_STATUS |
100239 | #define BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
100240 | #define BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
100241 | //BIFPLR6_2_PCIE_VC0_RESOURCE_CAP |
100242 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
100243 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
100244 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
100245 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
100246 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
100247 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
100248 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
100249 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
100250 | //BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL |
100251 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
100252 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
100253 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
100254 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
100255 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
100256 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
100257 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
100258 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
100259 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
100260 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
100261 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
100262 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
100263 | //BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS |
100264 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
100265 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
100266 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
100267 | #define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
100268 | //BIFPLR6_2_PCIE_VC1_RESOURCE_CAP |
100269 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
100270 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
100271 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
100272 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
100273 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
100274 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
100275 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
100276 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
100277 | //BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL |
100278 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
100279 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
100280 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
100281 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
100282 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
100283 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
100284 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
100285 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
100286 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
100287 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
100288 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
100289 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
100290 | //BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS |
100291 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
100292 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
100293 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
100294 | #define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
100295 | //BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
100296 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100297 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100298 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100299 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100300 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100301 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100302 | //BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1 |
100303 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
100304 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
100305 | //BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2 |
100306 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
100307 | #define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
100308 | //BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
100309 | #define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100310 | #define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100311 | #define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100312 | #define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100313 | #define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100314 | #define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100315 | //BIFPLR6_2_PCIE_UNCORR_ERR_STATUS |
100316 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
100317 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
100318 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
100319 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
100320 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
100321 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
100322 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
100323 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
100324 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
100325 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
100326 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
100327 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
100328 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
100329 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
100330 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
100331 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
100332 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
100333 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
100334 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
100335 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
100336 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
100337 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
100338 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
100339 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
100340 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
100341 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
100342 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
100343 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
100344 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
100345 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
100346 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
100347 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
100348 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
100349 | #define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
100350 | //BIFPLR6_2_PCIE_UNCORR_ERR_MASK |
100351 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
100352 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
100353 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
100354 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
100355 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
100356 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
100357 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
100358 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
100359 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
100360 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
100361 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
100362 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
100363 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
100364 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
100365 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
100366 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
100367 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
100368 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
100369 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
100370 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
100371 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
100372 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
100373 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
100374 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
100375 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
100376 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
100377 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
100378 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
100379 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
100380 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
100381 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
100382 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
100383 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
100384 | #define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
100385 | //BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY |
100386 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
100387 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
100388 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
100389 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
100390 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
100391 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
100392 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
100393 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
100394 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
100395 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
100396 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
100397 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
100398 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
100399 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
100400 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
100401 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
100402 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
100403 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
100404 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
100405 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
100406 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
100407 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
100408 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
100409 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
100410 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
100411 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
100412 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
100413 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
100414 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
100415 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
100416 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
100417 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
100418 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
100419 | #define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
100420 | //BIFPLR6_2_PCIE_CORR_ERR_STATUS |
100421 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
100422 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
100423 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
100424 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
100425 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
100426 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
100427 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
100428 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
100429 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
100430 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
100431 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
100432 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
100433 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
100434 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
100435 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
100436 | #define BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
100437 | //BIFPLR6_2_PCIE_CORR_ERR_MASK |
100438 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
100439 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
100440 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
100441 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
100442 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
100443 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
100444 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
100445 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
100446 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
100447 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
100448 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
100449 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
100450 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
100451 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
100452 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
100453 | #define BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
100454 | //BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL |
100455 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
100456 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
100457 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
100458 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
100459 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
100460 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
100461 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
100462 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
100463 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
100464 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
100465 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
100466 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
100467 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
100468 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
100469 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
100470 | #define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
100471 | //BIFPLR6_2_PCIE_HDR_LOG0 |
100472 | #define BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
100473 | #define BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
100474 | //BIFPLR6_2_PCIE_HDR_LOG1 |
100475 | #define BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
100476 | #define BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
100477 | //BIFPLR6_2_PCIE_HDR_LOG2 |
100478 | #define BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
100479 | #define BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
100480 | //BIFPLR6_2_PCIE_HDR_LOG3 |
100481 | #define BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
100482 | #define BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
100483 | //BIFPLR6_2_PCIE_ROOT_ERR_CMD |
100484 | #define BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
100485 | #define BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
100486 | #define BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
100487 | #define BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
100488 | #define BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
100489 | #define BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
100490 | //BIFPLR6_2_PCIE_ROOT_ERR_STATUS |
100491 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
100492 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
100493 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
100494 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
100495 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
100496 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
100497 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
100498 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
100499 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
100500 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
100501 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
100502 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
100503 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
100504 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
100505 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
100506 | #define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
100507 | //BIFPLR6_2_PCIE_ERR_SRC_ID |
100508 | #define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
100509 | #define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
100510 | #define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
100511 | #define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
100512 | //BIFPLR6_2_PCIE_TLP_PREFIX_LOG0 |
100513 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
100514 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
100515 | //BIFPLR6_2_PCIE_TLP_PREFIX_LOG1 |
100516 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
100517 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
100518 | //BIFPLR6_2_PCIE_TLP_PREFIX_LOG2 |
100519 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
100520 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
100521 | //BIFPLR6_2_PCIE_TLP_PREFIX_LOG3 |
100522 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
100523 | #define BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
100524 | //BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST |
100525 | #define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100526 | #define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100527 | #define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100528 | #define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100529 | #define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100530 | #define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100531 | //BIFPLR6_2_PCIE_LINK_CNTL3 |
100532 | #define BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
100533 | #define BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
100534 | #define BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
100535 | #define BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
100536 | #define BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
100537 | #define BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
100538 | #define BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
100539 | #define BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
100540 | //BIFPLR6_2_PCIE_LANE_ERROR_STATUS |
100541 | #define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
100542 | #define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
100543 | #define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
100544 | #define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
100545 | //BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL |
100546 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100547 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100548 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100549 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100550 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100551 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100552 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100553 | #define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100554 | //BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL |
100555 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100556 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100557 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100558 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100559 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100560 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100561 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100562 | #define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100563 | //BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL |
100564 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100565 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100566 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100567 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100568 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100569 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100570 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100571 | #define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100572 | //BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL |
100573 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100574 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100575 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100576 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100577 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100578 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100579 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100580 | #define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100581 | //BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL |
100582 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100583 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100584 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100585 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100586 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100587 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100588 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100589 | #define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100590 | //BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL |
100591 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100592 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100593 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100594 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100595 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100596 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100597 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100598 | #define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100599 | //BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL |
100600 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100601 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100602 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100603 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100604 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100605 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100606 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100607 | #define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100608 | //BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL |
100609 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100610 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100611 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100612 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100613 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100614 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100615 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100616 | #define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100617 | //BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL |
100618 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100619 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100620 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100621 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100622 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100623 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100624 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100625 | #define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100626 | //BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL |
100627 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100628 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100629 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100630 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100631 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100632 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100633 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100634 | #define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100635 | //BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL |
100636 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100637 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100638 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100639 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100640 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100641 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100642 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100643 | #define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100644 | //BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL |
100645 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100646 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100647 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100648 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100649 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100650 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100651 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100652 | #define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100653 | //BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL |
100654 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100655 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100656 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100657 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100658 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100659 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100660 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100661 | #define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100662 | //BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL |
100663 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100664 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100665 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100666 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100667 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100668 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100669 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100670 | #define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100671 | //BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL |
100672 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100673 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100674 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100675 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100676 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100677 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100678 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100679 | #define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100680 | //BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL |
100681 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
100682 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
100683 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
100684 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
100685 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
100686 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
100687 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
100688 | #define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
100689 | //BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST |
100690 | #define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100691 | #define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100692 | #define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100693 | #define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100694 | #define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100695 | #define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100696 | //BIFPLR6_2_PCIE_ACS_CAP |
100697 | #define BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
100698 | #define BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
100699 | #define BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
100700 | #define BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
100701 | #define BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
100702 | #define BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
100703 | #define BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
100704 | #define BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
100705 | #define BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
100706 | #define BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
100707 | #define BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
100708 | #define BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
100709 | #define BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
100710 | #define BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
100711 | #define BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
100712 | #define BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
100713 | //BIFPLR6_2_PCIE_ACS_CNTL |
100714 | #define BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
100715 | #define BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
100716 | #define BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
100717 | #define BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
100718 | #define BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
100719 | #define BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
100720 | #define BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
100721 | #define BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
100722 | #define BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
100723 | #define BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
100724 | #define BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
100725 | #define BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
100726 | #define BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
100727 | #define BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
100728 | //BIFPLR6_2_PCIE_MC_ENH_CAP_LIST |
100729 | #define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100730 | #define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100731 | #define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100732 | #define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100733 | #define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100734 | #define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100735 | //BIFPLR6_2_PCIE_MC_CAP |
100736 | #define BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
100737 | #define BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
100738 | #define BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
100739 | #define BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
100740 | //BIFPLR6_2_PCIE_MC_CNTL |
100741 | #define BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
100742 | #define BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
100743 | #define BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
100744 | #define BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
100745 | //BIFPLR6_2_PCIE_MC_ADDR0 |
100746 | #define BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
100747 | #define BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
100748 | #define BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
100749 | #define BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
100750 | //BIFPLR6_2_PCIE_MC_ADDR1 |
100751 | #define BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
100752 | #define BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
100753 | //BIFPLR6_2_PCIE_MC_RCV0 |
100754 | #define BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
100755 | #define BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
100756 | //BIFPLR6_2_PCIE_MC_RCV1 |
100757 | #define BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
100758 | #define BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
100759 | //BIFPLR6_2_PCIE_MC_BLOCK_ALL0 |
100760 | #define BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
100761 | #define BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
100762 | //BIFPLR6_2_PCIE_MC_BLOCK_ALL1 |
100763 | #define BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
100764 | #define BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
100765 | //BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
100766 | #define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
100767 | #define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
100768 | //BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
100769 | #define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
100770 | #define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
100771 | //BIFPLR6_2_PCIE_MC_OVERLAY_BAR0 |
100772 | #define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
100773 | #define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
100774 | #define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
100775 | #define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
100776 | //BIFPLR6_2_PCIE_MC_OVERLAY_BAR1 |
100777 | #define BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
100778 | #define BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
100779 | //BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST |
100780 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
100781 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
100782 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100783 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100784 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100785 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100786 | //BIFPLR6_2_PCIE_L1_PM_SUB_CAP |
100787 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
100788 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
100789 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
100790 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
100791 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
100792 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
100793 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
100794 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
100795 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
100796 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
100797 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
100798 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
100799 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
100800 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
100801 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
100802 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
100803 | //BIFPLR6_2_PCIE_L1_PM_SUB_CNTL |
100804 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
100805 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
100806 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
100807 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
100808 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
100809 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
100810 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
100811 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
100812 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
100813 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
100814 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
100815 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
100816 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
100817 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
100818 | //BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2 |
100819 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
100820 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
100821 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
100822 | #define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
100823 | //BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST |
100824 | #define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
100825 | #define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
100826 | #define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
100827 | #define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
100828 | #define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
100829 | #define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
100830 | //BIFPLR6_2_PCIE_DPC_CAP_LIST |
100831 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 |
100832 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 |
100833 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 |
100834 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 |
100835 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 |
100836 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc |
100837 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL |
100838 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L |
100839 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L |
100840 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L |
100841 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L |
100842 | #define BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L |
100843 | //BIFPLR6_2_PCIE_DPC_CNTL |
100844 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 |
100845 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 |
100846 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 |
100847 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 |
100848 | #define BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 |
100849 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 |
100850 | #define BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 |
100851 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L |
100852 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L |
100853 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L |
100854 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L |
100855 | #define BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L |
100856 | #define BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L |
100857 | #define BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L |
100858 | //BIFPLR6_2_PCIE_DPC_STATUS |
100859 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 |
100860 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 |
100861 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 |
100862 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 |
100863 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 |
100864 | #define BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 |
100865 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L |
100866 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L |
100867 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L |
100868 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L |
100869 | #define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L |
100870 | #define BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L |
100871 | //BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID |
100872 | #define BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 |
100873 | #define BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL |
100874 | //BIFPLR6_2_PCIE_RP_PIO_STATUS |
100875 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 |
100876 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 |
100877 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 |
100878 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 |
100879 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 |
100880 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa |
100881 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 |
100882 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 |
100883 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 |
100884 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L |
100885 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L |
100886 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L |
100887 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L |
100888 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L |
100889 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L |
100890 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L |
100891 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L |
100892 | #define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L |
100893 | //BIFPLR6_2_PCIE_RP_PIO_MASK |
100894 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 |
100895 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 |
100896 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 |
100897 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 |
100898 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 |
100899 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa |
100900 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 |
100901 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 |
100902 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 |
100903 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L |
100904 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L |
100905 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L |
100906 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L |
100907 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L |
100908 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L |
100909 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L |
100910 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L |
100911 | #define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L |
100912 | //BIFPLR6_2_PCIE_RP_PIO_SEVERITY |
100913 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 |
100914 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 |
100915 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 |
100916 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 |
100917 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 |
100918 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa |
100919 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 |
100920 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 |
100921 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 |
100922 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L |
100923 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L |
100924 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L |
100925 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L |
100926 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L |
100927 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L |
100928 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L |
100929 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L |
100930 | #define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L |
100931 | //BIFPLR6_2_PCIE_RP_PIO_SYSERROR |
100932 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 |
100933 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 |
100934 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 |
100935 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 |
100936 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 |
100937 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa |
100938 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 |
100939 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 |
100940 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 |
100941 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L |
100942 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L |
100943 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L |
100944 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L |
100945 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L |
100946 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L |
100947 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L |
100948 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L |
100949 | #define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L |
100950 | //BIFPLR6_2_PCIE_RP_PIO_EXCEPTION |
100951 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 |
100952 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 |
100953 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 |
100954 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 |
100955 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 |
100956 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa |
100957 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 |
100958 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 |
100959 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 |
100960 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L |
100961 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L |
100962 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L |
100963 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L |
100964 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L |
100965 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L |
100966 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L |
100967 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L |
100968 | #define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L |
100969 | //BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0 |
100970 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
100971 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
100972 | //BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1 |
100973 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
100974 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
100975 | //BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2 |
100976 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
100977 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
100978 | //BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3 |
100979 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
100980 | #define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
100981 | //BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG |
100982 | #define BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 |
100983 | #define BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL |
100984 | //BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0 |
100985 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
100986 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
100987 | //BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1 |
100988 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
100989 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
100990 | //BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2 |
100991 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
100992 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
100993 | //BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3 |
100994 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
100995 | #define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
100996 | //BIFPLR6_2_PCIE_ESM_CAP_LIST |
100997 | #define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
100998 | #define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
100999 | #define BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
101000 | #define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
101001 | #define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
101002 | #define BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
101003 | //BIFPLR6_2_PCIE_ESM_HEADER_1 |
101004 | #define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 |
101005 | #define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 |
101006 | #define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 |
101007 | #define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL |
101008 | #define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L |
101009 | #define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L |
101010 | //BIFPLR6_2_PCIE_ESM_HEADER_2 |
101011 | #define BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 |
101012 | #define BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL |
101013 | //BIFPLR6_2_PCIE_ESM_STATUS |
101014 | #define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
101015 | #define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
101016 | #define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
101017 | #define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
101018 | //BIFPLR6_2_PCIE_ESM_CTRL |
101019 | #define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
101020 | #define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
101021 | #define BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
101022 | #define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
101023 | #define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
101024 | #define BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
101025 | //BIFPLR6_2_PCIE_ESM_CAP_1 |
101026 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
101027 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
101028 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
101029 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
101030 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
101031 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
101032 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
101033 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
101034 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
101035 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
101036 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
101037 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
101038 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
101039 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
101040 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
101041 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
101042 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
101043 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
101044 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
101045 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
101046 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
101047 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
101048 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
101049 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
101050 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
101051 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
101052 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
101053 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
101054 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
101055 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
101056 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
101057 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
101058 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
101059 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
101060 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
101061 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
101062 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
101063 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
101064 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
101065 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
101066 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
101067 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
101068 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
101069 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
101070 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
101071 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
101072 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
101073 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
101074 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
101075 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
101076 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
101077 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
101078 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
101079 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
101080 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
101081 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
101082 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
101083 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
101084 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
101085 | #define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
101086 | //BIFPLR6_2_PCIE_ESM_CAP_2 |
101087 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
101088 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
101089 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
101090 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
101091 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
101092 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
101093 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
101094 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
101095 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
101096 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
101097 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
101098 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
101099 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
101100 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
101101 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
101102 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
101103 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
101104 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
101105 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
101106 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
101107 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
101108 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
101109 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
101110 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
101111 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
101112 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
101113 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
101114 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
101115 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
101116 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
101117 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
101118 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
101119 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
101120 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
101121 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
101122 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
101123 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
101124 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
101125 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
101126 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
101127 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
101128 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
101129 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
101130 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
101131 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
101132 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
101133 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
101134 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
101135 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
101136 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
101137 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
101138 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
101139 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
101140 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
101141 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
101142 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
101143 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
101144 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
101145 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
101146 | #define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
101147 | //BIFPLR6_2_PCIE_ESM_CAP_3 |
101148 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
101149 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
101150 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
101151 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
101152 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
101153 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
101154 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
101155 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
101156 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
101157 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
101158 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
101159 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
101160 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
101161 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
101162 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
101163 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
101164 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
101165 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
101166 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
101167 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
101168 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
101169 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
101170 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
101171 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
101172 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
101173 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
101174 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
101175 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
101176 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
101177 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
101178 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
101179 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
101180 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
101181 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
101182 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
101183 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
101184 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
101185 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
101186 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
101187 | #define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
101188 | //BIFPLR6_2_PCIE_ESM_CAP_4 |
101189 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
101190 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
101191 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
101192 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
101193 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
101194 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
101195 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
101196 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
101197 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
101198 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
101199 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
101200 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
101201 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
101202 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
101203 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
101204 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
101205 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
101206 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
101207 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
101208 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
101209 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
101210 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
101211 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
101212 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
101213 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
101214 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
101215 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
101216 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
101217 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
101218 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
101219 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
101220 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
101221 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
101222 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
101223 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
101224 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
101225 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
101226 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
101227 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
101228 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
101229 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
101230 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
101231 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
101232 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
101233 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
101234 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
101235 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
101236 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
101237 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
101238 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
101239 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
101240 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
101241 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
101242 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
101243 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
101244 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
101245 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
101246 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
101247 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
101248 | #define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
101249 | //BIFPLR6_2_PCIE_ESM_CAP_5 |
101250 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
101251 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
101252 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
101253 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
101254 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
101255 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
101256 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
101257 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
101258 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
101259 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
101260 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
101261 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
101262 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
101263 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
101264 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
101265 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
101266 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
101267 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
101268 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
101269 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
101270 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
101271 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
101272 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
101273 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
101274 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
101275 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
101276 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
101277 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
101278 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
101279 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
101280 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
101281 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
101282 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
101283 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
101284 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
101285 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
101286 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
101287 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
101288 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
101289 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
101290 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
101291 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
101292 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
101293 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
101294 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
101295 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
101296 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
101297 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
101298 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
101299 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
101300 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
101301 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
101302 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
101303 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
101304 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
101305 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
101306 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
101307 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
101308 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
101309 | #define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
101310 | //BIFPLR6_2_PCIE_ESM_CAP_6 |
101311 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
101312 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
101313 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
101314 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
101315 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
101316 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
101317 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
101318 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
101319 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
101320 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
101321 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
101322 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
101323 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
101324 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
101325 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
101326 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
101327 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
101328 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
101329 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
101330 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
101331 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
101332 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
101333 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
101334 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
101335 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
101336 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
101337 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
101338 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
101339 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
101340 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
101341 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
101342 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
101343 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
101344 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
101345 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
101346 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
101347 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
101348 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
101349 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
101350 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
101351 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
101352 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
101353 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
101354 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
101355 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
101356 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
101357 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
101358 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
101359 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
101360 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
101361 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
101362 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
101363 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
101364 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
101365 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
101366 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
101367 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
101368 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
101369 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
101370 | #define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
101371 | //BIFPLR6_2_PCIE_ESM_CAP_7 |
101372 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
101373 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
101374 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
101375 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
101376 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
101377 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
101378 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
101379 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
101380 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
101381 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
101382 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
101383 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
101384 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
101385 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
101386 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
101387 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
101388 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
101389 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
101390 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
101391 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
101392 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
101393 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
101394 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
101395 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
101396 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
101397 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
101398 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
101399 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
101400 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
101401 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
101402 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
101403 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
101404 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
101405 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
101406 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
101407 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
101408 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
101409 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
101410 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
101411 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
101412 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
101413 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
101414 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
101415 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
101416 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
101417 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
101418 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
101419 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
101420 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
101421 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
101422 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
101423 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
101424 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
101425 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
101426 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
101427 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
101428 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
101429 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
101430 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
101431 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
101432 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
101433 | #define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
101434 | |
101435 | |
101436 | // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
101437 | //NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID |
101438 | #define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
101439 | #define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 |
101440 | #define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL |
101441 | #define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L |
101442 | //NB_PCIEDUMMY1_2_STATUS_COMMAND |
101443 | #define NB_PCIEDUMMY1_2_STATUS_COMMAND__COMMAND__SHIFT 0x0 |
101444 | #define NB_PCIEDUMMY1_2_STATUS_COMMAND__STATUS__SHIFT 0x10 |
101445 | #define NB_PCIEDUMMY1_2_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL |
101446 | #define NB_PCIEDUMMY1_2_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L |
101447 | //NB_PCIEDUMMY1_2_CLASS_CODE_REVID |
101448 | #define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__REVID__SHIFT 0x0 |
101449 | #define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 |
101450 | #define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__REVID_MASK 0x000000FFL |
101451 | #define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L |
101452 | //NB_PCIEDUMMY1_2_HEADER_TYPE |
101453 | #define NB_PCIEDUMMY1_2_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 |
101454 | #define NB_PCIEDUMMY1_2_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 |
101455 | #define NB_PCIEDUMMY1_2_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L |
101456 | #define NB_PCIEDUMMY1_2_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L |
101457 | //NB_PCIEDUMMY1_2_HEADER_TYPE_W |
101458 | #define NB_PCIEDUMMY1_2_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 |
101459 | #define NB_PCIEDUMMY1_2_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L |
101460 | |
101461 | |
101462 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
101463 | //BIF_CFG_DEV0_RC2_VENDOR_ID |
101464 | #define BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
101465 | #define BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
101466 | //BIF_CFG_DEV0_RC2_DEVICE_ID |
101467 | #define BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
101468 | #define BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
101469 | //BIF_CFG_DEV0_RC2_COMMAND |
101470 | #define BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN__SHIFT 0x0 |
101471 | #define BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN__SHIFT 0x1 |
101472 | #define BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
101473 | #define BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
101474 | #define BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
101475 | #define BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
101476 | #define BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
101477 | #define BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING__SHIFT 0x7 |
101478 | #define BIF_CFG_DEV0_RC2_COMMAND__SERR_EN__SHIFT 0x8 |
101479 | #define BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
101480 | #define BIF_CFG_DEV0_RC2_COMMAND__INT_DIS__SHIFT 0xa |
101481 | #define BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN_MASK 0x0001L |
101482 | #define BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN_MASK 0x0002L |
101483 | #define BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
101484 | #define BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
101485 | #define BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
101486 | #define BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
101487 | #define BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
101488 | #define BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING_MASK 0x0080L |
101489 | #define BIF_CFG_DEV0_RC2_COMMAND__SERR_EN_MASK 0x0100L |
101490 | #define BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
101491 | #define BIF_CFG_DEV0_RC2_COMMAND__INT_DIS_MASK 0x0400L |
101492 | //BIF_CFG_DEV0_RC2_STATUS |
101493 | #define BIF_CFG_DEV0_RC2_STATUS__INT_STATUS__SHIFT 0x3 |
101494 | #define BIF_CFG_DEV0_RC2_STATUS__CAP_LIST__SHIFT 0x4 |
101495 | #define BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN__SHIFT 0x5 |
101496 | #define BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
101497 | #define BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
101498 | #define BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
101499 | #define BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
101500 | #define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
101501 | #define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
101502 | #define BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
101503 | #define BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
101504 | #define BIF_CFG_DEV0_RC2_STATUS__INT_STATUS_MASK 0x0008L |
101505 | #define BIF_CFG_DEV0_RC2_STATUS__CAP_LIST_MASK 0x0010L |
101506 | #define BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN_MASK 0x0020L |
101507 | #define BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
101508 | #define BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
101509 | #define BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
101510 | #define BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
101511 | #define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
101512 | #define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
101513 | #define BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
101514 | #define BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
101515 | //BIF_CFG_DEV0_RC2_REVISION_ID |
101516 | #define BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
101517 | #define BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
101518 | #define BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
101519 | #define BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
101520 | //BIF_CFG_DEV0_RC2_PROG_INTERFACE |
101521 | #define BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
101522 | #define BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
101523 | //BIF_CFG_DEV0_RC2_SUB_CLASS |
101524 | #define BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
101525 | #define BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
101526 | //BIF_CFG_DEV0_RC2_BASE_CLASS |
101527 | #define BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
101528 | #define BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
101529 | //BIF_CFG_DEV0_RC2_CACHE_LINE |
101530 | #define BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
101531 | #define BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
101532 | //BIF_CFG_DEV0_RC2_LATENCY |
101533 | #define BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
101534 | #define BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
101535 | //BIF_CFG_DEV0_RC2_HEADER |
101536 | #define BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE__SHIFT 0x0 |
101537 | #define BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
101538 | #define BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE_MASK 0x7FL |
101539 | #define BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE_MASK 0x80L |
101540 | //BIF_CFG_DEV0_RC2_BIST |
101541 | #define BIF_CFG_DEV0_RC2_BIST__BIST_COMP__SHIFT 0x0 |
101542 | #define BIF_CFG_DEV0_RC2_BIST__BIST_STRT__SHIFT 0x6 |
101543 | #define BIF_CFG_DEV0_RC2_BIST__BIST_CAP__SHIFT 0x7 |
101544 | #define BIF_CFG_DEV0_RC2_BIST__BIST_COMP_MASK 0x0FL |
101545 | #define BIF_CFG_DEV0_RC2_BIST__BIST_STRT_MASK 0x40L |
101546 | #define BIF_CFG_DEV0_RC2_BIST__BIST_CAP_MASK 0x80L |
101547 | //BIF_CFG_DEV0_RC2_BASE_ADDR_1 |
101548 | #define BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
101549 | #define BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
101550 | //BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY |
101551 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
101552 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
101553 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
101554 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
101555 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
101556 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
101557 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
101558 | #define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
101559 | //BIF_CFG_DEV0_RC2_IO_BASE_LIMIT |
101560 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
101561 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
101562 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
101563 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
101564 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
101565 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
101566 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
101567 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
101568 | //BIF_CFG_DEV0_RC2_SECONDARY_STATUS |
101569 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
101570 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
101571 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
101572 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
101573 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
101574 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
101575 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
101576 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
101577 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
101578 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
101579 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
101580 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
101581 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
101582 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
101583 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
101584 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
101585 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
101586 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
101587 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
101588 | #define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
101589 | //BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT |
101590 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
101591 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
101592 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
101593 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
101594 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
101595 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
101596 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
101597 | #define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
101598 | //BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT |
101599 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
101600 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
101601 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
101602 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
101603 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
101604 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
101605 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
101606 | #define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
101607 | //BIF_CFG_DEV0_RC2_PREF_BASE_UPPER |
101608 | #define BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
101609 | #define BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
101610 | //BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER |
101611 | #define BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
101612 | #define BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
101613 | //BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI |
101614 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
101615 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
101616 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
101617 | #define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
101618 | //BIF_CFG_DEV0_RC2_CAP_PTR |
101619 | #define BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
101620 | #define BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
101621 | //BIF_CFG_DEV0_RC2_INTERRUPT_LINE |
101622 | #define BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
101623 | #define BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
101624 | //BIF_CFG_DEV0_RC2_INTERRUPT_PIN |
101625 | #define BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
101626 | #define BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
101627 | //BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL |
101628 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
101629 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
101630 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
101631 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
101632 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
101633 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
101634 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
101635 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
101636 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
101637 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
101638 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
101639 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
101640 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
101641 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
101642 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
101643 | #define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
101644 | //BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL |
101645 | #define BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
101646 | #define BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
101647 | //BIF_CFG_DEV0_RC2_PMI_CAP_LIST |
101648 | #define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
101649 | #define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
101650 | #define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
101651 | #define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
101652 | //BIF_CFG_DEV0_RC2_PMI_CAP |
101653 | #define BIF_CFG_DEV0_RC2_PMI_CAP__VERSION__SHIFT 0x0 |
101654 | #define BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
101655 | #define BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
101656 | #define BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
101657 | #define BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
101658 | #define BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
101659 | #define BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
101660 | #define BIF_CFG_DEV0_RC2_PMI_CAP__VERSION_MASK 0x0007L |
101661 | #define BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
101662 | #define BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
101663 | #define BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
101664 | #define BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
101665 | #define BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
101666 | #define BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
101667 | //BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL |
101668 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
101669 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
101670 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
101671 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
101672 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
101673 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
101674 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
101675 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
101676 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
101677 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
101678 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
101679 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
101680 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
101681 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
101682 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
101683 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
101684 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
101685 | #define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
101686 | //BIF_CFG_DEV0_RC2_PCIE_CAP_LIST |
101687 | #define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
101688 | #define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
101689 | #define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
101690 | #define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
101691 | //BIF_CFG_DEV0_RC2_PCIE_CAP |
101692 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION__SHIFT 0x0 |
101693 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
101694 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
101695 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
101696 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION_MASK 0x000FL |
101697 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
101698 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
101699 | #define BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
101700 | //BIF_CFG_DEV0_RC2_DEVICE_CAP |
101701 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
101702 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
101703 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
101704 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
101705 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
101706 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
101707 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
101708 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
101709 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
101710 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
101711 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
101712 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
101713 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
101714 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
101715 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
101716 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
101717 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
101718 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
101719 | //BIF_CFG_DEV0_RC2_DEVICE_CNTL |
101720 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
101721 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
101722 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
101723 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
101724 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
101725 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
101726 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
101727 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
101728 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
101729 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
101730 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
101731 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
101732 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
101733 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
101734 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
101735 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
101736 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
101737 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
101738 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
101739 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
101740 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
101741 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
101742 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
101743 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
101744 | //BIF_CFG_DEV0_RC2_DEVICE_STATUS |
101745 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
101746 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
101747 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
101748 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
101749 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
101750 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
101751 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
101752 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
101753 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
101754 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
101755 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
101756 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
101757 | //BIF_CFG_DEV0_RC2_LINK_CAP |
101758 | #define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
101759 | #define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
101760 | #define BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
101761 | #define BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
101762 | #define BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
101763 | #define BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
101764 | #define BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
101765 | #define BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
101766 | #define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
101767 | #define BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
101768 | #define BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
101769 | #define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
101770 | #define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
101771 | #define BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
101772 | #define BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
101773 | #define BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
101774 | #define BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
101775 | #define BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
101776 | #define BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
101777 | #define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
101778 | #define BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
101779 | #define BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
101780 | //BIF_CFG_DEV0_RC2_LINK_CNTL |
101781 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
101782 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
101783 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
101784 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
101785 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
101786 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
101787 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
101788 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
101789 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
101790 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
101791 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
101792 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
101793 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
101794 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
101795 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
101796 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
101797 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
101798 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
101799 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
101800 | #define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
101801 | //BIF_CFG_DEV0_RC2_LINK_STATUS |
101802 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
101803 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
101804 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
101805 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
101806 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
101807 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
101808 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
101809 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
101810 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
101811 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
101812 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
101813 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
101814 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
101815 | #define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
101816 | //BIF_CFG_DEV0_RC2_SLOT_CAP |
101817 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
101818 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
101819 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
101820 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
101821 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
101822 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
101823 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
101824 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
101825 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
101826 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
101827 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
101828 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
101829 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
101830 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
101831 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
101832 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
101833 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
101834 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
101835 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
101836 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
101837 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
101838 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
101839 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
101840 | #define BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
101841 | //BIF_CFG_DEV0_RC2_SLOT_CNTL |
101842 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
101843 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
101844 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
101845 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
101846 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
101847 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
101848 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
101849 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
101850 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
101851 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
101852 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
101853 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
101854 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
101855 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
101856 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
101857 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
101858 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
101859 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
101860 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
101861 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
101862 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
101863 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
101864 | //BIF_CFG_DEV0_RC2_SLOT_STATUS |
101865 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
101866 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
101867 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
101868 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
101869 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
101870 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
101871 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
101872 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
101873 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
101874 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
101875 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
101876 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
101877 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
101878 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
101879 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
101880 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
101881 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
101882 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
101883 | //BIF_CFG_DEV0_RC2_ROOT_CNTL |
101884 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
101885 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
101886 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
101887 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
101888 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
101889 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
101890 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
101891 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
101892 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
101893 | #define BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
101894 | //BIF_CFG_DEV0_RC2_ROOT_CAP |
101895 | #define BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
101896 | #define BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
101897 | //BIF_CFG_DEV0_RC2_ROOT_STATUS |
101898 | #define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
101899 | #define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
101900 | #define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
101901 | #define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
101902 | #define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
101903 | #define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
101904 | //BIF_CFG_DEV0_RC2_DEVICE_CAP2 |
101905 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
101906 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
101907 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
101908 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
101909 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
101910 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
101911 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
101912 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
101913 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
101914 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
101915 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
101916 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
101917 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
101918 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
101919 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
101920 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
101921 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
101922 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
101923 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
101924 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
101925 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
101926 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
101927 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
101928 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
101929 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
101930 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
101931 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
101932 | #define BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
101933 | //BIF_CFG_DEV0_RC2_DEVICE_CNTL2 |
101934 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
101935 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
101936 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
101937 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
101938 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
101939 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
101940 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
101941 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
101942 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
101943 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
101944 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
101945 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
101946 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
101947 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
101948 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
101949 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
101950 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
101951 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
101952 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
101953 | #define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
101954 | //BIF_CFG_DEV0_RC2_DEVICE_STATUS2 |
101955 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
101956 | #define BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
101957 | //BIF_CFG_DEV0_RC2_LINK_CAP2 |
101958 | #define BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
101959 | #define BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
101960 | #define BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED__SHIFT 0x9 |
101961 | #define BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
101962 | #define BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
101963 | #define BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
101964 | //BIF_CFG_DEV0_RC2_LINK_CNTL2 |
101965 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
101966 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
101967 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
101968 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
101969 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
101970 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
101971 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
101972 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
101973 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
101974 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
101975 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
101976 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
101977 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
101978 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
101979 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
101980 | #define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
101981 | //BIF_CFG_DEV0_RC2_LINK_STATUS2 |
101982 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
101983 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
101984 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
101985 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
101986 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
101987 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
101988 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
101989 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
101990 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
101991 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
101992 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
101993 | #define BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
101994 | //BIF_CFG_DEV0_RC2_SLOT_CAP2 |
101995 | #define BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
101996 | #define BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
101997 | //BIF_CFG_DEV0_RC2_SLOT_CNTL2 |
101998 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
101999 | #define BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
102000 | //BIF_CFG_DEV0_RC2_SLOT_STATUS2 |
102001 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
102002 | #define BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
102003 | //BIF_CFG_DEV0_RC2_MSI_CAP_LIST |
102004 | #define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
102005 | #define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
102006 | #define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
102007 | #define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
102008 | //BIF_CFG_DEV0_RC2_MSI_MSG_CNTL |
102009 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
102010 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
102011 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
102012 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
102013 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
102014 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
102015 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
102016 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
102017 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
102018 | #define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
102019 | //BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO |
102020 | #define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
102021 | #define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
102022 | //BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI |
102023 | #define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
102024 | #define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
102025 | //BIF_CFG_DEV0_RC2_MSI_MSG_DATA |
102026 | #define BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
102027 | #define BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
102028 | //BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64 |
102029 | #define BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
102030 | #define BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
102031 | //BIF_CFG_DEV0_RC2_SSID_CAP_LIST |
102032 | #define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
102033 | #define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
102034 | #define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
102035 | #define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
102036 | //BIF_CFG_DEV0_RC2_SSID_CAP |
102037 | #define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
102038 | #define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
102039 | #define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
102040 | #define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
102041 | //BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST |
102042 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
102043 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
102044 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
102045 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
102046 | //BIF_CFG_DEV0_RC2_MSI_MAP_CAP |
102047 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN__SHIFT 0x0 |
102048 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
102049 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
102050 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN_MASK 0x0001L |
102051 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
102052 | #define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
102053 | //BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO |
102054 | #define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
102055 | #define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
102056 | //BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI |
102057 | #define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
102058 | #define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
102059 | //BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
102060 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
102061 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
102062 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
102063 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
102064 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
102065 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
102066 | //BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR |
102067 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
102068 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
102069 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
102070 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
102071 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
102072 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
102073 | //BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1 |
102074 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
102075 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
102076 | //BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2 |
102077 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
102078 | #define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
102079 | //BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST |
102080 | #define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
102081 | #define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
102082 | #define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
102083 | #define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
102084 | #define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
102085 | #define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
102086 | //BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1 |
102087 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
102088 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
102089 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
102090 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
102091 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
102092 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
102093 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
102094 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
102095 | //BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2 |
102096 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
102097 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
102098 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
102099 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
102100 | //BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL |
102101 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
102102 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
102103 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
102104 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
102105 | //BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS |
102106 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
102107 | #define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
102108 | //BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP |
102109 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
102110 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
102111 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
102112 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
102113 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
102114 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
102115 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
102116 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
102117 | //BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL |
102118 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
102119 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
102120 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
102121 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
102122 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
102123 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
102124 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
102125 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
102126 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
102127 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
102128 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
102129 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
102130 | //BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS |
102131 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
102132 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
102133 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
102134 | #define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
102135 | //BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP |
102136 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
102137 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
102138 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
102139 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
102140 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
102141 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
102142 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
102143 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
102144 | //BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL |
102145 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
102146 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
102147 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
102148 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
102149 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
102150 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
102151 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
102152 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
102153 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
102154 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
102155 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
102156 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
102157 | //BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS |
102158 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
102159 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
102160 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
102161 | #define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
102162 | //BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
102163 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
102164 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
102165 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
102166 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
102167 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
102168 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
102169 | //BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1 |
102170 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
102171 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
102172 | //BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2 |
102173 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
102174 | #define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
102175 | //BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
102176 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
102177 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
102178 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
102179 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
102180 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
102181 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
102182 | //BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS |
102183 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
102184 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
102185 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
102186 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
102187 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
102188 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
102189 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
102190 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
102191 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
102192 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
102193 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
102194 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
102195 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
102196 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
102197 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
102198 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
102199 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
102200 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
102201 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
102202 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
102203 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
102204 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
102205 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
102206 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
102207 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
102208 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
102209 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
102210 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
102211 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
102212 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
102213 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
102214 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
102215 | //BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK |
102216 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
102217 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
102218 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
102219 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
102220 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
102221 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
102222 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
102223 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
102224 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
102225 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
102226 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
102227 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
102228 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
102229 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
102230 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
102231 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
102232 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
102233 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
102234 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
102235 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
102236 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
102237 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
102238 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
102239 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
102240 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
102241 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
102242 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
102243 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
102244 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
102245 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
102246 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
102247 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
102248 | //BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY |
102249 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
102250 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
102251 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
102252 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
102253 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
102254 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
102255 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
102256 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
102257 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
102258 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
102259 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
102260 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
102261 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
102262 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
102263 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
102264 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
102265 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
102266 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
102267 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
102268 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
102269 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
102270 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
102271 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
102272 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
102273 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
102274 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
102275 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
102276 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
102277 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
102278 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
102279 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
102280 | #define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
102281 | //BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS |
102282 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
102283 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
102284 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
102285 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
102286 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
102287 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
102288 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
102289 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
102290 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
102291 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
102292 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
102293 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
102294 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
102295 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
102296 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
102297 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
102298 | //BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK |
102299 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
102300 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
102301 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
102302 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
102303 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
102304 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
102305 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
102306 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
102307 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
102308 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
102309 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
102310 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
102311 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
102312 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
102313 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
102314 | #define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
102315 | //BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL |
102316 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
102317 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
102318 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
102319 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
102320 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
102321 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
102322 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
102323 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
102324 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
102325 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
102326 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
102327 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
102328 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
102329 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
102330 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
102331 | #define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
102332 | //BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0 |
102333 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
102334 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
102335 | //BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1 |
102336 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
102337 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
102338 | //BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2 |
102339 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
102340 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
102341 | //BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3 |
102342 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
102343 | #define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
102344 | //BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD |
102345 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
102346 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
102347 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
102348 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
102349 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
102350 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
102351 | //BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS |
102352 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
102353 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
102354 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
102355 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
102356 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
102357 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
102358 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
102359 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
102360 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
102361 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
102362 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
102363 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
102364 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
102365 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
102366 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
102367 | #define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
102368 | //BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID |
102369 | #define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
102370 | #define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
102371 | #define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
102372 | #define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
102373 | //BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0 |
102374 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
102375 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
102376 | //BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1 |
102377 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
102378 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
102379 | //BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2 |
102380 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
102381 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
102382 | //BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3 |
102383 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
102384 | #define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
102385 | //BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST |
102386 | #define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
102387 | #define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
102388 | #define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
102389 | #define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
102390 | #define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
102391 | #define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
102392 | //BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3 |
102393 | #define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
102394 | #define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
102395 | #define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
102396 | #define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
102397 | #define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
102398 | #define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
102399 | //BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS |
102400 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
102401 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
102402 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
102403 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
102404 | //BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL |
102405 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102406 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102407 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102408 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102409 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102410 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102411 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102412 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102413 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102414 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102415 | //BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL |
102416 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102417 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102418 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102419 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102420 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102421 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102422 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102423 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102424 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102425 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102426 | //BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL |
102427 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102428 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102429 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102430 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102431 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102432 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102433 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102434 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102435 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102436 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102437 | //BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL |
102438 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102439 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102440 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102441 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102442 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102443 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102444 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102445 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102446 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102447 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102448 | //BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL |
102449 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102450 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102451 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102452 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102453 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102454 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102455 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102456 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102457 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102458 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102459 | //BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL |
102460 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102461 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102462 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102463 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102464 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102465 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102466 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102467 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102468 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102469 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102470 | //BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL |
102471 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102472 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102473 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102474 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102475 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102476 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102477 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102478 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102479 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102480 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102481 | //BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL |
102482 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102483 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102484 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102485 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102486 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102487 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102488 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102489 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102490 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102491 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102492 | //BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL |
102493 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102494 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102495 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102496 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102497 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102498 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102499 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102500 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102501 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102502 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102503 | //BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL |
102504 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102505 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102506 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102507 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102508 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102509 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102510 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102511 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102512 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102513 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102514 | //BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL |
102515 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102516 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102517 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102518 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102519 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102520 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102521 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102522 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102523 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102524 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102525 | //BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL |
102526 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102527 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102528 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102529 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102530 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102531 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102532 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102533 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102534 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102535 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102536 | //BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL |
102537 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102538 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102539 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102540 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102541 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102542 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102543 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102544 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102545 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102546 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102547 | //BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL |
102548 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102549 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102550 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102551 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102552 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102553 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102554 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102555 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102556 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102557 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102558 | //BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL |
102559 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102560 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102561 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102562 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102563 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102564 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102565 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102566 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102567 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102568 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102569 | //BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL |
102570 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
102571 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
102572 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
102573 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
102574 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
102575 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
102576 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
102577 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
102578 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
102579 | #define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
102580 | //BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST |
102581 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
102582 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
102583 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
102584 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
102585 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
102586 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
102587 | //BIF_CFG_DEV0_RC2_PCIE_ACS_CAP |
102588 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
102589 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
102590 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
102591 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
102592 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
102593 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
102594 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
102595 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
102596 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
102597 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
102598 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
102599 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
102600 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
102601 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
102602 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
102603 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
102604 | //BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL |
102605 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
102606 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
102607 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
102608 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
102609 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
102610 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
102611 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
102612 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
102613 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
102614 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
102615 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
102616 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
102617 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
102618 | #define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
102619 | |
102620 | |
102621 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
102622 | //BIF_CFG_DEV1_RC2_VENDOR_ID |
102623 | #define BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
102624 | #define BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
102625 | //BIF_CFG_DEV1_RC2_DEVICE_ID |
102626 | #define BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
102627 | #define BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
102628 | //BIF_CFG_DEV1_RC2_COMMAND |
102629 | #define BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN__SHIFT 0x0 |
102630 | #define BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN__SHIFT 0x1 |
102631 | #define BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
102632 | #define BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
102633 | #define BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
102634 | #define BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
102635 | #define BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
102636 | #define BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING__SHIFT 0x7 |
102637 | #define BIF_CFG_DEV1_RC2_COMMAND__SERR_EN__SHIFT 0x8 |
102638 | #define BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
102639 | #define BIF_CFG_DEV1_RC2_COMMAND__INT_DIS__SHIFT 0xa |
102640 | #define BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN_MASK 0x0001L |
102641 | #define BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN_MASK 0x0002L |
102642 | #define BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
102643 | #define BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
102644 | #define BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
102645 | #define BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
102646 | #define BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
102647 | #define BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING_MASK 0x0080L |
102648 | #define BIF_CFG_DEV1_RC2_COMMAND__SERR_EN_MASK 0x0100L |
102649 | #define BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
102650 | #define BIF_CFG_DEV1_RC2_COMMAND__INT_DIS_MASK 0x0400L |
102651 | //BIF_CFG_DEV1_RC2_STATUS |
102652 | #define BIF_CFG_DEV1_RC2_STATUS__INT_STATUS__SHIFT 0x3 |
102653 | #define BIF_CFG_DEV1_RC2_STATUS__CAP_LIST__SHIFT 0x4 |
102654 | #define BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN__SHIFT 0x5 |
102655 | #define BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
102656 | #define BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
102657 | #define BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
102658 | #define BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
102659 | #define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
102660 | #define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
102661 | #define BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
102662 | #define BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
102663 | #define BIF_CFG_DEV1_RC2_STATUS__INT_STATUS_MASK 0x0008L |
102664 | #define BIF_CFG_DEV1_RC2_STATUS__CAP_LIST_MASK 0x0010L |
102665 | #define BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN_MASK 0x0020L |
102666 | #define BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
102667 | #define BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
102668 | #define BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
102669 | #define BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
102670 | #define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
102671 | #define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
102672 | #define BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
102673 | #define BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
102674 | //BIF_CFG_DEV1_RC2_REVISION_ID |
102675 | #define BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
102676 | #define BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
102677 | #define BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
102678 | #define BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
102679 | //BIF_CFG_DEV1_RC2_PROG_INTERFACE |
102680 | #define BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
102681 | #define BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
102682 | //BIF_CFG_DEV1_RC2_SUB_CLASS |
102683 | #define BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
102684 | #define BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
102685 | //BIF_CFG_DEV1_RC2_BASE_CLASS |
102686 | #define BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
102687 | #define BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
102688 | //BIF_CFG_DEV1_RC2_CACHE_LINE |
102689 | #define BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
102690 | #define BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
102691 | //BIF_CFG_DEV1_RC2_LATENCY |
102692 | #define BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
102693 | #define BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
102694 | //BIF_CFG_DEV1_RC2_HEADER |
102695 | #define BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE__SHIFT 0x0 |
102696 | #define BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
102697 | #define BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE_MASK 0x7FL |
102698 | #define BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE_MASK 0x80L |
102699 | //BIF_CFG_DEV1_RC2_BIST |
102700 | #define BIF_CFG_DEV1_RC2_BIST__BIST_COMP__SHIFT 0x0 |
102701 | #define BIF_CFG_DEV1_RC2_BIST__BIST_STRT__SHIFT 0x6 |
102702 | #define BIF_CFG_DEV1_RC2_BIST__BIST_CAP__SHIFT 0x7 |
102703 | #define BIF_CFG_DEV1_RC2_BIST__BIST_COMP_MASK 0x0FL |
102704 | #define BIF_CFG_DEV1_RC2_BIST__BIST_STRT_MASK 0x40L |
102705 | #define BIF_CFG_DEV1_RC2_BIST__BIST_CAP_MASK 0x80L |
102706 | //BIF_CFG_DEV1_RC2_BASE_ADDR_1 |
102707 | #define BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
102708 | #define BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
102709 | //BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY |
102710 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
102711 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
102712 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
102713 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
102714 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
102715 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
102716 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
102717 | #define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
102718 | //BIF_CFG_DEV1_RC2_IO_BASE_LIMIT |
102719 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
102720 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
102721 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
102722 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
102723 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
102724 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
102725 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
102726 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
102727 | //BIF_CFG_DEV1_RC2_SECONDARY_STATUS |
102728 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
102729 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
102730 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
102731 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
102732 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
102733 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
102734 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
102735 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
102736 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
102737 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
102738 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
102739 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
102740 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
102741 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
102742 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
102743 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
102744 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
102745 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
102746 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
102747 | #define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
102748 | //BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT |
102749 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
102750 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
102751 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
102752 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
102753 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
102754 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
102755 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
102756 | #define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
102757 | //BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT |
102758 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
102759 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
102760 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
102761 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
102762 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
102763 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
102764 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
102765 | #define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
102766 | //BIF_CFG_DEV1_RC2_PREF_BASE_UPPER |
102767 | #define BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
102768 | #define BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
102769 | //BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER |
102770 | #define BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
102771 | #define BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
102772 | //BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI |
102773 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
102774 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
102775 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
102776 | #define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
102777 | //BIF_CFG_DEV1_RC2_CAP_PTR |
102778 | #define BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
102779 | #define BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
102780 | //BIF_CFG_DEV1_RC2_INTERRUPT_LINE |
102781 | #define BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
102782 | #define BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
102783 | //BIF_CFG_DEV1_RC2_INTERRUPT_PIN |
102784 | #define BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
102785 | #define BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
102786 | //BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL |
102787 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
102788 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
102789 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
102790 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
102791 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
102792 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
102793 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
102794 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
102795 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
102796 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
102797 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
102798 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
102799 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
102800 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
102801 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
102802 | #define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
102803 | //BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL |
102804 | #define BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
102805 | #define BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
102806 | //BIF_CFG_DEV1_RC2_PMI_CAP_LIST |
102807 | #define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
102808 | #define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
102809 | #define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
102810 | #define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
102811 | //BIF_CFG_DEV1_RC2_PMI_CAP |
102812 | #define BIF_CFG_DEV1_RC2_PMI_CAP__VERSION__SHIFT 0x0 |
102813 | #define BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
102814 | #define BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
102815 | #define BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
102816 | #define BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
102817 | #define BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
102818 | #define BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
102819 | #define BIF_CFG_DEV1_RC2_PMI_CAP__VERSION_MASK 0x0007L |
102820 | #define BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
102821 | #define BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
102822 | #define BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
102823 | #define BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
102824 | #define BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
102825 | #define BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
102826 | //BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL |
102827 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
102828 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
102829 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
102830 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
102831 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
102832 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
102833 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
102834 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
102835 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
102836 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
102837 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
102838 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
102839 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
102840 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
102841 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
102842 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
102843 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
102844 | #define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
102845 | //BIF_CFG_DEV1_RC2_PCIE_CAP_LIST |
102846 | #define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
102847 | #define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
102848 | #define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
102849 | #define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
102850 | //BIF_CFG_DEV1_RC2_PCIE_CAP |
102851 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION__SHIFT 0x0 |
102852 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
102853 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
102854 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
102855 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION_MASK 0x000FL |
102856 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
102857 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
102858 | #define BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
102859 | //BIF_CFG_DEV1_RC2_DEVICE_CAP |
102860 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
102861 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
102862 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
102863 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
102864 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
102865 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
102866 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
102867 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
102868 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
102869 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
102870 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
102871 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
102872 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
102873 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
102874 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
102875 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
102876 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
102877 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
102878 | //BIF_CFG_DEV1_RC2_DEVICE_CNTL |
102879 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
102880 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
102881 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
102882 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
102883 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
102884 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
102885 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
102886 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
102887 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
102888 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
102889 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
102890 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
102891 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
102892 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
102893 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
102894 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
102895 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
102896 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
102897 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
102898 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
102899 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
102900 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
102901 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
102902 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
102903 | //BIF_CFG_DEV1_RC2_DEVICE_STATUS |
102904 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
102905 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
102906 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
102907 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
102908 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
102909 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
102910 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
102911 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
102912 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
102913 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
102914 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
102915 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
102916 | //BIF_CFG_DEV1_RC2_LINK_CAP |
102917 | #define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
102918 | #define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
102919 | #define BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
102920 | #define BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
102921 | #define BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
102922 | #define BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
102923 | #define BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
102924 | #define BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
102925 | #define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
102926 | #define BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
102927 | #define BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
102928 | #define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
102929 | #define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
102930 | #define BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
102931 | #define BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
102932 | #define BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
102933 | #define BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
102934 | #define BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
102935 | #define BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
102936 | #define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
102937 | #define BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
102938 | #define BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
102939 | //BIF_CFG_DEV1_RC2_LINK_CNTL |
102940 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
102941 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
102942 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
102943 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
102944 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
102945 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
102946 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
102947 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
102948 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
102949 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
102950 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
102951 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
102952 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
102953 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
102954 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
102955 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
102956 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
102957 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
102958 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
102959 | #define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
102960 | //BIF_CFG_DEV1_RC2_LINK_STATUS |
102961 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
102962 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
102963 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
102964 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
102965 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
102966 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
102967 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
102968 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
102969 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
102970 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
102971 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
102972 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
102973 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
102974 | #define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
102975 | //BIF_CFG_DEV1_RC2_SLOT_CAP |
102976 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
102977 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
102978 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
102979 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
102980 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
102981 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
102982 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
102983 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
102984 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
102985 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
102986 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
102987 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
102988 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
102989 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
102990 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
102991 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
102992 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
102993 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
102994 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
102995 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
102996 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
102997 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
102998 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
102999 | #define BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
103000 | //BIF_CFG_DEV1_RC2_SLOT_CNTL |
103001 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
103002 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
103003 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
103004 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
103005 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
103006 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
103007 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
103008 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
103009 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
103010 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
103011 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
103012 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
103013 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
103014 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
103015 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
103016 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
103017 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
103018 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
103019 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
103020 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
103021 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
103022 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
103023 | //BIF_CFG_DEV1_RC2_SLOT_STATUS |
103024 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
103025 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
103026 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
103027 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
103028 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
103029 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
103030 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
103031 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
103032 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
103033 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
103034 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
103035 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
103036 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
103037 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
103038 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
103039 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
103040 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
103041 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
103042 | //BIF_CFG_DEV1_RC2_ROOT_CNTL |
103043 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
103044 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
103045 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
103046 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
103047 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
103048 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
103049 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
103050 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
103051 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
103052 | #define BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
103053 | //BIF_CFG_DEV1_RC2_ROOT_CAP |
103054 | #define BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
103055 | #define BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
103056 | //BIF_CFG_DEV1_RC2_ROOT_STATUS |
103057 | #define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
103058 | #define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
103059 | #define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
103060 | #define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
103061 | #define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
103062 | #define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
103063 | //BIF_CFG_DEV1_RC2_DEVICE_CAP2 |
103064 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
103065 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
103066 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
103067 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
103068 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
103069 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
103070 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
103071 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
103072 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
103073 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
103074 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
103075 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
103076 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
103077 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
103078 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
103079 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
103080 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
103081 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
103082 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
103083 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
103084 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
103085 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
103086 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
103087 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
103088 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
103089 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
103090 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
103091 | #define BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
103092 | //BIF_CFG_DEV1_RC2_DEVICE_CNTL2 |
103093 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
103094 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
103095 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
103096 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
103097 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
103098 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
103099 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
103100 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
103101 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
103102 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
103103 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
103104 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
103105 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
103106 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
103107 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
103108 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
103109 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
103110 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
103111 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
103112 | #define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
103113 | //BIF_CFG_DEV1_RC2_DEVICE_STATUS2 |
103114 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
103115 | #define BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
103116 | //BIF_CFG_DEV1_RC2_LINK_CAP2 |
103117 | #define BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
103118 | #define BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
103119 | #define BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED__SHIFT 0x9 |
103120 | #define BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
103121 | #define BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
103122 | #define BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
103123 | //BIF_CFG_DEV1_RC2_LINK_CNTL2 |
103124 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
103125 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
103126 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
103127 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
103128 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
103129 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
103130 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
103131 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
103132 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
103133 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
103134 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
103135 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
103136 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
103137 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
103138 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
103139 | #define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
103140 | //BIF_CFG_DEV1_RC2_LINK_STATUS2 |
103141 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
103142 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
103143 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
103144 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
103145 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
103146 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
103147 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
103148 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
103149 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
103150 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
103151 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
103152 | #define BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
103153 | //BIF_CFG_DEV1_RC2_SLOT_CAP2 |
103154 | #define BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
103155 | #define BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
103156 | //BIF_CFG_DEV1_RC2_SLOT_CNTL2 |
103157 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
103158 | #define BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
103159 | //BIF_CFG_DEV1_RC2_SLOT_STATUS2 |
103160 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
103161 | #define BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
103162 | //BIF_CFG_DEV1_RC2_MSI_CAP_LIST |
103163 | #define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
103164 | #define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
103165 | #define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
103166 | #define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
103167 | //BIF_CFG_DEV1_RC2_MSI_MSG_CNTL |
103168 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
103169 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
103170 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
103171 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
103172 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
103173 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
103174 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
103175 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
103176 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
103177 | #define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
103178 | //BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO |
103179 | #define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
103180 | #define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
103181 | //BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI |
103182 | #define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
103183 | #define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
103184 | //BIF_CFG_DEV1_RC2_MSI_MSG_DATA |
103185 | #define BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
103186 | #define BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
103187 | //BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64 |
103188 | #define BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
103189 | #define BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
103190 | //BIF_CFG_DEV1_RC2_SSID_CAP_LIST |
103191 | #define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
103192 | #define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
103193 | #define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
103194 | #define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
103195 | //BIF_CFG_DEV1_RC2_SSID_CAP |
103196 | #define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
103197 | #define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
103198 | #define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
103199 | #define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
103200 | //BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST |
103201 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
103202 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
103203 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
103204 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
103205 | //BIF_CFG_DEV1_RC2_MSI_MAP_CAP |
103206 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN__SHIFT 0x0 |
103207 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
103208 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
103209 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN_MASK 0x0001L |
103210 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD_MASK 0x0002L |
103211 | #define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
103212 | //BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO |
103213 | #define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
103214 | #define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
103215 | //BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI |
103216 | #define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
103217 | #define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
103218 | //BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
103219 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
103220 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
103221 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
103222 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
103223 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
103224 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
103225 | //BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR |
103226 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
103227 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
103228 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
103229 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
103230 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
103231 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
103232 | //BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1 |
103233 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
103234 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
103235 | //BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2 |
103236 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
103237 | #define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
103238 | //BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST |
103239 | #define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
103240 | #define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
103241 | #define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
103242 | #define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
103243 | #define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
103244 | #define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
103245 | //BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1 |
103246 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
103247 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
103248 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
103249 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
103250 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
103251 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
103252 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
103253 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
103254 | //BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2 |
103255 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
103256 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
103257 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
103258 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
103259 | //BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL |
103260 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
103261 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
103262 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
103263 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
103264 | //BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS |
103265 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
103266 | #define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
103267 | //BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP |
103268 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
103269 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
103270 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
103271 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
103272 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
103273 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
103274 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
103275 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
103276 | //BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL |
103277 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
103278 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
103279 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
103280 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
103281 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
103282 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
103283 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
103284 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
103285 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
103286 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
103287 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
103288 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
103289 | //BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS |
103290 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
103291 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
103292 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
103293 | #define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
103294 | //BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP |
103295 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
103296 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
103297 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
103298 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
103299 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
103300 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
103301 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
103302 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
103303 | //BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL |
103304 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
103305 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
103306 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
103307 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
103308 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
103309 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
103310 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
103311 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
103312 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
103313 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
103314 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
103315 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
103316 | //BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS |
103317 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
103318 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
103319 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
103320 | #define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
103321 | //BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
103322 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
103323 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
103324 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
103325 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
103326 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
103327 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
103328 | //BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1 |
103329 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
103330 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
103331 | //BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2 |
103332 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
103333 | #define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
103334 | //BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
103335 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
103336 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
103337 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
103338 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
103339 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
103340 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
103341 | //BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS |
103342 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
103343 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
103344 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
103345 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
103346 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
103347 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
103348 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
103349 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
103350 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
103351 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
103352 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
103353 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
103354 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
103355 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
103356 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
103357 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
103358 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
103359 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
103360 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
103361 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
103362 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
103363 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
103364 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
103365 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
103366 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
103367 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
103368 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
103369 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
103370 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
103371 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
103372 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
103373 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
103374 | //BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK |
103375 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
103376 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
103377 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
103378 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
103379 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
103380 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
103381 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
103382 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
103383 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
103384 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
103385 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
103386 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
103387 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
103388 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
103389 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
103390 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
103391 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
103392 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
103393 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
103394 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
103395 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
103396 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
103397 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
103398 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
103399 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
103400 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
103401 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
103402 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
103403 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
103404 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
103405 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
103406 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
103407 | //BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY |
103408 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
103409 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
103410 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
103411 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
103412 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
103413 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
103414 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
103415 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
103416 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
103417 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
103418 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
103419 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
103420 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
103421 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
103422 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
103423 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
103424 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
103425 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
103426 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
103427 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
103428 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
103429 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
103430 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
103431 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
103432 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
103433 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
103434 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
103435 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
103436 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
103437 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
103438 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
103439 | #define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
103440 | //BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS |
103441 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
103442 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
103443 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
103444 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
103445 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
103446 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
103447 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
103448 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
103449 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
103450 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
103451 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
103452 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
103453 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
103454 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
103455 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
103456 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
103457 | //BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK |
103458 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
103459 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
103460 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
103461 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
103462 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
103463 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
103464 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
103465 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
103466 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
103467 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
103468 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
103469 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
103470 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
103471 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
103472 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
103473 | #define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
103474 | //BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL |
103475 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
103476 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
103477 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
103478 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
103479 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
103480 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
103481 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
103482 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
103483 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
103484 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
103485 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
103486 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
103487 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
103488 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
103489 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
103490 | #define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
103491 | //BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0 |
103492 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
103493 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
103494 | //BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1 |
103495 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
103496 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
103497 | //BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2 |
103498 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
103499 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
103500 | //BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3 |
103501 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
103502 | #define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
103503 | //BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD |
103504 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
103505 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
103506 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
103507 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
103508 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
103509 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
103510 | //BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS |
103511 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
103512 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
103513 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
103514 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
103515 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
103516 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
103517 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
103518 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
103519 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
103520 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
103521 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
103522 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
103523 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
103524 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
103525 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
103526 | #define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
103527 | //BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID |
103528 | #define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
103529 | #define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
103530 | #define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
103531 | #define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
103532 | //BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0 |
103533 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
103534 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
103535 | //BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1 |
103536 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
103537 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
103538 | //BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2 |
103539 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
103540 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
103541 | //BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3 |
103542 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
103543 | #define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
103544 | //BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST |
103545 | #define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
103546 | #define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
103547 | #define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
103548 | #define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
103549 | #define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
103550 | #define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
103551 | //BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3 |
103552 | #define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
103553 | #define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
103554 | #define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
103555 | #define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
103556 | #define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
103557 | #define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
103558 | //BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS |
103559 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
103560 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
103561 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
103562 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
103563 | //BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL |
103564 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103565 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103566 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103567 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103568 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103569 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103570 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103571 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103572 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103573 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103574 | //BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL |
103575 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103576 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103577 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103578 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103579 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103580 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103581 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103582 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103583 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103584 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103585 | //BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL |
103586 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103587 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103588 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103589 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103590 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103591 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103592 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103593 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103594 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103595 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103596 | //BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL |
103597 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103598 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103599 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103600 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103601 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103602 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103603 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103604 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103605 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103606 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103607 | //BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL |
103608 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103609 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103610 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103611 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103612 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103613 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103614 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103615 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103616 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103617 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103618 | //BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL |
103619 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103620 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103621 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103622 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103623 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103624 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103625 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103626 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103627 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103628 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103629 | //BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL |
103630 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103631 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103632 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103633 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103634 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103635 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103636 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103637 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103638 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103639 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103640 | //BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL |
103641 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103642 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103643 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103644 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103645 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103646 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103647 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103648 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103649 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103650 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103651 | //BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL |
103652 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103653 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103654 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103655 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103656 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103657 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103658 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103659 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103660 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103661 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103662 | //BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL |
103663 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103664 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103665 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103666 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103667 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103668 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103669 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103670 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103671 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103672 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103673 | //BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL |
103674 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103675 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103676 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103677 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103678 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103679 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103680 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103681 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103682 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103683 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103684 | //BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL |
103685 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103686 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103687 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103688 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103689 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103690 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103691 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103692 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103693 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103694 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103695 | //BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL |
103696 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103697 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103698 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103699 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103700 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103701 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103702 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103703 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103704 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103705 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103706 | //BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL |
103707 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103708 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103709 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103710 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103711 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103712 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103713 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103714 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103715 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103716 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103717 | //BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL |
103718 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103719 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103720 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103721 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103722 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103723 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103724 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103725 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103726 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103727 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103728 | //BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL |
103729 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
103730 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
103731 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
103732 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
103733 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
103734 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
103735 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
103736 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
103737 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
103738 | #define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
103739 | //BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST |
103740 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
103741 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
103742 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
103743 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
103744 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
103745 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
103746 | //BIF_CFG_DEV1_RC2_PCIE_ACS_CAP |
103747 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
103748 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
103749 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
103750 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
103751 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
103752 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
103753 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
103754 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
103755 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
103756 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
103757 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
103758 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
103759 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
103760 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
103761 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
103762 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
103763 | //BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL |
103764 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
103765 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
103766 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
103767 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
103768 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
103769 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
103770 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
103771 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
103772 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
103773 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
103774 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
103775 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
103776 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
103777 | #define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
103778 | |
103779 | |
103780 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
103781 | //BIF_CFG_DEV0_EPF0_3_VENDOR_ID |
103782 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
103783 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
103784 | //BIF_CFG_DEV0_EPF0_3_DEVICE_ID |
103785 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
103786 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
103787 | //BIF_CFG_DEV0_EPF0_3_COMMAND |
103788 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
103789 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
103790 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
103791 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
103792 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
103793 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
103794 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
103795 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING__SHIFT 0x7 |
103796 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN__SHIFT 0x8 |
103797 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
103798 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS__SHIFT 0xa |
103799 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
103800 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
103801 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
103802 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
103803 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
103804 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
103805 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
103806 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING_MASK 0x0080L |
103807 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN_MASK 0x0100L |
103808 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN_MASK 0x0200L |
103809 | #define BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS_MASK 0x0400L |
103810 | //BIF_CFG_DEV0_EPF0_3_STATUS |
103811 | #define BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS__SHIFT 0x3 |
103812 | #define BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST__SHIFT 0x4 |
103813 | #define BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN__SHIFT 0x5 |
103814 | #define BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
103815 | #define BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
103816 | #define BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
103817 | #define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
103818 | #define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
103819 | #define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
103820 | #define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
103821 | #define BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
103822 | #define BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS_MASK 0x0008L |
103823 | #define BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST_MASK 0x0010L |
103824 | #define BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN_MASK 0x0020L |
103825 | #define BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
103826 | #define BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
103827 | #define BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING_MASK 0x0600L |
103828 | #define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
103829 | #define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
103830 | #define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
103831 | #define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
103832 | #define BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
103833 | //BIF_CFG_DEV0_EPF0_3_REVISION_ID |
103834 | #define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
103835 | #define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
103836 | #define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
103837 | #define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
103838 | //BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE |
103839 | #define BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
103840 | #define BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
103841 | //BIF_CFG_DEV0_EPF0_3_SUB_CLASS |
103842 | #define BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
103843 | #define BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
103844 | //BIF_CFG_DEV0_EPF0_3_BASE_CLASS |
103845 | #define BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
103846 | #define BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
103847 | //BIF_CFG_DEV0_EPF0_3_CACHE_LINE |
103848 | #define BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
103849 | #define BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
103850 | //BIF_CFG_DEV0_EPF0_3_LATENCY |
103851 | #define BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
103852 | #define BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER_MASK 0xFFL |
103853 | //BIF_CFG_DEV0_EPF0_3_HEADER |
103854 | #define BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE__SHIFT 0x0 |
103855 | #define BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE__SHIFT 0x7 |
103856 | #define BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE_MASK 0x7FL |
103857 | #define BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE_MASK 0x80L |
103858 | //BIF_CFG_DEV0_EPF0_3_BIST |
103859 | #define BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP__SHIFT 0x0 |
103860 | #define BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT__SHIFT 0x6 |
103861 | #define BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP__SHIFT 0x7 |
103862 | #define BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP_MASK 0x0FL |
103863 | #define BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT_MASK 0x40L |
103864 | #define BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP_MASK 0x80L |
103865 | //BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1 |
103866 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
103867 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
103868 | //BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2 |
103869 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
103870 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
103871 | //BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3 |
103872 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
103873 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
103874 | //BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4 |
103875 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
103876 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
103877 | //BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5 |
103878 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
103879 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
103880 | //BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6 |
103881 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
103882 | #define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
103883 | //BIF_CFG_DEV0_EPF0_3_ADAPTER_ID |
103884 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
103885 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
103886 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
103887 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
103888 | //BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR |
103889 | #define BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
103890 | #define BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
103891 | //BIF_CFG_DEV0_EPF0_3_CAP_PTR |
103892 | #define BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR__SHIFT 0x0 |
103893 | #define BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
103894 | //BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE |
103895 | #define BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
103896 | #define BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
103897 | //BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN |
103898 | #define BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
103899 | #define BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
103900 | //BIF_CFG_DEV0_EPF0_3_MIN_GRANT |
103901 | #define BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
103902 | #define BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT_MASK 0xFFL |
103903 | //BIF_CFG_DEV0_EPF0_3_MAX_LATENCY |
103904 | #define BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
103905 | #define BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
103906 | //BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST |
103907 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
103908 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
103909 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
103910 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
103911 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
103912 | #define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
103913 | //BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W |
103914 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
103915 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
103916 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
103917 | #define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
103918 | //BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST |
103919 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
103920 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
103921 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
103922 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
103923 | //BIF_CFG_DEV0_EPF0_3_PMI_CAP |
103924 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION__SHIFT 0x0 |
103925 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
103926 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
103927 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
103928 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
103929 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
103930 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
103931 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION_MASK 0x0007L |
103932 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK_MASK 0x0008L |
103933 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
103934 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
103935 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
103936 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
103937 | #define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
103938 | //BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL |
103939 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
103940 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
103941 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
103942 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
103943 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
103944 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
103945 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
103946 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
103947 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
103948 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
103949 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
103950 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
103951 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
103952 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
103953 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
103954 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
103955 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
103956 | #define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
103957 | //BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST |
103958 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
103959 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
103960 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
103961 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
103962 | //BIF_CFG_DEV0_EPF0_3_PCIE_CAP |
103963 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION__SHIFT 0x0 |
103964 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
103965 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
103966 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
103967 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION_MASK 0x000FL |
103968 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
103969 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
103970 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
103971 | //BIF_CFG_DEV0_EPF0_3_DEVICE_CAP |
103972 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
103973 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
103974 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
103975 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
103976 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
103977 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
103978 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
103979 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
103980 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
103981 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
103982 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
103983 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
103984 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
103985 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
103986 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
103987 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
103988 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
103989 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
103990 | //BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL |
103991 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
103992 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
103993 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
103994 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
103995 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
103996 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
103997 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
103998 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
103999 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
104000 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
104001 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
104002 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
104003 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
104004 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
104005 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
104006 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
104007 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
104008 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
104009 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
104010 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
104011 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
104012 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
104013 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
104014 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
104015 | //BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS |
104016 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
104017 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
104018 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
104019 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
104020 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
104021 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
104022 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
104023 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
104024 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
104025 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
104026 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
104027 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
104028 | //BIF_CFG_DEV0_EPF0_3_LINK_CAP |
104029 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
104030 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
104031 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
104032 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
104033 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
104034 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
104035 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
104036 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
104037 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
104038 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
104039 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
104040 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
104041 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
104042 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
104043 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
104044 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
104045 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
104046 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
104047 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
104048 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
104049 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
104050 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
104051 | //BIF_CFG_DEV0_EPF0_3_LINK_CNTL |
104052 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
104053 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
104054 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
104055 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
104056 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
104057 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
104058 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
104059 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
104060 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
104061 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
104062 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
104063 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
104064 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS_MASK 0x0010L |
104065 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
104066 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
104067 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
104068 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
104069 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
104070 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
104071 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
104072 | //BIF_CFG_DEV0_EPF0_3_LINK_STATUS |
104073 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
104074 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
104075 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
104076 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
104077 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
104078 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
104079 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
104080 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
104081 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
104082 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
104083 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
104084 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
104085 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
104086 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
104087 | //BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2 |
104088 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
104089 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
104090 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
104091 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
104092 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
104093 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
104094 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
104095 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
104096 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
104097 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
104098 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
104099 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
104100 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
104101 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
104102 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
104103 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
104104 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
104105 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
104106 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
104107 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
104108 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
104109 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
104110 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
104111 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
104112 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
104113 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
104114 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
104115 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
104116 | //BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2 |
104117 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
104118 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
104119 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
104120 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
104121 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
104122 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
104123 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
104124 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
104125 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
104126 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
104127 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
104128 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
104129 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
104130 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
104131 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
104132 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
104133 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
104134 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
104135 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
104136 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
104137 | //BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2 |
104138 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
104139 | #define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
104140 | //BIF_CFG_DEV0_EPF0_3_LINK_CAP2 |
104141 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
104142 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
104143 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED__SHIFT 0x9 |
104144 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
104145 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
104146 | #define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
104147 | //BIF_CFG_DEV0_EPF0_3_LINK_CNTL2 |
104148 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
104149 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
104150 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
104151 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
104152 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
104153 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
104154 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
104155 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
104156 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
104157 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
104158 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
104159 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
104160 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
104161 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
104162 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
104163 | #define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
104164 | //BIF_CFG_DEV0_EPF0_3_LINK_STATUS2 |
104165 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
104166 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
104167 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
104168 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
104169 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
104170 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
104171 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
104172 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
104173 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
104174 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
104175 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
104176 | #define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
104177 | //BIF_CFG_DEV0_EPF0_3_SLOT_CAP2 |
104178 | #define BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED__SHIFT 0x0 |
104179 | #define BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
104180 | //BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2 |
104181 | #define BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
104182 | #define BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
104183 | //BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2 |
104184 | #define BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
104185 | #define BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
104186 | //BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST |
104187 | #define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
104188 | #define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
104189 | #define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
104190 | #define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
104191 | //BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL |
104192 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
104193 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
104194 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
104195 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
104196 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
104197 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
104198 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
104199 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
104200 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
104201 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
104202 | //BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO |
104203 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
104204 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
104205 | //BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI |
104206 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
104207 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
104208 | //BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA |
104209 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
104210 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
104211 | //BIF_CFG_DEV0_EPF0_3_MSI_MASK |
104212 | #define BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK__SHIFT 0x0 |
104213 | #define BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
104214 | //BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64 |
104215 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
104216 | #define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
104217 | //BIF_CFG_DEV0_EPF0_3_MSI_MASK_64 |
104218 | #define BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
104219 | #define BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
104220 | //BIF_CFG_DEV0_EPF0_3_MSI_PENDING |
104221 | #define BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
104222 | #define BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
104223 | //BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64 |
104224 | #define BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
104225 | #define BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
104226 | //BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST |
104227 | #define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
104228 | #define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
104229 | #define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
104230 | #define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
104231 | //BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL |
104232 | #define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
104233 | #define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
104234 | #define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
104235 | #define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
104236 | #define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
104237 | #define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
104238 | //BIF_CFG_DEV0_EPF0_3_MSIX_TABLE |
104239 | #define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
104240 | #define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
104241 | #define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
104242 | #define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
104243 | //BIF_CFG_DEV0_EPF0_3_MSIX_PBA |
104244 | #define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
104245 | #define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
104246 | #define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
104247 | #define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
104248 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
104249 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104250 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104251 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104252 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104253 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104254 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104255 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR |
104256 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
104257 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
104258 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
104259 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
104260 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
104261 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
104262 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1 |
104263 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
104264 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
104265 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2 |
104266 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
104267 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
104268 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST |
104269 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104270 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104271 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104272 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104273 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104274 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104275 | //BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1 |
104276 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
104277 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
104278 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
104279 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
104280 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
104281 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
104282 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
104283 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
104284 | //BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2 |
104285 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
104286 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
104287 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
104288 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
104289 | //BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL |
104290 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
104291 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
104292 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
104293 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
104294 | //BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS |
104295 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
104296 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
104297 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP |
104298 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
104299 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
104300 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
104301 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
104302 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
104303 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
104304 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
104305 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
104306 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL |
104307 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
104308 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
104309 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
104310 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
104311 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
104312 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
104313 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
104314 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
104315 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
104316 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
104317 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
104318 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
104319 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS |
104320 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
104321 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
104322 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
104323 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
104324 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP |
104325 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
104326 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
104327 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
104328 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
104329 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
104330 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
104331 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
104332 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
104333 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL |
104334 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
104335 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
104336 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
104337 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
104338 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
104339 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
104340 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
104341 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
104342 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
104343 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
104344 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
104345 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
104346 | //BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS |
104347 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
104348 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
104349 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
104350 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
104351 | //BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
104352 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104353 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104354 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104355 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104356 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104357 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104358 | //BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1 |
104359 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
104360 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
104361 | //BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2 |
104362 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
104363 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
104364 | //BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
104365 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104366 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104367 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104368 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104369 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104370 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104371 | //BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS |
104372 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
104373 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
104374 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
104375 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
104376 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
104377 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
104378 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
104379 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
104380 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
104381 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
104382 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
104383 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
104384 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
104385 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
104386 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
104387 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
104388 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
104389 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
104390 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
104391 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
104392 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
104393 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
104394 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
104395 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
104396 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
104397 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
104398 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
104399 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
104400 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
104401 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
104402 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
104403 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
104404 | //BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK |
104405 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
104406 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
104407 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
104408 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
104409 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
104410 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
104411 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
104412 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
104413 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
104414 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
104415 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
104416 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
104417 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
104418 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
104419 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
104420 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
104421 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
104422 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
104423 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
104424 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
104425 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
104426 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
104427 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
104428 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
104429 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
104430 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
104431 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
104432 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
104433 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
104434 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
104435 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
104436 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
104437 | //BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY |
104438 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
104439 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
104440 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
104441 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
104442 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
104443 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
104444 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
104445 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
104446 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
104447 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
104448 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
104449 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
104450 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
104451 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
104452 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
104453 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
104454 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
104455 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
104456 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
104457 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
104458 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
104459 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
104460 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
104461 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
104462 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
104463 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
104464 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
104465 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
104466 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
104467 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
104468 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
104469 | #define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
104470 | //BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS |
104471 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
104472 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
104473 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
104474 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
104475 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
104476 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
104477 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
104478 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
104479 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
104480 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
104481 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
104482 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
104483 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
104484 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
104485 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
104486 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
104487 | //BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK |
104488 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
104489 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
104490 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
104491 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
104492 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
104493 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
104494 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
104495 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
104496 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
104497 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
104498 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
104499 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
104500 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
104501 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
104502 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
104503 | #define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
104504 | //BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL |
104505 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
104506 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
104507 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
104508 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
104509 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
104510 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
104511 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
104512 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
104513 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
104514 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
104515 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
104516 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
104517 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
104518 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
104519 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
104520 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
104521 | //BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0 |
104522 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
104523 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
104524 | //BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1 |
104525 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
104526 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
104527 | //BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2 |
104528 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
104529 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
104530 | //BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3 |
104531 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
104532 | #define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
104533 | //BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0 |
104534 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
104535 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
104536 | //BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1 |
104537 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
104538 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
104539 | //BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2 |
104540 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
104541 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
104542 | //BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3 |
104543 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
104544 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
104545 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST |
104546 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104547 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104548 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104549 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104550 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104551 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104552 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP |
104553 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
104554 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
104555 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL |
104556 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
104557 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
104558 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
104559 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
104560 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
104561 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
104562 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP |
104563 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
104564 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
104565 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL |
104566 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
104567 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
104568 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
104569 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
104570 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
104571 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
104572 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP |
104573 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
104574 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
104575 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL |
104576 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
104577 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
104578 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
104579 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
104580 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
104581 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
104582 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP |
104583 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
104584 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
104585 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL |
104586 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
104587 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
104588 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
104589 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
104590 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
104591 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
104592 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP |
104593 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
104594 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
104595 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL |
104596 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
104597 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
104598 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
104599 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
104600 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
104601 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
104602 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP |
104603 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
104604 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
104605 | //BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL |
104606 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
104607 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
104608 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
104609 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
104610 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
104611 | #define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
104612 | //BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST |
104613 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104614 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104615 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104616 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104617 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104618 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104619 | //BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT |
104620 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
104621 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
104622 | //BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA |
104623 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
104624 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
104625 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
104626 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
104627 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
104628 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
104629 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
104630 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
104631 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
104632 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
104633 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
104634 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
104635 | //BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP |
104636 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
104637 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
104638 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST |
104639 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104640 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104641 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104642 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104643 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104644 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104645 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP |
104646 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
104647 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
104648 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
104649 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
104650 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
104651 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
104652 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
104653 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
104654 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
104655 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
104656 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR |
104657 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
104658 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
104659 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS |
104660 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
104661 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
104662 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
104663 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
104664 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL |
104665 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
104666 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
104667 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
104668 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104669 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104670 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
104671 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104672 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104673 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
104674 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104675 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104676 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
104677 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104678 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104679 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
104680 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104681 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104682 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
104683 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104684 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104685 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
104686 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104687 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104688 | //BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
104689 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
104690 | #define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
104691 | //BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST |
104692 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104693 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104694 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104695 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104696 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104697 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104698 | //BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3 |
104699 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
104700 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
104701 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
104702 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
104703 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
104704 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
104705 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS |
104706 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
104707 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
104708 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
104709 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
104710 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL |
104711 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104712 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104713 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104714 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104715 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104716 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104717 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104718 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104719 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104720 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104721 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL |
104722 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104723 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104724 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104725 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104726 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104727 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104728 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104729 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104730 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104731 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104732 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL |
104733 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104734 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104735 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104736 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104737 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104738 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104739 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104740 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104741 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104742 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104743 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL |
104744 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104745 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104746 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104747 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104748 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104749 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104750 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104751 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104752 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104753 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104754 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL |
104755 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104756 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104757 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104758 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104759 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104760 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104761 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104762 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104763 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104764 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104765 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL |
104766 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104767 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104768 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104769 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104770 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104771 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104772 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104773 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104774 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104775 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104776 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL |
104777 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104778 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104779 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104780 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104781 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104782 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104783 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104784 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104785 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104786 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104787 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL |
104788 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104789 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104790 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104791 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104792 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104793 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104794 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104795 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104796 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104797 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104798 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL |
104799 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104800 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104801 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104802 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104803 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104804 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104805 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104806 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104807 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104808 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104809 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL |
104810 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104811 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104812 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104813 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104814 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104815 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104816 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104817 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104818 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104819 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104820 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL |
104821 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104822 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104823 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104824 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104825 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104826 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104827 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104828 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104829 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104830 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104831 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL |
104832 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104833 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104834 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104835 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104836 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104837 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104838 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104839 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104840 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104841 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104842 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL |
104843 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104844 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104845 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104846 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104847 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104848 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104849 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104850 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104851 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104852 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104853 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL |
104854 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104855 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104856 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104857 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104858 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104859 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104860 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104861 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104862 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104863 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104864 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL |
104865 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104866 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104867 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104868 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104869 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104870 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104871 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104872 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104873 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104874 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104875 | //BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL |
104876 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
104877 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
104878 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
104879 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
104880 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
104881 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
104882 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
104883 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
104884 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
104885 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
104886 | //BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST |
104887 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104888 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104889 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104890 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104891 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104892 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104893 | //BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP |
104894 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
104895 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
104896 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
104897 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
104898 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
104899 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
104900 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
104901 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
104902 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
104903 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
104904 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
104905 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
104906 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
104907 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
104908 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
104909 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
104910 | //BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL |
104911 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
104912 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
104913 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
104914 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
104915 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
104916 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
104917 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
104918 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
104919 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
104920 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
104921 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
104922 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
104923 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
104924 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
104925 | //BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST |
104926 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104927 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104928 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104929 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104930 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104931 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104932 | //BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP |
104933 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
104934 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
104935 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
104936 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
104937 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
104938 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
104939 | //BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL |
104940 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
104941 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
104942 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU_MASK 0x001FL |
104943 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
104944 | //BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST |
104945 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104946 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104947 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104948 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104949 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104950 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104951 | //BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL |
104952 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
104953 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
104954 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
104955 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
104956 | //BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS |
104957 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
104958 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
104959 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
104960 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
104961 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
104962 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
104963 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
104964 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
104965 | //BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
104966 | #define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
104967 | #define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
104968 | //BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
104969 | #define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
104970 | #define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
104971 | //BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST |
104972 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104973 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104974 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104975 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104976 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104977 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104978 | //BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP |
104979 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
104980 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
104981 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
104982 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
104983 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
104984 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
104985 | //BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL |
104986 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
104987 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
104988 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
104989 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
104990 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
104991 | #define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
104992 | //BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST |
104993 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
104994 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
104995 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
104996 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
104997 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
104998 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
104999 | //BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP |
105000 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
105001 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
105002 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
105003 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
105004 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
105005 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
105006 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
105007 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
105008 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
105009 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
105010 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
105011 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
105012 | //BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL |
105013 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
105014 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
105015 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
105016 | #define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
105017 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST |
105018 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
105019 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
105020 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
105021 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
105022 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
105023 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
105024 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP |
105025 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
105026 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
105027 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
105028 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
105029 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
105030 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
105031 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL |
105032 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
105033 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
105034 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
105035 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
105036 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0 |
105037 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
105038 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
105039 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
105040 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
105041 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1 |
105042 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
105043 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
105044 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0 |
105045 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
105046 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
105047 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1 |
105048 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
105049 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
105050 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0 |
105051 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
105052 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
105053 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1 |
105054 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
105055 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
105056 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0 |
105057 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
105058 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
105059 | //BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1 |
105060 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
105061 | #define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
105062 | //BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST |
105063 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
105064 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
105065 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
105066 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
105067 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
105068 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
105069 | //BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP |
105070 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
105071 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
105072 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
105073 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
105074 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
105075 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
105076 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
105077 | #define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
105078 | //BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST |
105079 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
105080 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
105081 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
105082 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
105083 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
105084 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
105085 | //BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP |
105086 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
105087 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
105088 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
105089 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
105090 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
105091 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
105092 | //BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL |
105093 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
105094 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
105095 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
105096 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
105097 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
105098 | #define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
105099 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST |
105100 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
105101 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
105102 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
105103 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
105104 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
105105 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
105106 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP |
105107 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
105108 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
105109 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
105110 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
105111 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
105112 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
105113 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL |
105114 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
105115 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
105116 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
105117 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
105118 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
105119 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
105120 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
105121 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
105122 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
105123 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
105124 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS |
105125 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
105126 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
105127 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS |
105128 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
105129 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
105130 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS |
105131 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
105132 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
105133 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS |
105134 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
105135 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
105136 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK |
105137 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
105138 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
105139 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET |
105140 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
105141 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
105142 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE |
105143 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
105144 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
105145 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID |
105146 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
105147 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
105148 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
105149 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
105150 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
105151 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
105152 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
105153 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
105154 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0 |
105155 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
105156 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
105157 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1 |
105158 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
105159 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
105160 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2 |
105161 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
105162 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
105163 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3 |
105164 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
105165 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
105166 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4 |
105167 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
105168 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
105169 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5 |
105170 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
105171 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
105172 | //BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
105173 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
105174 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
105175 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
105176 | #define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
105177 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
105178 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
105179 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
105180 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
105181 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
105182 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
105183 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
105184 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
105185 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
105186 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
105187 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
105188 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
105189 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
105190 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
105191 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
105192 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
105193 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
105194 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
105195 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
105196 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
105197 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
105198 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
105199 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
105200 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
105201 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
105202 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
105203 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
105204 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
105205 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
105206 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
105207 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
105208 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
105209 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
105210 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
105211 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
105212 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
105213 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
105214 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
105215 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
105216 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
105217 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
105218 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
105219 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
105220 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
105221 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
105222 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
105223 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
105224 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
105225 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
105226 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
105227 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
105228 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
105229 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
105230 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
105231 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
105232 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
105233 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
105234 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
105235 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
105236 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
105237 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
105238 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
105239 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
105240 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
105241 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
105242 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
105243 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
105244 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
105245 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
105246 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
105247 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
105248 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
105249 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
105250 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
105251 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
105252 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
105253 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
105254 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
105255 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
105256 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
105257 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
105258 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
105259 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
105260 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
105261 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
105262 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
105263 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
105264 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
105265 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
105266 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
105267 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
105268 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
105269 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
105270 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
105271 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
105272 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
105273 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
105274 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
105275 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
105276 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
105277 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
105278 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
105279 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
105280 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
105281 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
105282 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
105283 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
105284 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
105285 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
105286 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
105287 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
105288 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
105289 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
105290 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
105291 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
105292 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
105293 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
105294 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
105295 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
105296 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
105297 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
105298 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
105299 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
105300 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
105301 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
105302 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
105303 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
105304 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
105305 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
105306 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
105307 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
105308 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
105309 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
105310 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
105311 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
105312 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
105313 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
105314 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
105315 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
105316 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
105317 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
105318 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
105319 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
105320 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
105321 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
105322 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
105323 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
105324 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
105325 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
105326 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
105327 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
105328 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
105329 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
105330 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
105331 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
105332 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
105333 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
105334 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
105335 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
105336 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
105337 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
105338 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
105339 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
105340 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
105341 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
105342 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
105343 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
105344 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
105345 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
105346 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
105347 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
105348 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
105349 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
105350 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
105351 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
105352 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
105353 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
105354 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
105355 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
105356 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
105357 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
105358 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
105359 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
105360 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
105361 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
105362 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
105363 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
105364 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
105365 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
105366 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
105367 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
105368 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
105369 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
105370 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
105371 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
105372 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
105373 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
105374 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
105375 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
105376 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
105377 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
105378 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
105379 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
105380 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
105381 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
105382 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
105383 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
105384 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
105385 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
105386 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
105387 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
105388 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
105389 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
105390 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
105391 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
105392 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
105393 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
105394 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
105395 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
105396 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
105397 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
105398 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
105399 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
105400 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
105401 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
105402 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
105403 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
105404 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
105405 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
105406 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
105407 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
105408 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
105409 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
105410 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
105411 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
105412 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
105413 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
105414 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
105415 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
105416 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
105417 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
105418 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
105419 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
105420 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
105421 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
105422 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
105423 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
105424 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
105425 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
105426 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
105427 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
105428 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
105429 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
105430 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
105431 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
105432 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
105433 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
105434 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
105435 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
105436 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
105437 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
105438 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
105439 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
105440 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
105441 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
105442 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
105443 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
105444 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
105445 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
105446 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
105447 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
105448 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
105449 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
105450 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
105451 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
105452 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
105453 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
105454 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
105455 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
105456 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
105457 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
105458 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
105459 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
105460 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
105461 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
105462 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
105463 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
105464 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
105465 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
105466 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
105467 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
105468 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
105469 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
105470 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
105471 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
105472 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
105473 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
105474 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
105475 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
105476 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
105477 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
105478 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
105479 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
105480 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
105481 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
105482 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
105483 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
105484 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
105485 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
105486 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
105487 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
105488 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
105489 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
105490 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
105491 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
105492 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
105493 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
105494 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
105495 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
105496 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
105497 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
105498 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
105499 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
105500 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
105501 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
105502 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
105503 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
105504 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
105505 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
105506 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
105507 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
105508 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
105509 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
105510 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
105511 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
105512 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
105513 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
105514 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
105515 | //BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
105516 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
105517 | #define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
105518 | |
105519 | |
105520 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
105521 | //BIF_CFG_DEV0_EPF1_2_VENDOR_ID |
105522 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
105523 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
105524 | //BIF_CFG_DEV0_EPF1_2_DEVICE_ID |
105525 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
105526 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
105527 | //BIF_CFG_DEV0_EPF1_2_COMMAND |
105528 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
105529 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
105530 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
105531 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
105532 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
105533 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
105534 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
105535 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
105536 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN__SHIFT 0x8 |
105537 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
105538 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS__SHIFT 0xa |
105539 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
105540 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
105541 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
105542 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
105543 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
105544 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
105545 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
105546 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING_MASK 0x0080L |
105547 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN_MASK 0x0100L |
105548 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
105549 | #define BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS_MASK 0x0400L |
105550 | //BIF_CFG_DEV0_EPF1_2_STATUS |
105551 | #define BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS__SHIFT 0x3 |
105552 | #define BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST__SHIFT 0x4 |
105553 | #define BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN__SHIFT 0x5 |
105554 | #define BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
105555 | #define BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
105556 | #define BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
105557 | #define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
105558 | #define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
105559 | #define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
105560 | #define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
105561 | #define BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
105562 | #define BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS_MASK 0x0008L |
105563 | #define BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST_MASK 0x0010L |
105564 | #define BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN_MASK 0x0020L |
105565 | #define BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
105566 | #define BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
105567 | #define BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
105568 | #define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
105569 | #define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
105570 | #define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
105571 | #define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
105572 | #define BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
105573 | //BIF_CFG_DEV0_EPF1_2_REVISION_ID |
105574 | #define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
105575 | #define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
105576 | #define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
105577 | #define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
105578 | //BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE |
105579 | #define BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
105580 | #define BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
105581 | //BIF_CFG_DEV0_EPF1_2_SUB_CLASS |
105582 | #define BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
105583 | #define BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
105584 | //BIF_CFG_DEV0_EPF1_2_BASE_CLASS |
105585 | #define BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
105586 | #define BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
105587 | //BIF_CFG_DEV0_EPF1_2_CACHE_LINE |
105588 | #define BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
105589 | #define BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
105590 | //BIF_CFG_DEV0_EPF1_2_LATENCY |
105591 | #define BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
105592 | #define BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
105593 | //BIF_CFG_DEV0_EPF1_2_HEADER |
105594 | #define BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
105595 | #define BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
105596 | #define BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE_MASK 0x7FL |
105597 | #define BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE_MASK 0x80L |
105598 | //BIF_CFG_DEV0_EPF1_2_BIST |
105599 | #define BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP__SHIFT 0x0 |
105600 | #define BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT__SHIFT 0x6 |
105601 | #define BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP__SHIFT 0x7 |
105602 | #define BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP_MASK 0x0FL |
105603 | #define BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT_MASK 0x40L |
105604 | #define BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP_MASK 0x80L |
105605 | //BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1 |
105606 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
105607 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
105608 | //BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2 |
105609 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
105610 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
105611 | //BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3 |
105612 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
105613 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
105614 | //BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4 |
105615 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
105616 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
105617 | //BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5 |
105618 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
105619 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
105620 | //BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6 |
105621 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
105622 | #define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
105623 | //BIF_CFG_DEV0_EPF1_2_ADAPTER_ID |
105624 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
105625 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
105626 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
105627 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
105628 | //BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR |
105629 | #define BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
105630 | #define BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
105631 | //BIF_CFG_DEV0_EPF1_2_CAP_PTR |
105632 | #define BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
105633 | #define BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
105634 | //BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE |
105635 | #define BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
105636 | #define BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
105637 | //BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN |
105638 | #define BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
105639 | #define BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
105640 | //BIF_CFG_DEV0_EPF1_2_MIN_GRANT |
105641 | #define BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
105642 | #define BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
105643 | //BIF_CFG_DEV0_EPF1_2_MAX_LATENCY |
105644 | #define BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
105645 | #define BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
105646 | //BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST |
105647 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
105648 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
105649 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
105650 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
105651 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
105652 | #define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
105653 | //BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W |
105654 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
105655 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
105656 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
105657 | #define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
105658 | //BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST |
105659 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
105660 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
105661 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
105662 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
105663 | //BIF_CFG_DEV0_EPF1_2_PMI_CAP |
105664 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION__SHIFT 0x0 |
105665 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
105666 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
105667 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
105668 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
105669 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
105670 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
105671 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION_MASK 0x0007L |
105672 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
105673 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
105674 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
105675 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
105676 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
105677 | #define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
105678 | //BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL |
105679 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
105680 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
105681 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
105682 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
105683 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
105684 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
105685 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
105686 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
105687 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
105688 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
105689 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
105690 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
105691 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
105692 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
105693 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
105694 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
105695 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
105696 | #define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
105697 | //BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST |
105698 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
105699 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
105700 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
105701 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
105702 | //BIF_CFG_DEV0_EPF1_2_PCIE_CAP |
105703 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION__SHIFT 0x0 |
105704 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
105705 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
105706 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
105707 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION_MASK 0x000FL |
105708 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
105709 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
105710 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
105711 | //BIF_CFG_DEV0_EPF1_2_DEVICE_CAP |
105712 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
105713 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
105714 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
105715 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
105716 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
105717 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
105718 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
105719 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
105720 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
105721 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
105722 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
105723 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
105724 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
105725 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
105726 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
105727 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
105728 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
105729 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
105730 | //BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL |
105731 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
105732 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
105733 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
105734 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
105735 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
105736 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
105737 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
105738 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
105739 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
105740 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
105741 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
105742 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
105743 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
105744 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
105745 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
105746 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
105747 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
105748 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
105749 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
105750 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
105751 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
105752 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
105753 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
105754 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
105755 | //BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS |
105756 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
105757 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
105758 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
105759 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
105760 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
105761 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
105762 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
105763 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
105764 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
105765 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
105766 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
105767 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
105768 | //BIF_CFG_DEV0_EPF1_2_LINK_CAP |
105769 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
105770 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
105771 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
105772 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
105773 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
105774 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
105775 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
105776 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
105777 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
105778 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
105779 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
105780 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
105781 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
105782 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
105783 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
105784 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
105785 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
105786 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
105787 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
105788 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
105789 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
105790 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
105791 | //BIF_CFG_DEV0_EPF1_2_LINK_CNTL |
105792 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
105793 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
105794 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
105795 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
105796 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
105797 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
105798 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
105799 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
105800 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
105801 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
105802 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
105803 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
105804 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
105805 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
105806 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
105807 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
105808 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
105809 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
105810 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
105811 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
105812 | //BIF_CFG_DEV0_EPF1_2_LINK_STATUS |
105813 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
105814 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
105815 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
105816 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
105817 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
105818 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
105819 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
105820 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
105821 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
105822 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
105823 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
105824 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
105825 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
105826 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
105827 | //BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2 |
105828 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
105829 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
105830 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
105831 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
105832 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
105833 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
105834 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
105835 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
105836 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
105837 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
105838 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
105839 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
105840 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
105841 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
105842 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
105843 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
105844 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
105845 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
105846 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
105847 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
105848 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
105849 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
105850 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
105851 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
105852 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
105853 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
105854 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
105855 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
105856 | //BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2 |
105857 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
105858 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
105859 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
105860 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
105861 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
105862 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
105863 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
105864 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
105865 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
105866 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
105867 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
105868 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
105869 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
105870 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
105871 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
105872 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
105873 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
105874 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
105875 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
105876 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
105877 | //BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2 |
105878 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
105879 | #define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
105880 | //BIF_CFG_DEV0_EPF1_2_LINK_CAP2 |
105881 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
105882 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
105883 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
105884 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
105885 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
105886 | #define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
105887 | //BIF_CFG_DEV0_EPF1_2_LINK_CNTL2 |
105888 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
105889 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
105890 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
105891 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
105892 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
105893 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
105894 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
105895 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
105896 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
105897 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
105898 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
105899 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
105900 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
105901 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
105902 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
105903 | #define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
105904 | //BIF_CFG_DEV0_EPF1_2_LINK_STATUS2 |
105905 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
105906 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
105907 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
105908 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
105909 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
105910 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
105911 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
105912 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
105913 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
105914 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
105915 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
105916 | #define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
105917 | //BIF_CFG_DEV0_EPF1_2_SLOT_CAP2 |
105918 | #define BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
105919 | #define BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
105920 | //BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2 |
105921 | #define BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
105922 | #define BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
105923 | //BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2 |
105924 | #define BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
105925 | #define BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
105926 | //BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST |
105927 | #define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
105928 | #define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
105929 | #define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
105930 | #define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
105931 | //BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL |
105932 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
105933 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
105934 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
105935 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
105936 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
105937 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
105938 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
105939 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
105940 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
105941 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
105942 | //BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO |
105943 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
105944 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
105945 | //BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI |
105946 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
105947 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
105948 | //BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA |
105949 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
105950 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
105951 | //BIF_CFG_DEV0_EPF1_2_MSI_MASK |
105952 | #define BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
105953 | #define BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
105954 | //BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64 |
105955 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
105956 | #define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
105957 | //BIF_CFG_DEV0_EPF1_2_MSI_MASK_64 |
105958 | #define BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
105959 | #define BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
105960 | //BIF_CFG_DEV0_EPF1_2_MSI_PENDING |
105961 | #define BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
105962 | #define BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
105963 | //BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64 |
105964 | #define BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
105965 | #define BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
105966 | //BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST |
105967 | #define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
105968 | #define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
105969 | #define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
105970 | #define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
105971 | //BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL |
105972 | #define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
105973 | #define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
105974 | #define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
105975 | #define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
105976 | #define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
105977 | #define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
105978 | //BIF_CFG_DEV0_EPF1_2_MSIX_TABLE |
105979 | #define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
105980 | #define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
105981 | #define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
105982 | #define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
105983 | //BIF_CFG_DEV0_EPF1_2_MSIX_PBA |
105984 | #define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
105985 | #define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
105986 | #define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
105987 | #define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
105988 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
105989 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
105990 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
105991 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
105992 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
105993 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
105994 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
105995 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR |
105996 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
105997 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
105998 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
105999 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
106000 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
106001 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
106002 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1 |
106003 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
106004 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
106005 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2 |
106006 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
106007 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
106008 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST |
106009 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106010 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106011 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106012 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106013 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106014 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106015 | //BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1 |
106016 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
106017 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
106018 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
106019 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
106020 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
106021 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
106022 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
106023 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
106024 | //BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2 |
106025 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
106026 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
106027 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
106028 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
106029 | //BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL |
106030 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
106031 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
106032 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
106033 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
106034 | //BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS |
106035 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
106036 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
106037 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP |
106038 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
106039 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
106040 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
106041 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
106042 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
106043 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
106044 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
106045 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
106046 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL |
106047 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
106048 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
106049 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
106050 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
106051 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
106052 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
106053 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
106054 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
106055 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
106056 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
106057 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
106058 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
106059 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS |
106060 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
106061 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
106062 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
106063 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
106064 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP |
106065 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
106066 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
106067 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
106068 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
106069 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
106070 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
106071 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
106072 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
106073 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL |
106074 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
106075 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
106076 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
106077 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
106078 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
106079 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
106080 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
106081 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
106082 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
106083 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
106084 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
106085 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
106086 | //BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS |
106087 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
106088 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
106089 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
106090 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
106091 | //BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
106092 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106093 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106094 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106095 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106096 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106097 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106098 | //BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1 |
106099 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
106100 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
106101 | //BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2 |
106102 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
106103 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
106104 | //BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
106105 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106106 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106107 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106108 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106109 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106110 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106111 | //BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS |
106112 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
106113 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
106114 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
106115 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
106116 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
106117 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
106118 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
106119 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
106120 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
106121 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
106122 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
106123 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
106124 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
106125 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
106126 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
106127 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
106128 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
106129 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
106130 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
106131 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
106132 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
106133 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
106134 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
106135 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
106136 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
106137 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
106138 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
106139 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
106140 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
106141 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
106142 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
106143 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
106144 | //BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK |
106145 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
106146 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
106147 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
106148 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
106149 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
106150 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
106151 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
106152 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
106153 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
106154 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
106155 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
106156 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
106157 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
106158 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
106159 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
106160 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
106161 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
106162 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
106163 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
106164 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
106165 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
106166 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
106167 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
106168 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
106169 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
106170 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
106171 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
106172 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
106173 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
106174 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
106175 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
106176 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
106177 | //BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY |
106178 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
106179 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
106180 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
106181 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
106182 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
106183 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
106184 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
106185 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
106186 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
106187 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
106188 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
106189 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
106190 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
106191 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
106192 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
106193 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
106194 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
106195 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
106196 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
106197 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
106198 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
106199 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
106200 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
106201 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
106202 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
106203 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
106204 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
106205 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
106206 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
106207 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
106208 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
106209 | #define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
106210 | //BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS |
106211 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
106212 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
106213 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
106214 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
106215 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
106216 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
106217 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
106218 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
106219 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
106220 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
106221 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
106222 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
106223 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
106224 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
106225 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
106226 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
106227 | //BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK |
106228 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
106229 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
106230 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
106231 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
106232 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
106233 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
106234 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
106235 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
106236 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
106237 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
106238 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
106239 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
106240 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
106241 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
106242 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
106243 | #define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
106244 | //BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL |
106245 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
106246 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
106247 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
106248 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
106249 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
106250 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
106251 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
106252 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
106253 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
106254 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
106255 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
106256 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
106257 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
106258 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
106259 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
106260 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
106261 | //BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0 |
106262 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
106263 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
106264 | //BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1 |
106265 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
106266 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
106267 | //BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2 |
106268 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
106269 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
106270 | //BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3 |
106271 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
106272 | #define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
106273 | //BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0 |
106274 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
106275 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
106276 | //BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1 |
106277 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
106278 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
106279 | //BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2 |
106280 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
106281 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
106282 | //BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3 |
106283 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
106284 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
106285 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST |
106286 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106287 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106288 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106289 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106290 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106291 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106292 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP |
106293 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
106294 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
106295 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL |
106296 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
106297 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
106298 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
106299 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
106300 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
106301 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
106302 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP |
106303 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
106304 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
106305 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL |
106306 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
106307 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
106308 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
106309 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
106310 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
106311 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
106312 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP |
106313 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
106314 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
106315 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL |
106316 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
106317 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
106318 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
106319 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
106320 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
106321 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
106322 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP |
106323 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
106324 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
106325 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL |
106326 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
106327 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
106328 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
106329 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
106330 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
106331 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
106332 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP |
106333 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
106334 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
106335 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL |
106336 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
106337 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
106338 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
106339 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
106340 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
106341 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
106342 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP |
106343 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
106344 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
106345 | //BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL |
106346 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
106347 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
106348 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
106349 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
106350 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
106351 | #define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
106352 | //BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
106353 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106354 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106355 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106356 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106357 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106358 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106359 | //BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT |
106360 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
106361 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
106362 | //BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA |
106363 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
106364 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
106365 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
106366 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
106367 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
106368 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
106369 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
106370 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
106371 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
106372 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
106373 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
106374 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
106375 | //BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP |
106376 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
106377 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
106378 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST |
106379 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106380 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106381 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106382 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106383 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106384 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106385 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP |
106386 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
106387 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
106388 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
106389 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
106390 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
106391 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
106392 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
106393 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
106394 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
106395 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
106396 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR |
106397 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
106398 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
106399 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS |
106400 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
106401 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
106402 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
106403 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
106404 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL |
106405 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
106406 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
106407 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
106408 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106409 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106410 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
106411 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106412 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106413 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
106414 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106415 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106416 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
106417 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106418 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106419 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
106420 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106421 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106422 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
106423 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106424 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106425 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
106426 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106427 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106428 | //BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
106429 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
106430 | #define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
106431 | //BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST |
106432 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106433 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106434 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106435 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106436 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106437 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106438 | //BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3 |
106439 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
106440 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
106441 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
106442 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
106443 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
106444 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
106445 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS |
106446 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
106447 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
106448 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
106449 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
106450 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL |
106451 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106452 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106453 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106454 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106455 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106456 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106457 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106458 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106459 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106460 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106461 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL |
106462 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106463 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106464 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106465 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106466 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106467 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106468 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106469 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106470 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106471 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106472 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL |
106473 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106474 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106475 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106476 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106477 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106478 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106479 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106480 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106481 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106482 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106483 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL |
106484 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106485 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106486 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106487 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106488 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106489 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106490 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106491 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106492 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106493 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106494 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL |
106495 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106496 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106497 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106498 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106499 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106500 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106501 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106502 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106503 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106504 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106505 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL |
106506 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106507 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106508 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106509 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106510 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106511 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106512 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106513 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106514 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106515 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106516 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL |
106517 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106518 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106519 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106520 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106521 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106522 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106523 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106524 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106525 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106526 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106527 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL |
106528 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106529 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106530 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106531 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106532 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106533 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106534 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106535 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106536 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106537 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106538 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL |
106539 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106540 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106541 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106542 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106543 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106544 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106545 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106546 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106547 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106548 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106549 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL |
106550 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106551 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106552 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106553 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106554 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106555 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106556 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106557 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106558 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106559 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106560 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL |
106561 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106562 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106563 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106564 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106565 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106566 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106567 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106568 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106569 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106570 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106571 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL |
106572 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106573 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106574 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106575 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106576 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106577 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106578 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106579 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106580 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106581 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106582 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL |
106583 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106584 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106585 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106586 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106587 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106588 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106589 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106590 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106591 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106592 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106593 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL |
106594 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106595 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106596 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106597 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106598 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106599 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106600 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106601 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106602 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106603 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106604 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL |
106605 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106606 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106607 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106608 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106609 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106610 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106611 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106612 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106613 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106614 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106615 | //BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL |
106616 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
106617 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
106618 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
106619 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
106620 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
106621 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
106622 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
106623 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
106624 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
106625 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
106626 | //BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST |
106627 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106628 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106629 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106630 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106631 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106632 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106633 | //BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP |
106634 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
106635 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
106636 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
106637 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
106638 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
106639 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
106640 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
106641 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
106642 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
106643 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
106644 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
106645 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
106646 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
106647 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
106648 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
106649 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
106650 | //BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL |
106651 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
106652 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
106653 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
106654 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
106655 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
106656 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
106657 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
106658 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
106659 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
106660 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
106661 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
106662 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
106663 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
106664 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
106665 | //BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST |
106666 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106667 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106668 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106669 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106670 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106671 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106672 | //BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP |
106673 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
106674 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
106675 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
106676 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
106677 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
106678 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
106679 | //BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL |
106680 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
106681 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
106682 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU_MASK 0x001FL |
106683 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
106684 | //BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST |
106685 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106686 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106687 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106688 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106689 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106690 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106691 | //BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL |
106692 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
106693 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
106694 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
106695 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
106696 | //BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS |
106697 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
106698 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
106699 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
106700 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
106701 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
106702 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
106703 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
106704 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
106705 | //BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
106706 | #define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
106707 | #define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
106708 | //BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
106709 | #define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
106710 | #define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
106711 | //BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST |
106712 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106713 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106714 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106715 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106716 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106717 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106718 | //BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP |
106719 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
106720 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
106721 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
106722 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
106723 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
106724 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
106725 | //BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL |
106726 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
106727 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
106728 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
106729 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
106730 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
106731 | #define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
106732 | //BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST |
106733 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106734 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106735 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106736 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106737 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106738 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106739 | //BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP |
106740 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
106741 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
106742 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
106743 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
106744 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
106745 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
106746 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
106747 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
106748 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
106749 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
106750 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
106751 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
106752 | //BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL |
106753 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
106754 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
106755 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
106756 | #define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
106757 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST |
106758 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106759 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106760 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106761 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106762 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106763 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106764 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP |
106765 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
106766 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
106767 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
106768 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
106769 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
106770 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
106771 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL |
106772 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
106773 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
106774 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
106775 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
106776 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0 |
106777 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
106778 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
106779 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
106780 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
106781 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1 |
106782 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
106783 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
106784 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0 |
106785 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
106786 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
106787 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1 |
106788 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
106789 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
106790 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0 |
106791 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
106792 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
106793 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1 |
106794 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
106795 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
106796 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0 |
106797 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
106798 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
106799 | //BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1 |
106800 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
106801 | #define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
106802 | //BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST |
106803 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106804 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106805 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106806 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106807 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106808 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106809 | //BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP |
106810 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
106811 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
106812 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
106813 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
106814 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
106815 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
106816 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
106817 | #define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
106818 | //BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST |
106819 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106820 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106821 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106822 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106823 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106824 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106825 | //BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP |
106826 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
106827 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
106828 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
106829 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
106830 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
106831 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
106832 | //BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL |
106833 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
106834 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
106835 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
106836 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
106837 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
106838 | #define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
106839 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST |
106840 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
106841 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
106842 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
106843 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
106844 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
106845 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
106846 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP |
106847 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
106848 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
106849 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
106850 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
106851 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
106852 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
106853 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL |
106854 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
106855 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
106856 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
106857 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
106858 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
106859 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
106860 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
106861 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
106862 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
106863 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
106864 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS |
106865 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
106866 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
106867 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS |
106868 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
106869 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
106870 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS |
106871 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
106872 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
106873 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS |
106874 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
106875 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
106876 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK |
106877 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
106878 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
106879 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET |
106880 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
106881 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
106882 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE |
106883 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
106884 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
106885 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID |
106886 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
106887 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
106888 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
106889 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
106890 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
106891 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
106892 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
106893 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
106894 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0 |
106895 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
106896 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
106897 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1 |
106898 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
106899 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
106900 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2 |
106901 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
106902 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
106903 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3 |
106904 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
106905 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
106906 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4 |
106907 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
106908 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
106909 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5 |
106910 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
106911 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
106912 | //BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
106913 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
106914 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
106915 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
106916 | #define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
106917 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
106918 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
106919 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
106920 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
106921 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
106922 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
106923 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
106924 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
106925 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
106926 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
106927 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
106928 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
106929 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
106930 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
106931 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
106932 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
106933 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
106934 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
106935 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
106936 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
106937 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
106938 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
106939 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
106940 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
106941 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
106942 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
106943 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
106944 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
106945 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
106946 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
106947 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
106948 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
106949 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
106950 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
106951 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
106952 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
106953 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
106954 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
106955 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
106956 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
106957 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
106958 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
106959 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
106960 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
106961 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
106962 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
106963 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
106964 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
106965 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
106966 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
106967 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
106968 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
106969 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
106970 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
106971 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
106972 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
106973 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
106974 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
106975 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
106976 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
106977 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
106978 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
106979 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
106980 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
106981 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
106982 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
106983 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
106984 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
106985 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
106986 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
106987 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
106988 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
106989 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
106990 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
106991 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
106992 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
106993 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
106994 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
106995 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
106996 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
106997 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
106998 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
106999 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
107000 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
107001 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
107002 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
107003 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
107004 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
107005 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
107006 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
107007 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
107008 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
107009 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
107010 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
107011 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
107012 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
107013 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
107014 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
107015 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
107016 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
107017 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
107018 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
107019 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
107020 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
107021 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
107022 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
107023 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
107024 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
107025 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
107026 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
107027 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
107028 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
107029 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
107030 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
107031 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
107032 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
107033 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
107034 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
107035 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
107036 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
107037 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
107038 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
107039 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
107040 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
107041 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
107042 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
107043 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
107044 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
107045 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
107046 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
107047 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
107048 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
107049 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
107050 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
107051 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
107052 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
107053 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
107054 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
107055 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
107056 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
107057 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
107058 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
107059 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
107060 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
107061 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
107062 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
107063 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
107064 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
107065 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
107066 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
107067 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
107068 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
107069 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
107070 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
107071 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
107072 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
107073 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
107074 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
107075 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
107076 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
107077 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
107078 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
107079 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
107080 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
107081 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
107082 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
107083 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
107084 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
107085 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
107086 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
107087 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
107088 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
107089 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
107090 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
107091 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
107092 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
107093 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
107094 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
107095 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
107096 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
107097 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
107098 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
107099 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
107100 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
107101 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
107102 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
107103 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
107104 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
107105 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
107106 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
107107 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
107108 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
107109 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
107110 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
107111 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
107112 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
107113 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
107114 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
107115 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
107116 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
107117 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
107118 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
107119 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
107120 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
107121 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
107122 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
107123 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
107124 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
107125 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
107126 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
107127 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
107128 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
107129 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
107130 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
107131 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
107132 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
107133 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
107134 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
107135 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
107136 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
107137 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
107138 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
107139 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
107140 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
107141 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
107142 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
107143 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
107144 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
107145 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
107146 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
107147 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
107148 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
107149 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
107150 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
107151 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
107152 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
107153 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
107154 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
107155 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
107156 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
107157 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
107158 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
107159 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
107160 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
107161 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
107162 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
107163 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
107164 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
107165 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
107166 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
107167 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
107168 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
107169 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
107170 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
107171 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
107172 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
107173 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
107174 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
107175 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
107176 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
107177 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
107178 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
107179 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
107180 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
107181 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
107182 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
107183 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
107184 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
107185 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
107186 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
107187 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
107188 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
107189 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
107190 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
107191 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
107192 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
107193 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
107194 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
107195 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
107196 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
107197 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
107198 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
107199 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
107200 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
107201 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
107202 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
107203 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
107204 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
107205 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
107206 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
107207 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
107208 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
107209 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
107210 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
107211 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
107212 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
107213 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
107214 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
107215 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
107216 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
107217 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
107218 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
107219 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
107220 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
107221 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
107222 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
107223 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
107224 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
107225 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
107226 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
107227 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
107228 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
107229 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
107230 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
107231 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
107232 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
107233 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
107234 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
107235 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
107236 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
107237 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
107238 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
107239 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
107240 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
107241 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
107242 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
107243 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
107244 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
107245 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
107246 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
107247 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
107248 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
107249 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
107250 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
107251 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
107252 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
107253 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
107254 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
107255 | //BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
107256 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
107257 | #define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
107258 | |
107259 | |
107260 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
107261 | //BIF_CFG_DEV0_EPF2_2_VENDOR_ID |
107262 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
107263 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
107264 | //BIF_CFG_DEV0_EPF2_2_DEVICE_ID |
107265 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
107266 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
107267 | //BIF_CFG_DEV0_EPF2_2_COMMAND |
107268 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
107269 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
107270 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
107271 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
107272 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
107273 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
107274 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
107275 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
107276 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN__SHIFT 0x8 |
107277 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
107278 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS__SHIFT 0xa |
107279 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
107280 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
107281 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
107282 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
107283 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
107284 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
107285 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
107286 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING_MASK 0x0080L |
107287 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN_MASK 0x0100L |
107288 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
107289 | #define BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS_MASK 0x0400L |
107290 | //BIF_CFG_DEV0_EPF2_2_STATUS |
107291 | #define BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS__SHIFT 0x3 |
107292 | #define BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST__SHIFT 0x4 |
107293 | #define BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN__SHIFT 0x5 |
107294 | #define BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
107295 | #define BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
107296 | #define BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
107297 | #define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
107298 | #define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
107299 | #define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
107300 | #define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
107301 | #define BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
107302 | #define BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS_MASK 0x0008L |
107303 | #define BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST_MASK 0x0010L |
107304 | #define BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN_MASK 0x0020L |
107305 | #define BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
107306 | #define BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
107307 | #define BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
107308 | #define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
107309 | #define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
107310 | #define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
107311 | #define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
107312 | #define BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
107313 | //BIF_CFG_DEV0_EPF2_2_REVISION_ID |
107314 | #define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
107315 | #define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
107316 | #define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
107317 | #define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
107318 | //BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE |
107319 | #define BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
107320 | #define BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
107321 | //BIF_CFG_DEV0_EPF2_2_SUB_CLASS |
107322 | #define BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
107323 | #define BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
107324 | //BIF_CFG_DEV0_EPF2_2_BASE_CLASS |
107325 | #define BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
107326 | #define BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
107327 | //BIF_CFG_DEV0_EPF2_2_CACHE_LINE |
107328 | #define BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
107329 | #define BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
107330 | //BIF_CFG_DEV0_EPF2_2_LATENCY |
107331 | #define BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
107332 | #define BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
107333 | //BIF_CFG_DEV0_EPF2_2_HEADER |
107334 | #define BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
107335 | #define BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
107336 | #define BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE_MASK 0x7FL |
107337 | #define BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE_MASK 0x80L |
107338 | //BIF_CFG_DEV0_EPF2_2_BIST |
107339 | #define BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP__SHIFT 0x0 |
107340 | #define BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT__SHIFT 0x6 |
107341 | #define BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP__SHIFT 0x7 |
107342 | #define BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP_MASK 0x0FL |
107343 | #define BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT_MASK 0x40L |
107344 | #define BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP_MASK 0x80L |
107345 | //BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1 |
107346 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
107347 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
107348 | //BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2 |
107349 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
107350 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
107351 | //BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3 |
107352 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
107353 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
107354 | //BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4 |
107355 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
107356 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
107357 | //BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5 |
107358 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
107359 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
107360 | //BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6 |
107361 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
107362 | #define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
107363 | //BIF_CFG_DEV0_EPF2_2_ADAPTER_ID |
107364 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
107365 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
107366 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
107367 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
107368 | //BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR |
107369 | #define BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
107370 | #define BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
107371 | //BIF_CFG_DEV0_EPF2_2_CAP_PTR |
107372 | #define BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
107373 | #define BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
107374 | //BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE |
107375 | #define BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
107376 | #define BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
107377 | //BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN |
107378 | #define BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
107379 | #define BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
107380 | //BIF_CFG_DEV0_EPF2_2_MIN_GRANT |
107381 | #define BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
107382 | #define BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
107383 | //BIF_CFG_DEV0_EPF2_2_MAX_LATENCY |
107384 | #define BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
107385 | #define BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
107386 | //BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST |
107387 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
107388 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
107389 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
107390 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
107391 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
107392 | #define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
107393 | //BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W |
107394 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
107395 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
107396 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
107397 | #define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
107398 | //BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST |
107399 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
107400 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
107401 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
107402 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
107403 | //BIF_CFG_DEV0_EPF2_2_PMI_CAP |
107404 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION__SHIFT 0x0 |
107405 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
107406 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
107407 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
107408 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
107409 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
107410 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
107411 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION_MASK 0x0007L |
107412 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
107413 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
107414 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
107415 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
107416 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
107417 | #define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
107418 | //BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL |
107419 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
107420 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
107421 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
107422 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
107423 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
107424 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
107425 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
107426 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
107427 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
107428 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
107429 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
107430 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
107431 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
107432 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
107433 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
107434 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
107435 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
107436 | #define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
107437 | //BIF_CFG_DEV0_EPF2_2_SBRN |
107438 | #define BIF_CFG_DEV0_EPF2_2_SBRN__SBRN__SHIFT 0x0 |
107439 | #define BIF_CFG_DEV0_EPF2_2_SBRN__SBRN_MASK 0xFFL |
107440 | //BIF_CFG_DEV0_EPF2_2_FLADJ |
107441 | #define BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ__SHIFT 0x0 |
107442 | #define BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ_MASK 0x3FL |
107443 | //BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD |
107444 | #define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
107445 | #define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
107446 | #define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
107447 | #define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
107448 | //BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST |
107449 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
107450 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
107451 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
107452 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
107453 | //BIF_CFG_DEV0_EPF2_2_PCIE_CAP |
107454 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION__SHIFT 0x0 |
107455 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
107456 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
107457 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
107458 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION_MASK 0x000FL |
107459 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
107460 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
107461 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
107462 | //BIF_CFG_DEV0_EPF2_2_DEVICE_CAP |
107463 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
107464 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
107465 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
107466 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
107467 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
107468 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
107469 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
107470 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
107471 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
107472 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
107473 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
107474 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
107475 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
107476 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
107477 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
107478 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
107479 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
107480 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
107481 | //BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL |
107482 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
107483 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
107484 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
107485 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
107486 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
107487 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
107488 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
107489 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
107490 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
107491 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
107492 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
107493 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
107494 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
107495 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
107496 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
107497 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
107498 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
107499 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
107500 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
107501 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
107502 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
107503 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
107504 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
107505 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
107506 | //BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS |
107507 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
107508 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
107509 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
107510 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
107511 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
107512 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
107513 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
107514 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
107515 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
107516 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
107517 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
107518 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
107519 | //BIF_CFG_DEV0_EPF2_2_LINK_CAP |
107520 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
107521 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
107522 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
107523 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
107524 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
107525 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
107526 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
107527 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
107528 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
107529 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
107530 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
107531 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
107532 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
107533 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
107534 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
107535 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
107536 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
107537 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
107538 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
107539 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
107540 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
107541 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
107542 | //BIF_CFG_DEV0_EPF2_2_LINK_CNTL |
107543 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
107544 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
107545 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
107546 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
107547 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
107548 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
107549 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
107550 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
107551 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
107552 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
107553 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
107554 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
107555 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
107556 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
107557 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
107558 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
107559 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
107560 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
107561 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
107562 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
107563 | //BIF_CFG_DEV0_EPF2_2_LINK_STATUS |
107564 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
107565 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
107566 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
107567 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
107568 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
107569 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
107570 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
107571 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
107572 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
107573 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
107574 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
107575 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
107576 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
107577 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
107578 | //BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2 |
107579 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
107580 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
107581 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
107582 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
107583 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
107584 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
107585 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
107586 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
107587 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
107588 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
107589 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
107590 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
107591 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
107592 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
107593 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
107594 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
107595 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
107596 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
107597 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
107598 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
107599 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
107600 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
107601 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
107602 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
107603 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
107604 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
107605 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
107606 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
107607 | //BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2 |
107608 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
107609 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
107610 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
107611 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
107612 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
107613 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
107614 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
107615 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
107616 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
107617 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
107618 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
107619 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
107620 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
107621 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
107622 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
107623 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
107624 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
107625 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
107626 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
107627 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
107628 | //BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2 |
107629 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
107630 | #define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
107631 | //BIF_CFG_DEV0_EPF2_2_LINK_CAP2 |
107632 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
107633 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
107634 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
107635 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
107636 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
107637 | #define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
107638 | //BIF_CFG_DEV0_EPF2_2_LINK_CNTL2 |
107639 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
107640 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
107641 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
107642 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
107643 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
107644 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
107645 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
107646 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
107647 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
107648 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
107649 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
107650 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
107651 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
107652 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
107653 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
107654 | #define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
107655 | //BIF_CFG_DEV0_EPF2_2_LINK_STATUS2 |
107656 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
107657 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
107658 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
107659 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
107660 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
107661 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
107662 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
107663 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
107664 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
107665 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
107666 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
107667 | #define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
107668 | //BIF_CFG_DEV0_EPF2_2_SLOT_CAP2 |
107669 | #define BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
107670 | #define BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
107671 | //BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2 |
107672 | #define BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
107673 | #define BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
107674 | //BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2 |
107675 | #define BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
107676 | #define BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
107677 | //BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST |
107678 | #define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
107679 | #define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
107680 | #define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
107681 | #define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
107682 | //BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL |
107683 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
107684 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
107685 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
107686 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
107687 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
107688 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
107689 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
107690 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
107691 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
107692 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
107693 | //BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO |
107694 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
107695 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
107696 | //BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI |
107697 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
107698 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
107699 | //BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA |
107700 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
107701 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
107702 | //BIF_CFG_DEV0_EPF2_2_MSI_MASK |
107703 | #define BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
107704 | #define BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
107705 | //BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64 |
107706 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
107707 | #define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
107708 | //BIF_CFG_DEV0_EPF2_2_MSI_MASK_64 |
107709 | #define BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
107710 | #define BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
107711 | //BIF_CFG_DEV0_EPF2_2_MSI_PENDING |
107712 | #define BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
107713 | #define BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
107714 | //BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64 |
107715 | #define BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
107716 | #define BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
107717 | //BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST |
107718 | #define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
107719 | #define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
107720 | #define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
107721 | #define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
107722 | //BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL |
107723 | #define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
107724 | #define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
107725 | #define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
107726 | #define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
107727 | #define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
107728 | #define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
107729 | //BIF_CFG_DEV0_EPF2_2_MSIX_TABLE |
107730 | #define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
107731 | #define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
107732 | #define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
107733 | #define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
107734 | //BIF_CFG_DEV0_EPF2_2_MSIX_PBA |
107735 | #define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
107736 | #define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
107737 | #define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
107738 | #define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
107739 | //BIF_CFG_DEV0_EPF2_2_SATA_CAP_0 |
107740 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
107741 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
107742 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
107743 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
107744 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
107745 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
107746 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
107747 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
107748 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
107749 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
107750 | //BIF_CFG_DEV0_EPF2_2_SATA_CAP_1 |
107751 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
107752 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
107753 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
107754 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
107755 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
107756 | #define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
107757 | //BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX |
107758 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
107759 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
107760 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
107761 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
107762 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
107763 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
107764 | //BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA |
107765 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
107766 | #define BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
107767 | //BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
107768 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
107769 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
107770 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
107771 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
107772 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
107773 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
107774 | //BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR |
107775 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
107776 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
107777 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
107778 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
107779 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
107780 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
107781 | //BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1 |
107782 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
107783 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
107784 | //BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2 |
107785 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
107786 | #define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
107787 | //BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
107788 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
107789 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
107790 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
107791 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
107792 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
107793 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
107794 | //BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS |
107795 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
107796 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
107797 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
107798 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
107799 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
107800 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
107801 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
107802 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
107803 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
107804 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
107805 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
107806 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
107807 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
107808 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
107809 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
107810 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
107811 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
107812 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
107813 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
107814 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
107815 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
107816 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
107817 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
107818 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
107819 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
107820 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
107821 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
107822 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
107823 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
107824 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
107825 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
107826 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
107827 | //BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK |
107828 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
107829 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
107830 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
107831 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
107832 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
107833 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
107834 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
107835 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
107836 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
107837 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
107838 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
107839 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
107840 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
107841 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
107842 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
107843 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
107844 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
107845 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
107846 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
107847 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
107848 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
107849 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
107850 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
107851 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
107852 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
107853 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
107854 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
107855 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
107856 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
107857 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
107858 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
107859 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
107860 | //BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY |
107861 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
107862 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
107863 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
107864 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
107865 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
107866 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
107867 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
107868 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
107869 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
107870 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
107871 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
107872 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
107873 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
107874 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
107875 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
107876 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
107877 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
107878 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
107879 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
107880 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
107881 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
107882 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
107883 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
107884 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
107885 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
107886 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
107887 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
107888 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
107889 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
107890 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
107891 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
107892 | #define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
107893 | //BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS |
107894 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
107895 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
107896 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
107897 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
107898 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
107899 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
107900 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
107901 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
107902 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
107903 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
107904 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
107905 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
107906 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
107907 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
107908 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
107909 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
107910 | //BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK |
107911 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
107912 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
107913 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
107914 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
107915 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
107916 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
107917 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
107918 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
107919 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
107920 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
107921 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
107922 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
107923 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
107924 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
107925 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
107926 | #define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
107927 | //BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL |
107928 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
107929 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
107930 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
107931 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
107932 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
107933 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
107934 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
107935 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
107936 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
107937 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
107938 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
107939 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
107940 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
107941 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
107942 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
107943 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
107944 | //BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0 |
107945 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
107946 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
107947 | //BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1 |
107948 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
107949 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
107950 | //BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2 |
107951 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
107952 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
107953 | //BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3 |
107954 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
107955 | #define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
107956 | //BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0 |
107957 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
107958 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
107959 | //BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1 |
107960 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
107961 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
107962 | //BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2 |
107963 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
107964 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
107965 | //BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3 |
107966 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
107967 | #define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
107968 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST |
107969 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
107970 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
107971 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
107972 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
107973 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
107974 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
107975 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP |
107976 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
107977 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
107978 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL |
107979 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
107980 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
107981 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
107982 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
107983 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
107984 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
107985 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP |
107986 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
107987 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
107988 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL |
107989 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
107990 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
107991 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
107992 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
107993 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
107994 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
107995 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP |
107996 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
107997 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
107998 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL |
107999 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
108000 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108001 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
108002 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
108003 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108004 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
108005 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP |
108006 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108007 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108008 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL |
108009 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
108010 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108011 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
108012 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
108013 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108014 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
108015 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP |
108016 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108017 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108018 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL |
108019 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
108020 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108021 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
108022 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
108023 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108024 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
108025 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP |
108026 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108027 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108028 | //BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL |
108029 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
108030 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108031 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
108032 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
108033 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108034 | #define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
108035 | //BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
108036 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108037 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108038 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108039 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108040 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108041 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108042 | //BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT |
108043 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
108044 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
108045 | //BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA |
108046 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
108047 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
108048 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
108049 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
108050 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
108051 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
108052 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
108053 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
108054 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
108055 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
108056 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
108057 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
108058 | //BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP |
108059 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
108060 | #define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
108061 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST |
108062 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108063 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108064 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108065 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108066 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108067 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108068 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP |
108069 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
108070 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
108071 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
108072 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
108073 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
108074 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
108075 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
108076 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
108077 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
108078 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
108079 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR |
108080 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
108081 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
108082 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS |
108083 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
108084 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
108085 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
108086 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
108087 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL |
108088 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
108089 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
108090 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
108091 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108092 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108093 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
108094 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108095 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108096 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
108097 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108098 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108099 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
108100 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108101 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108102 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
108103 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108104 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108105 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
108106 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108107 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108108 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
108109 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108110 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108111 | //BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
108112 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
108113 | #define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
108114 | //BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST |
108115 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108116 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108117 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108118 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108119 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108120 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108121 | //BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP |
108122 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
108123 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
108124 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
108125 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
108126 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
108127 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
108128 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
108129 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
108130 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
108131 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
108132 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
108133 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
108134 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
108135 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
108136 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
108137 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
108138 | //BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL |
108139 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
108140 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
108141 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
108142 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
108143 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
108144 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
108145 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
108146 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
108147 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
108148 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
108149 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
108150 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
108151 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
108152 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
108153 | //BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST |
108154 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108155 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108156 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108157 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108158 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108159 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108160 | //BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP |
108161 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
108162 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
108163 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
108164 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
108165 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
108166 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
108167 | //BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL |
108168 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
108169 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
108170 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
108171 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
108172 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
108173 | #define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
108174 | |
108175 | |
108176 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
108177 | //BIF_CFG_DEV0_EPF3_2_VENDOR_ID |
108178 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
108179 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
108180 | //BIF_CFG_DEV0_EPF3_2_DEVICE_ID |
108181 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
108182 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
108183 | //BIF_CFG_DEV0_EPF3_2_COMMAND |
108184 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
108185 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
108186 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
108187 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
108188 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
108189 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
108190 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
108191 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
108192 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN__SHIFT 0x8 |
108193 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
108194 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS__SHIFT 0xa |
108195 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
108196 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
108197 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
108198 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
108199 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
108200 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
108201 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
108202 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING_MASK 0x0080L |
108203 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN_MASK 0x0100L |
108204 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
108205 | #define BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS_MASK 0x0400L |
108206 | //BIF_CFG_DEV0_EPF3_2_STATUS |
108207 | #define BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS__SHIFT 0x3 |
108208 | #define BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST__SHIFT 0x4 |
108209 | #define BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN__SHIFT 0x5 |
108210 | #define BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
108211 | #define BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
108212 | #define BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
108213 | #define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
108214 | #define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
108215 | #define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
108216 | #define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
108217 | #define BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
108218 | #define BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS_MASK 0x0008L |
108219 | #define BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST_MASK 0x0010L |
108220 | #define BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN_MASK 0x0020L |
108221 | #define BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
108222 | #define BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
108223 | #define BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
108224 | #define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
108225 | #define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
108226 | #define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
108227 | #define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
108228 | #define BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
108229 | //BIF_CFG_DEV0_EPF3_2_REVISION_ID |
108230 | #define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
108231 | #define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
108232 | #define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
108233 | #define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
108234 | //BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE |
108235 | #define BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
108236 | #define BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
108237 | //BIF_CFG_DEV0_EPF3_2_SUB_CLASS |
108238 | #define BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
108239 | #define BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
108240 | //BIF_CFG_DEV0_EPF3_2_BASE_CLASS |
108241 | #define BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
108242 | #define BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
108243 | //BIF_CFG_DEV0_EPF3_2_CACHE_LINE |
108244 | #define BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
108245 | #define BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
108246 | //BIF_CFG_DEV0_EPF3_2_LATENCY |
108247 | #define BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
108248 | #define BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
108249 | //BIF_CFG_DEV0_EPF3_2_HEADER |
108250 | #define BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
108251 | #define BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
108252 | #define BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE_MASK 0x7FL |
108253 | #define BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE_MASK 0x80L |
108254 | //BIF_CFG_DEV0_EPF3_2_BIST |
108255 | #define BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP__SHIFT 0x0 |
108256 | #define BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT__SHIFT 0x6 |
108257 | #define BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP__SHIFT 0x7 |
108258 | #define BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP_MASK 0x0FL |
108259 | #define BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT_MASK 0x40L |
108260 | #define BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP_MASK 0x80L |
108261 | //BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1 |
108262 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
108263 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
108264 | //BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2 |
108265 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
108266 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
108267 | //BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3 |
108268 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
108269 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
108270 | //BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4 |
108271 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
108272 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
108273 | //BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5 |
108274 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
108275 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
108276 | //BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6 |
108277 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
108278 | #define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
108279 | //BIF_CFG_DEV0_EPF3_2_ADAPTER_ID |
108280 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
108281 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
108282 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
108283 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
108284 | //BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR |
108285 | #define BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
108286 | #define BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
108287 | //BIF_CFG_DEV0_EPF3_2_CAP_PTR |
108288 | #define BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
108289 | #define BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
108290 | //BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE |
108291 | #define BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
108292 | #define BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
108293 | //BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN |
108294 | #define BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
108295 | #define BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
108296 | //BIF_CFG_DEV0_EPF3_2_MIN_GRANT |
108297 | #define BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
108298 | #define BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
108299 | //BIF_CFG_DEV0_EPF3_2_MAX_LATENCY |
108300 | #define BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
108301 | #define BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
108302 | //BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST |
108303 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
108304 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
108305 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
108306 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
108307 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
108308 | #define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
108309 | //BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W |
108310 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
108311 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
108312 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
108313 | #define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
108314 | //BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST |
108315 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
108316 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
108317 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
108318 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
108319 | //BIF_CFG_DEV0_EPF3_2_PMI_CAP |
108320 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION__SHIFT 0x0 |
108321 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
108322 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
108323 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
108324 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
108325 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
108326 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
108327 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION_MASK 0x0007L |
108328 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
108329 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
108330 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
108331 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
108332 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
108333 | #define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
108334 | //BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL |
108335 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
108336 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
108337 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
108338 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
108339 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
108340 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
108341 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
108342 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
108343 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
108344 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
108345 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
108346 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
108347 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
108348 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
108349 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
108350 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
108351 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
108352 | #define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
108353 | //BIF_CFG_DEV0_EPF3_2_SBRN |
108354 | #define BIF_CFG_DEV0_EPF3_2_SBRN__SBRN__SHIFT 0x0 |
108355 | #define BIF_CFG_DEV0_EPF3_2_SBRN__SBRN_MASK 0xFFL |
108356 | //BIF_CFG_DEV0_EPF3_2_FLADJ |
108357 | #define BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ__SHIFT 0x0 |
108358 | #define BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ_MASK 0x3FL |
108359 | //BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD |
108360 | #define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
108361 | #define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
108362 | #define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
108363 | #define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
108364 | //BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST |
108365 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
108366 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
108367 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
108368 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
108369 | //BIF_CFG_DEV0_EPF3_2_PCIE_CAP |
108370 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION__SHIFT 0x0 |
108371 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
108372 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
108373 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
108374 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION_MASK 0x000FL |
108375 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
108376 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
108377 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
108378 | //BIF_CFG_DEV0_EPF3_2_DEVICE_CAP |
108379 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
108380 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
108381 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
108382 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
108383 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
108384 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
108385 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
108386 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
108387 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
108388 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
108389 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
108390 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
108391 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
108392 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
108393 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
108394 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
108395 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
108396 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
108397 | //BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL |
108398 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
108399 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
108400 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
108401 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
108402 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
108403 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
108404 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
108405 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
108406 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
108407 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
108408 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
108409 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
108410 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
108411 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
108412 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
108413 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
108414 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
108415 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
108416 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
108417 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
108418 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
108419 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
108420 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
108421 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
108422 | //BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS |
108423 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
108424 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
108425 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
108426 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
108427 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
108428 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
108429 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
108430 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
108431 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
108432 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
108433 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
108434 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
108435 | //BIF_CFG_DEV0_EPF3_2_LINK_CAP |
108436 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
108437 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
108438 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
108439 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
108440 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
108441 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
108442 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
108443 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
108444 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
108445 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
108446 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
108447 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
108448 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
108449 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
108450 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
108451 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
108452 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
108453 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
108454 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
108455 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
108456 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
108457 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
108458 | //BIF_CFG_DEV0_EPF3_2_LINK_CNTL |
108459 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
108460 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
108461 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
108462 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
108463 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
108464 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
108465 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
108466 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
108467 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
108468 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
108469 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
108470 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
108471 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
108472 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
108473 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
108474 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
108475 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
108476 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
108477 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
108478 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
108479 | //BIF_CFG_DEV0_EPF3_2_LINK_STATUS |
108480 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
108481 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
108482 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
108483 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
108484 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
108485 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
108486 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
108487 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
108488 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
108489 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
108490 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
108491 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
108492 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
108493 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
108494 | //BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2 |
108495 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
108496 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
108497 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
108498 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
108499 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
108500 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
108501 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
108502 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
108503 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
108504 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
108505 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
108506 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
108507 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
108508 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
108509 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
108510 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
108511 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
108512 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
108513 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
108514 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
108515 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
108516 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
108517 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
108518 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
108519 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
108520 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
108521 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
108522 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
108523 | //BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2 |
108524 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
108525 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
108526 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
108527 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
108528 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
108529 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
108530 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
108531 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
108532 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
108533 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
108534 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
108535 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
108536 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
108537 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
108538 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
108539 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
108540 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
108541 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
108542 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
108543 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
108544 | //BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2 |
108545 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
108546 | #define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
108547 | //BIF_CFG_DEV0_EPF3_2_LINK_CAP2 |
108548 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
108549 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
108550 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
108551 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
108552 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
108553 | #define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
108554 | //BIF_CFG_DEV0_EPF3_2_LINK_CNTL2 |
108555 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
108556 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
108557 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
108558 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
108559 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
108560 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
108561 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
108562 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
108563 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
108564 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
108565 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
108566 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
108567 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
108568 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
108569 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
108570 | #define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
108571 | //BIF_CFG_DEV0_EPF3_2_LINK_STATUS2 |
108572 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
108573 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
108574 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
108575 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
108576 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
108577 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
108578 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
108579 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
108580 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
108581 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
108582 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
108583 | #define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
108584 | //BIF_CFG_DEV0_EPF3_2_SLOT_CAP2 |
108585 | #define BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
108586 | #define BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
108587 | //BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2 |
108588 | #define BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
108589 | #define BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
108590 | //BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2 |
108591 | #define BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
108592 | #define BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
108593 | //BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST |
108594 | #define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
108595 | #define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
108596 | #define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
108597 | #define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
108598 | //BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL |
108599 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
108600 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
108601 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
108602 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
108603 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
108604 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
108605 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
108606 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
108607 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
108608 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
108609 | //BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO |
108610 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
108611 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
108612 | //BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI |
108613 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
108614 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
108615 | //BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA |
108616 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
108617 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
108618 | //BIF_CFG_DEV0_EPF3_2_MSI_MASK |
108619 | #define BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
108620 | #define BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
108621 | //BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64 |
108622 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
108623 | #define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
108624 | //BIF_CFG_DEV0_EPF3_2_MSI_MASK_64 |
108625 | #define BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
108626 | #define BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
108627 | //BIF_CFG_DEV0_EPF3_2_MSI_PENDING |
108628 | #define BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
108629 | #define BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
108630 | //BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64 |
108631 | #define BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
108632 | #define BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
108633 | //BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST |
108634 | #define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
108635 | #define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
108636 | #define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
108637 | #define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
108638 | //BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL |
108639 | #define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
108640 | #define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
108641 | #define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
108642 | #define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
108643 | #define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
108644 | #define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
108645 | //BIF_CFG_DEV0_EPF3_2_MSIX_TABLE |
108646 | #define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
108647 | #define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
108648 | #define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
108649 | #define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
108650 | //BIF_CFG_DEV0_EPF3_2_MSIX_PBA |
108651 | #define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
108652 | #define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
108653 | #define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
108654 | #define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
108655 | //BIF_CFG_DEV0_EPF3_2_SATA_CAP_0 |
108656 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
108657 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
108658 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
108659 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
108660 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
108661 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
108662 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
108663 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
108664 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
108665 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
108666 | //BIF_CFG_DEV0_EPF3_2_SATA_CAP_1 |
108667 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
108668 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
108669 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
108670 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
108671 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
108672 | #define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
108673 | //BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX |
108674 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
108675 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
108676 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
108677 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
108678 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
108679 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
108680 | //BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA |
108681 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
108682 | #define BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
108683 | //BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
108684 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108685 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108686 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108687 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108688 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108689 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108690 | //BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR |
108691 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
108692 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
108693 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
108694 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
108695 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
108696 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
108697 | //BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1 |
108698 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
108699 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
108700 | //BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2 |
108701 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
108702 | #define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
108703 | //BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
108704 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108705 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108706 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108707 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108708 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108709 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108710 | //BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS |
108711 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
108712 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
108713 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
108714 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
108715 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
108716 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
108717 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
108718 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
108719 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
108720 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
108721 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
108722 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
108723 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
108724 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
108725 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
108726 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
108727 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
108728 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
108729 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
108730 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
108731 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
108732 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
108733 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
108734 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
108735 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
108736 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
108737 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
108738 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
108739 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
108740 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
108741 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
108742 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
108743 | //BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK |
108744 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
108745 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
108746 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
108747 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
108748 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
108749 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
108750 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
108751 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
108752 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
108753 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
108754 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
108755 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
108756 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
108757 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
108758 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
108759 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
108760 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
108761 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
108762 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
108763 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
108764 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
108765 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
108766 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
108767 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
108768 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
108769 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
108770 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
108771 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
108772 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
108773 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
108774 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
108775 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
108776 | //BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY |
108777 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
108778 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
108779 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
108780 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
108781 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
108782 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
108783 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
108784 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
108785 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
108786 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
108787 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
108788 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
108789 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
108790 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
108791 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
108792 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
108793 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
108794 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
108795 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
108796 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
108797 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
108798 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
108799 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
108800 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
108801 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
108802 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
108803 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
108804 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
108805 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
108806 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
108807 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
108808 | #define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
108809 | //BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS |
108810 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
108811 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
108812 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
108813 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
108814 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
108815 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
108816 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
108817 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
108818 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
108819 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
108820 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
108821 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
108822 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
108823 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
108824 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
108825 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
108826 | //BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK |
108827 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
108828 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
108829 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
108830 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
108831 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
108832 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
108833 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
108834 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
108835 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
108836 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
108837 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
108838 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
108839 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
108840 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
108841 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
108842 | #define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
108843 | //BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL |
108844 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
108845 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
108846 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
108847 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
108848 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
108849 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
108850 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
108851 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
108852 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
108853 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
108854 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
108855 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
108856 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
108857 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
108858 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
108859 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
108860 | //BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0 |
108861 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
108862 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
108863 | //BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1 |
108864 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
108865 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
108866 | //BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2 |
108867 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
108868 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
108869 | //BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3 |
108870 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
108871 | #define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
108872 | //BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0 |
108873 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
108874 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
108875 | //BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1 |
108876 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
108877 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
108878 | //BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2 |
108879 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
108880 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
108881 | //BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3 |
108882 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
108883 | #define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
108884 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST |
108885 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108886 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108887 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108888 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108889 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108890 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108891 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP |
108892 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108893 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108894 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL |
108895 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
108896 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108897 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
108898 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
108899 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108900 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
108901 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP |
108902 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108903 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108904 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL |
108905 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
108906 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108907 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
108908 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
108909 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108910 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
108911 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP |
108912 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108913 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108914 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL |
108915 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
108916 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108917 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
108918 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
108919 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108920 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
108921 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP |
108922 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108923 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108924 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL |
108925 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
108926 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108927 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
108928 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
108929 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108930 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
108931 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP |
108932 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108933 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108934 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL |
108935 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
108936 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108937 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
108938 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
108939 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108940 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
108941 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP |
108942 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
108943 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
108944 | //BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL |
108945 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
108946 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
108947 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
108948 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
108949 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
108950 | #define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
108951 | //BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
108952 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108953 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108954 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108955 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108956 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108957 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108958 | //BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT |
108959 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
108960 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
108961 | //BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA |
108962 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
108963 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
108964 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
108965 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
108966 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
108967 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
108968 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
108969 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
108970 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
108971 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
108972 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
108973 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
108974 | //BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP |
108975 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
108976 | #define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
108977 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST |
108978 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
108979 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
108980 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
108981 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
108982 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
108983 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
108984 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP |
108985 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
108986 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
108987 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
108988 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
108989 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
108990 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
108991 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
108992 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
108993 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
108994 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
108995 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR |
108996 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
108997 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
108998 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS |
108999 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
109000 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
109001 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
109002 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
109003 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL |
109004 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
109005 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
109006 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
109007 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109008 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109009 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
109010 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109011 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109012 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
109013 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109014 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109015 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
109016 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109017 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109018 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
109019 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109020 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109021 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
109022 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109023 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109024 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
109025 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109026 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109027 | //BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
109028 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109029 | #define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109030 | //BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST |
109031 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109032 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109033 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109034 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109035 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109036 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109037 | //BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP |
109038 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
109039 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
109040 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
109041 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
109042 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
109043 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
109044 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
109045 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
109046 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
109047 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
109048 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
109049 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
109050 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
109051 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
109052 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
109053 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
109054 | //BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL |
109055 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
109056 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
109057 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
109058 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
109059 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
109060 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
109061 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
109062 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
109063 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
109064 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
109065 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
109066 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
109067 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
109068 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
109069 | //BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST |
109070 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109071 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109072 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109073 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109074 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109075 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109076 | //BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP |
109077 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
109078 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
109079 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
109080 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
109081 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
109082 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
109083 | //BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL |
109084 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
109085 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
109086 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
109087 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
109088 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
109089 | #define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
109090 | |
109091 | |
109092 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
109093 | //BIF_CFG_DEV0_EPF4_2_VENDOR_ID |
109094 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
109095 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
109096 | //BIF_CFG_DEV0_EPF4_2_DEVICE_ID |
109097 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
109098 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
109099 | //BIF_CFG_DEV0_EPF4_2_COMMAND |
109100 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
109101 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
109102 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
109103 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
109104 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
109105 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
109106 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
109107 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
109108 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN__SHIFT 0x8 |
109109 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
109110 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS__SHIFT 0xa |
109111 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
109112 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
109113 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
109114 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
109115 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
109116 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
109117 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
109118 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING_MASK 0x0080L |
109119 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN_MASK 0x0100L |
109120 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
109121 | #define BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS_MASK 0x0400L |
109122 | //BIF_CFG_DEV0_EPF4_2_STATUS |
109123 | #define BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS__SHIFT 0x3 |
109124 | #define BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST__SHIFT 0x4 |
109125 | #define BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN__SHIFT 0x5 |
109126 | #define BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
109127 | #define BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
109128 | #define BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
109129 | #define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
109130 | #define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
109131 | #define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
109132 | #define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
109133 | #define BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
109134 | #define BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS_MASK 0x0008L |
109135 | #define BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST_MASK 0x0010L |
109136 | #define BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN_MASK 0x0020L |
109137 | #define BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
109138 | #define BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
109139 | #define BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
109140 | #define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
109141 | #define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
109142 | #define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
109143 | #define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
109144 | #define BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
109145 | //BIF_CFG_DEV0_EPF4_2_REVISION_ID |
109146 | #define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
109147 | #define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
109148 | #define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
109149 | #define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
109150 | //BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE |
109151 | #define BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
109152 | #define BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
109153 | //BIF_CFG_DEV0_EPF4_2_SUB_CLASS |
109154 | #define BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
109155 | #define BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
109156 | //BIF_CFG_DEV0_EPF4_2_BASE_CLASS |
109157 | #define BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
109158 | #define BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
109159 | //BIF_CFG_DEV0_EPF4_2_CACHE_LINE |
109160 | #define BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
109161 | #define BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
109162 | //BIF_CFG_DEV0_EPF4_2_LATENCY |
109163 | #define BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
109164 | #define BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
109165 | //BIF_CFG_DEV0_EPF4_2_HEADER |
109166 | #define BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
109167 | #define BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
109168 | #define BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE_MASK 0x7FL |
109169 | #define BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE_MASK 0x80L |
109170 | //BIF_CFG_DEV0_EPF4_2_BIST |
109171 | #define BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP__SHIFT 0x0 |
109172 | #define BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT__SHIFT 0x6 |
109173 | #define BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP__SHIFT 0x7 |
109174 | #define BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP_MASK 0x0FL |
109175 | #define BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT_MASK 0x40L |
109176 | #define BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP_MASK 0x80L |
109177 | //BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1 |
109178 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
109179 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
109180 | //BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2 |
109181 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
109182 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
109183 | //BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3 |
109184 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
109185 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
109186 | //BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4 |
109187 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
109188 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
109189 | //BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5 |
109190 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
109191 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
109192 | //BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6 |
109193 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
109194 | #define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
109195 | //BIF_CFG_DEV0_EPF4_2_ADAPTER_ID |
109196 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
109197 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
109198 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
109199 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
109200 | //BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR |
109201 | #define BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
109202 | #define BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
109203 | //BIF_CFG_DEV0_EPF4_2_CAP_PTR |
109204 | #define BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
109205 | #define BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
109206 | //BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE |
109207 | #define BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
109208 | #define BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
109209 | //BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN |
109210 | #define BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
109211 | #define BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
109212 | //BIF_CFG_DEV0_EPF4_2_MIN_GRANT |
109213 | #define BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
109214 | #define BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
109215 | //BIF_CFG_DEV0_EPF4_2_MAX_LATENCY |
109216 | #define BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
109217 | #define BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
109218 | //BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST |
109219 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
109220 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
109221 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
109222 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
109223 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
109224 | #define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
109225 | //BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W |
109226 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
109227 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
109228 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
109229 | #define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
109230 | //BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST |
109231 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
109232 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
109233 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
109234 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
109235 | //BIF_CFG_DEV0_EPF4_2_PMI_CAP |
109236 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION__SHIFT 0x0 |
109237 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
109238 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
109239 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
109240 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
109241 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
109242 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
109243 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION_MASK 0x0007L |
109244 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
109245 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
109246 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
109247 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
109248 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
109249 | #define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
109250 | //BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL |
109251 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
109252 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
109253 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
109254 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
109255 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
109256 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
109257 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
109258 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
109259 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
109260 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
109261 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
109262 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
109263 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
109264 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
109265 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
109266 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
109267 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
109268 | #define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
109269 | //BIF_CFG_DEV0_EPF4_2_SBRN |
109270 | #define BIF_CFG_DEV0_EPF4_2_SBRN__SBRN__SHIFT 0x0 |
109271 | #define BIF_CFG_DEV0_EPF4_2_SBRN__SBRN_MASK 0xFFL |
109272 | //BIF_CFG_DEV0_EPF4_2_FLADJ |
109273 | #define BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ__SHIFT 0x0 |
109274 | #define BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ_MASK 0x3FL |
109275 | //BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD |
109276 | #define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
109277 | #define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
109278 | #define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
109279 | #define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
109280 | //BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST |
109281 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
109282 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
109283 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
109284 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
109285 | //BIF_CFG_DEV0_EPF4_2_PCIE_CAP |
109286 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION__SHIFT 0x0 |
109287 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
109288 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
109289 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
109290 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION_MASK 0x000FL |
109291 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
109292 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
109293 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
109294 | //BIF_CFG_DEV0_EPF4_2_DEVICE_CAP |
109295 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
109296 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
109297 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
109298 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
109299 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
109300 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
109301 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
109302 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
109303 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
109304 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
109305 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
109306 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
109307 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
109308 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
109309 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
109310 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
109311 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
109312 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
109313 | //BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL |
109314 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
109315 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
109316 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
109317 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
109318 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
109319 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
109320 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
109321 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
109322 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
109323 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
109324 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
109325 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
109326 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
109327 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
109328 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
109329 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
109330 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
109331 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
109332 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
109333 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
109334 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
109335 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
109336 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
109337 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
109338 | //BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS |
109339 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
109340 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
109341 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
109342 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
109343 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
109344 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
109345 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
109346 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
109347 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
109348 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
109349 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
109350 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
109351 | //BIF_CFG_DEV0_EPF4_2_LINK_CAP |
109352 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
109353 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
109354 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
109355 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
109356 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
109357 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
109358 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
109359 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
109360 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
109361 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
109362 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
109363 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
109364 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
109365 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
109366 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
109367 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
109368 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
109369 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
109370 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
109371 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
109372 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
109373 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
109374 | //BIF_CFG_DEV0_EPF4_2_LINK_CNTL |
109375 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
109376 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
109377 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
109378 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
109379 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
109380 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
109381 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
109382 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
109383 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
109384 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
109385 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
109386 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
109387 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
109388 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
109389 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
109390 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
109391 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
109392 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
109393 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
109394 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
109395 | //BIF_CFG_DEV0_EPF4_2_LINK_STATUS |
109396 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
109397 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
109398 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
109399 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
109400 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
109401 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
109402 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
109403 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
109404 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
109405 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
109406 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
109407 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
109408 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
109409 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
109410 | //BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2 |
109411 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
109412 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
109413 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
109414 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
109415 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
109416 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
109417 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
109418 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
109419 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
109420 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
109421 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
109422 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
109423 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
109424 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
109425 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
109426 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
109427 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
109428 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
109429 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
109430 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
109431 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
109432 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
109433 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
109434 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
109435 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
109436 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
109437 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
109438 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
109439 | //BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2 |
109440 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
109441 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
109442 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
109443 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
109444 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
109445 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
109446 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
109447 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
109448 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
109449 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
109450 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
109451 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
109452 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
109453 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
109454 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
109455 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
109456 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
109457 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
109458 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
109459 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
109460 | //BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2 |
109461 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
109462 | #define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
109463 | //BIF_CFG_DEV0_EPF4_2_LINK_CAP2 |
109464 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
109465 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
109466 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
109467 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
109468 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
109469 | #define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
109470 | //BIF_CFG_DEV0_EPF4_2_LINK_CNTL2 |
109471 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
109472 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
109473 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
109474 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
109475 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
109476 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
109477 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
109478 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
109479 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
109480 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
109481 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
109482 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
109483 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
109484 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
109485 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
109486 | #define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
109487 | //BIF_CFG_DEV0_EPF4_2_LINK_STATUS2 |
109488 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
109489 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
109490 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
109491 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
109492 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
109493 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
109494 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
109495 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
109496 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
109497 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
109498 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
109499 | #define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
109500 | //BIF_CFG_DEV0_EPF4_2_SLOT_CAP2 |
109501 | #define BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
109502 | #define BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
109503 | //BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2 |
109504 | #define BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
109505 | #define BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
109506 | //BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2 |
109507 | #define BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
109508 | #define BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
109509 | //BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST |
109510 | #define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
109511 | #define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
109512 | #define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
109513 | #define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
109514 | //BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL |
109515 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
109516 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
109517 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
109518 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
109519 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
109520 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
109521 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
109522 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
109523 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
109524 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
109525 | //BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO |
109526 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
109527 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
109528 | //BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI |
109529 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
109530 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
109531 | //BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA |
109532 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
109533 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
109534 | //BIF_CFG_DEV0_EPF4_2_MSI_MASK |
109535 | #define BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
109536 | #define BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
109537 | //BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64 |
109538 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
109539 | #define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
109540 | //BIF_CFG_DEV0_EPF4_2_MSI_MASK_64 |
109541 | #define BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
109542 | #define BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
109543 | //BIF_CFG_DEV0_EPF4_2_MSI_PENDING |
109544 | #define BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
109545 | #define BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
109546 | //BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64 |
109547 | #define BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
109548 | #define BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
109549 | //BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST |
109550 | #define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
109551 | #define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
109552 | #define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
109553 | #define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
109554 | //BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL |
109555 | #define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
109556 | #define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
109557 | #define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
109558 | #define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
109559 | #define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
109560 | #define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
109561 | //BIF_CFG_DEV0_EPF4_2_MSIX_TABLE |
109562 | #define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
109563 | #define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
109564 | #define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
109565 | #define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
109566 | //BIF_CFG_DEV0_EPF4_2_MSIX_PBA |
109567 | #define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
109568 | #define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
109569 | #define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
109570 | #define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
109571 | //BIF_CFG_DEV0_EPF4_2_SATA_CAP_0 |
109572 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
109573 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
109574 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
109575 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
109576 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
109577 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
109578 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
109579 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
109580 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
109581 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
109582 | //BIF_CFG_DEV0_EPF4_2_SATA_CAP_1 |
109583 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
109584 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
109585 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
109586 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
109587 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
109588 | #define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
109589 | //BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX |
109590 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
109591 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
109592 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
109593 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
109594 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
109595 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
109596 | //BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA |
109597 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
109598 | #define BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
109599 | //BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
109600 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109601 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109602 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109603 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109604 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109605 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109606 | //BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR |
109607 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
109608 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
109609 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
109610 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
109611 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
109612 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
109613 | //BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1 |
109614 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
109615 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
109616 | //BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2 |
109617 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
109618 | #define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
109619 | //BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
109620 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109621 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109622 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109623 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109624 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109625 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109626 | //BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS |
109627 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
109628 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
109629 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
109630 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
109631 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
109632 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
109633 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
109634 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
109635 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
109636 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
109637 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
109638 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
109639 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
109640 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
109641 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
109642 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
109643 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
109644 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
109645 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
109646 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
109647 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
109648 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
109649 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
109650 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
109651 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
109652 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
109653 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
109654 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
109655 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
109656 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
109657 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
109658 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
109659 | //BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK |
109660 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
109661 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
109662 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
109663 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
109664 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
109665 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
109666 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
109667 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
109668 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
109669 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
109670 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
109671 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
109672 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
109673 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
109674 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
109675 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
109676 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
109677 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
109678 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
109679 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
109680 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
109681 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
109682 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
109683 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
109684 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
109685 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
109686 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
109687 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
109688 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
109689 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
109690 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
109691 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
109692 | //BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY |
109693 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
109694 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
109695 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
109696 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
109697 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
109698 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
109699 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
109700 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
109701 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
109702 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
109703 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
109704 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
109705 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
109706 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
109707 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
109708 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
109709 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
109710 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
109711 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
109712 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
109713 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
109714 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
109715 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
109716 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
109717 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
109718 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
109719 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
109720 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
109721 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
109722 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
109723 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
109724 | #define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
109725 | //BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS |
109726 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
109727 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
109728 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
109729 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
109730 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
109731 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
109732 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
109733 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
109734 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
109735 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
109736 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
109737 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
109738 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
109739 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
109740 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
109741 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
109742 | //BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK |
109743 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
109744 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
109745 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
109746 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
109747 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
109748 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
109749 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
109750 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
109751 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
109752 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
109753 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
109754 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
109755 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
109756 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
109757 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
109758 | #define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
109759 | //BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL |
109760 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
109761 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
109762 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
109763 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
109764 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
109765 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
109766 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
109767 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
109768 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
109769 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
109770 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
109771 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
109772 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
109773 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
109774 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
109775 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
109776 | //BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0 |
109777 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
109778 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
109779 | //BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1 |
109780 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
109781 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
109782 | //BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2 |
109783 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
109784 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
109785 | //BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3 |
109786 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
109787 | #define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
109788 | //BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0 |
109789 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
109790 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
109791 | //BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1 |
109792 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
109793 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
109794 | //BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2 |
109795 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
109796 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
109797 | //BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3 |
109798 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
109799 | #define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
109800 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST |
109801 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109802 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109803 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109804 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109805 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109806 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109807 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP |
109808 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
109809 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
109810 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL |
109811 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
109812 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
109813 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
109814 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
109815 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
109816 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
109817 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP |
109818 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
109819 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
109820 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL |
109821 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
109822 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
109823 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
109824 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
109825 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
109826 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
109827 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP |
109828 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
109829 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
109830 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL |
109831 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
109832 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
109833 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
109834 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
109835 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
109836 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
109837 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP |
109838 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
109839 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
109840 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL |
109841 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
109842 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
109843 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
109844 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
109845 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
109846 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
109847 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP |
109848 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
109849 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
109850 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL |
109851 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
109852 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
109853 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
109854 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
109855 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
109856 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
109857 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP |
109858 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
109859 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
109860 | //BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL |
109861 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
109862 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
109863 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
109864 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
109865 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
109866 | #define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
109867 | //BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
109868 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109869 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109870 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109871 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109872 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109873 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109874 | //BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT |
109875 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
109876 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
109877 | //BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA |
109878 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
109879 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
109880 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
109881 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
109882 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
109883 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
109884 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
109885 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
109886 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
109887 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
109888 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
109889 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
109890 | //BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP |
109891 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
109892 | #define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
109893 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST |
109894 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109895 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109896 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109897 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109898 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109899 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109900 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP |
109901 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
109902 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
109903 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
109904 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
109905 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
109906 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
109907 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
109908 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
109909 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
109910 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
109911 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR |
109912 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
109913 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
109914 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS |
109915 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
109916 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
109917 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
109918 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
109919 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL |
109920 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
109921 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
109922 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
109923 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109924 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109925 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
109926 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109927 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109928 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
109929 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109930 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109931 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
109932 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109933 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109934 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
109935 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109936 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109937 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
109938 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109939 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109940 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
109941 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109942 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109943 | //BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
109944 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
109945 | #define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
109946 | //BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST |
109947 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109948 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109949 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109950 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109951 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109952 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109953 | //BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP |
109954 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
109955 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
109956 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
109957 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
109958 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
109959 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
109960 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
109961 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
109962 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
109963 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
109964 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
109965 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
109966 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
109967 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
109968 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
109969 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
109970 | //BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL |
109971 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
109972 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
109973 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
109974 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
109975 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
109976 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
109977 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
109978 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
109979 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
109980 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
109981 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
109982 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
109983 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
109984 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
109985 | //BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST |
109986 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
109987 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
109988 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
109989 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
109990 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
109991 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
109992 | //BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP |
109993 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
109994 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
109995 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
109996 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
109997 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
109998 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
109999 | //BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL |
110000 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
110001 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
110002 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
110003 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
110004 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
110005 | #define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
110006 | |
110007 | |
110008 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
110009 | //BIF_CFG_DEV0_EPF5_2_VENDOR_ID |
110010 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
110011 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
110012 | //BIF_CFG_DEV0_EPF5_2_DEVICE_ID |
110013 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
110014 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
110015 | //BIF_CFG_DEV0_EPF5_2_COMMAND |
110016 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
110017 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
110018 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
110019 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
110020 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
110021 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
110022 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
110023 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
110024 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN__SHIFT 0x8 |
110025 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
110026 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS__SHIFT 0xa |
110027 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
110028 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
110029 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
110030 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
110031 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
110032 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
110033 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
110034 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING_MASK 0x0080L |
110035 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN_MASK 0x0100L |
110036 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
110037 | #define BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS_MASK 0x0400L |
110038 | //BIF_CFG_DEV0_EPF5_2_STATUS |
110039 | #define BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS__SHIFT 0x3 |
110040 | #define BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST__SHIFT 0x4 |
110041 | #define BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN__SHIFT 0x5 |
110042 | #define BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
110043 | #define BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
110044 | #define BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
110045 | #define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
110046 | #define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
110047 | #define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
110048 | #define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
110049 | #define BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
110050 | #define BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS_MASK 0x0008L |
110051 | #define BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST_MASK 0x0010L |
110052 | #define BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN_MASK 0x0020L |
110053 | #define BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
110054 | #define BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
110055 | #define BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
110056 | #define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
110057 | #define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
110058 | #define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
110059 | #define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
110060 | #define BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
110061 | //BIF_CFG_DEV0_EPF5_2_REVISION_ID |
110062 | #define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
110063 | #define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
110064 | #define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
110065 | #define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
110066 | //BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE |
110067 | #define BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
110068 | #define BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
110069 | //BIF_CFG_DEV0_EPF5_2_SUB_CLASS |
110070 | #define BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
110071 | #define BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
110072 | //BIF_CFG_DEV0_EPF5_2_BASE_CLASS |
110073 | #define BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
110074 | #define BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
110075 | //BIF_CFG_DEV0_EPF5_2_CACHE_LINE |
110076 | #define BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
110077 | #define BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
110078 | //BIF_CFG_DEV0_EPF5_2_LATENCY |
110079 | #define BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
110080 | #define BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
110081 | //BIF_CFG_DEV0_EPF5_2_HEADER |
110082 | #define BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
110083 | #define BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
110084 | #define BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE_MASK 0x7FL |
110085 | #define BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE_MASK 0x80L |
110086 | //BIF_CFG_DEV0_EPF5_2_BIST |
110087 | #define BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP__SHIFT 0x0 |
110088 | #define BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT__SHIFT 0x6 |
110089 | #define BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP__SHIFT 0x7 |
110090 | #define BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP_MASK 0x0FL |
110091 | #define BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT_MASK 0x40L |
110092 | #define BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP_MASK 0x80L |
110093 | //BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1 |
110094 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
110095 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
110096 | //BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2 |
110097 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
110098 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
110099 | //BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3 |
110100 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
110101 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
110102 | //BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4 |
110103 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
110104 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
110105 | //BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5 |
110106 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
110107 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
110108 | //BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6 |
110109 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
110110 | #define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
110111 | //BIF_CFG_DEV0_EPF5_2_ADAPTER_ID |
110112 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
110113 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
110114 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
110115 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
110116 | //BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR |
110117 | #define BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
110118 | #define BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
110119 | //BIF_CFG_DEV0_EPF5_2_CAP_PTR |
110120 | #define BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
110121 | #define BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
110122 | //BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE |
110123 | #define BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
110124 | #define BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
110125 | //BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN |
110126 | #define BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
110127 | #define BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
110128 | //BIF_CFG_DEV0_EPF5_2_MIN_GRANT |
110129 | #define BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
110130 | #define BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
110131 | //BIF_CFG_DEV0_EPF5_2_MAX_LATENCY |
110132 | #define BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
110133 | #define BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
110134 | //BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST |
110135 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
110136 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
110137 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
110138 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
110139 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
110140 | #define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
110141 | //BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W |
110142 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
110143 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
110144 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
110145 | #define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
110146 | //BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST |
110147 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
110148 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
110149 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
110150 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
110151 | //BIF_CFG_DEV0_EPF5_2_PMI_CAP |
110152 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION__SHIFT 0x0 |
110153 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
110154 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
110155 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
110156 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
110157 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
110158 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
110159 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION_MASK 0x0007L |
110160 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
110161 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
110162 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
110163 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
110164 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
110165 | #define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
110166 | //BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL |
110167 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
110168 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
110169 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
110170 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
110171 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
110172 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
110173 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
110174 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
110175 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
110176 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
110177 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
110178 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
110179 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
110180 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
110181 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
110182 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
110183 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
110184 | #define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
110185 | //BIF_CFG_DEV0_EPF5_2_SBRN |
110186 | #define BIF_CFG_DEV0_EPF5_2_SBRN__SBRN__SHIFT 0x0 |
110187 | #define BIF_CFG_DEV0_EPF5_2_SBRN__SBRN_MASK 0xFFL |
110188 | //BIF_CFG_DEV0_EPF5_2_FLADJ |
110189 | #define BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ__SHIFT 0x0 |
110190 | #define BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ_MASK 0x3FL |
110191 | //BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD |
110192 | #define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
110193 | #define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
110194 | #define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
110195 | #define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
110196 | //BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST |
110197 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
110198 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
110199 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
110200 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
110201 | //BIF_CFG_DEV0_EPF5_2_PCIE_CAP |
110202 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION__SHIFT 0x0 |
110203 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
110204 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
110205 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
110206 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION_MASK 0x000FL |
110207 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
110208 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
110209 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
110210 | //BIF_CFG_DEV0_EPF5_2_DEVICE_CAP |
110211 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
110212 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
110213 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
110214 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
110215 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
110216 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
110217 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
110218 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
110219 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
110220 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
110221 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
110222 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
110223 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
110224 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
110225 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
110226 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
110227 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
110228 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
110229 | //BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL |
110230 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
110231 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
110232 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
110233 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
110234 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
110235 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
110236 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
110237 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
110238 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
110239 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
110240 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
110241 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
110242 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
110243 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
110244 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
110245 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
110246 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
110247 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
110248 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
110249 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
110250 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
110251 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
110252 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
110253 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
110254 | //BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS |
110255 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
110256 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
110257 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
110258 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
110259 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
110260 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
110261 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
110262 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
110263 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
110264 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
110265 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
110266 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
110267 | //BIF_CFG_DEV0_EPF5_2_LINK_CAP |
110268 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
110269 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
110270 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
110271 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
110272 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
110273 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
110274 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
110275 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
110276 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
110277 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
110278 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
110279 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
110280 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
110281 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
110282 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
110283 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
110284 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
110285 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
110286 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
110287 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
110288 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
110289 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
110290 | //BIF_CFG_DEV0_EPF5_2_LINK_CNTL |
110291 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
110292 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
110293 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
110294 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
110295 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
110296 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
110297 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
110298 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
110299 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
110300 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
110301 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
110302 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
110303 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
110304 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
110305 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
110306 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
110307 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
110308 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
110309 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
110310 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
110311 | //BIF_CFG_DEV0_EPF5_2_LINK_STATUS |
110312 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
110313 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
110314 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
110315 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
110316 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
110317 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
110318 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
110319 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
110320 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
110321 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
110322 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
110323 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
110324 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
110325 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
110326 | //BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2 |
110327 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
110328 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
110329 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
110330 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
110331 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
110332 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
110333 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
110334 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
110335 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
110336 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
110337 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
110338 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
110339 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
110340 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
110341 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
110342 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
110343 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
110344 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
110345 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
110346 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
110347 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
110348 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
110349 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
110350 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
110351 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
110352 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
110353 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
110354 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
110355 | //BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2 |
110356 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
110357 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
110358 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
110359 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
110360 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
110361 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
110362 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
110363 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
110364 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
110365 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
110366 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
110367 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
110368 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
110369 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
110370 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
110371 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
110372 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
110373 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
110374 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
110375 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
110376 | //BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2 |
110377 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
110378 | #define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
110379 | //BIF_CFG_DEV0_EPF5_2_LINK_CAP2 |
110380 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
110381 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
110382 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
110383 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
110384 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
110385 | #define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
110386 | //BIF_CFG_DEV0_EPF5_2_LINK_CNTL2 |
110387 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
110388 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
110389 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
110390 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
110391 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
110392 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
110393 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
110394 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
110395 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
110396 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
110397 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
110398 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
110399 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
110400 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
110401 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
110402 | #define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
110403 | //BIF_CFG_DEV0_EPF5_2_LINK_STATUS2 |
110404 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
110405 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
110406 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
110407 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
110408 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
110409 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
110410 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
110411 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
110412 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
110413 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
110414 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
110415 | #define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
110416 | //BIF_CFG_DEV0_EPF5_2_SLOT_CAP2 |
110417 | #define BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
110418 | #define BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
110419 | //BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2 |
110420 | #define BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
110421 | #define BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
110422 | //BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2 |
110423 | #define BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
110424 | #define BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
110425 | //BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST |
110426 | #define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
110427 | #define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
110428 | #define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
110429 | #define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
110430 | //BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL |
110431 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
110432 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
110433 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
110434 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
110435 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
110436 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
110437 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
110438 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
110439 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
110440 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
110441 | //BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO |
110442 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
110443 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
110444 | //BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI |
110445 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
110446 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
110447 | //BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA |
110448 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
110449 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
110450 | //BIF_CFG_DEV0_EPF5_2_MSI_MASK |
110451 | #define BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
110452 | #define BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
110453 | //BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64 |
110454 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
110455 | #define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
110456 | //BIF_CFG_DEV0_EPF5_2_MSI_MASK_64 |
110457 | #define BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
110458 | #define BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
110459 | //BIF_CFG_DEV0_EPF5_2_MSI_PENDING |
110460 | #define BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
110461 | #define BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
110462 | //BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64 |
110463 | #define BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
110464 | #define BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
110465 | //BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST |
110466 | #define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
110467 | #define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
110468 | #define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
110469 | #define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
110470 | //BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL |
110471 | #define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
110472 | #define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
110473 | #define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
110474 | #define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
110475 | #define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
110476 | #define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
110477 | //BIF_CFG_DEV0_EPF5_2_MSIX_TABLE |
110478 | #define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
110479 | #define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
110480 | #define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
110481 | #define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
110482 | //BIF_CFG_DEV0_EPF5_2_MSIX_PBA |
110483 | #define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
110484 | #define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
110485 | #define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
110486 | #define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
110487 | //BIF_CFG_DEV0_EPF5_2_SATA_CAP_0 |
110488 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
110489 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
110490 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
110491 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
110492 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
110493 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
110494 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
110495 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
110496 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
110497 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
110498 | //BIF_CFG_DEV0_EPF5_2_SATA_CAP_1 |
110499 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
110500 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
110501 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
110502 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
110503 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
110504 | #define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
110505 | //BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX |
110506 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
110507 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
110508 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
110509 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
110510 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
110511 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
110512 | //BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA |
110513 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
110514 | #define BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
110515 | //BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
110516 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110517 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110518 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110519 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110520 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110521 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110522 | //BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR |
110523 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
110524 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
110525 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
110526 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
110527 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
110528 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
110529 | //BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1 |
110530 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
110531 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
110532 | //BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2 |
110533 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
110534 | #define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
110535 | //BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
110536 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110537 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110538 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110539 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110540 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110541 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110542 | //BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS |
110543 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
110544 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
110545 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
110546 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
110547 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
110548 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
110549 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
110550 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
110551 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
110552 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
110553 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
110554 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
110555 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
110556 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
110557 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
110558 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
110559 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
110560 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
110561 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
110562 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
110563 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
110564 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
110565 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
110566 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
110567 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
110568 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
110569 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
110570 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
110571 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
110572 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
110573 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
110574 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
110575 | //BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK |
110576 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
110577 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
110578 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
110579 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
110580 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
110581 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
110582 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
110583 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
110584 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
110585 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
110586 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
110587 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
110588 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
110589 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
110590 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
110591 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
110592 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
110593 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
110594 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
110595 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
110596 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
110597 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
110598 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
110599 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
110600 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
110601 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
110602 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
110603 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
110604 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
110605 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
110606 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
110607 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
110608 | //BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY |
110609 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
110610 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
110611 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
110612 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
110613 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
110614 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
110615 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
110616 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
110617 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
110618 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
110619 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
110620 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
110621 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
110622 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
110623 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
110624 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
110625 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
110626 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
110627 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
110628 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
110629 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
110630 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
110631 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
110632 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
110633 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
110634 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
110635 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
110636 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
110637 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
110638 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
110639 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
110640 | #define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
110641 | //BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS |
110642 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
110643 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
110644 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
110645 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
110646 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
110647 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
110648 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
110649 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
110650 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
110651 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
110652 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
110653 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
110654 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
110655 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
110656 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
110657 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
110658 | //BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK |
110659 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
110660 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
110661 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
110662 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
110663 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
110664 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
110665 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
110666 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
110667 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
110668 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
110669 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
110670 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
110671 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
110672 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
110673 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
110674 | #define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
110675 | //BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL |
110676 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
110677 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
110678 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
110679 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
110680 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
110681 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
110682 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
110683 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
110684 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
110685 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
110686 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
110687 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
110688 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
110689 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
110690 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
110691 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
110692 | //BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0 |
110693 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
110694 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
110695 | //BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1 |
110696 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
110697 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
110698 | //BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2 |
110699 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
110700 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
110701 | //BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3 |
110702 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
110703 | #define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
110704 | //BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0 |
110705 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
110706 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
110707 | //BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1 |
110708 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
110709 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
110710 | //BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2 |
110711 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
110712 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
110713 | //BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3 |
110714 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
110715 | #define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
110716 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST |
110717 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110718 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110719 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110720 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110721 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110722 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110723 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP |
110724 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
110725 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
110726 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL |
110727 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
110728 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
110729 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
110730 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
110731 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
110732 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
110733 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP |
110734 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
110735 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
110736 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL |
110737 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
110738 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
110739 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
110740 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
110741 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
110742 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
110743 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP |
110744 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
110745 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
110746 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL |
110747 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
110748 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
110749 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
110750 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
110751 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
110752 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
110753 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP |
110754 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
110755 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
110756 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL |
110757 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
110758 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
110759 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
110760 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
110761 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
110762 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
110763 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP |
110764 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
110765 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
110766 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL |
110767 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
110768 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
110769 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
110770 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
110771 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
110772 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
110773 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP |
110774 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
110775 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
110776 | //BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL |
110777 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
110778 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
110779 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
110780 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
110781 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
110782 | #define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
110783 | //BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
110784 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110785 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110786 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110787 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110788 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110789 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110790 | //BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT |
110791 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
110792 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
110793 | //BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA |
110794 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
110795 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
110796 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
110797 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
110798 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
110799 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
110800 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
110801 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
110802 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
110803 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
110804 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
110805 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
110806 | //BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP |
110807 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
110808 | #define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
110809 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST |
110810 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110811 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110812 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110813 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110814 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110815 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110816 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP |
110817 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
110818 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
110819 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
110820 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
110821 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
110822 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
110823 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
110824 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
110825 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
110826 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
110827 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR |
110828 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
110829 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
110830 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS |
110831 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
110832 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
110833 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
110834 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
110835 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL |
110836 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
110837 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
110838 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
110839 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110840 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110841 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
110842 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110843 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110844 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
110845 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110846 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110847 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
110848 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110849 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110850 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
110851 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110852 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110853 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
110854 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110855 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110856 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
110857 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110858 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110859 | //BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
110860 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
110861 | #define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
110862 | //BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST |
110863 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110864 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110865 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110866 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110867 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110868 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110869 | //BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP |
110870 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
110871 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
110872 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
110873 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
110874 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
110875 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
110876 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
110877 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
110878 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
110879 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
110880 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
110881 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
110882 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
110883 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
110884 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
110885 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
110886 | //BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL |
110887 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
110888 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
110889 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
110890 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
110891 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
110892 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
110893 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
110894 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
110895 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
110896 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
110897 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
110898 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
110899 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
110900 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
110901 | //BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST |
110902 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
110903 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
110904 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
110905 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
110906 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
110907 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
110908 | //BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP |
110909 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
110910 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
110911 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
110912 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
110913 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
110914 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
110915 | //BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL |
110916 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
110917 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
110918 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
110919 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
110920 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
110921 | #define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
110922 | |
110923 | |
110924 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
110925 | //BIF_CFG_DEV0_EPF6_2_VENDOR_ID |
110926 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
110927 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
110928 | //BIF_CFG_DEV0_EPF6_2_DEVICE_ID |
110929 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
110930 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
110931 | //BIF_CFG_DEV0_EPF6_2_COMMAND |
110932 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
110933 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
110934 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
110935 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
110936 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
110937 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
110938 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
110939 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
110940 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN__SHIFT 0x8 |
110941 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
110942 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS__SHIFT 0xa |
110943 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
110944 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
110945 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
110946 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
110947 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
110948 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
110949 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
110950 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING_MASK 0x0080L |
110951 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN_MASK 0x0100L |
110952 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
110953 | #define BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS_MASK 0x0400L |
110954 | //BIF_CFG_DEV0_EPF6_2_STATUS |
110955 | #define BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS__SHIFT 0x3 |
110956 | #define BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST__SHIFT 0x4 |
110957 | #define BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN__SHIFT 0x5 |
110958 | #define BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
110959 | #define BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
110960 | #define BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
110961 | #define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
110962 | #define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
110963 | #define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
110964 | #define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
110965 | #define BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
110966 | #define BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS_MASK 0x0008L |
110967 | #define BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST_MASK 0x0010L |
110968 | #define BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN_MASK 0x0020L |
110969 | #define BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
110970 | #define BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
110971 | #define BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
110972 | #define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
110973 | #define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
110974 | #define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
110975 | #define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
110976 | #define BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
110977 | //BIF_CFG_DEV0_EPF6_2_REVISION_ID |
110978 | #define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
110979 | #define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
110980 | #define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
110981 | #define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
110982 | //BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE |
110983 | #define BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
110984 | #define BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
110985 | //BIF_CFG_DEV0_EPF6_2_SUB_CLASS |
110986 | #define BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
110987 | #define BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
110988 | //BIF_CFG_DEV0_EPF6_2_BASE_CLASS |
110989 | #define BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
110990 | #define BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
110991 | //BIF_CFG_DEV0_EPF6_2_CACHE_LINE |
110992 | #define BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
110993 | #define BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
110994 | //BIF_CFG_DEV0_EPF6_2_LATENCY |
110995 | #define BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
110996 | #define BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
110997 | //BIF_CFG_DEV0_EPF6_2_HEADER |
110998 | #define BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
110999 | #define BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
111000 | #define BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE_MASK 0x7FL |
111001 | #define BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE_MASK 0x80L |
111002 | //BIF_CFG_DEV0_EPF6_2_BIST |
111003 | #define BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP__SHIFT 0x0 |
111004 | #define BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT__SHIFT 0x6 |
111005 | #define BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP__SHIFT 0x7 |
111006 | #define BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP_MASK 0x0FL |
111007 | #define BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT_MASK 0x40L |
111008 | #define BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP_MASK 0x80L |
111009 | //BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1 |
111010 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
111011 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
111012 | //BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2 |
111013 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
111014 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
111015 | //BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3 |
111016 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
111017 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
111018 | //BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4 |
111019 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
111020 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
111021 | //BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5 |
111022 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
111023 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
111024 | //BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6 |
111025 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
111026 | #define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
111027 | //BIF_CFG_DEV0_EPF6_2_ADAPTER_ID |
111028 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
111029 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
111030 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
111031 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
111032 | //BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR |
111033 | #define BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
111034 | #define BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
111035 | //BIF_CFG_DEV0_EPF6_2_CAP_PTR |
111036 | #define BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
111037 | #define BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
111038 | //BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE |
111039 | #define BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
111040 | #define BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
111041 | //BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN |
111042 | #define BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
111043 | #define BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
111044 | //BIF_CFG_DEV0_EPF6_2_MIN_GRANT |
111045 | #define BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
111046 | #define BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
111047 | //BIF_CFG_DEV0_EPF6_2_MAX_LATENCY |
111048 | #define BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
111049 | #define BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
111050 | //BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST |
111051 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
111052 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111053 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
111054 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
111055 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
111056 | #define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
111057 | //BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W |
111058 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
111059 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
111060 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
111061 | #define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
111062 | //BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST |
111063 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
111064 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111065 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
111066 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
111067 | //BIF_CFG_DEV0_EPF6_2_PMI_CAP |
111068 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION__SHIFT 0x0 |
111069 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
111070 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
111071 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
111072 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
111073 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
111074 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
111075 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION_MASK 0x0007L |
111076 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
111077 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
111078 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
111079 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
111080 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
111081 | #define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
111082 | //BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL |
111083 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
111084 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
111085 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
111086 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
111087 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
111088 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
111089 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
111090 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
111091 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
111092 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
111093 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
111094 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
111095 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
111096 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
111097 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
111098 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
111099 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
111100 | #define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
111101 | //BIF_CFG_DEV0_EPF6_2_SBRN |
111102 | #define BIF_CFG_DEV0_EPF6_2_SBRN__SBRN__SHIFT 0x0 |
111103 | #define BIF_CFG_DEV0_EPF6_2_SBRN__SBRN_MASK 0xFFL |
111104 | //BIF_CFG_DEV0_EPF6_2_FLADJ |
111105 | #define BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ__SHIFT 0x0 |
111106 | #define BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ_MASK 0x3FL |
111107 | //BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD |
111108 | #define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
111109 | #define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
111110 | #define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
111111 | #define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
111112 | //BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST |
111113 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
111114 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111115 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
111116 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
111117 | //BIF_CFG_DEV0_EPF6_2_PCIE_CAP |
111118 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION__SHIFT 0x0 |
111119 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
111120 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
111121 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
111122 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION_MASK 0x000FL |
111123 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
111124 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
111125 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
111126 | //BIF_CFG_DEV0_EPF6_2_DEVICE_CAP |
111127 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
111128 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
111129 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
111130 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
111131 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
111132 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
111133 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
111134 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
111135 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
111136 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
111137 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
111138 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
111139 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
111140 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
111141 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
111142 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
111143 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
111144 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
111145 | //BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL |
111146 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
111147 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
111148 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
111149 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
111150 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
111151 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
111152 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
111153 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
111154 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
111155 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
111156 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
111157 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
111158 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
111159 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
111160 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
111161 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
111162 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
111163 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
111164 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
111165 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
111166 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
111167 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
111168 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
111169 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
111170 | //BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS |
111171 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
111172 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
111173 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
111174 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
111175 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
111176 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
111177 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
111178 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
111179 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
111180 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
111181 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
111182 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
111183 | //BIF_CFG_DEV0_EPF6_2_LINK_CAP |
111184 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
111185 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
111186 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
111187 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
111188 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
111189 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
111190 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
111191 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
111192 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
111193 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
111194 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
111195 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
111196 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
111197 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
111198 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
111199 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
111200 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
111201 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
111202 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
111203 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
111204 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
111205 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
111206 | //BIF_CFG_DEV0_EPF6_2_LINK_CNTL |
111207 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
111208 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
111209 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
111210 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
111211 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
111212 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
111213 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
111214 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
111215 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
111216 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
111217 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
111218 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
111219 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
111220 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
111221 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
111222 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
111223 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
111224 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
111225 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
111226 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
111227 | //BIF_CFG_DEV0_EPF6_2_LINK_STATUS |
111228 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
111229 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
111230 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
111231 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
111232 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
111233 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
111234 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
111235 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
111236 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
111237 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
111238 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
111239 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
111240 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
111241 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
111242 | //BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2 |
111243 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
111244 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
111245 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
111246 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
111247 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
111248 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
111249 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
111250 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
111251 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
111252 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
111253 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
111254 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
111255 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
111256 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
111257 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
111258 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
111259 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
111260 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
111261 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
111262 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
111263 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
111264 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
111265 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
111266 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
111267 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
111268 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
111269 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
111270 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
111271 | //BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2 |
111272 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
111273 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
111274 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
111275 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
111276 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
111277 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
111278 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
111279 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
111280 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
111281 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
111282 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
111283 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
111284 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
111285 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
111286 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
111287 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
111288 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
111289 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
111290 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
111291 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
111292 | //BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2 |
111293 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
111294 | #define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
111295 | //BIF_CFG_DEV0_EPF6_2_LINK_CAP2 |
111296 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
111297 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
111298 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
111299 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
111300 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
111301 | #define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
111302 | //BIF_CFG_DEV0_EPF6_2_LINK_CNTL2 |
111303 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
111304 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
111305 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
111306 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
111307 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
111308 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
111309 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
111310 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
111311 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
111312 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
111313 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
111314 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
111315 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
111316 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
111317 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
111318 | #define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
111319 | //BIF_CFG_DEV0_EPF6_2_LINK_STATUS2 |
111320 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
111321 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
111322 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
111323 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
111324 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
111325 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
111326 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
111327 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
111328 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
111329 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
111330 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
111331 | #define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
111332 | //BIF_CFG_DEV0_EPF6_2_SLOT_CAP2 |
111333 | #define BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
111334 | #define BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
111335 | //BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2 |
111336 | #define BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
111337 | #define BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
111338 | //BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2 |
111339 | #define BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
111340 | #define BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
111341 | //BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST |
111342 | #define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
111343 | #define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111344 | #define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
111345 | #define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
111346 | //BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL |
111347 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
111348 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
111349 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
111350 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
111351 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
111352 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
111353 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
111354 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
111355 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
111356 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
111357 | //BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO |
111358 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
111359 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
111360 | //BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI |
111361 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
111362 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
111363 | //BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA |
111364 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
111365 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
111366 | //BIF_CFG_DEV0_EPF6_2_MSI_MASK |
111367 | #define BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
111368 | #define BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
111369 | //BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64 |
111370 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
111371 | #define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
111372 | //BIF_CFG_DEV0_EPF6_2_MSI_MASK_64 |
111373 | #define BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
111374 | #define BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
111375 | //BIF_CFG_DEV0_EPF6_2_MSI_PENDING |
111376 | #define BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
111377 | #define BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
111378 | //BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64 |
111379 | #define BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
111380 | #define BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
111381 | //BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST |
111382 | #define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
111383 | #define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111384 | #define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
111385 | #define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
111386 | //BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL |
111387 | #define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
111388 | #define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
111389 | #define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
111390 | #define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
111391 | #define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
111392 | #define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
111393 | //BIF_CFG_DEV0_EPF6_2_MSIX_TABLE |
111394 | #define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
111395 | #define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
111396 | #define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
111397 | #define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
111398 | //BIF_CFG_DEV0_EPF6_2_MSIX_PBA |
111399 | #define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
111400 | #define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
111401 | #define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
111402 | #define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
111403 | //BIF_CFG_DEV0_EPF6_2_SATA_CAP_0 |
111404 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
111405 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
111406 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
111407 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
111408 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
111409 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
111410 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
111411 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
111412 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
111413 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
111414 | //BIF_CFG_DEV0_EPF6_2_SATA_CAP_1 |
111415 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
111416 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
111417 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
111418 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
111419 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
111420 | #define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
111421 | //BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX |
111422 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
111423 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
111424 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
111425 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
111426 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
111427 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
111428 | //BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA |
111429 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
111430 | #define BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
111431 | //BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
111432 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111433 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111434 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111435 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111436 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111437 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111438 | //BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR |
111439 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
111440 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
111441 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
111442 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
111443 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
111444 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
111445 | //BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1 |
111446 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
111447 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
111448 | //BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2 |
111449 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
111450 | #define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
111451 | //BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
111452 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111453 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111454 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111455 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111456 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111457 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111458 | //BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS |
111459 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
111460 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
111461 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
111462 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
111463 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
111464 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
111465 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
111466 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
111467 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
111468 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
111469 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
111470 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
111471 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
111472 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
111473 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
111474 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
111475 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
111476 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
111477 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
111478 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
111479 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
111480 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
111481 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
111482 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
111483 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
111484 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
111485 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
111486 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
111487 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
111488 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
111489 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
111490 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
111491 | //BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK |
111492 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
111493 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
111494 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
111495 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
111496 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
111497 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
111498 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
111499 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
111500 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
111501 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
111502 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
111503 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
111504 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
111505 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
111506 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
111507 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
111508 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
111509 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
111510 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
111511 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
111512 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
111513 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
111514 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
111515 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
111516 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
111517 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
111518 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
111519 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
111520 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
111521 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
111522 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
111523 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
111524 | //BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY |
111525 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
111526 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
111527 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
111528 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
111529 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
111530 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
111531 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
111532 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
111533 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
111534 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
111535 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
111536 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
111537 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
111538 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
111539 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
111540 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
111541 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
111542 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
111543 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
111544 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
111545 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
111546 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
111547 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
111548 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
111549 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
111550 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
111551 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
111552 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
111553 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
111554 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
111555 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
111556 | #define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
111557 | //BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS |
111558 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
111559 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
111560 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
111561 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
111562 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
111563 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
111564 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
111565 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
111566 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
111567 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
111568 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
111569 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
111570 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
111571 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
111572 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
111573 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
111574 | //BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK |
111575 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
111576 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
111577 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
111578 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
111579 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
111580 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
111581 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
111582 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
111583 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
111584 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
111585 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
111586 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
111587 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
111588 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
111589 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
111590 | #define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
111591 | //BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL |
111592 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
111593 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
111594 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
111595 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
111596 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
111597 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
111598 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
111599 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
111600 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
111601 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
111602 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
111603 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
111604 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
111605 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
111606 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
111607 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
111608 | //BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0 |
111609 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
111610 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
111611 | //BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1 |
111612 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
111613 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
111614 | //BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2 |
111615 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
111616 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
111617 | //BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3 |
111618 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
111619 | #define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
111620 | //BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0 |
111621 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
111622 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
111623 | //BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1 |
111624 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
111625 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
111626 | //BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2 |
111627 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
111628 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
111629 | //BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3 |
111630 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
111631 | #define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
111632 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST |
111633 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111634 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111635 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111636 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111637 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111638 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111639 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP |
111640 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
111641 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
111642 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL |
111643 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
111644 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
111645 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
111646 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
111647 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
111648 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
111649 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP |
111650 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
111651 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
111652 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL |
111653 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
111654 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
111655 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
111656 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
111657 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
111658 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
111659 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP |
111660 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
111661 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
111662 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL |
111663 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
111664 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
111665 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
111666 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
111667 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
111668 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
111669 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP |
111670 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
111671 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
111672 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL |
111673 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
111674 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
111675 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
111676 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
111677 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
111678 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
111679 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP |
111680 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
111681 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
111682 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL |
111683 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
111684 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
111685 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
111686 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
111687 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
111688 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
111689 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP |
111690 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
111691 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
111692 | //BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL |
111693 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
111694 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
111695 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
111696 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
111697 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
111698 | #define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
111699 | //BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
111700 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111701 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111702 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111703 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111704 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111705 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111706 | //BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT |
111707 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
111708 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
111709 | //BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA |
111710 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
111711 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
111712 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
111713 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
111714 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
111715 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
111716 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
111717 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
111718 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
111719 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
111720 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
111721 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
111722 | //BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP |
111723 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
111724 | #define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
111725 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST |
111726 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111727 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111728 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111729 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111730 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111731 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111732 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP |
111733 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
111734 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
111735 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
111736 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
111737 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
111738 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
111739 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
111740 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
111741 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
111742 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
111743 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR |
111744 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
111745 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
111746 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS |
111747 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
111748 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
111749 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
111750 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
111751 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL |
111752 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
111753 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
111754 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
111755 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111756 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111757 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
111758 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111759 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111760 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
111761 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111762 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111763 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
111764 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111765 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111766 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
111767 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111768 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111769 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
111770 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111771 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111772 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
111773 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111774 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111775 | //BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
111776 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
111777 | #define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
111778 | //BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST |
111779 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111780 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111781 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111782 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111783 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111784 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111785 | //BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP |
111786 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
111787 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
111788 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
111789 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
111790 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
111791 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
111792 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
111793 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
111794 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
111795 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
111796 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
111797 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
111798 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
111799 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
111800 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
111801 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
111802 | //BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL |
111803 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
111804 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
111805 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
111806 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
111807 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
111808 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
111809 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
111810 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
111811 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
111812 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
111813 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
111814 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
111815 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
111816 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
111817 | //BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST |
111818 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
111819 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
111820 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
111821 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
111822 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
111823 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
111824 | //BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP |
111825 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
111826 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
111827 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
111828 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
111829 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
111830 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
111831 | //BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL |
111832 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
111833 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
111834 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
111835 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
111836 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
111837 | #define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
111838 | |
111839 | |
111840 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
111841 | //BIF_CFG_DEV0_EPF7_2_VENDOR_ID |
111842 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
111843 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
111844 | //BIF_CFG_DEV0_EPF7_2_DEVICE_ID |
111845 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
111846 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
111847 | //BIF_CFG_DEV0_EPF7_2_COMMAND |
111848 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
111849 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
111850 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
111851 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
111852 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
111853 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
111854 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
111855 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
111856 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN__SHIFT 0x8 |
111857 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
111858 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS__SHIFT 0xa |
111859 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
111860 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
111861 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
111862 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
111863 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
111864 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
111865 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
111866 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING_MASK 0x0080L |
111867 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN_MASK 0x0100L |
111868 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
111869 | #define BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS_MASK 0x0400L |
111870 | //BIF_CFG_DEV0_EPF7_2_STATUS |
111871 | #define BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS__SHIFT 0x3 |
111872 | #define BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST__SHIFT 0x4 |
111873 | #define BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN__SHIFT 0x5 |
111874 | #define BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
111875 | #define BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
111876 | #define BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
111877 | #define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
111878 | #define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
111879 | #define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
111880 | #define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
111881 | #define BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
111882 | #define BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS_MASK 0x0008L |
111883 | #define BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST_MASK 0x0010L |
111884 | #define BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN_MASK 0x0020L |
111885 | #define BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
111886 | #define BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
111887 | #define BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
111888 | #define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
111889 | #define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
111890 | #define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
111891 | #define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
111892 | #define BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
111893 | //BIF_CFG_DEV0_EPF7_2_REVISION_ID |
111894 | #define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
111895 | #define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
111896 | #define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
111897 | #define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
111898 | //BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE |
111899 | #define BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
111900 | #define BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
111901 | //BIF_CFG_DEV0_EPF7_2_SUB_CLASS |
111902 | #define BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
111903 | #define BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
111904 | //BIF_CFG_DEV0_EPF7_2_BASE_CLASS |
111905 | #define BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
111906 | #define BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
111907 | //BIF_CFG_DEV0_EPF7_2_CACHE_LINE |
111908 | #define BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
111909 | #define BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
111910 | //BIF_CFG_DEV0_EPF7_2_LATENCY |
111911 | #define BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
111912 | #define BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
111913 | //BIF_CFG_DEV0_EPF7_2_HEADER |
111914 | #define BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
111915 | #define BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
111916 | #define BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE_MASK 0x7FL |
111917 | #define BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE_MASK 0x80L |
111918 | //BIF_CFG_DEV0_EPF7_2_BIST |
111919 | #define BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP__SHIFT 0x0 |
111920 | #define BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT__SHIFT 0x6 |
111921 | #define BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP__SHIFT 0x7 |
111922 | #define BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP_MASK 0x0FL |
111923 | #define BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT_MASK 0x40L |
111924 | #define BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP_MASK 0x80L |
111925 | //BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1 |
111926 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
111927 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
111928 | //BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2 |
111929 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
111930 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
111931 | //BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3 |
111932 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
111933 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
111934 | //BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4 |
111935 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
111936 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
111937 | //BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5 |
111938 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
111939 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
111940 | //BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6 |
111941 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
111942 | #define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
111943 | //BIF_CFG_DEV0_EPF7_2_ADAPTER_ID |
111944 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
111945 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
111946 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
111947 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
111948 | //BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR |
111949 | #define BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
111950 | #define BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
111951 | //BIF_CFG_DEV0_EPF7_2_CAP_PTR |
111952 | #define BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
111953 | #define BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
111954 | //BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE |
111955 | #define BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
111956 | #define BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
111957 | //BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN |
111958 | #define BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
111959 | #define BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
111960 | //BIF_CFG_DEV0_EPF7_2_MIN_GRANT |
111961 | #define BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
111962 | #define BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
111963 | //BIF_CFG_DEV0_EPF7_2_MAX_LATENCY |
111964 | #define BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
111965 | #define BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
111966 | //BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST |
111967 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
111968 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111969 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
111970 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
111971 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
111972 | #define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
111973 | //BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W |
111974 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
111975 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
111976 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
111977 | #define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
111978 | //BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST |
111979 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
111980 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
111981 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
111982 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
111983 | //BIF_CFG_DEV0_EPF7_2_PMI_CAP |
111984 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION__SHIFT 0x0 |
111985 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
111986 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
111987 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
111988 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
111989 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
111990 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
111991 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION_MASK 0x0007L |
111992 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
111993 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
111994 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
111995 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
111996 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
111997 | #define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
111998 | //BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL |
111999 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
112000 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
112001 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
112002 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
112003 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
112004 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
112005 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
112006 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
112007 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
112008 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
112009 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
112010 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
112011 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
112012 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
112013 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
112014 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
112015 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
112016 | #define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
112017 | //BIF_CFG_DEV0_EPF7_2_SBRN |
112018 | #define BIF_CFG_DEV0_EPF7_2_SBRN__SBRN__SHIFT 0x0 |
112019 | #define BIF_CFG_DEV0_EPF7_2_SBRN__SBRN_MASK 0xFFL |
112020 | //BIF_CFG_DEV0_EPF7_2_FLADJ |
112021 | #define BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ__SHIFT 0x0 |
112022 | #define BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ_MASK 0x3FL |
112023 | //BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD |
112024 | #define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
112025 | #define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
112026 | #define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
112027 | #define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
112028 | //BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST |
112029 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
112030 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
112031 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
112032 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
112033 | //BIF_CFG_DEV0_EPF7_2_PCIE_CAP |
112034 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION__SHIFT 0x0 |
112035 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
112036 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
112037 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
112038 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION_MASK 0x000FL |
112039 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
112040 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
112041 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
112042 | //BIF_CFG_DEV0_EPF7_2_DEVICE_CAP |
112043 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
112044 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
112045 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
112046 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
112047 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
112048 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
112049 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
112050 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
112051 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
112052 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
112053 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
112054 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
112055 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
112056 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
112057 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
112058 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
112059 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
112060 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
112061 | //BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL |
112062 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
112063 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
112064 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
112065 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
112066 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
112067 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
112068 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
112069 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
112070 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
112071 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
112072 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
112073 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
112074 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
112075 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
112076 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
112077 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
112078 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
112079 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
112080 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
112081 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
112082 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
112083 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
112084 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
112085 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
112086 | //BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS |
112087 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
112088 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
112089 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
112090 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
112091 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
112092 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
112093 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
112094 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
112095 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
112096 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
112097 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
112098 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
112099 | //BIF_CFG_DEV0_EPF7_2_LINK_CAP |
112100 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
112101 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
112102 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
112103 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
112104 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
112105 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
112106 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
112107 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
112108 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
112109 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
112110 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
112111 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
112112 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
112113 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
112114 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
112115 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
112116 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
112117 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
112118 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
112119 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
112120 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
112121 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
112122 | //BIF_CFG_DEV0_EPF7_2_LINK_CNTL |
112123 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
112124 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
112125 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
112126 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
112127 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
112128 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
112129 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
112130 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
112131 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
112132 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
112133 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
112134 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
112135 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
112136 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
112137 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
112138 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
112139 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
112140 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
112141 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
112142 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
112143 | //BIF_CFG_DEV0_EPF7_2_LINK_STATUS |
112144 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
112145 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
112146 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
112147 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
112148 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
112149 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
112150 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
112151 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
112152 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
112153 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
112154 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
112155 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
112156 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
112157 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
112158 | //BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2 |
112159 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
112160 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
112161 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
112162 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
112163 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
112164 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
112165 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
112166 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
112167 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
112168 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
112169 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
112170 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
112171 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
112172 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
112173 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
112174 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
112175 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
112176 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
112177 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
112178 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
112179 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
112180 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
112181 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
112182 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
112183 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
112184 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
112185 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
112186 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
112187 | //BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2 |
112188 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
112189 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
112190 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
112191 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
112192 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
112193 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
112194 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
112195 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
112196 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
112197 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
112198 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
112199 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
112200 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
112201 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
112202 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
112203 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
112204 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
112205 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
112206 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
112207 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
112208 | //BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2 |
112209 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
112210 | #define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
112211 | //BIF_CFG_DEV0_EPF7_2_LINK_CAP2 |
112212 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
112213 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
112214 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
112215 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
112216 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
112217 | #define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
112218 | //BIF_CFG_DEV0_EPF7_2_LINK_CNTL2 |
112219 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
112220 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
112221 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
112222 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
112223 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
112224 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
112225 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
112226 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
112227 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
112228 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
112229 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
112230 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
112231 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
112232 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
112233 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
112234 | #define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
112235 | //BIF_CFG_DEV0_EPF7_2_LINK_STATUS2 |
112236 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
112237 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
112238 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
112239 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
112240 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
112241 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
112242 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
112243 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
112244 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
112245 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
112246 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
112247 | #define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
112248 | //BIF_CFG_DEV0_EPF7_2_SLOT_CAP2 |
112249 | #define BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
112250 | #define BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
112251 | //BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2 |
112252 | #define BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
112253 | #define BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
112254 | //BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2 |
112255 | #define BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
112256 | #define BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
112257 | //BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST |
112258 | #define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
112259 | #define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
112260 | #define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
112261 | #define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
112262 | //BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL |
112263 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
112264 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
112265 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
112266 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
112267 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
112268 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
112269 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
112270 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
112271 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
112272 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
112273 | //BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO |
112274 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
112275 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
112276 | //BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI |
112277 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
112278 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
112279 | //BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA |
112280 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
112281 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
112282 | //BIF_CFG_DEV0_EPF7_2_MSI_MASK |
112283 | #define BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
112284 | #define BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
112285 | //BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64 |
112286 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
112287 | #define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
112288 | //BIF_CFG_DEV0_EPF7_2_MSI_MASK_64 |
112289 | #define BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
112290 | #define BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
112291 | //BIF_CFG_DEV0_EPF7_2_MSI_PENDING |
112292 | #define BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
112293 | #define BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
112294 | //BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64 |
112295 | #define BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
112296 | #define BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
112297 | //BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST |
112298 | #define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
112299 | #define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
112300 | #define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
112301 | #define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
112302 | //BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL |
112303 | #define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
112304 | #define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
112305 | #define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
112306 | #define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
112307 | #define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
112308 | #define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
112309 | //BIF_CFG_DEV0_EPF7_2_MSIX_TABLE |
112310 | #define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
112311 | #define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
112312 | #define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
112313 | #define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
112314 | //BIF_CFG_DEV0_EPF7_2_MSIX_PBA |
112315 | #define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
112316 | #define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
112317 | #define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
112318 | #define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
112319 | //BIF_CFG_DEV0_EPF7_2_SATA_CAP_0 |
112320 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
112321 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
112322 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
112323 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
112324 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
112325 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
112326 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
112327 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
112328 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
112329 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
112330 | //BIF_CFG_DEV0_EPF7_2_SATA_CAP_1 |
112331 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
112332 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
112333 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
112334 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
112335 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
112336 | #define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
112337 | //BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX |
112338 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
112339 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
112340 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
112341 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
112342 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
112343 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
112344 | //BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA |
112345 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
112346 | #define BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
112347 | //BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
112348 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112349 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112350 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112351 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112352 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112353 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112354 | //BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR |
112355 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
112356 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
112357 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
112358 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
112359 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
112360 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
112361 | //BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1 |
112362 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
112363 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
112364 | //BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2 |
112365 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
112366 | #define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
112367 | //BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
112368 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112369 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112370 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112371 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112372 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112373 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112374 | //BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS |
112375 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
112376 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
112377 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
112378 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
112379 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
112380 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
112381 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
112382 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
112383 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
112384 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
112385 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
112386 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
112387 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
112388 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
112389 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
112390 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
112391 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
112392 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
112393 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
112394 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
112395 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
112396 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
112397 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
112398 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
112399 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
112400 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
112401 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
112402 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
112403 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
112404 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
112405 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
112406 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
112407 | //BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK |
112408 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
112409 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
112410 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
112411 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
112412 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
112413 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
112414 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
112415 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
112416 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
112417 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
112418 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
112419 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
112420 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
112421 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
112422 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
112423 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
112424 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
112425 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
112426 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
112427 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
112428 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
112429 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
112430 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
112431 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
112432 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
112433 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
112434 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
112435 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
112436 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
112437 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
112438 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
112439 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
112440 | //BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY |
112441 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
112442 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
112443 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
112444 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
112445 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
112446 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
112447 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
112448 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
112449 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
112450 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
112451 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
112452 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
112453 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
112454 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
112455 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
112456 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
112457 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
112458 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
112459 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
112460 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
112461 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
112462 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
112463 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
112464 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
112465 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
112466 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
112467 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
112468 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
112469 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
112470 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
112471 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
112472 | #define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
112473 | //BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS |
112474 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
112475 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
112476 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
112477 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
112478 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
112479 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
112480 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
112481 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
112482 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
112483 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
112484 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
112485 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
112486 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
112487 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
112488 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
112489 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
112490 | //BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK |
112491 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
112492 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
112493 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
112494 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
112495 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
112496 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
112497 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
112498 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
112499 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
112500 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
112501 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
112502 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
112503 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
112504 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
112505 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
112506 | #define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
112507 | //BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL |
112508 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
112509 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
112510 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
112511 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
112512 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
112513 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
112514 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
112515 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
112516 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
112517 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
112518 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
112519 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
112520 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
112521 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
112522 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
112523 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
112524 | //BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0 |
112525 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
112526 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
112527 | //BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1 |
112528 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
112529 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
112530 | //BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2 |
112531 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
112532 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
112533 | //BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3 |
112534 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
112535 | #define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
112536 | //BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0 |
112537 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
112538 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
112539 | //BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1 |
112540 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
112541 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
112542 | //BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2 |
112543 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
112544 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
112545 | //BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3 |
112546 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
112547 | #define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
112548 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST |
112549 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112550 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112551 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112552 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112553 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112554 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112555 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP |
112556 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
112557 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
112558 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL |
112559 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
112560 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
112561 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
112562 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
112563 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
112564 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
112565 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP |
112566 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
112567 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
112568 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL |
112569 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
112570 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
112571 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
112572 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
112573 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
112574 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
112575 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP |
112576 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
112577 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
112578 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL |
112579 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
112580 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
112581 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
112582 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
112583 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
112584 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
112585 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP |
112586 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
112587 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
112588 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL |
112589 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
112590 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
112591 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
112592 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
112593 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
112594 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
112595 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP |
112596 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
112597 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
112598 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL |
112599 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
112600 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
112601 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
112602 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
112603 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
112604 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
112605 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP |
112606 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
112607 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
112608 | //BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL |
112609 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
112610 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
112611 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
112612 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
112613 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
112614 | #define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
112615 | //BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
112616 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112617 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112618 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112619 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112620 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112621 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112622 | //BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT |
112623 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
112624 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
112625 | //BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA |
112626 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
112627 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
112628 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
112629 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
112630 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
112631 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
112632 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
112633 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
112634 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
112635 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
112636 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
112637 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
112638 | //BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP |
112639 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
112640 | #define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
112641 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST |
112642 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112643 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112644 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112645 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112646 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112647 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112648 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP |
112649 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
112650 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
112651 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
112652 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
112653 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
112654 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
112655 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
112656 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
112657 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
112658 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
112659 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR |
112660 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
112661 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
112662 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS |
112663 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
112664 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
112665 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
112666 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
112667 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL |
112668 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
112669 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
112670 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
112671 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112672 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112673 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
112674 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112675 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112676 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
112677 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112678 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112679 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
112680 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112681 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112682 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
112683 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112684 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112685 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
112686 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112687 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112688 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
112689 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112690 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112691 | //BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
112692 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
112693 | #define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
112694 | //BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST |
112695 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112696 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112697 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112698 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112699 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112700 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112701 | //BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP |
112702 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
112703 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
112704 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
112705 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
112706 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
112707 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
112708 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
112709 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
112710 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
112711 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
112712 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
112713 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
112714 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
112715 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
112716 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
112717 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
112718 | //BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL |
112719 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
112720 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
112721 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
112722 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
112723 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
112724 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
112725 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
112726 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
112727 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
112728 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
112729 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
112730 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
112731 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
112732 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
112733 | //BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST |
112734 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
112735 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
112736 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
112737 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
112738 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
112739 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
112740 | //BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP |
112741 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
112742 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
112743 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
112744 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
112745 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
112746 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
112747 | //BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL |
112748 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
112749 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
112750 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
112751 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
112752 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
112753 | #define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
112754 | |
112755 | |
112756 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
112757 | //BIF_CFG_DEV1_EPF0_2_VENDOR_ID |
112758 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
112759 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
112760 | //BIF_CFG_DEV1_EPF0_2_DEVICE_ID |
112761 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
112762 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
112763 | //BIF_CFG_DEV1_EPF0_2_COMMAND |
112764 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
112765 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
112766 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
112767 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
112768 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
112769 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
112770 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
112771 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
112772 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN__SHIFT 0x8 |
112773 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
112774 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS__SHIFT 0xa |
112775 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
112776 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
112777 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
112778 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
112779 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
112780 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
112781 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
112782 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING_MASK 0x0080L |
112783 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN_MASK 0x0100L |
112784 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
112785 | #define BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS_MASK 0x0400L |
112786 | //BIF_CFG_DEV1_EPF0_2_STATUS |
112787 | #define BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS__SHIFT 0x3 |
112788 | #define BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST__SHIFT 0x4 |
112789 | #define BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN__SHIFT 0x5 |
112790 | #define BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
112791 | #define BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
112792 | #define BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
112793 | #define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
112794 | #define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
112795 | #define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
112796 | #define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
112797 | #define BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
112798 | #define BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS_MASK 0x0008L |
112799 | #define BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST_MASK 0x0010L |
112800 | #define BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN_MASK 0x0020L |
112801 | #define BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
112802 | #define BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
112803 | #define BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
112804 | #define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
112805 | #define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
112806 | #define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
112807 | #define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
112808 | #define BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
112809 | //BIF_CFG_DEV1_EPF0_2_REVISION_ID |
112810 | #define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
112811 | #define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
112812 | #define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
112813 | #define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
112814 | //BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE |
112815 | #define BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
112816 | #define BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
112817 | //BIF_CFG_DEV1_EPF0_2_SUB_CLASS |
112818 | #define BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
112819 | #define BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
112820 | //BIF_CFG_DEV1_EPF0_2_BASE_CLASS |
112821 | #define BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
112822 | #define BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
112823 | //BIF_CFG_DEV1_EPF0_2_CACHE_LINE |
112824 | #define BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
112825 | #define BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
112826 | //BIF_CFG_DEV1_EPF0_2_LATENCY |
112827 | #define BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
112828 | #define BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
112829 | //BIF_CFG_DEV1_EPF0_2_HEADER |
112830 | #define BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
112831 | #define BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
112832 | #define BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE_MASK 0x7FL |
112833 | #define BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE_MASK 0x80L |
112834 | //BIF_CFG_DEV1_EPF0_2_BIST |
112835 | #define BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP__SHIFT 0x0 |
112836 | #define BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT__SHIFT 0x6 |
112837 | #define BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP__SHIFT 0x7 |
112838 | #define BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP_MASK 0x0FL |
112839 | #define BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT_MASK 0x40L |
112840 | #define BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP_MASK 0x80L |
112841 | //BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1 |
112842 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
112843 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
112844 | //BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2 |
112845 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
112846 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
112847 | //BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3 |
112848 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
112849 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
112850 | //BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4 |
112851 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
112852 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
112853 | //BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5 |
112854 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
112855 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
112856 | //BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6 |
112857 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
112858 | #define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
112859 | //BIF_CFG_DEV1_EPF0_2_ADAPTER_ID |
112860 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
112861 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
112862 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
112863 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
112864 | //BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR |
112865 | #define BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
112866 | #define BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
112867 | //BIF_CFG_DEV1_EPF0_2_CAP_PTR |
112868 | #define BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
112869 | #define BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
112870 | //BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE |
112871 | #define BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
112872 | #define BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
112873 | //BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN |
112874 | #define BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
112875 | #define BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
112876 | //BIF_CFG_DEV1_EPF0_2_MIN_GRANT |
112877 | #define BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
112878 | #define BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
112879 | //BIF_CFG_DEV1_EPF0_2_MAX_LATENCY |
112880 | #define BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
112881 | #define BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
112882 | //BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST |
112883 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
112884 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
112885 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
112886 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
112887 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
112888 | #define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
112889 | //BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W |
112890 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
112891 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
112892 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
112893 | #define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
112894 | //BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST |
112895 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
112896 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
112897 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
112898 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
112899 | //BIF_CFG_DEV1_EPF0_2_PMI_CAP |
112900 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION__SHIFT 0x0 |
112901 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
112902 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
112903 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
112904 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
112905 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
112906 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
112907 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION_MASK 0x0007L |
112908 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
112909 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
112910 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
112911 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
112912 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
112913 | #define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
112914 | //BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL |
112915 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
112916 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
112917 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
112918 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
112919 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
112920 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
112921 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
112922 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
112923 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
112924 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
112925 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
112926 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
112927 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
112928 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
112929 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
112930 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
112931 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
112932 | #define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
112933 | //BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST |
112934 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
112935 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
112936 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
112937 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
112938 | //BIF_CFG_DEV1_EPF0_2_PCIE_CAP |
112939 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION__SHIFT 0x0 |
112940 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
112941 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
112942 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
112943 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION_MASK 0x000FL |
112944 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
112945 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
112946 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
112947 | //BIF_CFG_DEV1_EPF0_2_DEVICE_CAP |
112948 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
112949 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
112950 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
112951 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
112952 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
112953 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
112954 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
112955 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
112956 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
112957 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
112958 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
112959 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
112960 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
112961 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
112962 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
112963 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
112964 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
112965 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
112966 | //BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL |
112967 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
112968 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
112969 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
112970 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
112971 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
112972 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
112973 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
112974 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
112975 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
112976 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
112977 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
112978 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
112979 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
112980 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
112981 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
112982 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
112983 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
112984 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
112985 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
112986 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
112987 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
112988 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
112989 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
112990 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
112991 | //BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS |
112992 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
112993 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
112994 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
112995 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
112996 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
112997 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
112998 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
112999 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
113000 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
113001 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
113002 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
113003 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
113004 | //BIF_CFG_DEV1_EPF0_2_LINK_CAP |
113005 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
113006 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
113007 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
113008 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
113009 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
113010 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
113011 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
113012 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
113013 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
113014 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
113015 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
113016 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
113017 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
113018 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
113019 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
113020 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
113021 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
113022 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
113023 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
113024 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
113025 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
113026 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
113027 | //BIF_CFG_DEV1_EPF0_2_LINK_CNTL |
113028 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
113029 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
113030 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
113031 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
113032 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
113033 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
113034 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
113035 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
113036 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
113037 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
113038 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
113039 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
113040 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
113041 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
113042 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
113043 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
113044 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
113045 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
113046 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
113047 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
113048 | //BIF_CFG_DEV1_EPF0_2_LINK_STATUS |
113049 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
113050 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
113051 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
113052 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
113053 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
113054 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
113055 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
113056 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
113057 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
113058 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
113059 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
113060 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
113061 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
113062 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
113063 | //BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2 |
113064 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
113065 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
113066 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
113067 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
113068 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
113069 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
113070 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
113071 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
113072 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
113073 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
113074 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
113075 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
113076 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
113077 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
113078 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
113079 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
113080 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
113081 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
113082 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
113083 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
113084 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
113085 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
113086 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
113087 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
113088 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
113089 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
113090 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
113091 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
113092 | //BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2 |
113093 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
113094 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
113095 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
113096 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
113097 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
113098 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
113099 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
113100 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
113101 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
113102 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
113103 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
113104 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
113105 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
113106 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
113107 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
113108 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
113109 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
113110 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
113111 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
113112 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
113113 | //BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2 |
113114 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
113115 | #define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
113116 | //BIF_CFG_DEV1_EPF0_2_LINK_CAP2 |
113117 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
113118 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
113119 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
113120 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
113121 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
113122 | #define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
113123 | //BIF_CFG_DEV1_EPF0_2_LINK_CNTL2 |
113124 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
113125 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
113126 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
113127 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
113128 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
113129 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
113130 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
113131 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
113132 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
113133 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
113134 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
113135 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
113136 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
113137 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
113138 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
113139 | #define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
113140 | //BIF_CFG_DEV1_EPF0_2_LINK_STATUS2 |
113141 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
113142 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
113143 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
113144 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
113145 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
113146 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
113147 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
113148 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
113149 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
113150 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
113151 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
113152 | #define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
113153 | //BIF_CFG_DEV1_EPF0_2_SLOT_CAP2 |
113154 | #define BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
113155 | #define BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
113156 | //BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2 |
113157 | #define BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
113158 | #define BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
113159 | //BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2 |
113160 | #define BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
113161 | #define BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
113162 | //BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST |
113163 | #define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
113164 | #define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
113165 | #define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
113166 | #define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
113167 | //BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL |
113168 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
113169 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
113170 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
113171 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
113172 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
113173 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
113174 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
113175 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
113176 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
113177 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
113178 | //BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO |
113179 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
113180 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
113181 | //BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI |
113182 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
113183 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
113184 | //BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA |
113185 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
113186 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
113187 | //BIF_CFG_DEV1_EPF0_2_MSI_MASK |
113188 | #define BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
113189 | #define BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
113190 | //BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64 |
113191 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
113192 | #define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
113193 | //BIF_CFG_DEV1_EPF0_2_MSI_MASK_64 |
113194 | #define BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
113195 | #define BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
113196 | //BIF_CFG_DEV1_EPF0_2_MSI_PENDING |
113197 | #define BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
113198 | #define BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
113199 | //BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64 |
113200 | #define BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
113201 | #define BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
113202 | //BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST |
113203 | #define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
113204 | #define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
113205 | #define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
113206 | #define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
113207 | //BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL |
113208 | #define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
113209 | #define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
113210 | #define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
113211 | #define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
113212 | #define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
113213 | #define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
113214 | //BIF_CFG_DEV1_EPF0_2_MSIX_TABLE |
113215 | #define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
113216 | #define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
113217 | #define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
113218 | #define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
113219 | //BIF_CFG_DEV1_EPF0_2_MSIX_PBA |
113220 | #define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
113221 | #define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
113222 | #define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
113223 | #define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
113224 | //BIF_CFG_DEV1_EPF0_2_SATA_CAP_0 |
113225 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
113226 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
113227 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
113228 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
113229 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
113230 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
113231 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
113232 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
113233 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
113234 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
113235 | //BIF_CFG_DEV1_EPF0_2_SATA_CAP_1 |
113236 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
113237 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
113238 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
113239 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
113240 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
113241 | #define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
113242 | //BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX |
113243 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
113244 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
113245 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
113246 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
113247 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
113248 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
113249 | //BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA |
113250 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
113251 | #define BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
113252 | //BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
113253 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113254 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113255 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113256 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113257 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113258 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113259 | //BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR |
113260 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
113261 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
113262 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
113263 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
113264 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
113265 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
113266 | //BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1 |
113267 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
113268 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
113269 | //BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2 |
113270 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
113271 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
113272 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST |
113273 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113274 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113275 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113276 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113277 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113278 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113279 | //BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1 |
113280 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
113281 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
113282 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
113283 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
113284 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
113285 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
113286 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
113287 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
113288 | //BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2 |
113289 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
113290 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
113291 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
113292 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
113293 | //BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL |
113294 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
113295 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
113296 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
113297 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
113298 | //BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS |
113299 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
113300 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
113301 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP |
113302 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
113303 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
113304 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
113305 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
113306 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
113307 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
113308 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
113309 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
113310 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL |
113311 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
113312 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
113313 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
113314 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
113315 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
113316 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
113317 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
113318 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
113319 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
113320 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
113321 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
113322 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
113323 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS |
113324 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
113325 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
113326 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
113327 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
113328 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP |
113329 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
113330 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
113331 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
113332 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
113333 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
113334 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
113335 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
113336 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
113337 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL |
113338 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
113339 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
113340 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
113341 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
113342 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
113343 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
113344 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
113345 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
113346 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
113347 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
113348 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
113349 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
113350 | //BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS |
113351 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
113352 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
113353 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
113354 | #define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
113355 | //BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
113356 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113357 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113358 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113359 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113360 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113361 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113362 | //BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS |
113363 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
113364 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
113365 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
113366 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
113367 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
113368 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
113369 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
113370 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
113371 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
113372 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
113373 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
113374 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
113375 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
113376 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
113377 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
113378 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
113379 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
113380 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
113381 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
113382 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
113383 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
113384 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
113385 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
113386 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
113387 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
113388 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
113389 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
113390 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
113391 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
113392 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
113393 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
113394 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
113395 | //BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK |
113396 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
113397 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
113398 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
113399 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
113400 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
113401 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
113402 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
113403 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
113404 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
113405 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
113406 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
113407 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
113408 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
113409 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
113410 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
113411 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
113412 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
113413 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
113414 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
113415 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
113416 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
113417 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
113418 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
113419 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
113420 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
113421 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
113422 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
113423 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
113424 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
113425 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
113426 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
113427 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
113428 | //BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY |
113429 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
113430 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
113431 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
113432 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
113433 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
113434 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
113435 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
113436 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
113437 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
113438 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
113439 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
113440 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
113441 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
113442 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
113443 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
113444 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
113445 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
113446 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
113447 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
113448 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
113449 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
113450 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
113451 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
113452 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
113453 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
113454 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
113455 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
113456 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
113457 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
113458 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
113459 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
113460 | #define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
113461 | //BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS |
113462 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
113463 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
113464 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
113465 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
113466 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
113467 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
113468 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
113469 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
113470 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
113471 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
113472 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
113473 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
113474 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
113475 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
113476 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
113477 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
113478 | //BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK |
113479 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
113480 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
113481 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
113482 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
113483 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
113484 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
113485 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
113486 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
113487 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
113488 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
113489 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
113490 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
113491 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
113492 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
113493 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
113494 | #define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
113495 | //BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL |
113496 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
113497 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
113498 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
113499 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
113500 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
113501 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
113502 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
113503 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
113504 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
113505 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
113506 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
113507 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
113508 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
113509 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
113510 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
113511 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
113512 | //BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0 |
113513 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
113514 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
113515 | //BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1 |
113516 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
113517 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
113518 | //BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2 |
113519 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
113520 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
113521 | //BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3 |
113522 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
113523 | #define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
113524 | //BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0 |
113525 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
113526 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
113527 | //BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1 |
113528 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
113529 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
113530 | //BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2 |
113531 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
113532 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
113533 | //BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3 |
113534 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
113535 | #define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
113536 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST |
113537 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113538 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113539 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113540 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113541 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113542 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113543 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP |
113544 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
113545 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
113546 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL |
113547 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
113548 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
113549 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
113550 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
113551 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
113552 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
113553 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP |
113554 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
113555 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
113556 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL |
113557 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
113558 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
113559 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
113560 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
113561 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
113562 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
113563 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP |
113564 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
113565 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
113566 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL |
113567 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
113568 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
113569 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
113570 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
113571 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
113572 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
113573 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP |
113574 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
113575 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
113576 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL |
113577 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
113578 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
113579 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
113580 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
113581 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
113582 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
113583 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP |
113584 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
113585 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
113586 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL |
113587 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
113588 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
113589 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
113590 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
113591 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
113592 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
113593 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP |
113594 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
113595 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
113596 | //BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL |
113597 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
113598 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
113599 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
113600 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
113601 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
113602 | #define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
113603 | //BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
113604 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113605 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113606 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113607 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113608 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113609 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113610 | //BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT |
113611 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
113612 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
113613 | //BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA |
113614 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
113615 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
113616 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
113617 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
113618 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
113619 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
113620 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
113621 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
113622 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
113623 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
113624 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
113625 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
113626 | //BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP |
113627 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
113628 | #define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
113629 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST |
113630 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113631 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113632 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113633 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113634 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113635 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113636 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP |
113637 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
113638 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
113639 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
113640 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
113641 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
113642 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
113643 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
113644 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
113645 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
113646 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
113647 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR |
113648 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
113649 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
113650 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS |
113651 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
113652 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
113653 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
113654 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
113655 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL |
113656 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
113657 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
113658 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
113659 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113660 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113661 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
113662 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113663 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113664 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
113665 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113666 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113667 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
113668 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113669 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113670 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
113671 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113672 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113673 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
113674 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113675 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113676 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
113677 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113678 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113679 | //BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
113680 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
113681 | #define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
113682 | //BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST |
113683 | #define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113684 | #define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113685 | #define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113686 | #define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113687 | #define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113688 | #define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113689 | //BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3 |
113690 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
113691 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
113692 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
113693 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
113694 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
113695 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
113696 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS |
113697 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
113698 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
113699 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
113700 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
113701 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL |
113702 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113703 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113704 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113705 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113706 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113707 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113708 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113709 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113710 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113711 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113712 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL |
113713 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113714 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113715 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113716 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113717 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113718 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113719 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113720 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113721 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113722 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113723 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL |
113724 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113725 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113726 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113727 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113728 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113729 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113730 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113731 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113732 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113733 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113734 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL |
113735 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113736 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113737 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113738 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113739 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113740 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113741 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113742 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113743 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113744 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113745 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL |
113746 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113747 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113748 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113749 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113750 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113751 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113752 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113753 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113754 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113755 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113756 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL |
113757 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113758 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113759 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113760 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113761 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113762 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113763 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113764 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113765 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113766 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113767 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL |
113768 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113769 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113770 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113771 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113772 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113773 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113774 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113775 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113776 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113777 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113778 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL |
113779 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113780 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113781 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113782 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113783 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113784 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113785 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113786 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113787 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113788 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113789 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL |
113790 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113791 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113792 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113793 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113794 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113795 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113796 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113797 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113798 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113799 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113800 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL |
113801 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113802 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113803 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113804 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113805 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113806 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113807 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113808 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113809 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113810 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113811 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL |
113812 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113813 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113814 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113815 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113816 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113817 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113818 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113819 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113820 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113821 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113822 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL |
113823 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113824 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113825 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113826 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113827 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113828 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113829 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113830 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113831 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113832 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113833 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL |
113834 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113835 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113836 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113837 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113838 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113839 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113840 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113841 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113842 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113843 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113844 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL |
113845 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113846 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113847 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113848 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113849 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113850 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113851 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113852 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113853 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113854 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113855 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL |
113856 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113857 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113858 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113859 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113860 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113861 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113862 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113863 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113864 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113865 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113866 | //BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL |
113867 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
113868 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
113869 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
113870 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
113871 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
113872 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
113873 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
113874 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
113875 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
113876 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
113877 | //BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST |
113878 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113879 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113880 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113881 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113882 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113883 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113884 | //BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP |
113885 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
113886 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
113887 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
113888 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
113889 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
113890 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
113891 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
113892 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
113893 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
113894 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
113895 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
113896 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
113897 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
113898 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
113899 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
113900 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
113901 | //BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL |
113902 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
113903 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
113904 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
113905 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
113906 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
113907 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
113908 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
113909 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
113910 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
113911 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
113912 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
113913 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
113914 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
113915 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
113916 | //BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST |
113917 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113918 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113919 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113920 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113921 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113922 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113923 | //BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP |
113924 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
113925 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
113926 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
113927 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
113928 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
113929 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
113930 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
113931 | #define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
113932 | //BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST |
113933 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
113934 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
113935 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
113936 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
113937 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
113938 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
113939 | //BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP |
113940 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
113941 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
113942 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
113943 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
113944 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
113945 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
113946 | //BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL |
113947 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
113948 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
113949 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
113950 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
113951 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
113952 | #define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
113953 | |
113954 | |
113955 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
113956 | //BIF_CFG_DEV1_EPF1_2_VENDOR_ID |
113957 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
113958 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
113959 | //BIF_CFG_DEV1_EPF1_2_DEVICE_ID |
113960 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
113961 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
113962 | //BIF_CFG_DEV1_EPF1_2_COMMAND |
113963 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
113964 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
113965 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
113966 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
113967 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
113968 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
113969 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
113970 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
113971 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN__SHIFT 0x8 |
113972 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
113973 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS__SHIFT 0xa |
113974 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
113975 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
113976 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
113977 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
113978 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
113979 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
113980 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
113981 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING_MASK 0x0080L |
113982 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN_MASK 0x0100L |
113983 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
113984 | #define BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS_MASK 0x0400L |
113985 | //BIF_CFG_DEV1_EPF1_2_STATUS |
113986 | #define BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS__SHIFT 0x3 |
113987 | #define BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST__SHIFT 0x4 |
113988 | #define BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN__SHIFT 0x5 |
113989 | #define BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
113990 | #define BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
113991 | #define BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
113992 | #define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
113993 | #define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
113994 | #define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
113995 | #define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
113996 | #define BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
113997 | #define BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS_MASK 0x0008L |
113998 | #define BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST_MASK 0x0010L |
113999 | #define BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN_MASK 0x0020L |
114000 | #define BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
114001 | #define BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
114002 | #define BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
114003 | #define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
114004 | #define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
114005 | #define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
114006 | #define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
114007 | #define BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
114008 | //BIF_CFG_DEV1_EPF1_2_REVISION_ID |
114009 | #define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
114010 | #define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
114011 | #define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
114012 | #define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
114013 | //BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE |
114014 | #define BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
114015 | #define BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
114016 | //BIF_CFG_DEV1_EPF1_2_SUB_CLASS |
114017 | #define BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
114018 | #define BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
114019 | //BIF_CFG_DEV1_EPF1_2_BASE_CLASS |
114020 | #define BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
114021 | #define BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
114022 | //BIF_CFG_DEV1_EPF1_2_CACHE_LINE |
114023 | #define BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
114024 | #define BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
114025 | //BIF_CFG_DEV1_EPF1_2_LATENCY |
114026 | #define BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
114027 | #define BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
114028 | //BIF_CFG_DEV1_EPF1_2_HEADER |
114029 | #define BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
114030 | #define BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
114031 | #define BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE_MASK 0x7FL |
114032 | #define BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE_MASK 0x80L |
114033 | //BIF_CFG_DEV1_EPF1_2_BIST |
114034 | #define BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP__SHIFT 0x0 |
114035 | #define BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT__SHIFT 0x6 |
114036 | #define BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP__SHIFT 0x7 |
114037 | #define BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP_MASK 0x0FL |
114038 | #define BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT_MASK 0x40L |
114039 | #define BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP_MASK 0x80L |
114040 | //BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1 |
114041 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
114042 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
114043 | //BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2 |
114044 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
114045 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
114046 | //BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3 |
114047 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
114048 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
114049 | //BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4 |
114050 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
114051 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
114052 | //BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5 |
114053 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
114054 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
114055 | //BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6 |
114056 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
114057 | #define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
114058 | //BIF_CFG_DEV1_EPF1_2_ADAPTER_ID |
114059 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
114060 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
114061 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
114062 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
114063 | //BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR |
114064 | #define BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
114065 | #define BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
114066 | //BIF_CFG_DEV1_EPF1_2_CAP_PTR |
114067 | #define BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
114068 | #define BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
114069 | //BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE |
114070 | #define BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
114071 | #define BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
114072 | //BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN |
114073 | #define BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
114074 | #define BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
114075 | //BIF_CFG_DEV1_EPF1_2_MIN_GRANT |
114076 | #define BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
114077 | #define BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
114078 | //BIF_CFG_DEV1_EPF1_2_MAX_LATENCY |
114079 | #define BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
114080 | #define BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
114081 | //BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST |
114082 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
114083 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
114084 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
114085 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
114086 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
114087 | #define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
114088 | //BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W |
114089 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
114090 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
114091 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
114092 | #define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
114093 | //BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST |
114094 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
114095 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
114096 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
114097 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
114098 | //BIF_CFG_DEV1_EPF1_2_PMI_CAP |
114099 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION__SHIFT 0x0 |
114100 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
114101 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
114102 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
114103 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
114104 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
114105 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
114106 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION_MASK 0x0007L |
114107 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
114108 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
114109 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
114110 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
114111 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
114112 | #define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
114113 | //BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL |
114114 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
114115 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
114116 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
114117 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
114118 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
114119 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
114120 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
114121 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
114122 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
114123 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
114124 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
114125 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
114126 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
114127 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
114128 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
114129 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
114130 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
114131 | #define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
114132 | //BIF_CFG_DEV1_EPF1_2_SBRN |
114133 | #define BIF_CFG_DEV1_EPF1_2_SBRN__SBRN__SHIFT 0x0 |
114134 | #define BIF_CFG_DEV1_EPF1_2_SBRN__SBRN_MASK 0xFFL |
114135 | //BIF_CFG_DEV1_EPF1_2_FLADJ |
114136 | #define BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ__SHIFT 0x0 |
114137 | #define BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ_MASK 0x3FL |
114138 | //BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD |
114139 | #define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
114140 | #define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
114141 | #define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
114142 | #define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
114143 | //BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST |
114144 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
114145 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
114146 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
114147 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
114148 | //BIF_CFG_DEV1_EPF1_2_PCIE_CAP |
114149 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION__SHIFT 0x0 |
114150 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
114151 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
114152 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
114153 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION_MASK 0x000FL |
114154 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
114155 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
114156 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
114157 | //BIF_CFG_DEV1_EPF1_2_DEVICE_CAP |
114158 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
114159 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
114160 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
114161 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
114162 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
114163 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
114164 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
114165 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
114166 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
114167 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
114168 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
114169 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
114170 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
114171 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
114172 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
114173 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
114174 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
114175 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
114176 | //BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL |
114177 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
114178 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
114179 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
114180 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
114181 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
114182 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
114183 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
114184 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
114185 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
114186 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
114187 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
114188 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
114189 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
114190 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
114191 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
114192 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
114193 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
114194 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
114195 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
114196 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
114197 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
114198 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
114199 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
114200 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
114201 | //BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS |
114202 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
114203 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
114204 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
114205 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
114206 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
114207 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
114208 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
114209 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
114210 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
114211 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
114212 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
114213 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
114214 | //BIF_CFG_DEV1_EPF1_2_LINK_CAP |
114215 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
114216 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
114217 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
114218 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
114219 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
114220 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
114221 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
114222 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
114223 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
114224 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
114225 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
114226 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
114227 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
114228 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
114229 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
114230 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
114231 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
114232 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
114233 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
114234 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
114235 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
114236 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
114237 | //BIF_CFG_DEV1_EPF1_2_LINK_CNTL |
114238 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
114239 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
114240 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
114241 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
114242 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
114243 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
114244 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
114245 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
114246 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
114247 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
114248 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
114249 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
114250 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
114251 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
114252 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
114253 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
114254 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
114255 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
114256 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
114257 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
114258 | //BIF_CFG_DEV1_EPF1_2_LINK_STATUS |
114259 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
114260 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
114261 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
114262 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
114263 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
114264 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
114265 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
114266 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
114267 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
114268 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
114269 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
114270 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
114271 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
114272 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
114273 | //BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2 |
114274 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
114275 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
114276 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
114277 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
114278 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
114279 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
114280 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
114281 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
114282 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
114283 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
114284 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
114285 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
114286 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
114287 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
114288 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
114289 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
114290 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
114291 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
114292 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
114293 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
114294 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
114295 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
114296 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
114297 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
114298 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
114299 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
114300 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
114301 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
114302 | //BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2 |
114303 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
114304 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
114305 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
114306 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
114307 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
114308 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
114309 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
114310 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
114311 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
114312 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
114313 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
114314 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
114315 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
114316 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
114317 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
114318 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
114319 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
114320 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
114321 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
114322 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
114323 | //BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2 |
114324 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
114325 | #define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
114326 | //BIF_CFG_DEV1_EPF1_2_LINK_CAP2 |
114327 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
114328 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
114329 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
114330 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
114331 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
114332 | #define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
114333 | //BIF_CFG_DEV1_EPF1_2_LINK_CNTL2 |
114334 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
114335 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
114336 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
114337 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
114338 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
114339 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
114340 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
114341 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
114342 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
114343 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
114344 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
114345 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
114346 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
114347 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
114348 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
114349 | #define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
114350 | //BIF_CFG_DEV1_EPF1_2_LINK_STATUS2 |
114351 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
114352 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
114353 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
114354 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
114355 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
114356 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
114357 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
114358 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
114359 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
114360 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
114361 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
114362 | #define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
114363 | //BIF_CFG_DEV1_EPF1_2_SLOT_CAP2 |
114364 | #define BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
114365 | #define BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
114366 | //BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2 |
114367 | #define BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
114368 | #define BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
114369 | //BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2 |
114370 | #define BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
114371 | #define BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
114372 | //BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST |
114373 | #define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
114374 | #define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
114375 | #define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
114376 | #define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
114377 | //BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL |
114378 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
114379 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
114380 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
114381 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
114382 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
114383 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
114384 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
114385 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
114386 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
114387 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
114388 | //BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO |
114389 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
114390 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
114391 | //BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI |
114392 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
114393 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
114394 | //BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA |
114395 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
114396 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
114397 | //BIF_CFG_DEV1_EPF1_2_MSI_MASK |
114398 | #define BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
114399 | #define BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
114400 | //BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64 |
114401 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
114402 | #define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
114403 | //BIF_CFG_DEV1_EPF1_2_MSI_MASK_64 |
114404 | #define BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
114405 | #define BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
114406 | //BIF_CFG_DEV1_EPF1_2_MSI_PENDING |
114407 | #define BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
114408 | #define BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
114409 | //BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64 |
114410 | #define BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
114411 | #define BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
114412 | //BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST |
114413 | #define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
114414 | #define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
114415 | #define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
114416 | #define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
114417 | //BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL |
114418 | #define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
114419 | #define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
114420 | #define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
114421 | #define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
114422 | #define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
114423 | #define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
114424 | //BIF_CFG_DEV1_EPF1_2_MSIX_TABLE |
114425 | #define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
114426 | #define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
114427 | #define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
114428 | #define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
114429 | //BIF_CFG_DEV1_EPF1_2_MSIX_PBA |
114430 | #define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
114431 | #define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
114432 | #define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
114433 | #define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
114434 | //BIF_CFG_DEV1_EPF1_2_SATA_CAP_0 |
114435 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
114436 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
114437 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
114438 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
114439 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
114440 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
114441 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
114442 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
114443 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
114444 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
114445 | //BIF_CFG_DEV1_EPF1_2_SATA_CAP_1 |
114446 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
114447 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
114448 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
114449 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
114450 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
114451 | #define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
114452 | //BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX |
114453 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
114454 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
114455 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
114456 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
114457 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
114458 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
114459 | //BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA |
114460 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
114461 | #define BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
114462 | //BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
114463 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114464 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114465 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114466 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114467 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114468 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114469 | //BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR |
114470 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
114471 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
114472 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
114473 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
114474 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
114475 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
114476 | //BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1 |
114477 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
114478 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
114479 | //BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2 |
114480 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
114481 | #define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
114482 | //BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
114483 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114484 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114485 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114486 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114487 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114488 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114489 | //BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS |
114490 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
114491 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
114492 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
114493 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
114494 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
114495 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
114496 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
114497 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
114498 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
114499 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
114500 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
114501 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
114502 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
114503 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
114504 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
114505 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
114506 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
114507 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
114508 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
114509 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
114510 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
114511 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
114512 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
114513 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
114514 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
114515 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
114516 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
114517 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
114518 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
114519 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
114520 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
114521 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
114522 | //BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK |
114523 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
114524 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
114525 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
114526 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
114527 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
114528 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
114529 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
114530 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
114531 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
114532 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
114533 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
114534 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
114535 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
114536 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
114537 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
114538 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
114539 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
114540 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
114541 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
114542 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
114543 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
114544 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
114545 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
114546 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
114547 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
114548 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
114549 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
114550 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
114551 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
114552 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
114553 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
114554 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
114555 | //BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY |
114556 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
114557 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
114558 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
114559 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
114560 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
114561 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
114562 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
114563 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
114564 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
114565 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
114566 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
114567 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
114568 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
114569 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
114570 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
114571 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
114572 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
114573 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
114574 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
114575 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
114576 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
114577 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
114578 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
114579 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
114580 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
114581 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
114582 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
114583 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
114584 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
114585 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
114586 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
114587 | #define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
114588 | //BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS |
114589 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
114590 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
114591 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
114592 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
114593 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
114594 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
114595 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
114596 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
114597 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
114598 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
114599 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
114600 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
114601 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
114602 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
114603 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
114604 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
114605 | //BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK |
114606 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
114607 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
114608 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
114609 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
114610 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
114611 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
114612 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
114613 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
114614 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
114615 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
114616 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
114617 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
114618 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
114619 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
114620 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
114621 | #define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
114622 | //BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL |
114623 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
114624 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
114625 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
114626 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
114627 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
114628 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
114629 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
114630 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
114631 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
114632 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
114633 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
114634 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
114635 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
114636 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
114637 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
114638 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
114639 | //BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0 |
114640 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
114641 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
114642 | //BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1 |
114643 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
114644 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
114645 | //BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2 |
114646 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
114647 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
114648 | //BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3 |
114649 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
114650 | #define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
114651 | //BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0 |
114652 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
114653 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
114654 | //BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1 |
114655 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
114656 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
114657 | //BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2 |
114658 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
114659 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
114660 | //BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3 |
114661 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
114662 | #define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
114663 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST |
114664 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114665 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114666 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114667 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114668 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114669 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114670 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP |
114671 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
114672 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
114673 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL |
114674 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
114675 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
114676 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
114677 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
114678 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
114679 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
114680 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP |
114681 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
114682 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
114683 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL |
114684 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
114685 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
114686 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
114687 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
114688 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
114689 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
114690 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP |
114691 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
114692 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
114693 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL |
114694 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
114695 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
114696 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
114697 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
114698 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
114699 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
114700 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP |
114701 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
114702 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
114703 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL |
114704 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
114705 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
114706 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
114707 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
114708 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
114709 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
114710 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP |
114711 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
114712 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
114713 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL |
114714 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
114715 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
114716 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
114717 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
114718 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
114719 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
114720 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP |
114721 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
114722 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
114723 | //BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL |
114724 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
114725 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
114726 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
114727 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
114728 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
114729 | #define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
114730 | //BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
114731 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114732 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114733 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114734 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114735 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114736 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114737 | //BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT |
114738 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
114739 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
114740 | //BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA |
114741 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
114742 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
114743 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
114744 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
114745 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
114746 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
114747 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
114748 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
114749 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
114750 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
114751 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
114752 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
114753 | //BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP |
114754 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
114755 | #define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
114756 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST |
114757 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114758 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114759 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114760 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114761 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114762 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114763 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP |
114764 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
114765 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
114766 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
114767 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
114768 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
114769 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
114770 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
114771 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
114772 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
114773 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
114774 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR |
114775 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
114776 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
114777 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS |
114778 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
114779 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
114780 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
114781 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
114782 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL |
114783 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
114784 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
114785 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
114786 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114787 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114788 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
114789 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114790 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114791 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
114792 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114793 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114794 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
114795 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114796 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114797 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
114798 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114799 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114800 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
114801 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114802 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114803 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
114804 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114805 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114806 | //BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
114807 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
114808 | #define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
114809 | //BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST |
114810 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114811 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114812 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114813 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114814 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114815 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114816 | //BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP |
114817 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
114818 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
114819 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
114820 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
114821 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
114822 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
114823 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
114824 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
114825 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
114826 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
114827 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
114828 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
114829 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
114830 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
114831 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
114832 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
114833 | //BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL |
114834 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
114835 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
114836 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
114837 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
114838 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
114839 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
114840 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
114841 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
114842 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
114843 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
114844 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
114845 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
114846 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
114847 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
114848 | //BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST |
114849 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
114850 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
114851 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
114852 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
114853 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
114854 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
114855 | //BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP |
114856 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
114857 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
114858 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
114859 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
114860 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
114861 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
114862 | //BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL |
114863 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
114864 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
114865 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
114866 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
114867 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
114868 | #define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
114869 | |
114870 | |
114871 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
114872 | //BIF_CFG_DEV1_EPF2_2_VENDOR_ID |
114873 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
114874 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
114875 | //BIF_CFG_DEV1_EPF2_2_DEVICE_ID |
114876 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
114877 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
114878 | //BIF_CFG_DEV1_EPF2_2_COMMAND |
114879 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
114880 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
114881 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
114882 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
114883 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
114884 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
114885 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
114886 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING__SHIFT 0x7 |
114887 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN__SHIFT 0x8 |
114888 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
114889 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS__SHIFT 0xa |
114890 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
114891 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
114892 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
114893 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
114894 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
114895 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
114896 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
114897 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING_MASK 0x0080L |
114898 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN_MASK 0x0100L |
114899 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
114900 | #define BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS_MASK 0x0400L |
114901 | //BIF_CFG_DEV1_EPF2_2_STATUS |
114902 | #define BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS__SHIFT 0x3 |
114903 | #define BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST__SHIFT 0x4 |
114904 | #define BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN__SHIFT 0x5 |
114905 | #define BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
114906 | #define BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
114907 | #define BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
114908 | #define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
114909 | #define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
114910 | #define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
114911 | #define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
114912 | #define BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
114913 | #define BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS_MASK 0x0008L |
114914 | #define BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST_MASK 0x0010L |
114915 | #define BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN_MASK 0x0020L |
114916 | #define BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
114917 | #define BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
114918 | #define BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
114919 | #define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
114920 | #define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
114921 | #define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
114922 | #define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
114923 | #define BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
114924 | //BIF_CFG_DEV1_EPF2_2_REVISION_ID |
114925 | #define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
114926 | #define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
114927 | #define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
114928 | #define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
114929 | //BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE |
114930 | #define BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
114931 | #define BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
114932 | //BIF_CFG_DEV1_EPF2_2_SUB_CLASS |
114933 | #define BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
114934 | #define BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
114935 | //BIF_CFG_DEV1_EPF2_2_BASE_CLASS |
114936 | #define BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
114937 | #define BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
114938 | //BIF_CFG_DEV1_EPF2_2_CACHE_LINE |
114939 | #define BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
114940 | #define BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
114941 | //BIF_CFG_DEV1_EPF2_2_LATENCY |
114942 | #define BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
114943 | #define BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
114944 | //BIF_CFG_DEV1_EPF2_2_HEADER |
114945 | #define BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE__SHIFT 0x0 |
114946 | #define BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE__SHIFT 0x7 |
114947 | #define BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE_MASK 0x7FL |
114948 | #define BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE_MASK 0x80L |
114949 | //BIF_CFG_DEV1_EPF2_2_BIST |
114950 | #define BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP__SHIFT 0x0 |
114951 | #define BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT__SHIFT 0x6 |
114952 | #define BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP__SHIFT 0x7 |
114953 | #define BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP_MASK 0x0FL |
114954 | #define BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT_MASK 0x40L |
114955 | #define BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP_MASK 0x80L |
114956 | //BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1 |
114957 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
114958 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
114959 | //BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2 |
114960 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
114961 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
114962 | //BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3 |
114963 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
114964 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
114965 | //BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4 |
114966 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
114967 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
114968 | //BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5 |
114969 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
114970 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
114971 | //BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6 |
114972 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
114973 | #define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
114974 | //BIF_CFG_DEV1_EPF2_2_ADAPTER_ID |
114975 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
114976 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
114977 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
114978 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
114979 | //BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR |
114980 | #define BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
114981 | #define BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
114982 | //BIF_CFG_DEV1_EPF2_2_CAP_PTR |
114983 | #define BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
114984 | #define BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
114985 | //BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE |
114986 | #define BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
114987 | #define BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
114988 | //BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN |
114989 | #define BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
114990 | #define BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
114991 | //BIF_CFG_DEV1_EPF2_2_MIN_GRANT |
114992 | #define BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
114993 | #define BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
114994 | //BIF_CFG_DEV1_EPF2_2_MAX_LATENCY |
114995 | #define BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
114996 | #define BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
114997 | //BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST |
114998 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
114999 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
115000 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
115001 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
115002 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
115003 | #define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
115004 | //BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W |
115005 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
115006 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
115007 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
115008 | #define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
115009 | //BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST |
115010 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
115011 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
115012 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
115013 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
115014 | //BIF_CFG_DEV1_EPF2_2_PMI_CAP |
115015 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION__SHIFT 0x0 |
115016 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
115017 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
115018 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
115019 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
115020 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
115021 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
115022 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION_MASK 0x0007L |
115023 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
115024 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
115025 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
115026 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
115027 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
115028 | #define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
115029 | //BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL |
115030 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
115031 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
115032 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
115033 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
115034 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
115035 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
115036 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
115037 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
115038 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
115039 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
115040 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
115041 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
115042 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
115043 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
115044 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
115045 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
115046 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
115047 | #define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
115048 | //BIF_CFG_DEV1_EPF2_2_SBRN |
115049 | #define BIF_CFG_DEV1_EPF2_2_SBRN__SBRN__SHIFT 0x0 |
115050 | #define BIF_CFG_DEV1_EPF2_2_SBRN__SBRN_MASK 0xFFL |
115051 | //BIF_CFG_DEV1_EPF2_2_FLADJ |
115052 | #define BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ__SHIFT 0x0 |
115053 | #define BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ_MASK 0x3FL |
115054 | //BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD |
115055 | #define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
115056 | #define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
115057 | #define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL_MASK 0x0FL |
115058 | #define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
115059 | //BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST |
115060 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
115061 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
115062 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
115063 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
115064 | //BIF_CFG_DEV1_EPF2_2_PCIE_CAP |
115065 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION__SHIFT 0x0 |
115066 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
115067 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
115068 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
115069 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION_MASK 0x000FL |
115070 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
115071 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
115072 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
115073 | //BIF_CFG_DEV1_EPF2_2_DEVICE_CAP |
115074 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
115075 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
115076 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
115077 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
115078 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
115079 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
115080 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
115081 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
115082 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
115083 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
115084 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
115085 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
115086 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
115087 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
115088 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
115089 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
115090 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
115091 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
115092 | //BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL |
115093 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
115094 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
115095 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
115096 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
115097 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
115098 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
115099 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
115100 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
115101 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
115102 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
115103 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
115104 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
115105 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
115106 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
115107 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
115108 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
115109 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
115110 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
115111 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
115112 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
115113 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
115114 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
115115 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
115116 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
115117 | //BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS |
115118 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
115119 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
115120 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
115121 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
115122 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
115123 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
115124 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
115125 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
115126 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
115127 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
115128 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
115129 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
115130 | //BIF_CFG_DEV1_EPF2_2_LINK_CAP |
115131 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
115132 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
115133 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
115134 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
115135 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
115136 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
115137 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
115138 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
115139 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
115140 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
115141 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
115142 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
115143 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
115144 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
115145 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
115146 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
115147 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
115148 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
115149 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
115150 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
115151 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
115152 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
115153 | //BIF_CFG_DEV1_EPF2_2_LINK_CNTL |
115154 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
115155 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
115156 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
115157 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
115158 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
115159 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
115160 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
115161 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
115162 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
115163 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
115164 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
115165 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
115166 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
115167 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
115168 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
115169 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
115170 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
115171 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
115172 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
115173 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
115174 | //BIF_CFG_DEV1_EPF2_2_LINK_STATUS |
115175 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
115176 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
115177 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
115178 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
115179 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
115180 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
115181 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
115182 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
115183 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
115184 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
115185 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
115186 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
115187 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
115188 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
115189 | //BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2 |
115190 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
115191 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
115192 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
115193 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
115194 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
115195 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
115196 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
115197 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
115198 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
115199 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
115200 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
115201 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
115202 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
115203 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
115204 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
115205 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
115206 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
115207 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
115208 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
115209 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
115210 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
115211 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
115212 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
115213 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
115214 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
115215 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
115216 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
115217 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
115218 | //BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2 |
115219 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
115220 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
115221 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
115222 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
115223 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
115224 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
115225 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
115226 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
115227 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
115228 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
115229 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
115230 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
115231 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
115232 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
115233 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
115234 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
115235 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
115236 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
115237 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
115238 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
115239 | //BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2 |
115240 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
115241 | #define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
115242 | //BIF_CFG_DEV1_EPF2_2_LINK_CAP2 |
115243 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
115244 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
115245 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED__SHIFT 0x9 |
115246 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
115247 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
115248 | #define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
115249 | //BIF_CFG_DEV1_EPF2_2_LINK_CNTL2 |
115250 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
115251 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
115252 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
115253 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
115254 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
115255 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
115256 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
115257 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
115258 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
115259 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
115260 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
115261 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
115262 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
115263 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
115264 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
115265 | #define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
115266 | //BIF_CFG_DEV1_EPF2_2_LINK_STATUS2 |
115267 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
115268 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
115269 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
115270 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
115271 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
115272 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
115273 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
115274 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
115275 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
115276 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
115277 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
115278 | #define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
115279 | //BIF_CFG_DEV1_EPF2_2_SLOT_CAP2 |
115280 | #define BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED__SHIFT 0x0 |
115281 | #define BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
115282 | //BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2 |
115283 | #define BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
115284 | #define BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
115285 | //BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2 |
115286 | #define BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
115287 | #define BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
115288 | //BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST |
115289 | #define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
115290 | #define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
115291 | #define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
115292 | #define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
115293 | //BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL |
115294 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
115295 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
115296 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
115297 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
115298 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
115299 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
115300 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
115301 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
115302 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
115303 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
115304 | //BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO |
115305 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
115306 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
115307 | //BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI |
115308 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
115309 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
115310 | //BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA |
115311 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
115312 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
115313 | //BIF_CFG_DEV1_EPF2_2_MSI_MASK |
115314 | #define BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
115315 | #define BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
115316 | //BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64 |
115317 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
115318 | #define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
115319 | //BIF_CFG_DEV1_EPF2_2_MSI_MASK_64 |
115320 | #define BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
115321 | #define BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
115322 | //BIF_CFG_DEV1_EPF2_2_MSI_PENDING |
115323 | #define BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
115324 | #define BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
115325 | //BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64 |
115326 | #define BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
115327 | #define BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
115328 | //BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST |
115329 | #define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
115330 | #define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
115331 | #define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
115332 | #define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
115333 | //BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL |
115334 | #define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
115335 | #define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
115336 | #define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
115337 | #define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
115338 | #define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
115339 | #define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
115340 | //BIF_CFG_DEV1_EPF2_2_MSIX_TABLE |
115341 | #define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
115342 | #define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
115343 | #define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
115344 | #define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
115345 | //BIF_CFG_DEV1_EPF2_2_MSIX_PBA |
115346 | #define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
115347 | #define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
115348 | #define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
115349 | #define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
115350 | //BIF_CFG_DEV1_EPF2_2_SATA_CAP_0 |
115351 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
115352 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
115353 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
115354 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
115355 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
115356 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
115357 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
115358 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
115359 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
115360 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
115361 | //BIF_CFG_DEV1_EPF2_2_SATA_CAP_1 |
115362 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
115363 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
115364 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
115365 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
115366 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
115367 | #define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
115368 | //BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX |
115369 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
115370 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
115371 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
115372 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
115373 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
115374 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
115375 | //BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA |
115376 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
115377 | #define BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
115378 | //BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
115379 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115380 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115381 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115382 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115383 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115384 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115385 | //BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR |
115386 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
115387 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
115388 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
115389 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
115390 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
115391 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
115392 | //BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1 |
115393 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
115394 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
115395 | //BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2 |
115396 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
115397 | #define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
115398 | //BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
115399 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115400 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115401 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115402 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115403 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115404 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115405 | //BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS |
115406 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
115407 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
115408 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
115409 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
115410 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
115411 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
115412 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
115413 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
115414 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
115415 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
115416 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
115417 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
115418 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
115419 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
115420 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
115421 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
115422 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
115423 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
115424 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
115425 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
115426 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
115427 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
115428 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
115429 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
115430 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
115431 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
115432 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
115433 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
115434 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
115435 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
115436 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
115437 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
115438 | //BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK |
115439 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
115440 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
115441 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
115442 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
115443 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
115444 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
115445 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
115446 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
115447 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
115448 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
115449 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
115450 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
115451 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
115452 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
115453 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
115454 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
115455 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
115456 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
115457 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
115458 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
115459 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
115460 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
115461 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
115462 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
115463 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
115464 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
115465 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
115466 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
115467 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
115468 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
115469 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
115470 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
115471 | //BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY |
115472 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
115473 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
115474 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
115475 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
115476 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
115477 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
115478 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
115479 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
115480 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
115481 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
115482 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
115483 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
115484 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
115485 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
115486 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
115487 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
115488 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
115489 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
115490 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
115491 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
115492 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
115493 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
115494 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
115495 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
115496 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
115497 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
115498 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
115499 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
115500 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
115501 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
115502 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
115503 | #define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
115504 | //BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS |
115505 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
115506 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
115507 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
115508 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
115509 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
115510 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
115511 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
115512 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
115513 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
115514 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
115515 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
115516 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
115517 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
115518 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
115519 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
115520 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
115521 | //BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK |
115522 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
115523 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
115524 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
115525 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
115526 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
115527 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
115528 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
115529 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
115530 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
115531 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
115532 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
115533 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
115534 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
115535 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
115536 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
115537 | #define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
115538 | //BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL |
115539 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
115540 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
115541 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
115542 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
115543 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
115544 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
115545 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
115546 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
115547 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
115548 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
115549 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
115550 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
115551 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
115552 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
115553 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
115554 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
115555 | //BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0 |
115556 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
115557 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
115558 | //BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1 |
115559 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
115560 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
115561 | //BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2 |
115562 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
115563 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
115564 | //BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3 |
115565 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
115566 | #define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
115567 | //BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0 |
115568 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
115569 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
115570 | //BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1 |
115571 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
115572 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
115573 | //BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2 |
115574 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
115575 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
115576 | //BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3 |
115577 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
115578 | #define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
115579 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST |
115580 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115581 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115582 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115583 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115584 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115585 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115586 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP |
115587 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
115588 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
115589 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL |
115590 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
115591 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
115592 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
115593 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
115594 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
115595 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
115596 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP |
115597 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
115598 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
115599 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL |
115600 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
115601 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
115602 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
115603 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
115604 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
115605 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
115606 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP |
115607 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
115608 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
115609 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL |
115610 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
115611 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
115612 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
115613 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
115614 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
115615 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
115616 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP |
115617 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
115618 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
115619 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL |
115620 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
115621 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
115622 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
115623 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
115624 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
115625 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
115626 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP |
115627 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
115628 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
115629 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL |
115630 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
115631 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
115632 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
115633 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
115634 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
115635 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
115636 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP |
115637 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
115638 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
115639 | //BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL |
115640 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
115641 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
115642 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
115643 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
115644 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
115645 | #define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
115646 | //BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
115647 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115648 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115649 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115650 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115651 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115652 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115653 | //BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT |
115654 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
115655 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
115656 | //BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA |
115657 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
115658 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
115659 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
115660 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
115661 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
115662 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
115663 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
115664 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
115665 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
115666 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
115667 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
115668 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
115669 | //BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP |
115670 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
115671 | #define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
115672 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST |
115673 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115674 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115675 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115676 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115677 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115678 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115679 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP |
115680 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
115681 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
115682 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
115683 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
115684 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
115685 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
115686 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
115687 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
115688 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
115689 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
115690 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR |
115691 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
115692 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
115693 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS |
115694 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
115695 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
115696 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
115697 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
115698 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL |
115699 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
115700 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
115701 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
115702 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115703 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115704 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
115705 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115706 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115707 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
115708 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115709 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115710 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
115711 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115712 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115713 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
115714 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115715 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115716 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
115717 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115718 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115719 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
115720 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115721 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115722 | //BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
115723 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
115724 | #define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
115725 | //BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST |
115726 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115727 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115728 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115729 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115730 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115731 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115732 | //BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP |
115733 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
115734 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
115735 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
115736 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
115737 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
115738 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
115739 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
115740 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
115741 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
115742 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
115743 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
115744 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
115745 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
115746 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
115747 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
115748 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
115749 | //BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL |
115750 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
115751 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
115752 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
115753 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
115754 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
115755 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
115756 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
115757 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
115758 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
115759 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
115760 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
115761 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
115762 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
115763 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
115764 | //BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST |
115765 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
115766 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
115767 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
115768 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
115769 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
115770 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
115771 | //BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP |
115772 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
115773 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
115774 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
115775 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
115776 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
115777 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
115778 | //BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL |
115779 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
115780 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
115781 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
115782 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
115783 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
115784 | #define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
115785 | |
115786 | |
115787 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
115788 | //BIF_BX_PF1_MM_INDEX |
115789 | #define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
115790 | #define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f |
115791 | #define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
115792 | #define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L |
115793 | //BIF_BX_PF1_MM_DATA |
115794 | #define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 |
115795 | #define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
115796 | //BIF_BX_PF1_MM_INDEX_HI |
115797 | #define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
115798 | #define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
115799 | |
115800 | |
115801 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
115802 | //BIF_BX_PF1_SYSHUB_INDEX_OVLP |
115803 | #define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 |
115804 | #define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL |
115805 | //BIF_BX_PF1_SYSHUB_DATA_OVLP |
115806 | #define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 |
115807 | #define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL |
115808 | //BIF_BX_PF1_PCIE_INDEX |
115809 | #define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
115810 | #define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
115811 | //BIF_BX_PF1_PCIE_DATA |
115812 | #define BIF_BX_PF1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
115813 | #define BIF_BX_PF1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
115814 | //BIF_BX_PF1_PCIE_INDEX2 |
115815 | #define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
115816 | #define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
115817 | //BIF_BX_PF1_PCIE_DATA2 |
115818 | #define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
115819 | #define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
115820 | //BIF_BX_PF1_SBIOS_SCRATCH_0 |
115821 | #define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
115822 | #define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
115823 | //BIF_BX_PF1_SBIOS_SCRATCH_1 |
115824 | #define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
115825 | #define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
115826 | //BIF_BX_PF1_SBIOS_SCRATCH_2 |
115827 | #define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
115828 | #define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
115829 | //BIF_BX_PF1_SBIOS_SCRATCH_3 |
115830 | #define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
115831 | #define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
115832 | //BIF_BX_PF1_BIOS_SCRATCH_0 |
115833 | #define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
115834 | #define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
115835 | //BIF_BX_PF1_BIOS_SCRATCH_1 |
115836 | #define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
115837 | #define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
115838 | //BIF_BX_PF1_BIOS_SCRATCH_2 |
115839 | #define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
115840 | #define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
115841 | //BIF_BX_PF1_BIOS_SCRATCH_3 |
115842 | #define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
115843 | #define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
115844 | //BIF_BX_PF1_BIOS_SCRATCH_4 |
115845 | #define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
115846 | #define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
115847 | //BIF_BX_PF1_BIOS_SCRATCH_5 |
115848 | #define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
115849 | #define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
115850 | //BIF_BX_PF1_BIOS_SCRATCH_6 |
115851 | #define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
115852 | #define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
115853 | //BIF_BX_PF1_BIOS_SCRATCH_7 |
115854 | #define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
115855 | #define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
115856 | //BIF_BX_PF1_BIOS_SCRATCH_8 |
115857 | #define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
115858 | #define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
115859 | //BIF_BX_PF1_BIOS_SCRATCH_9 |
115860 | #define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
115861 | #define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
115862 | //BIF_BX_PF1_BIOS_SCRATCH_10 |
115863 | #define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
115864 | #define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
115865 | //BIF_BX_PF1_BIOS_SCRATCH_11 |
115866 | #define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
115867 | #define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
115868 | //BIF_BX_PF1_BIOS_SCRATCH_12 |
115869 | #define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
115870 | #define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
115871 | //BIF_BX_PF1_BIOS_SCRATCH_13 |
115872 | #define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
115873 | #define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
115874 | //BIF_BX_PF1_BIOS_SCRATCH_14 |
115875 | #define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
115876 | #define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
115877 | //BIF_BX_PF1_BIOS_SCRATCH_15 |
115878 | #define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
115879 | #define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
115880 | //BIF_BX_PF1_BIF_RLC_INTR_CNTL |
115881 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
115882 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
115883 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
115884 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
115885 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
115886 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
115887 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
115888 | #define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
115889 | //BIF_BX_PF1_BIF_VCE_INTR_CNTL |
115890 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
115891 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
115892 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
115893 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
115894 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
115895 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
115896 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
115897 | #define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
115898 | //BIF_BX_PF1_BIF_UVD_INTR_CNTL |
115899 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
115900 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
115901 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
115902 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
115903 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
115904 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
115905 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
115906 | #define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
115907 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0 |
115908 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
115909 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
115910 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0 |
115911 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
115912 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
115913 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1 |
115914 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
115915 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
115916 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1 |
115917 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
115918 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
115919 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2 |
115920 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
115921 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
115922 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2 |
115923 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
115924 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
115925 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3 |
115926 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
115927 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
115928 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3 |
115929 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
115930 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
115931 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4 |
115932 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
115933 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
115934 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4 |
115935 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
115936 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
115937 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5 |
115938 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
115939 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
115940 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5 |
115941 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
115942 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
115943 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6 |
115944 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
115945 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
115946 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6 |
115947 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
115948 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
115949 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7 |
115950 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
115951 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
115952 | //BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7 |
115953 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
115954 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
115955 | //BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL |
115956 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
115957 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
115958 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL |
115959 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
115960 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
115961 | //BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL |
115962 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
115963 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
115964 | //BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
115965 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
115966 | #define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
115967 | |
115968 | |
115969 | // addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec |
115970 | //SYSHUB_MMREG_IND0_SYSHUB_INDEX |
115971 | #define SYSHUB_MMREG_IND0_SYSHUB_INDEX__INDEX__SHIFT 0x0 |
115972 | #define SYSHUB_MMREG_IND0_SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL |
115973 | //SYSHUB_MMREG_IND0_SYSHUB_DATA |
115974 | #define SYSHUB_MMREG_IND0_SYSHUB_DATA__DATA__SHIFT 0x0 |
115975 | #define SYSHUB_MMREG_IND0_SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL |
115976 | |
115977 | |
115978 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
115979 | //RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 |
115980 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
115981 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
115982 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
115983 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
115984 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
115985 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
115986 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
115987 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
115988 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
115989 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
115990 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
115991 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
115992 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
115993 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
115994 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
115995 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
115996 | |
115997 | |
115998 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
115999 | //RCC_EP_DEV0_2_EP_PCIE_SCRATCH |
116000 | #define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
116001 | #define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
116002 | //RCC_EP_DEV0_2_EP_PCIE_CNTL |
116003 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
116004 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
116005 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
116006 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
116007 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
116008 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
116009 | //RCC_EP_DEV0_2_EP_PCIE_INT_CNTL |
116010 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
116011 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
116012 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
116013 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
116014 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
116015 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
116016 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
116017 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
116018 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
116019 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
116020 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
116021 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
116022 | //RCC_EP_DEV0_2_EP_PCIE_INT_STATUS |
116023 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
116024 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
116025 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
116026 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
116027 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
116028 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
116029 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
116030 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
116031 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
116032 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
116033 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
116034 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
116035 | //RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 |
116036 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
116037 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
116038 | //RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL |
116039 | #define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
116040 | #define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
116041 | //RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL |
116042 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
116043 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
116044 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
116045 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
116046 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
116047 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
116048 | //RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL |
116049 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
116050 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
116051 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
116052 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
116053 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
116054 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
116055 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
116056 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
116057 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
116058 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
116059 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
116060 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
116061 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
116062 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
116063 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
116064 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
116065 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
116066 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
116067 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
116068 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
116069 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
116070 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116071 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116072 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
116073 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116074 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116075 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
116076 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116077 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116078 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
116079 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116080 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116081 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
116082 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116083 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116084 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
116085 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116086 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116087 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
116088 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116089 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116090 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
116091 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116092 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116093 | //RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP |
116094 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
116095 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
116096 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
116097 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
116098 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
116099 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
116100 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
116101 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
116102 | //RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
116103 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
116104 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
116105 | //RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL |
116106 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
116107 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
116108 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
116109 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
116110 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
116111 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116112 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116113 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
116114 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116115 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116116 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
116117 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116118 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116119 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
116120 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116121 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116122 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
116123 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116124 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116125 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
116126 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116127 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116128 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
116129 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116130 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116131 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
116132 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
116133 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
116134 | //RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL |
116135 | #define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
116136 | #define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
116137 | //RCC_EP_DEV0_2_EP_PCIEP_RESERVED |
116138 | #define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
116139 | #define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
116140 | //RCC_EP_DEV0_2_EP_PCIE_TX_CNTL |
116141 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
116142 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
116143 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
116144 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
116145 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
116146 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
116147 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
116148 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
116149 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
116150 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
116151 | //RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID |
116152 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
116153 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
116154 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
116155 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
116156 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
116157 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
116158 | //RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL |
116159 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
116160 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
116161 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
116162 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
116163 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
116164 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
116165 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
116166 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
116167 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
116168 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
116169 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
116170 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
116171 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
116172 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
116173 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
116174 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
116175 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
116176 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
116177 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
116178 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
116179 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
116180 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
116181 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
116182 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
116183 | //RCC_EP_DEV0_2_EP_PCIE_RX_CNTL |
116184 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
116185 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
116186 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
116187 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
116188 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
116189 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
116190 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
116191 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
116192 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
116193 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
116194 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
116195 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
116196 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
116197 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
116198 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
116199 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
116200 | //RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL |
116201 | #define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
116202 | #define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
116203 | #define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
116204 | #define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
116205 | |
116206 | |
116207 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
116208 | //RCC_DWN_DEV0_2_DN_PCIE_RESERVED |
116209 | #define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
116210 | #define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
116211 | //RCC_DWN_DEV0_2_DN_PCIE_SCRATCH |
116212 | #define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
116213 | #define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
116214 | //RCC_DWN_DEV0_2_DN_PCIE_CNTL |
116215 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
116216 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
116217 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
116218 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
116219 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
116220 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
116221 | //RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL |
116222 | #define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
116223 | #define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
116224 | //RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 |
116225 | #define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
116226 | #define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
116227 | //RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL |
116228 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
116229 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
116230 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
116231 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
116232 | //RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL |
116233 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
116234 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
116235 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
116236 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
116237 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
116238 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
116239 | |
116240 | |
116241 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
116242 | //RCC_DWNP_DEV0_2_PCIE_ERR_CNTL |
116243 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
116244 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
116245 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
116246 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
116247 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
116248 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
116249 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
116250 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
116251 | //RCC_DWNP_DEV0_2_PCIE_RX_CNTL |
116252 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
116253 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
116254 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
116255 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
116256 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
116257 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
116258 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
116259 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
116260 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
116261 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
116262 | //RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL |
116263 | #define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
116264 | #define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
116265 | #define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
116266 | #define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
116267 | //RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 |
116268 | #define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
116269 | #define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
116270 | //RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC |
116271 | #define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
116272 | #define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
116273 | //RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP |
116274 | #define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
116275 | #define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
116276 | |
116277 | |
116278 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
116279 | //BIF_BX_PF1_BIF_MM_INDACCESS_CNTL |
116280 | #define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
116281 | #define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
116282 | //BIF_BX_PF1_BUS_CNTL |
116283 | #define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 |
116284 | #define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 |
116285 | #define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 |
116286 | #define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
116287 | #define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
116288 | #define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
116289 | #define BIF_BX_PF1_BUS_CNTL__SET_MC_TC__SHIFT 0xd |
116290 | #define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
116291 | #define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
116292 | #define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
116293 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 |
116294 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 |
116295 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 |
116296 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 |
116297 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 |
116298 | #define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 |
116299 | #define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
116300 | #define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
116301 | #define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b |
116302 | #define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c |
116303 | #define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
116304 | #define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
116305 | #define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
116306 | #define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L |
116307 | #define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L |
116308 | #define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L |
116309 | #define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
116310 | #define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
116311 | #define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
116312 | #define BIF_BX_PF1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
116313 | #define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
116314 | #define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
116315 | #define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
116316 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L |
116317 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L |
116318 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L |
116319 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L |
116320 | #define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L |
116321 | #define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L |
116322 | #define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
116323 | #define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
116324 | #define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L |
116325 | #define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L |
116326 | #define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
116327 | #define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
116328 | #define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
116329 | //BIF_BX_PF1_BIF_SCRATCH0 |
116330 | #define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
116331 | #define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
116332 | //BIF_BX_PF1_BIF_SCRATCH1 |
116333 | #define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
116334 | #define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
116335 | //BIF_BX_PF1_BX_RESET_EN |
116336 | #define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 |
116337 | #define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 |
116338 | #define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 |
116339 | #define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 |
116340 | #define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
116341 | #define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L |
116342 | #define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L |
116343 | #define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L |
116344 | #define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L |
116345 | #define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
116346 | //BIF_BX_PF1_MM_CFGREGS_CNTL |
116347 | #define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
116348 | #define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
116349 | #define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
116350 | #define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
116351 | #define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
116352 | #define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
116353 | //BIF_BX_PF1_BX_RESET_CNTL |
116354 | #define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
116355 | #define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
116356 | //BIF_BX_PF1_INTERRUPT_CNTL |
116357 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
116358 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
116359 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
116360 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
116361 | #define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
116362 | #define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
116363 | #define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
116364 | #define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
116365 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
116366 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
116367 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
116368 | #define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
116369 | #define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
116370 | #define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
116371 | #define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
116372 | #define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
116373 | //BIF_BX_PF1_INTERRUPT_CNTL2 |
116374 | #define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
116375 | #define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
116376 | //BIF_BX_PF1_CLKREQB_PAD_CNTL |
116377 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
116378 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
116379 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
116380 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
116381 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
116382 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
116383 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
116384 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
116385 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
116386 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
116387 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
116388 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
116389 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
116390 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
116391 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
116392 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
116393 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
116394 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
116395 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
116396 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
116397 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
116398 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
116399 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
116400 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
116401 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
116402 | #define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
116403 | //BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC |
116404 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
116405 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
116406 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
116407 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
116408 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
116409 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
116410 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
116411 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 |
116412 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 |
116413 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
116414 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
116415 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
116416 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
116417 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
116418 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
116419 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
116420 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
116421 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L |
116422 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L |
116423 | #define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
116424 | //BIF_BX_PF1_BIF_DOORBELL_CNTL |
116425 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
116426 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
116427 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
116428 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
116429 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
116430 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
116431 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
116432 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
116433 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
116434 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
116435 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
116436 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
116437 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
116438 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
116439 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
116440 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
116441 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
116442 | #define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
116443 | //BIF_BX_PF1_BIF_DOORBELL_INT_CNTL |
116444 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
116445 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 |
116446 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
116447 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 |
116448 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
116449 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L |
116450 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
116451 | #define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L |
116452 | //BIF_BX_PF1_BIF_FB_EN |
116453 | #define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
116454 | #define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
116455 | #define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
116456 | #define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
116457 | //BIF_BX_PF1_BIF_BUSY_DELAY_CNTR |
116458 | #define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 |
116459 | #define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL |
116460 | //BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF |
116461 | #define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
116462 | #define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL |
116463 | //BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF |
116464 | #define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
116465 | #define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL |
116466 | //BIF_BX_PF1_BACO_CNTL |
116467 | #define BIF_BX_PF1_BACO_CNTL__BACO_EN__SHIFT 0x0 |
116468 | #define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 |
116469 | #define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
116470 | #define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
116471 | #define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
116472 | #define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
116473 | #define BIF_BX_PF1_BACO_CNTL__BACO_MODE__SHIFT 0x8 |
116474 | #define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
116475 | #define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
116476 | #define BIF_BX_PF1_BACO_CNTL__BACO_EN_MASK 0x00000001L |
116477 | #define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L |
116478 | #define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
116479 | #define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
116480 | #define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
116481 | #define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
116482 | #define BIF_BX_PF1_BACO_CNTL__BACO_MODE_MASK 0x00000100L |
116483 | #define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
116484 | #define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
116485 | //BIF_BX_PF1_BIF_BACO_EXIT_TIME0 |
116486 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
116487 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
116488 | //BIF_BX_PF1_BIF_BACO_EXIT_TIMER1 |
116489 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
116490 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
116491 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19 |
116492 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
116493 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
116494 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
116495 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
116496 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
116497 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
116498 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
116499 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L |
116500 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
116501 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
116502 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
116503 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
116504 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
116505 | //BIF_BX_PF1_BIF_BACO_EXIT_TIMER2 |
116506 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
116507 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
116508 | //BIF_BX_PF1_BIF_BACO_EXIT_TIMER3 |
116509 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
116510 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
116511 | //BIF_BX_PF1_BIF_BACO_EXIT_TIMER4 |
116512 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
116513 | #define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
116514 | //BIF_BX_PF1_MEM_TYPE_CNTL |
116515 | #define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
116516 | #define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
116517 | //BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS |
116518 | #define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 |
116519 | #define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L |
116520 | //BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER |
116521 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 |
116522 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e |
116523 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f |
116524 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL |
116525 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L |
116526 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L |
116527 | //BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER |
116528 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 |
116529 | #define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL |
116530 | //BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER |
116531 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 |
116532 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e |
116533 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f |
116534 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL |
116535 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L |
116536 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L |
116537 | //BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER |
116538 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 |
116539 | #define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL |
116540 | //BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER |
116541 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 |
116542 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e |
116543 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f |
116544 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL |
116545 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L |
116546 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L |
116547 | //BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER |
116548 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 |
116549 | #define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL |
116550 | //BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER |
116551 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 |
116552 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e |
116553 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f |
116554 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL |
116555 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L |
116556 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L |
116557 | //BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER |
116558 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 |
116559 | #define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL |
116560 | //BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER |
116561 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 |
116562 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e |
116563 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f |
116564 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL |
116565 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L |
116566 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L |
116567 | //BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER |
116568 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 |
116569 | #define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL |
116570 | //BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER |
116571 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 |
116572 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e |
116573 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f |
116574 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL |
116575 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L |
116576 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L |
116577 | //BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER |
116578 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 |
116579 | #define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL |
116580 | //BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER |
116581 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 |
116582 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e |
116583 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f |
116584 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL |
116585 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L |
116586 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L |
116587 | //BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER |
116588 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 |
116589 | #define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL |
116590 | //BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER |
116591 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 |
116592 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e |
116593 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f |
116594 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL |
116595 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L |
116596 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L |
116597 | //BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER |
116598 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 |
116599 | #define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL |
116600 | //BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER |
116601 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 |
116602 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e |
116603 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f |
116604 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL |
116605 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L |
116606 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L |
116607 | //BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER |
116608 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 |
116609 | #define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL |
116610 | //BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER |
116611 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 |
116612 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e |
116613 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f |
116614 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL |
116615 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L |
116616 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L |
116617 | //BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER |
116618 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 |
116619 | #define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL |
116620 | //BIF_BX_PF1_BIF_VDDGFX_FB_CMP |
116621 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 |
116622 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 |
116623 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 |
116624 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 |
116625 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 |
116626 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 |
116627 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L |
116628 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L |
116629 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L |
116630 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L |
116631 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L |
116632 | #define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L |
116633 | //BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER |
116634 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 |
116635 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f |
116636 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL |
116637 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L |
116638 | //BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER |
116639 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 |
116640 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL |
116641 | //BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER |
116642 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 |
116643 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f |
116644 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL |
116645 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L |
116646 | //BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER |
116647 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 |
116648 | #define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL |
116649 | //BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL |
116650 | #define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
116651 | #define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
116652 | //BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL |
116653 | #define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
116654 | #define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
116655 | //BIF_BX_PF1_BIF_RB_CNTL |
116656 | #define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
116657 | #define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
116658 | #define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
116659 | #define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
116660 | #define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
116661 | #define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
116662 | #define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
116663 | #define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
116664 | #define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
116665 | #define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
116666 | #define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
116667 | #define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
116668 | //BIF_BX_PF1_BIF_RB_BASE |
116669 | #define BIF_BX_PF1_BIF_RB_BASE__ADDR__SHIFT 0x0 |
116670 | #define BIF_BX_PF1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
116671 | //BIF_BX_PF1_BIF_RB_RPTR |
116672 | #define BIF_BX_PF1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
116673 | #define BIF_BX_PF1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
116674 | //BIF_BX_PF1_BIF_RB_WPTR |
116675 | #define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
116676 | #define BIF_BX_PF1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
116677 | #define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
116678 | #define BIF_BX_PF1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
116679 | //BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI |
116680 | #define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
116681 | #define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
116682 | //BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO |
116683 | #define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
116684 | #define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
116685 | //BIF_BX_PF1_MAILBOX_INDEX |
116686 | #define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
116687 | #define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
116688 | //BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE |
116689 | #define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 |
116690 | #define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
116691 | //BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE |
116692 | #define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 |
116693 | #define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
116694 | //BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
116695 | #define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
116696 | #define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
116697 | //BIF_BX_PF1_BIF_PERSTB_PAD_CNTL |
116698 | #define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
116699 | #define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
116700 | //BIF_BX_PF1_BIF_PX_EN_PAD_CNTL |
116701 | #define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
116702 | #define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
116703 | //BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL |
116704 | #define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
116705 | #define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
116706 | //BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL |
116707 | #define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
116708 | #define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
116709 | |
116710 | |
116711 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
116712 | //BIF_BX_PF1_BIF_BME_STATUS |
116713 | #define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
116714 | #define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
116715 | #define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
116716 | #define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
116717 | //BIF_BX_PF1_BIF_ATOMIC_ERR_LOG |
116718 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
116719 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
116720 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
116721 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
116722 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
116723 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
116724 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
116725 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
116726 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
116727 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
116728 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
116729 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
116730 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
116731 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
116732 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
116733 | #define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
116734 | //BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
116735 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
116736 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
116737 | //BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
116738 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
116739 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
116740 | //BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL |
116741 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
116742 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
116743 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
116744 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
116745 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
116746 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
116747 | //BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL |
116748 | #define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
116749 | #define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
116750 | //BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL |
116751 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
116752 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
116753 | //BIF_BX_PF1_GPU_HDP_FLUSH_REQ |
116754 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
116755 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
116756 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
116757 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
116758 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
116759 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
116760 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
116761 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
116762 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
116763 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
116764 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
116765 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
116766 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
116767 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
116768 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
116769 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
116770 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
116771 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
116772 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
116773 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
116774 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
116775 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
116776 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
116777 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
116778 | //BIF_BX_PF1_GPU_HDP_FLUSH_DONE |
116779 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
116780 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
116781 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
116782 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
116783 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
116784 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
116785 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
116786 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
116787 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
116788 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
116789 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
116790 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
116791 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
116792 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
116793 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
116794 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
116795 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
116796 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
116797 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
116798 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
116799 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
116800 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
116801 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
116802 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
116803 | //BIF_BX_PF1_BIF_TRANS_PENDING |
116804 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
116805 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
116806 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
116807 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
116808 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 |
116809 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
116810 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116811 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 |
116812 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
116813 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116814 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 |
116815 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
116816 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116817 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 |
116818 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
116819 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116820 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 |
116821 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
116822 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116823 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 |
116824 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
116825 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116826 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 |
116827 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
116828 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116829 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 |
116830 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
116831 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
116832 | //BIF_BX_PF1_MAILBOX_CONTROL |
116833 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
116834 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
116835 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
116836 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
116837 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
116838 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
116839 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
116840 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
116841 | //BIF_BX_PF1_MAILBOX_INT_CNTL |
116842 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
116843 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
116844 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
116845 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
116846 | //BIF_BX_PF1_BIF_VMHV_MAILBOX |
116847 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
116848 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
116849 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
116850 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
116851 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
116852 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
116853 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
116854 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
116855 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
116856 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
116857 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
116858 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
116859 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
116860 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
116861 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
116862 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
116863 | |
116864 | |
116865 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
116866 | //GDC1_NGDC_SDP_PORT_CTRL |
116867 | #define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
116868 | #define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL |
116869 | //GDC1_SHUB_REGS_IF_CTL |
116870 | #define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
116871 | #define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
116872 | //GDC1_NGDC_RESERVED_0 |
116873 | #define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 |
116874 | #define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL |
116875 | //GDC1_NGDC_RESERVED_1 |
116876 | #define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 |
116877 | #define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL |
116878 | //GDC1_NGDC_SDP_PORT_CTRL_SOCCLK |
116879 | #define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 |
116880 | #define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL |
116881 | //GDC1_BIF_SDMA0_DOORBELL_RANGE |
116882 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
116883 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
116884 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
116885 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
116886 | //GDC1_BIF_SDMA1_DOORBELL_RANGE |
116887 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
116888 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
116889 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
116890 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
116891 | //GDC1_BIF_IH_DOORBELL_RANGE |
116892 | #define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
116893 | #define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
116894 | #define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
116895 | #define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
116896 | //GDC1_BIF_MMSCH0_DOORBELL_RANGE |
116897 | #define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
116898 | #define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
116899 | #define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
116900 | #define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
116901 | //GDC1_ATDMA_MISC_CNTL |
116902 | #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 |
116903 | #define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 |
116904 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 |
116905 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 |
116906 | #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L |
116907 | #define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L |
116908 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L |
116909 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L |
116910 | //GDC1_BIF_DOORBELL_FENCE_CNTL |
116911 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 |
116912 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L |
116913 | //GDC1_S2A_MISC_CNTL |
116914 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 |
116915 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 |
116916 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 |
116917 | #define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 |
116918 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L |
116919 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L |
116920 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L |
116921 | #define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L |
116922 | //GDC1_GDC_PG_MISC_CNTL |
116923 | #define GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0 |
116924 | #define GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L |
116925 | |
116926 | |
116927 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
116928 | //MM_INDEX |
116929 | #define MM_INDEX__MM_OFFSET__SHIFT 0x0 |
116930 | #define MM_INDEX__MM_APER__SHIFT 0x1f |
116931 | #define MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
116932 | #define MM_INDEX__MM_APER_MASK 0x80000000L |
116933 | //MM_DATA |
116934 | #define MM_DATA__MM_DATA__SHIFT 0x0 |
116935 | #define MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
116936 | //MM_INDEX_HI |
116937 | #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
116938 | #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
116939 | |
116940 | |
116941 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
116942 | //SYSHUB_INDEX_OVLP |
116943 | #define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 |
116944 | #define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL |
116945 | //SYSHUB_DATA_OVLP |
116946 | #define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 |
116947 | #define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL |
116948 | //PCIE_INDEX |
116949 | #define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
116950 | #define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
116951 | //PCIE_DATA |
116952 | #define PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
116953 | #define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
116954 | //PCIE_INDEX2 |
116955 | #define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
116956 | #define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
116957 | //PCIE_DATA2 |
116958 | #define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
116959 | #define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
116960 | //SBIOS_SCRATCH_0 |
116961 | #define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
116962 | #define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
116963 | //SBIOS_SCRATCH_1 |
116964 | #define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
116965 | #define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
116966 | //SBIOS_SCRATCH_2 |
116967 | #define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
116968 | #define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
116969 | //SBIOS_SCRATCH_3 |
116970 | #define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
116971 | #define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
116972 | //BIOS_SCRATCH_0 |
116973 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
116974 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
116975 | //BIOS_SCRATCH_1 |
116976 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
116977 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
116978 | //BIOS_SCRATCH_2 |
116979 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
116980 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
116981 | //BIOS_SCRATCH_3 |
116982 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
116983 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
116984 | //BIOS_SCRATCH_4 |
116985 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
116986 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
116987 | //BIOS_SCRATCH_5 |
116988 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
116989 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
116990 | //BIOS_SCRATCH_6 |
116991 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
116992 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
116993 | //BIOS_SCRATCH_7 |
116994 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
116995 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
116996 | //BIOS_SCRATCH_8 |
116997 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
116998 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
116999 | //BIOS_SCRATCH_9 |
117000 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
117001 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
117002 | //BIOS_SCRATCH_10 |
117003 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
117004 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
117005 | //BIOS_SCRATCH_11 |
117006 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
117007 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
117008 | //BIOS_SCRATCH_12 |
117009 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
117010 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
117011 | //BIOS_SCRATCH_13 |
117012 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
117013 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
117014 | //BIOS_SCRATCH_14 |
117015 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
117016 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
117017 | //BIOS_SCRATCH_15 |
117018 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
117019 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
117020 | //BIF_RLC_INTR_CNTL |
117021 | #define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
117022 | #define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
117023 | #define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
117024 | #define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
117025 | #define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
117026 | #define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
117027 | #define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
117028 | #define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
117029 | //BIF_VCE_INTR_CNTL |
117030 | #define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
117031 | #define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
117032 | #define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
117033 | #define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
117034 | #define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
117035 | #define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
117036 | #define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
117037 | #define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
117038 | //BIF_UVD_INTR_CNTL |
117039 | #define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
117040 | #define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
117041 | #define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
117042 | #define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
117043 | #define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
117044 | #define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
117045 | #define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
117046 | #define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
117047 | //GFX_MMIOREG_CAM_ADDR0 |
117048 | #define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
117049 | #define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
117050 | //GFX_MMIOREG_CAM_REMAP_ADDR0 |
117051 | #define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
117052 | #define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
117053 | //GFX_MMIOREG_CAM_ADDR1 |
117054 | #define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
117055 | #define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
117056 | //GFX_MMIOREG_CAM_REMAP_ADDR1 |
117057 | #define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
117058 | #define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
117059 | //GFX_MMIOREG_CAM_ADDR2 |
117060 | #define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
117061 | #define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
117062 | //GFX_MMIOREG_CAM_REMAP_ADDR2 |
117063 | #define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
117064 | #define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
117065 | //GFX_MMIOREG_CAM_ADDR3 |
117066 | #define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
117067 | #define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
117068 | //GFX_MMIOREG_CAM_REMAP_ADDR3 |
117069 | #define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
117070 | #define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
117071 | //GFX_MMIOREG_CAM_ADDR4 |
117072 | #define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
117073 | #define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
117074 | //GFX_MMIOREG_CAM_REMAP_ADDR4 |
117075 | #define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
117076 | #define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
117077 | //GFX_MMIOREG_CAM_ADDR5 |
117078 | #define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
117079 | #define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
117080 | //GFX_MMIOREG_CAM_REMAP_ADDR5 |
117081 | #define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
117082 | #define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
117083 | //GFX_MMIOREG_CAM_ADDR6 |
117084 | #define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
117085 | #define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
117086 | //GFX_MMIOREG_CAM_REMAP_ADDR6 |
117087 | #define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
117088 | #define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
117089 | //GFX_MMIOREG_CAM_ADDR7 |
117090 | #define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
117091 | #define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
117092 | //GFX_MMIOREG_CAM_REMAP_ADDR7 |
117093 | #define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
117094 | #define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
117095 | //GFX_MMIOREG_CAM_CNTL |
117096 | #define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
117097 | #define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
117098 | //GFX_MMIOREG_CAM_ZERO_CPL |
117099 | #define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
117100 | #define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
117101 | //GFX_MMIOREG_CAM_ONE_CPL |
117102 | #define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
117103 | #define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
117104 | //GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
117105 | #define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
117106 | #define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
117107 | |
117108 | |
117109 | // addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec |
117110 | //SYSHUB_INDEX |
117111 | #define SYSHUB_INDEX__INDEX__SHIFT 0x0 |
117112 | #define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL |
117113 | //SYSHUB_DATA |
117114 | #define SYSHUB_DATA__DATA__SHIFT 0x0 |
117115 | #define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL |
117116 | |
117117 | |
117118 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
117119 | //RCC_DEV0_EPF0_STRAP0 |
117120 | #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
117121 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
117122 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
117123 | #define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
117124 | #define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
117125 | #define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
117126 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
117127 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
117128 | #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
117129 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
117130 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
117131 | #define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
117132 | #define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
117133 | #define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
117134 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
117135 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
117136 | |
117137 | |
117138 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
117139 | //EP_PCIE_SCRATCH |
117140 | #define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
117141 | #define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
117142 | //EP_PCIE_CNTL |
117143 | #define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
117144 | #define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
117145 | #define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
117146 | #define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
117147 | #define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
117148 | #define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
117149 | //EP_PCIE_INT_CNTL |
117150 | #define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
117151 | #define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
117152 | #define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
117153 | #define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
117154 | #define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
117155 | #define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
117156 | #define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
117157 | #define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
117158 | #define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
117159 | #define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
117160 | #define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
117161 | #define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
117162 | //EP_PCIE_INT_STATUS |
117163 | #define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
117164 | #define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
117165 | #define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
117166 | #define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
117167 | #define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
117168 | #define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
117169 | #define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
117170 | #define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
117171 | #define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
117172 | #define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
117173 | #define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
117174 | #define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
117175 | //EP_PCIE_RX_CNTL2 |
117176 | #define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
117177 | #define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
117178 | //EP_PCIE_BUS_CNTL |
117179 | #define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
117180 | #define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
117181 | //EP_PCIE_CFG_CNTL |
117182 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
117183 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
117184 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
117185 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
117186 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
117187 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
117188 | //EP_PCIE_TX_LTR_CNTL |
117189 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
117190 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
117191 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
117192 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
117193 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
117194 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
117195 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
117196 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
117197 | #define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
117198 | #define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
117199 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
117200 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
117201 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
117202 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
117203 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
117204 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
117205 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
117206 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
117207 | #define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
117208 | #define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
117209 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
117210 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117211 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117212 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
117213 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117214 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117215 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
117216 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117217 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117218 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
117219 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117220 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117221 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
117222 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117223 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117224 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
117225 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117226 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117227 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
117228 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117229 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117230 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
117231 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117232 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117233 | //EP_PCIE_F0_DPA_CAP |
117234 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
117235 | #define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
117236 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
117237 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
117238 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
117239 | #define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
117240 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
117241 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
117242 | //EP_PCIE_F0_DPA_LATENCY_INDICATOR |
117243 | #define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
117244 | #define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
117245 | //EP_PCIE_F0_DPA_CNTL |
117246 | #define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
117247 | #define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
117248 | #define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
117249 | #define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
117250 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
117251 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117252 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117253 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
117254 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117255 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117256 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
117257 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117258 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117259 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
117260 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117261 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117262 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
117263 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117264 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117265 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
117266 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117267 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117268 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
117269 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117270 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117271 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
117272 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
117273 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
117274 | //EP_PCIE_PME_CONTROL |
117275 | #define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
117276 | #define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
117277 | //EP_PCIEP_RESERVED |
117278 | #define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
117279 | #define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
117280 | //EP_PCIE_TX_CNTL |
117281 | #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
117282 | #define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
117283 | #define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
117284 | #define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
117285 | #define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
117286 | #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
117287 | #define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
117288 | #define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
117289 | #define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
117290 | #define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
117291 | //EP_PCIE_TX_REQUESTER_ID |
117292 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
117293 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
117294 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
117295 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
117296 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
117297 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
117298 | //EP_PCIE_ERR_CNTL |
117299 | #define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
117300 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
117301 | #define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
117302 | #define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
117303 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
117304 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
117305 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
117306 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
117307 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
117308 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
117309 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
117310 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
117311 | #define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
117312 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
117313 | #define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
117314 | #define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
117315 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
117316 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
117317 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
117318 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
117319 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
117320 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
117321 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
117322 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
117323 | //EP_PCIE_RX_CNTL |
117324 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
117325 | #define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
117326 | #define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
117327 | #define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
117328 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
117329 | #define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
117330 | #define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
117331 | #define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
117332 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
117333 | #define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
117334 | #define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
117335 | #define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
117336 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
117337 | #define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
117338 | #define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
117339 | #define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
117340 | //EP_PCIE_LC_SPEED_CNTL |
117341 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
117342 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
117343 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
117344 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
117345 | |
117346 | |
117347 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
117348 | //DN_PCIE_RESERVED |
117349 | #define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
117350 | #define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
117351 | //DN_PCIE_SCRATCH |
117352 | #define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
117353 | #define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
117354 | //DN_PCIE_CNTL |
117355 | #define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
117356 | #define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
117357 | #define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
117358 | #define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
117359 | #define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
117360 | #define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
117361 | //DN_PCIE_CONFIG_CNTL |
117362 | #define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
117363 | #define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
117364 | //DN_PCIE_RX_CNTL2 |
117365 | #define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
117366 | #define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
117367 | //DN_PCIE_BUS_CNTL |
117368 | #define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
117369 | #define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
117370 | #define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
117371 | #define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
117372 | //DN_PCIE_CFG_CNTL |
117373 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
117374 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
117375 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
117376 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
117377 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
117378 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
117379 | |
117380 | |
117381 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
117382 | //PCIE_ERR_CNTL |
117383 | #define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
117384 | #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
117385 | #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
117386 | #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
117387 | #define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
117388 | #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
117389 | #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
117390 | #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
117391 | //PCIE_RX_CNTL |
117392 | #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
117393 | #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
117394 | #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
117395 | #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
117396 | #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
117397 | #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
117398 | #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
117399 | #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
117400 | #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
117401 | #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
117402 | //PCIE_LC_SPEED_CNTL |
117403 | #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
117404 | #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
117405 | #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
117406 | #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
117407 | //PCIE_LC_CNTL2 |
117408 | #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
117409 | #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
117410 | //PCIEP_STRAP_MISC |
117411 | #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
117412 | #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
117413 | //LTR_MSG_INFO_FROM_EP |
117414 | #define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
117415 | #define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
117416 | |
117417 | |
117418 | // addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 |
117419 | //RCC_ERR_LOG |
117420 | #define RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
117421 | #define RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
117422 | #define RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
117423 | #define RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
117424 | //RCC_DOORBELL_APER_EN |
117425 | #define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
117426 | #define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
117427 | //RCC_CONFIG_MEMSIZE |
117428 | #define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
117429 | #define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
117430 | //RCC_CONFIG_RESERVED |
117431 | #define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
117432 | #define RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
117433 | //RCC_IOV_FUNC_IDENTIFIER |
117434 | #define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
117435 | #define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
117436 | #define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
117437 | #define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
117438 | |
117439 | |
117440 | // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 |
117441 | //RCC_ERR_INT_CNTL |
117442 | #define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 |
117443 | #define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L |
117444 | //RCC_BACO_CNTL_MISC |
117445 | #define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 |
117446 | #define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 |
117447 | #define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L |
117448 | #define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L |
117449 | //RCC_RESET_EN |
117450 | #define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf |
117451 | #define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L |
117452 | //RCC_VDM_SUPPORT |
117453 | #define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 |
117454 | #define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 |
117455 | #define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 |
117456 | #define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 |
117457 | #define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 |
117458 | #define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L |
117459 | #define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L |
117460 | #define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L |
117461 | #define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L |
117462 | #define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L |
117463 | //RCC_PEER_REG_RANGE0 |
117464 | #define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 |
117465 | #define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 |
117466 | #define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL |
117467 | #define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L |
117468 | //RCC_PEER_REG_RANGE1 |
117469 | #define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 |
117470 | #define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 |
117471 | #define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL |
117472 | #define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L |
117473 | //RCC_BUS_CNTL |
117474 | #define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 |
117475 | #define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 |
117476 | #define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 |
117477 | #define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 |
117478 | #define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 |
117479 | #define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 |
117480 | #define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 |
117481 | #define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc |
117482 | #define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd |
117483 | #define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 |
117484 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 |
117485 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 |
117486 | #define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 |
117487 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 |
117488 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 |
117489 | #define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 |
117490 | #define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 |
117491 | #define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c |
117492 | #define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d |
117493 | #define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L |
117494 | #define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L |
117495 | #define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L |
117496 | #define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L |
117497 | #define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L |
117498 | #define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L |
117499 | #define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L |
117500 | #define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L |
117501 | #define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L |
117502 | #define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L |
117503 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L |
117504 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L |
117505 | #define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L |
117506 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L |
117507 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L |
117508 | #define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L |
117509 | #define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L |
117510 | #define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L |
117511 | #define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L |
117512 | //RCC_CONFIG_CNTL |
117513 | #define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 |
117514 | #define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 |
117515 | #define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 |
117516 | #define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L |
117517 | #define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L |
117518 | #define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L |
117519 | //RCC_CONFIG_F0_BASE |
117520 | #define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 |
117521 | #define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL |
117522 | //RCC_CONFIG_APER_SIZE |
117523 | #define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 |
117524 | #define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL |
117525 | //RCC_CONFIG_REG_APER_SIZE |
117526 | #define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 |
117527 | #define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000FFFFFL |
117528 | //RCC_XDMA_LO |
117529 | #define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 |
117530 | #define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f |
117531 | #define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL |
117532 | #define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L |
117533 | //RCC_XDMA_HI |
117534 | #define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 |
117535 | #define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL |
117536 | //RCC_FEATURES_CONTROL_MISC |
117537 | #define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 |
117538 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 |
117539 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 |
117540 | #define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 |
117541 | #define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 |
117542 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 |
117543 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa |
117544 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb |
117545 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc |
117546 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd |
117547 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe |
117548 | #define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf |
117549 | #define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 |
117550 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 |
117551 | #define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 |
117552 | #define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 |
117553 | #define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L |
117554 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L |
117555 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L |
117556 | #define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L |
117557 | #define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L |
117558 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L |
117559 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L |
117560 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L |
117561 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L |
117562 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L |
117563 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L |
117564 | #define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L |
117565 | #define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L |
117566 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L |
117567 | #define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L |
117568 | #define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L |
117569 | //RCC_BUSNUM_CNTL1 |
117570 | #define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 |
117571 | #define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL |
117572 | //RCC_BUSNUM_LIST0 |
117573 | #define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 |
117574 | #define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 |
117575 | #define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 |
117576 | #define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 |
117577 | #define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL |
117578 | #define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L |
117579 | #define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L |
117580 | #define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L |
117581 | //RCC_BUSNUM_LIST1 |
117582 | #define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 |
117583 | #define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 |
117584 | #define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 |
117585 | #define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 |
117586 | #define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL |
117587 | #define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L |
117588 | #define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L |
117589 | #define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L |
117590 | //RCC_BUSNUM_CNTL2 |
117591 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 |
117592 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 |
117593 | #define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 |
117594 | #define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 |
117595 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL |
117596 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L |
117597 | #define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L |
117598 | #define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L |
117599 | //RCC_CAPTURE_HOST_BUSNUM |
117600 | #define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 |
117601 | #define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L |
117602 | //RCC_HOST_BUSNUM |
117603 | #define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 |
117604 | #define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL |
117605 | //RCC_PEER0_FB_OFFSET_HI |
117606 | #define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 |
117607 | #define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL |
117608 | //RCC_PEER0_FB_OFFSET_LO |
117609 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 |
117610 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f |
117611 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL |
117612 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L |
117613 | //RCC_PEER1_FB_OFFSET_HI |
117614 | #define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 |
117615 | #define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL |
117616 | //RCC_PEER1_FB_OFFSET_LO |
117617 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 |
117618 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f |
117619 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL |
117620 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L |
117621 | //RCC_PEER2_FB_OFFSET_HI |
117622 | #define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 |
117623 | #define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL |
117624 | //RCC_PEER2_FB_OFFSET_LO |
117625 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 |
117626 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f |
117627 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL |
117628 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L |
117629 | //RCC_PEER3_FB_OFFSET_HI |
117630 | #define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 |
117631 | #define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL |
117632 | //RCC_PEER3_FB_OFFSET_LO |
117633 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 |
117634 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f |
117635 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL |
117636 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L |
117637 | //RCC_CMN_LINK_CNTL |
117638 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 |
117639 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 |
117640 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 |
117641 | #define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 |
117642 | #define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 |
117643 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L |
117644 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L |
117645 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L |
117646 | #define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L |
117647 | #define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L |
117648 | //RCC_EP_REQUESTERID_RESTORE |
117649 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 |
117650 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 |
117651 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL |
117652 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L |
117653 | //RCC_LTR_LSWITCH_CNTL |
117654 | #define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 |
117655 | #define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL |
117656 | //RCC_MH_ARB_CNTL |
117657 | #define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 |
117658 | #define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 |
117659 | #define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L |
117660 | #define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL |
117661 | |
117662 | |
117663 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
117664 | //BIF_MM_INDACCESS_CNTL |
117665 | #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
117666 | #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
117667 | //BUS_CNTL |
117668 | #define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 |
117669 | #define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 |
117670 | #define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 |
117671 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
117672 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
117673 | #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
117674 | #define BUS_CNTL__SET_MC_TC__SHIFT 0xd |
117675 | #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
117676 | #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
117677 | #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
117678 | #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 |
117679 | #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 |
117680 | #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 |
117681 | #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 |
117682 | #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 |
117683 | #define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 |
117684 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
117685 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
117686 | #define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b |
117687 | #define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c |
117688 | #define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
117689 | #define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
117690 | #define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
117691 | #define BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L |
117692 | #define BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L |
117693 | #define BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L |
117694 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
117695 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
117696 | #define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
117697 | #define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
117698 | #define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
117699 | #define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
117700 | #define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
117701 | #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L |
117702 | #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L |
117703 | #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L |
117704 | #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L |
117705 | #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L |
117706 | #define BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L |
117707 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
117708 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
117709 | #define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L |
117710 | #define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L |
117711 | #define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
117712 | #define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
117713 | #define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
117714 | //BIF_SCRATCH0 |
117715 | #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
117716 | #define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
117717 | //BIF_SCRATCH1 |
117718 | #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
117719 | #define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
117720 | //BX_RESET_EN |
117721 | #define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 |
117722 | #define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 |
117723 | #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 |
117724 | #define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 |
117725 | #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
117726 | #define BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L |
117727 | #define BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L |
117728 | #define BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L |
117729 | #define BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L |
117730 | #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
117731 | //MM_CFGREGS_CNTL |
117732 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
117733 | #define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
117734 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
117735 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
117736 | #define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
117737 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
117738 | //BX_RESET_CNTL |
117739 | #define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
117740 | #define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
117741 | //INTERRUPT_CNTL |
117742 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
117743 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
117744 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
117745 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
117746 | #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
117747 | #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
117748 | #define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
117749 | #define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
117750 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
117751 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
117752 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
117753 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
117754 | #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
117755 | #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
117756 | #define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
117757 | #define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
117758 | //INTERRUPT_CNTL2 |
117759 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
117760 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
117761 | //CLKREQB_PAD_CNTL |
117762 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
117763 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
117764 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
117765 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
117766 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
117767 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
117768 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
117769 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
117770 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
117771 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
117772 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
117773 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
117774 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
117775 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
117776 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
117777 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
117778 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
117779 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
117780 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
117781 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
117782 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
117783 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
117784 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
117785 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
117786 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
117787 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
117788 | //BIF_FEATURES_CONTROL_MISC |
117789 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
117790 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
117791 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
117792 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
117793 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
117794 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
117795 | #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
117796 | #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 |
117797 | #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 |
117798 | #define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
117799 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
117800 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
117801 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
117802 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
117803 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
117804 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
117805 | #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
117806 | #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L |
117807 | #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L |
117808 | #define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
117809 | //BIF_DOORBELL_CNTL |
117810 | #define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
117811 | #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
117812 | #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
117813 | #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
117814 | #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
117815 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
117816 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
117817 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
117818 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
117819 | #define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
117820 | #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
117821 | #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
117822 | #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
117823 | #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
117824 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
117825 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
117826 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
117827 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
117828 | //BIF_DOORBELL_INT_CNTL |
117829 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
117830 | #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 |
117831 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
117832 | #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 |
117833 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
117834 | #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L |
117835 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
117836 | #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L |
117837 | //BIF_FB_EN |
117838 | #define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
117839 | #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
117840 | #define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
117841 | #define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
117842 | //BIF_BUSY_DELAY_CNTR |
117843 | #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 |
117844 | #define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL |
117845 | //BIF_MST_TRANS_PENDING_VF |
117846 | #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
117847 | #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL |
117848 | //BIF_SLV_TRANS_PENDING_VF |
117849 | #define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
117850 | #define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL |
117851 | //BACO_CNTL |
117852 | #define BACO_CNTL__BACO_EN__SHIFT 0x0 |
117853 | #define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 |
117854 | #define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
117855 | #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
117856 | #define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
117857 | #define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
117858 | #define BACO_CNTL__BACO_MODE__SHIFT 0x8 |
117859 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
117860 | #define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
117861 | #define BACO_CNTL__BACO_EN_MASK 0x00000001L |
117862 | #define BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L |
117863 | #define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
117864 | #define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
117865 | #define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
117866 | #define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
117867 | #define BACO_CNTL__BACO_MODE_MASK 0x00000100L |
117868 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
117869 | #define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
117870 | //BIF_BACO_EXIT_TIME0 |
117871 | #define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
117872 | #define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
117873 | //BIF_BACO_EXIT_TIMER1 |
117874 | #define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
117875 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
117876 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19 |
117877 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
117878 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
117879 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
117880 | #define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
117881 | #define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
117882 | #define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
117883 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
117884 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L |
117885 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
117886 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
117887 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
117888 | #define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
117889 | #define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
117890 | //BIF_BACO_EXIT_TIMER2 |
117891 | #define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
117892 | #define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
117893 | //BIF_BACO_EXIT_TIMER3 |
117894 | #define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
117895 | #define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
117896 | //BIF_BACO_EXIT_TIMER4 |
117897 | #define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
117898 | #define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
117899 | //MEM_TYPE_CNTL |
117900 | #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
117901 | #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
117902 | //SMU_BIF_VDDGFX_PWR_STATUS |
117903 | #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 |
117904 | #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L |
117905 | //BIF_VDDGFX_GFX0_LOWER |
117906 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 |
117907 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e |
117908 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f |
117909 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL |
117910 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L |
117911 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L |
117912 | //BIF_VDDGFX_GFX0_UPPER |
117913 | #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 |
117914 | #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL |
117915 | //BIF_VDDGFX_GFX1_LOWER |
117916 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 |
117917 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e |
117918 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f |
117919 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL |
117920 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L |
117921 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L |
117922 | //BIF_VDDGFX_GFX1_UPPER |
117923 | #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 |
117924 | #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL |
117925 | //BIF_VDDGFX_GFX2_LOWER |
117926 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 |
117927 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e |
117928 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f |
117929 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL |
117930 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L |
117931 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L |
117932 | //BIF_VDDGFX_GFX2_UPPER |
117933 | #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 |
117934 | #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL |
117935 | //BIF_VDDGFX_GFX3_LOWER |
117936 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 |
117937 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e |
117938 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f |
117939 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL |
117940 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L |
117941 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L |
117942 | //BIF_VDDGFX_GFX3_UPPER |
117943 | #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 |
117944 | #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL |
117945 | //BIF_VDDGFX_GFX4_LOWER |
117946 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 |
117947 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e |
117948 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f |
117949 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL |
117950 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L |
117951 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L |
117952 | //BIF_VDDGFX_GFX4_UPPER |
117953 | #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 |
117954 | #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL |
117955 | //BIF_VDDGFX_GFX5_LOWER |
117956 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 |
117957 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e |
117958 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f |
117959 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL |
117960 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L |
117961 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L |
117962 | //BIF_VDDGFX_GFX5_UPPER |
117963 | #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 |
117964 | #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL |
117965 | //BIF_VDDGFX_RSV1_LOWER |
117966 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 |
117967 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e |
117968 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f |
117969 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL |
117970 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L |
117971 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L |
117972 | //BIF_VDDGFX_RSV1_UPPER |
117973 | #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 |
117974 | #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL |
117975 | //BIF_VDDGFX_RSV2_LOWER |
117976 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 |
117977 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e |
117978 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f |
117979 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL |
117980 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L |
117981 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L |
117982 | //BIF_VDDGFX_RSV2_UPPER |
117983 | #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 |
117984 | #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL |
117985 | //BIF_VDDGFX_RSV3_LOWER |
117986 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 |
117987 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e |
117988 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f |
117989 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL |
117990 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L |
117991 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L |
117992 | //BIF_VDDGFX_RSV3_UPPER |
117993 | #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 |
117994 | #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL |
117995 | //BIF_VDDGFX_RSV4_LOWER |
117996 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 |
117997 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e |
117998 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f |
117999 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL |
118000 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L |
118001 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L |
118002 | //BIF_VDDGFX_RSV4_UPPER |
118003 | #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 |
118004 | #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL |
118005 | //BIF_VDDGFX_FB_CMP |
118006 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 |
118007 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 |
118008 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 |
118009 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 |
118010 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 |
118011 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 |
118012 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L |
118013 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L |
118014 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L |
118015 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L |
118016 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L |
118017 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L |
118018 | //BIF_DOORBELL_GBLAPER1_LOWER |
118019 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 |
118020 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f |
118021 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL |
118022 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L |
118023 | //BIF_DOORBELL_GBLAPER1_UPPER |
118024 | #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 |
118025 | #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL |
118026 | //BIF_DOORBELL_GBLAPER2_LOWER |
118027 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 |
118028 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f |
118029 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL |
118030 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L |
118031 | //BIF_DOORBELL_GBLAPER2_UPPER |
118032 | #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 |
118033 | #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL |
118034 | //REMAP_HDP_MEM_FLUSH_CNTL |
118035 | #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
118036 | #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
118037 | //REMAP_HDP_REG_FLUSH_CNTL |
118038 | #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
118039 | #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
118040 | //BIF_RB_CNTL |
118041 | #define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
118042 | #define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
118043 | #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
118044 | #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
118045 | #define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
118046 | #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
118047 | #define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
118048 | #define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
118049 | #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
118050 | #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
118051 | #define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
118052 | #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
118053 | //BIF_RB_BASE |
118054 | #define BIF_RB_BASE__ADDR__SHIFT 0x0 |
118055 | #define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
118056 | //BIF_RB_RPTR |
118057 | #define BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
118058 | #define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
118059 | //BIF_RB_WPTR |
118060 | #define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
118061 | #define BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
118062 | #define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
118063 | #define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
118064 | //BIF_RB_WPTR_ADDR_HI |
118065 | #define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
118066 | #define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
118067 | //BIF_RB_WPTR_ADDR_LO |
118068 | #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
118069 | #define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
118070 | //MAILBOX_INDEX |
118071 | #define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
118072 | #define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
118073 | //BIF_UVD_GPUIOV_CFG_SIZE |
118074 | #define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 |
118075 | #define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
118076 | //BIF_VCE_GPUIOV_CFG_SIZE |
118077 | #define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 |
118078 | #define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
118079 | //BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
118080 | #define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
118081 | #define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
118082 | //BIF_PERSTB_PAD_CNTL |
118083 | #define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
118084 | #define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
118085 | //BIF_PX_EN_PAD_CNTL |
118086 | #define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
118087 | #define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
118088 | //BIF_REFPADKIN_PAD_CNTL |
118089 | #define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
118090 | #define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
118091 | //BIF_CLKREQB_PAD_CNTL |
118092 | #define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
118093 | #define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
118094 | |
118095 | |
118096 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
118097 | //BIF_BME_STATUS |
118098 | #define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
118099 | #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
118100 | #define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
118101 | #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
118102 | //BIF_ATOMIC_ERR_LOG |
118103 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
118104 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
118105 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
118106 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
118107 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
118108 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
118109 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
118110 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
118111 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
118112 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
118113 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
118114 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
118115 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
118116 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
118117 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
118118 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
118119 | //DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
118120 | #define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
118121 | #define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
118122 | //DOORBELL_SELFRING_GPA_APER_BASE_LOW |
118123 | #define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
118124 | #define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
118125 | //DOORBELL_SELFRING_GPA_APER_CNTL |
118126 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
118127 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
118128 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
118129 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
118130 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
118131 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
118132 | //HDP_REG_COHERENCY_FLUSH_CNTL |
118133 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
118134 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
118135 | //HDP_MEM_COHERENCY_FLUSH_CNTL |
118136 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
118137 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
118138 | //GPU_HDP_FLUSH_REQ |
118139 | #define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
118140 | #define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
118141 | #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
118142 | #define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
118143 | #define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
118144 | #define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
118145 | #define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
118146 | #define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
118147 | #define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
118148 | #define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
118149 | #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
118150 | #define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
118151 | #define GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
118152 | #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
118153 | #define GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
118154 | #define GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
118155 | #define GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
118156 | #define GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
118157 | #define GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
118158 | #define GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
118159 | #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
118160 | #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
118161 | #define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
118162 | #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
118163 | //GPU_HDP_FLUSH_DONE |
118164 | #define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
118165 | #define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
118166 | #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
118167 | #define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
118168 | #define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
118169 | #define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
118170 | #define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
118171 | #define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
118172 | #define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
118173 | #define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
118174 | #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
118175 | #define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
118176 | #define GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
118177 | #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
118178 | #define GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
118179 | #define GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
118180 | #define GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
118181 | #define GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
118182 | #define GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
118183 | #define GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
118184 | #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
118185 | #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
118186 | #define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
118187 | #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
118188 | //BIF_TRANS_PENDING |
118189 | #define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
118190 | #define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
118191 | #define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
118192 | #define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
118193 | //MAILBOX_MSGBUF_TRN_DW0 |
118194 | #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
118195 | #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118196 | //MAILBOX_MSGBUF_TRN_DW1 |
118197 | #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
118198 | #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118199 | //MAILBOX_MSGBUF_TRN_DW2 |
118200 | #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
118201 | #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118202 | //MAILBOX_MSGBUF_TRN_DW3 |
118203 | #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
118204 | #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118205 | //MAILBOX_MSGBUF_RCV_DW0 |
118206 | #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
118207 | #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118208 | //MAILBOX_MSGBUF_RCV_DW1 |
118209 | #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
118210 | #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118211 | //MAILBOX_MSGBUF_RCV_DW2 |
118212 | #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
118213 | #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118214 | //MAILBOX_MSGBUF_RCV_DW3 |
118215 | #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
118216 | #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
118217 | //MAILBOX_CONTROL |
118218 | #define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
118219 | #define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
118220 | #define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
118221 | #define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
118222 | #define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
118223 | #define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
118224 | #define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
118225 | #define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
118226 | //MAILBOX_INT_CNTL |
118227 | #define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
118228 | #define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
118229 | #define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
118230 | #define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
118231 | //BIF_VMHV_MAILBOX |
118232 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
118233 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
118234 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
118235 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
118236 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
118237 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
118238 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
118239 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
118240 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
118241 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
118242 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
118243 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
118244 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
118245 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
118246 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
118247 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
118248 | |
118249 | |
118250 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
118251 | //NGDC_SDP_PORT_CTRL |
118252 | #define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
118253 | #define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL |
118254 | //SHUB_REGS_IF_CTL |
118255 | #define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
118256 | #define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
118257 | //NGDC_RESERVED_0 |
118258 | #define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 |
118259 | #define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL |
118260 | //NGDC_RESERVED_1 |
118261 | #define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 |
118262 | #define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL |
118263 | //NGDC_SDP_PORT_CTRL_SOCCLK |
118264 | #define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 |
118265 | #define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL |
118266 | //BIF_SDMA0_DOORBELL_RANGE |
118267 | #define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
118268 | #define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
118269 | #define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
118270 | #define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
118271 | //BIF_SDMA1_DOORBELL_RANGE |
118272 | #define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
118273 | #define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
118274 | #define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
118275 | #define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
118276 | //BIF_IH_DOORBELL_RANGE |
118277 | #define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
118278 | #define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
118279 | #define BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
118280 | #define BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
118281 | //BIF_MMSCH0_DOORBELL_RANGE |
118282 | #define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
118283 | #define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
118284 | #define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
118285 | #define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
118286 | //ATDMA_MISC_CNTL |
118287 | #define ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 |
118288 | #define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 |
118289 | #define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 |
118290 | #define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 |
118291 | #define ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L |
118292 | #define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L |
118293 | #define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L |
118294 | #define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L |
118295 | //BIF_DOORBELL_FENCE_CNTL |
118296 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 |
118297 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L |
118298 | //S2A_MISC_CNTL |
118299 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 |
118300 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 |
118301 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 |
118302 | #define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 |
118303 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L |
118304 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L |
118305 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L |
118306 | #define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L |
118307 | //GDC_PG_MISC_CNTL |
118308 | #define GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0 |
118309 | #define GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L |
118310 | |
118311 | |
118312 | // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 |
118313 | //GFXMSIX_VECT0_ADDR_LO |
118314 | #define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
118315 | #define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
118316 | //GFXMSIX_VECT0_ADDR_HI |
118317 | #define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
118318 | #define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
118319 | //GFXMSIX_VECT0_MSG_DATA |
118320 | #define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
118321 | #define GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
118322 | //GFXMSIX_VECT0_CONTROL |
118323 | #define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
118324 | #define GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
118325 | //GFXMSIX_VECT1_ADDR_LO |
118326 | #define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
118327 | #define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
118328 | //GFXMSIX_VECT1_ADDR_HI |
118329 | #define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
118330 | #define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
118331 | //GFXMSIX_VECT1_MSG_DATA |
118332 | #define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
118333 | #define GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
118334 | //GFXMSIX_VECT1_CONTROL |
118335 | #define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
118336 | #define GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
118337 | //GFXMSIX_VECT2_ADDR_LO |
118338 | #define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
118339 | #define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
118340 | //GFXMSIX_VECT2_ADDR_HI |
118341 | #define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
118342 | #define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
118343 | //GFXMSIX_VECT2_MSG_DATA |
118344 | #define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
118345 | #define GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
118346 | //GFXMSIX_VECT2_CONTROL |
118347 | #define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
118348 | #define GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
118349 | //GFXMSIX_PBA |
118350 | #define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
118351 | #define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
118352 | #define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
118353 | #define GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
118354 | #define GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
118355 | #define GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
118356 | |
118357 | |
118358 | // addressBlock: syshub_mmreg_ind_syshubind |
118359 | //SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK |
118360 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 |
118361 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 |
118362 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 |
118363 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 |
118364 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 |
118365 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 |
118366 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 |
118367 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 |
118368 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 |
118369 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 |
118370 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 |
118371 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 |
118372 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 |
118373 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 |
118374 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 |
118375 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 |
118376 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c |
118377 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f |
118378 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L |
118379 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L |
118380 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L |
118381 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L |
118382 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L |
118383 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L |
118384 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L |
118385 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L |
118386 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L |
118387 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L |
118388 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L |
118389 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L |
118390 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L |
118391 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L |
118392 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L |
118393 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L |
118394 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L |
118395 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L |
118396 | //SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK |
118397 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 |
118398 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL |
118399 | //SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK |
118400 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 |
118401 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 |
118402 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf |
118403 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 |
118404 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 |
118405 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L |
118406 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L |
118407 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L |
118408 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L |
118409 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L |
118410 | //SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK |
118411 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 |
118412 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 |
118413 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf |
118414 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 |
118415 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 |
118416 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L |
118417 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L |
118418 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L |
118419 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L |
118420 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L |
118421 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL |
118422 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
118423 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
118424 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
118425 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
118426 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
118427 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
118428 | //SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL |
118429 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
118430 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
118431 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
118432 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
118433 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
118434 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
118435 | //SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL |
118436 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
118437 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
118438 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
118439 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
118440 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
118441 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
118442 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL |
118443 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118444 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118445 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118446 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118447 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118448 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118449 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118450 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118451 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118452 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118453 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118454 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118455 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL |
118456 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118457 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118458 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118459 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118460 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118461 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118462 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118463 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118464 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118465 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118466 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118467 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118468 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL |
118469 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118470 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118471 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118472 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118473 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118474 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118475 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118476 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118477 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118478 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118479 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118480 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118481 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL |
118482 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118483 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118484 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118485 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118486 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118487 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118488 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118489 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118490 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118491 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118492 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118493 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118494 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL |
118495 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118496 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118497 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118498 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118499 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118500 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118501 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118502 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118503 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118504 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118505 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118506 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118507 | //SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL |
118508 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118509 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118510 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118511 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118512 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118513 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118514 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118515 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118516 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118517 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118518 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118519 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118520 | //SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL |
118521 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118522 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118523 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118524 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118525 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118526 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118527 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118528 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118529 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118530 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118531 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118532 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118533 | //SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL |
118534 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118535 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118536 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118537 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118538 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118539 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118540 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118541 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118542 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118543 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118544 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118545 | #define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118546 | //SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL |
118547 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118548 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118549 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118550 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118551 | //SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL |
118552 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118553 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118554 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118555 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118556 | //SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL |
118557 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118558 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118559 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118560 | #define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118561 | //SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL |
118562 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118563 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118564 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118565 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118566 | //SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL |
118567 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118568 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118569 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118570 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118571 | //SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL |
118572 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118573 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118574 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118575 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118576 | //SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL |
118577 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118578 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118579 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118580 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118581 | //SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL |
118582 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118583 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118584 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118585 | #define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118586 | //SYSHUB_MMREG_IND_SYSHUB_CG_CNTL |
118587 | #define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 |
118588 | #define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 |
118589 | #define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 |
118590 | #define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L |
118591 | #define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L |
118592 | #define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L |
118593 | //SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE |
118594 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 |
118595 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 |
118596 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 |
118597 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 |
118598 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 |
118599 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 |
118600 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 |
118601 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 |
118602 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 |
118603 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 |
118604 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa |
118605 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb |
118606 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc |
118607 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd |
118608 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe |
118609 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf |
118610 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 |
118611 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L |
118612 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L |
118613 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L |
118614 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L |
118615 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L |
118616 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L |
118617 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L |
118618 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L |
118619 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L |
118620 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L |
118621 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L |
118622 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L |
118623 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L |
118624 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L |
118625 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L |
118626 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L |
118627 | #define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L |
118628 | //SYSHUB_MMREG_IND_SYSHUB_HP_TIMER |
118629 | #define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 |
118630 | #define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL |
118631 | //SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK |
118632 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 |
118633 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 |
118634 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 |
118635 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa |
118636 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb |
118637 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc |
118638 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd |
118639 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L |
118640 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L |
118641 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL |
118642 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L |
118643 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L |
118644 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L |
118645 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L |
118646 | //SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET |
118647 | #define SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET__SHIFT 0x0 |
118648 | #define SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET_MASK 0x00000001L |
118649 | //SYSHUB_MMREG_IND_SYSHUB_SCRATCH |
118650 | #define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 |
118651 | #define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
118652 | //SYSHUB_MMREG_IND_SYSHUB_CL_MASK |
118653 | #define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1 |
118654 | #define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2 |
118655 | #define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L |
118656 | #define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L |
118657 | //SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK |
118658 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 |
118659 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 |
118660 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 |
118661 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 |
118662 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 |
118663 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 |
118664 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 |
118665 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 |
118666 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 |
118667 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 |
118668 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 |
118669 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 |
118670 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 |
118671 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 |
118672 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 |
118673 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 |
118674 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c |
118675 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f |
118676 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L |
118677 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L |
118678 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L |
118679 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L |
118680 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L |
118681 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L |
118682 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L |
118683 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L |
118684 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L |
118685 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L |
118686 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L |
118687 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L |
118688 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L |
118689 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L |
118690 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L |
118691 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L |
118692 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L |
118693 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L |
118694 | //SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK |
118695 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 |
118696 | #define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL |
118697 | //SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK |
118698 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf |
118699 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 |
118700 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L |
118701 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L |
118702 | //SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK |
118703 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf |
118704 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 |
118705 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L |
118706 | #define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L |
118707 | //SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL |
118708 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
118709 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
118710 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
118711 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
118712 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
118713 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
118714 | //SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL |
118715 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
118716 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
118717 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
118718 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
118719 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
118720 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
118721 | //SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL |
118722 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118723 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118724 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118725 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118726 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118727 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118728 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118729 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118730 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118731 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118732 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118733 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118734 | //SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL |
118735 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118736 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118737 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118738 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118739 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118740 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118741 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118742 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118743 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118744 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118745 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118746 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118747 | //SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL |
118748 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118749 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118750 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118751 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118752 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118753 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118754 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118755 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118756 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118757 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118758 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118759 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118760 | //SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL |
118761 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118762 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118763 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118764 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118765 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118766 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118767 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118768 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118769 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118770 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118771 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118772 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118773 | //SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL |
118774 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118775 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118776 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118777 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118778 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118779 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118780 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118781 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118782 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118783 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118784 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118785 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118786 | //SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL |
118787 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118788 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118789 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118790 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118791 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118792 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118793 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118794 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118795 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118796 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118797 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118798 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118799 | //SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL |
118800 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118801 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118802 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118803 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118804 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118805 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118806 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118807 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118808 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118809 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118810 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118811 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118812 | //SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL |
118813 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118814 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118815 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118816 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118817 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118818 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118819 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118820 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118821 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118822 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118823 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118824 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118825 | //SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL |
118826 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118827 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118828 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118829 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118830 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118831 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118832 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118833 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118834 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118835 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118836 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118837 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118838 | //SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL |
118839 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
118840 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
118841 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
118842 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
118843 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
118844 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
118845 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
118846 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
118847 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
118848 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
118849 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
118850 | #define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
118851 | //SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK |
118852 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0 |
118853 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1 |
118854 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2 |
118855 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa |
118856 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb |
118857 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc |
118858 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L |
118859 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L |
118860 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL |
118861 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L |
118862 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L |
118863 | #define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L |
118864 | //SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD |
118865 | #define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118866 | #define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118867 | #define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118868 | #define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118869 | //SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS |
118870 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
118871 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
118872 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
118873 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
118874 | //SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS |
118875 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
118876 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
118877 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
118878 | #define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
118879 | //SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD |
118880 | #define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118881 | #define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118882 | #define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118883 | #define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118884 | //SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD |
118885 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118886 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118887 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118888 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118889 | //SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD |
118890 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
118891 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
118892 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
118893 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
118894 | //SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD |
118895 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0 |
118896 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1 |
118897 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L |
118898 | #define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L |
118899 | //SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD |
118900 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118901 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118902 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118903 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118904 | //SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD |
118905 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
118906 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
118907 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
118908 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
118909 | //SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD |
118910 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 |
118911 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 |
118912 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L |
118913 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L |
118914 | //SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD |
118915 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 |
118916 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 |
118917 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L |
118918 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L |
118919 | //SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD |
118920 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 |
118921 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 |
118922 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L |
118923 | #define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L |
118924 | //SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS |
118925 | #define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
118926 | #define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
118927 | #define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
118928 | #define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
118929 | //SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD |
118930 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118931 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118932 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118933 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118934 | //SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD |
118935 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
118936 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
118937 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
118938 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
118939 | //SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD |
118940 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 |
118941 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 |
118942 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L |
118943 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L |
118944 | //SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD |
118945 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 |
118946 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 |
118947 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L |
118948 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L |
118949 | //SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD |
118950 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 |
118951 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 |
118952 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L |
118953 | #define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L |
118954 | //SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD |
118955 | #define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118956 | #define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118957 | #define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118958 | #define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118959 | //SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD |
118960 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118961 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118962 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118963 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118964 | //SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD |
118965 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
118966 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
118967 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
118968 | #define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
118969 | //SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD |
118970 | #define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
118971 | #define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
118972 | #define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
118973 | #define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
118974 | |
118975 | #endif |
118976 |