| 1 | /* |
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| 2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef _nbio_7_4_0_SMN_HEADER |
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| 23 | #define |
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| 24 | |
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| 25 | // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk |
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| 26 | // base address: 0x10100000 |
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| 27 | #define smnBIFL_RAS_CENTRAL_STATUS 0x10139040 |
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| 28 | |
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| 29 | #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c |
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| 30 | #define smnCPM_CONTROL 0x11180460 |
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| 31 | #define smnPCIE_CNTL2 0x11180070 |
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| 32 | #define smnPCIE_CI_CNTL 0x11180080 |
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| 33 | |
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| 34 | #define smnPCIE_PERF_COUNT_CNTL 0x11180200 |
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| 35 | #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204 |
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| 36 | #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208 |
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| 37 | #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c |
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| 38 | #define smnPCIE_PERF_CNTL_TXCLK2 0x11180210 |
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| 39 | #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180214 |
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| 40 | #define smnPCIE_PERF_COUNT1_TXCLK2 0x11180218 |
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| 41 | #define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c |
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| 42 | #define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220 |
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| 43 | #define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224 |
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| 44 | #define smnPCIE_PERF_CNTL_TXCLK4 0x11180228 |
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| 45 | #define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c |
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| 46 | #define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230 |
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| 47 | #define smnPCIE_PERF_CNTL_SCLK1 0x11180234 |
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| 48 | #define smnPCIE_PERF_COUNT0_SCLK1 0x11180238 |
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| 49 | #define smnPCIE_PERF_COUNT1_SCLK1 0x1118023c |
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| 50 | #define smnPCIE_PERF_CNTL_SCLK2 0x11180240 |
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| 51 | #define smnPCIE_PERF_COUNT0_SCLK2 0x11180244 |
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| 52 | #define smnPCIE_PERF_COUNT1_SCLK2 0x11180248 |
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| 53 | #define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x1118024c |
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| 54 | #define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x11180250 |
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| 55 | |
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| 56 | #define smnPCIE_RX_NUM_NAK 0x11180038 |
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| 57 | #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c |
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| 58 | |
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| 59 | // addressBlock: nbio_iohub_nb_misc_misc_cfgdec |
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| 60 | // base address: 0x13a10000 |
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| 61 | #define smnIOHC_INTERRUPT_EOI 0x13a10120 |
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| 62 | |
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| 63 | // addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec |
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| 64 | // base address: 0x13a20000 |
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| 65 | #define smnRAS_GLOBAL_STATUS_LO 0x13a20020 |
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| 66 | #define smnRAS_GLOBAL_STATUS_HI 0x13a20024 |
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| 67 | |
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| 68 | #endif // _nbio_7_4_0_SMN_HEADER |
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| 69 | |
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