1 | /* |
2 | * OSS_2_0 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef OSS_2_0_D_H |
25 | #define OSS_2_0_D_H |
26 | |
27 | #define mmIH_VMID_0_LUT 0xf50 |
28 | #define mmIH_VMID_1_LUT 0xf51 |
29 | #define mmIH_VMID_2_LUT 0xf52 |
30 | #define mmIH_VMID_3_LUT 0xf53 |
31 | #define mmIH_VMID_4_LUT 0xf54 |
32 | #define mmIH_VMID_5_LUT 0xf55 |
33 | #define mmIH_VMID_6_LUT 0xf56 |
34 | #define mmIH_VMID_7_LUT 0xf57 |
35 | #define mmIH_VMID_8_LUT 0xf58 |
36 | #define mmIH_VMID_9_LUT 0xf59 |
37 | #define mmIH_VMID_10_LUT 0xf5a |
38 | #define mmIH_VMID_11_LUT 0xf5b |
39 | #define mmIH_VMID_12_LUT 0xf5c |
40 | #define mmIH_VMID_13_LUT 0xf5d |
41 | #define mmIH_VMID_14_LUT 0xf5e |
42 | #define mmIH_VMID_15_LUT 0xf5f |
43 | #define mmIH_RB_CNTL 0xf80 |
44 | #define mmIH_RB_BASE 0xf81 |
45 | #define mmIH_RB_RPTR 0xf82 |
46 | #define mmIH_RB_WPTR 0xf83 |
47 | #define mmIH_RB_WPTR_ADDR_HI 0xf84 |
48 | #define mmIH_RB_WPTR_ADDR_LO 0xf85 |
49 | #define mmIH_CNTL 0xf86 |
50 | #define mmIH_LEVEL_STATUS 0xf87 |
51 | #define mmIH_STATUS 0xf88 |
52 | #define mmIH_PERFMON_CNTL 0xf89 |
53 | #define mmIH_PERFCOUNTER0_RESULT 0xf8a |
54 | #define mmIH_PERFCOUNTER1_RESULT 0xf8b |
55 | #define mmIH_ADVFAULT_CNTL 0xf8c |
56 | #define mmSEM_MCIF_CONFIG 0xf90 |
57 | #define mmSDMA_CONFIG 0xf91 |
58 | #define mmSDMA1_CONFIG 0xf92 |
59 | #define mmUVD_CONFIG 0xf93 |
60 | #define mmVCE_CONFIG 0xf94 |
61 | #define mmACP_CONFIG 0xf95 |
62 | #define mmCPG_CONFIG 0xf96 |
63 | #define mmCPC1_CONFIG 0xf97 |
64 | #define mmCPC2_CONFIG 0xf98 |
65 | #define mmSEM_STATUS 0xf99 |
66 | #define mmSEM_EDC_CONFIG 0xf9a |
67 | #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b |
68 | #define mmSEM_MAILBOX 0xf9c |
69 | #define mmSEM_MAILBOX_CONTROL 0xf9d |
70 | #define mmSEM_CHICKEN_BITS 0xf9e |
71 | #define mmSRBM_CNTL 0x390 |
72 | #define mmSRBM_GFX_CNTL 0x391 |
73 | #define mmSRBM_STATUS2 0x393 |
74 | #define mmSRBM_STATUS 0x394 |
75 | #define mmSRBM_CAM_INDEX 0x396 |
76 | #define mmSRBM_CAM_DATA 0x397 |
77 | #define mmSRBM_SOFT_RESET 0x398 |
78 | #define mmSRBM_DEBUG_CNTL 0x399 |
79 | #define mmSRBM_DEBUG_DATA 0x39a |
80 | #define mmSRBM_CHIP_REVISION 0x39b |
81 | #define mmCC_SYS_RB_REDUNDANCY 0x39f |
82 | #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 |
83 | #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 |
84 | #define mmSRBM_MC_CLKEN_CNTL 0x3b3 |
85 | #define mmSRBM_SYS_CLKEN_CNTL 0x3b4 |
86 | #define mmSRBM_VCE_CLKEN_CNTL 0x3b5 |
87 | #define mmSRBM_UVD_CLKEN_CNTL 0x3b6 |
88 | #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 |
89 | #define mmSRBM_SAM_CLKEN_CNTL 0x3b8 |
90 | #define mmSRBM_DEBUG 0x3a4 |
91 | #define mmSRBM_DEBUG_SNAPSHOT 0x3a5 |
92 | #define mmSRBM_READ_ERROR 0x3a6 |
93 | #define mmSRBM_INT_CNTL 0x3a8 |
94 | #define mmSRBM_INT_STATUS 0x3a9 |
95 | #define mmSRBM_INT_ACK 0x3aa |
96 | #define mmSRBM_PERFMON_CNTL 0x700 |
97 | #define mmSRBM_PERFCOUNTER0_SELECT 0x701 |
98 | #define mmSRBM_PERFCOUNTER1_SELECT 0x702 |
99 | #define mmSRBM_PERFCOUNTER0_LO 0x703 |
100 | #define mmSRBM_PERFCOUNTER0_HI 0x704 |
101 | #define mmSRBM_PERFCOUNTER1_LO 0x705 |
102 | #define mmSRBM_PERFCOUNTER1_HI 0x706 |
103 | #define mmCC_DRM_ID_STRAPS 0x1559 |
104 | #define mmCGTT_DRM_CLK_CTRL0 0x1579 |
105 | #define ixDH_TEST 0x0 |
106 | #define ixKHFS0 0x4 |
107 | #define ixKHFS1 0x8 |
108 | #define ixKHFS2 0xc |
109 | #define ixKHFS3 0x10 |
110 | #define ixKSESSION0 0x14 |
111 | #define ixKSESSION1 0x18 |
112 | #define ixKSESSION2 0x1c |
113 | #define ixKSESSION3 0x20 |
114 | #define ixKSIG0 0x24 |
115 | #define ixKSIG1 0x28 |
116 | #define ixKSIG2 0x2c |
117 | #define ixKSIG3 0x30 |
118 | #define ixEXP0 0x34 |
119 | #define ixEXP1 0x38 |
120 | #define ixEXP2 0x3c |
121 | #define ixEXP3 0x40 |
122 | #define ixEXP4 0x44 |
123 | #define ixEXP5 0x48 |
124 | #define ixEXP6 0x4c |
125 | #define ixEXP7 0x50 |
126 | #define ixLX0 0x54 |
127 | #define ixLX1 0x58 |
128 | #define ixLX2 0x5c |
129 | #define ixLX3 0x60 |
130 | #define ixCLIENT2_K0 0x1b4 |
131 | #define ixCLIENT2_K1 0x1b8 |
132 | #define ixCLIENT2_K2 0x1bc |
133 | #define ixCLIENT2_K3 0x1c0 |
134 | #define ixCLIENT2_CK0 0x1c4 |
135 | #define ixCLIENT2_CK1 0x1c8 |
136 | #define ixCLIENT2_CK2 0x1cc |
137 | #define ixCLIENT2_CK3 0x1d0 |
138 | #define ixCLIENT2_CD0 0x1d4 |
139 | #define ixCLIENT2_CD1 0x1d8 |
140 | #define ixCLIENT2_CD2 0x1dc |
141 | #define ixCLIENT2_CD3 0x1e0 |
142 | #define ixCLIENT2_BM 0x1e4 |
143 | #define ixCLIENT2_OFFSET 0x1e8 |
144 | #define ixCLIENT2_STATUS 0x1ec |
145 | #define ixCLIENT0_K0 0x1f0 |
146 | #define ixCLIENT0_K1 0x1f4 |
147 | #define ixCLIENT0_K2 0x1f8 |
148 | #define ixCLIENT0_K3 0x1fc |
149 | #define ixCLIENT0_CK0 0x200 |
150 | #define ixCLIENT0_CK1 0x204 |
151 | #define ixCLIENT0_CK2 0x208 |
152 | #define ixCLIENT0_CK3 0x20c |
153 | #define ixCLIENT0_CD0 0x210 |
154 | #define ixCLIENT0_CD1 0x214 |
155 | #define ixCLIENT0_CD2 0x218 |
156 | #define ixCLIENT0_CD3 0x21c |
157 | #define ixCLIENT0_BM 0x220 |
158 | #define ixCLIENT0_OFFSET 0x224 |
159 | #define ixCLIENT0_STATUS 0x228 |
160 | #define ixCLIENT1_K0 0x22c |
161 | #define ixCLIENT1_K1 0x230 |
162 | #define ixCLIENT1_K2 0x234 |
163 | #define ixCLIENT1_K3 0x238 |
164 | #define ixCLIENT1_CK0 0x23c |
165 | #define ixCLIENT1_CK1 0x240 |
166 | #define ixCLIENT1_CK2 0x244 |
167 | #define ixCLIENT1_CK3 0x248 |
168 | #define ixCLIENT1_CD0 0x24c |
169 | #define ixCLIENT1_CD1 0x250 |
170 | #define ixCLIENT1_CD2 0x254 |
171 | #define ixCLIENT1_CD3 0x258 |
172 | #define ixCLIENT1_BM 0x25c |
173 | #define ixCLIENT1_OFFSET 0x260 |
174 | #define ixCLIENT1_PORT_STATUS 0x264 |
175 | #define ixKEFUSE0 0x268 |
176 | #define ixKEFUSE1 0x26c |
177 | #define ixKEFUSE2 0x270 |
178 | #define ixKEFUSE3 0x274 |
179 | #define ixHFS_SEED0 0x278 |
180 | #define ixHFS_SEED1 0x27c |
181 | #define ixHFS_SEED2 0x280 |
182 | #define ixHFS_SEED3 0x284 |
183 | #define ixRINGOSC_MASK 0x288 |
184 | #define ixCLIENT0_OFFSET_HI 0x290 |
185 | #define ixCLIENT1_OFFSET_HI 0x294 |
186 | #define ixCLIENT2_OFFSET_HI 0x298 |
187 | #define ixSPU_PORT_STATUS 0x29c |
188 | #define ixCLIENT3_OFFSET_HI 0x2a0 |
189 | #define ixCLIENT3_K0 0x2a4 |
190 | #define ixCLIENT3_K1 0x2a8 |
191 | #define ixCLIENT3_K2 0x2ac |
192 | #define ixCLIENT3_K3 0x2b0 |
193 | #define ixCLIENT3_CK0 0x2b4 |
194 | #define ixCLIENT3_CK1 0x2b8 |
195 | #define ixCLIENT3_CK2 0x2bc |
196 | #define ixCLIENT3_CK3 0x2c0 |
197 | #define ixCLIENT3_CD0 0x2c4 |
198 | #define ixCLIENT3_CD1 0x2c8 |
199 | #define ixCLIENT3_CD2 0x2cc |
200 | #define ixCLIENT3_CD3 0x2d0 |
201 | #define ixCLIENT3_BM 0x2d4 |
202 | #define ixCLIENT3_OFFSET 0x2d8 |
203 | #define ixCLIENT3_STATUS 0x2dc |
204 | #define mmDC_TEST_DEBUG_INDEX 0x157c |
205 | #define mmDC_TEST_DEBUG_DATA 0x157d |
206 | #define mmXDMA_SLV_CNTL 0x460 |
207 | #define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 |
208 | #define mmXDMA_SLV_SLS_PITCH 0x462 |
209 | #define mmXDMA_SLV_READ_URGENT_CNTL 0x463 |
210 | #define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 |
211 | #define mmXDMA_SLV_WB_RATE_CNTL 0x465 |
212 | #define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 |
213 | #define mmXDMA_SLV_READ_LATENCY_AVE 0x467 |
214 | #define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 |
215 | #define mmXDMA_SLV_MEM_NACK_STATUS 0x469 |
216 | #define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a |
217 | #define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b |
218 | #define mmXDMA_SLV_FLIP_PENDING 0x46c |
219 | #define mmSDMA0_UCODE_ADDR 0x3400 |
220 | #define mmSDMA0_UCODE_DATA 0x3401 |
221 | #define mmSDMA0_POWER_CNTL 0x3402 |
222 | #define mmSDMA0_CLK_CTRL 0x3403 |
223 | #define mmSDMA0_CNTL 0x3404 |
224 | #define mmSDMA0_CHICKEN_BITS 0x3405 |
225 | #define mmSDMA0_TILING_CONFIG 0x3406 |
226 | #define mmSDMA0_HASH 0x3407 |
227 | #define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL 0x3408 |
228 | #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 |
229 | #define mmSDMA0_RB_RPTR_FETCH 0x340a |
230 | #define mmSDMA0_IB_OFFSET_FETCH 0x340b |
231 | #define mmSDMA0_PROGRAM 0x340c |
232 | #define mmSDMA0_STATUS_REG 0x340d |
233 | #define mmSDMA0_STATUS1_REG 0x340e |
234 | #define mmSDMA0_PERFMON_CNTL 0x340f |
235 | #define mmSDMA0_PERFCOUNTER0_RESULT 0x3410 |
236 | #define mmSDMA0_PERFCOUNTER1_RESULT 0x3411 |
237 | #define mmSDMA0_F32_CNTL 0x3412 |
238 | #define mmSDMA0_FREEZE 0x3413 |
239 | #define mmSDMA0_PHASE0_QUANTUM 0x3414 |
240 | #define mmSDMA0_PHASE1_QUANTUM 0x3415 |
241 | #define mmSDMA_POWER_GATING 0x3416 |
242 | #define mmSDMA_PGFSM_CONFIG 0x3417 |
243 | #define mmSDMA_PGFSM_WRITE 0x3418 |
244 | #define mmSDMA_PGFSM_READ 0x3419 |
245 | #define mmSDMA0_EDC_CONFIG 0x341a |
246 | #define mmSDMA0_GFX_RB_CNTL 0x3480 |
247 | #define mmSDMA0_GFX_RB_BASE 0x3481 |
248 | #define mmSDMA0_GFX_RB_BASE_HI 0x3482 |
249 | #define mmSDMA0_GFX_RB_RPTR 0x3483 |
250 | #define mmSDMA0_GFX_RB_WPTR 0x3484 |
251 | #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 |
252 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 |
253 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 |
254 | #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 |
255 | #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 |
256 | #define mmSDMA0_GFX_IB_CNTL 0x348a |
257 | #define mmSDMA0_GFX_IB_RPTR 0x348b |
258 | #define mmSDMA0_GFX_IB_OFFSET 0x348c |
259 | #define mmSDMA0_GFX_IB_BASE_LO 0x348d |
260 | #define mmSDMA0_GFX_IB_BASE_HI 0x348e |
261 | #define mmSDMA0_GFX_IB_SIZE 0x348f |
262 | #define mmSDMA0_GFX_SKIP_CNTL 0x3490 |
263 | #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 |
264 | #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 |
265 | #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 |
266 | #define mmSDMA0_GFX_APE1_CNTL 0x34a8 |
267 | #define mmSDMA0_GFX_WATERMARK 0x34aa |
268 | #define mmSDMA0_RLC0_RB_CNTL 0x3500 |
269 | #define mmSDMA0_RLC0_RB_BASE 0x3501 |
270 | #define mmSDMA0_RLC0_RB_BASE_HI 0x3502 |
271 | #define mmSDMA0_RLC0_RB_RPTR 0x3503 |
272 | #define mmSDMA0_RLC0_RB_WPTR 0x3504 |
273 | #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 |
274 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 |
275 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 |
276 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 |
277 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 |
278 | #define mmSDMA0_RLC0_IB_CNTL 0x350a |
279 | #define mmSDMA0_RLC0_IB_RPTR 0x350b |
280 | #define mmSDMA0_RLC0_IB_OFFSET 0x350c |
281 | #define mmSDMA0_RLC0_IB_BASE_LO 0x350d |
282 | #define mmSDMA0_RLC0_IB_BASE_HI 0x350e |
283 | #define mmSDMA0_RLC0_IB_SIZE 0x350f |
284 | #define mmSDMA0_RLC0_SKIP_CNTL 0x3510 |
285 | #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 |
286 | #define mmSDMA0_RLC0_DOORBELL 0x3512 |
287 | #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 |
288 | #define mmSDMA0_RLC0_APE1_CNTL 0x3528 |
289 | #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 |
290 | #define mmSDMA0_RLC0_WATERMARK 0x352a |
291 | #define mmSDMA0_RLC1_RB_CNTL 0x3580 |
292 | #define mmSDMA0_RLC1_RB_BASE 0x3581 |
293 | #define mmSDMA0_RLC1_RB_BASE_HI 0x3582 |
294 | #define mmSDMA0_RLC1_RB_RPTR 0x3583 |
295 | #define mmSDMA0_RLC1_RB_WPTR 0x3584 |
296 | #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 |
297 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 |
298 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 |
299 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 |
300 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 |
301 | #define mmSDMA0_RLC1_IB_CNTL 0x358a |
302 | #define mmSDMA0_RLC1_IB_RPTR 0x358b |
303 | #define mmSDMA0_RLC1_IB_OFFSET 0x358c |
304 | #define mmSDMA0_RLC1_IB_BASE_LO 0x358d |
305 | #define mmSDMA0_RLC1_IB_BASE_HI 0x358e |
306 | #define mmSDMA0_RLC1_IB_SIZE 0x358f |
307 | #define mmSDMA0_RLC1_SKIP_CNTL 0x3590 |
308 | #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 |
309 | #define mmSDMA0_RLC1_DOORBELL 0x3592 |
310 | #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 |
311 | #define mmSDMA0_RLC1_APE1_CNTL 0x35a8 |
312 | #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 |
313 | #define mmSDMA0_RLC1_WATERMARK 0x35aa |
314 | #define mmSDMA1_UCODE_ADDR 0x3600 |
315 | #define mmSDMA1_UCODE_DATA 0x3601 |
316 | #define mmSDMA1_POWER_CNTL 0x3602 |
317 | #define mmSDMA1_CLK_CTRL 0x3603 |
318 | #define mmSDMA1_CNTL 0x3604 |
319 | #define mmSDMA1_CHICKEN_BITS 0x3605 |
320 | #define mmSDMA1_TILING_CONFIG 0x3606 |
321 | #define mmSDMA1_HASH 0x3607 |
322 | #define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL 0x3608 |
323 | #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 |
324 | #define mmSDMA1_RB_RPTR_FETCH 0x360a |
325 | #define mmSDMA1_IB_OFFSET_FETCH 0x360b |
326 | #define mmSDMA1_PROGRAM 0x360c |
327 | #define mmSDMA1_STATUS_REG 0x360d |
328 | #define mmSDMA1_STATUS1_REG 0x360e |
329 | #define mmSDMA1_PERFMON_CNTL 0x360f |
330 | #define mmSDMA1_PERFCOUNTER0_RESULT 0x3610 |
331 | #define mmSDMA1_PERFCOUNTER1_RESULT 0x3611 |
332 | #define mmSDMA1_F32_CNTL 0x3612 |
333 | #define mmSDMA1_FREEZE 0x3613 |
334 | #define mmSDMA1_PHASE0_QUANTUM 0x3614 |
335 | #define mmSDMA1_PHASE1_QUANTUM 0x3615 |
336 | #define mmSDMA1_EDC_CONFIG 0x361a |
337 | #define mmSDMA1_GFX_RB_CNTL 0x3680 |
338 | #define mmSDMA1_GFX_RB_BASE 0x3681 |
339 | #define mmSDMA1_GFX_RB_BASE_HI 0x3682 |
340 | #define mmSDMA1_GFX_RB_RPTR 0x3683 |
341 | #define mmSDMA1_GFX_RB_WPTR 0x3684 |
342 | #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 |
343 | #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 |
344 | #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 |
345 | #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 |
346 | #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 |
347 | #define mmSDMA1_GFX_IB_CNTL 0x368a |
348 | #define mmSDMA1_GFX_IB_RPTR 0x368b |
349 | #define mmSDMA1_GFX_IB_OFFSET 0x368c |
350 | #define mmSDMA1_GFX_IB_BASE_LO 0x368d |
351 | #define mmSDMA1_GFX_IB_BASE_HI 0x368e |
352 | #define mmSDMA1_GFX_IB_SIZE 0x368f |
353 | #define mmSDMA1_GFX_SKIP_CNTL 0x3690 |
354 | #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 |
355 | #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 |
356 | #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 |
357 | #define mmSDMA1_GFX_APE1_CNTL 0x36a8 |
358 | #define mmSDMA1_GFX_WATERMARK 0x36aa |
359 | #define mmSDMA1_RLC0_RB_CNTL 0x3700 |
360 | #define mmSDMA1_RLC0_RB_BASE 0x3701 |
361 | #define mmSDMA1_RLC0_RB_BASE_HI 0x3702 |
362 | #define mmSDMA1_RLC0_RB_RPTR 0x3703 |
363 | #define mmSDMA1_RLC0_RB_WPTR 0x3704 |
364 | #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 |
365 | #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 |
366 | #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 |
367 | #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 |
368 | #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 |
369 | #define mmSDMA1_RLC0_IB_CNTL 0x370a |
370 | #define mmSDMA1_RLC0_IB_RPTR 0x370b |
371 | #define mmSDMA1_RLC0_IB_OFFSET 0x370c |
372 | #define mmSDMA1_RLC0_IB_BASE_LO 0x370d |
373 | #define mmSDMA1_RLC0_IB_BASE_HI 0x370e |
374 | #define mmSDMA1_RLC0_IB_SIZE 0x370f |
375 | #define mmSDMA1_RLC0_SKIP_CNTL 0x3710 |
376 | #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 |
377 | #define mmSDMA1_RLC0_DOORBELL 0x3712 |
378 | #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 |
379 | #define mmSDMA1_RLC0_APE1_CNTL 0x3728 |
380 | #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 |
381 | #define mmSDMA1_RLC0_WATERMARK 0x372a |
382 | #define mmSDMA1_RLC1_RB_CNTL 0x3780 |
383 | #define mmSDMA1_RLC1_RB_BASE 0x3781 |
384 | #define mmSDMA1_RLC1_RB_BASE_HI 0x3782 |
385 | #define mmSDMA1_RLC1_RB_RPTR 0x3783 |
386 | #define mmSDMA1_RLC1_RB_WPTR 0x3784 |
387 | #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 |
388 | #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 |
389 | #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 |
390 | #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 |
391 | #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 |
392 | #define mmSDMA1_RLC1_IB_CNTL 0x378a |
393 | #define mmSDMA1_RLC1_IB_RPTR 0x378b |
394 | #define mmSDMA1_RLC1_IB_OFFSET 0x378c |
395 | #define mmSDMA1_RLC1_IB_BASE_LO 0x378d |
396 | #define mmSDMA1_RLC1_IB_BASE_HI 0x378e |
397 | #define mmSDMA1_RLC1_IB_SIZE 0x378f |
398 | #define mmSDMA1_RLC1_SKIP_CNTL 0x3790 |
399 | #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 |
400 | #define mmSDMA1_RLC1_DOORBELL 0x3792 |
401 | #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 |
402 | #define mmSDMA1_RLC1_APE1_CNTL 0x37a8 |
403 | #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 |
404 | #define mmSDMA1_RLC1_WATERMARK 0x37aa |
405 | #define mmXDMA_SLV_CHANNEL_CNTL 0x470 |
406 | #define mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 |
407 | #define mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 |
408 | #define mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 |
409 | #define mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 |
410 | #define mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 |
411 | #define mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 |
412 | #define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 |
413 | #define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 |
414 | #define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 |
415 | #define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 |
416 | #define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 |
417 | #define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 |
418 | #define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 |
419 | #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 |
420 | #define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 |
421 | #define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a |
422 | #define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 |
423 | #define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a |
424 | #define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 |
425 | #define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a |
426 | #define mmXDMA_MSTR_PIPE_CNTL 0x400 |
427 | #define mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 |
428 | #define mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 |
429 | #define mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 |
430 | #define mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 |
431 | #define mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 |
432 | #define mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 |
433 | #define mmXDMA_MSTR_READ_COMMAND 0x401 |
434 | #define mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 |
435 | #define mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 |
436 | #define mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 |
437 | #define mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 |
438 | #define mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 |
439 | #define mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 |
440 | #define mmXDMA_MSTR_CHANNEL_DIM 0x402 |
441 | #define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 |
442 | #define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 |
443 | #define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 |
444 | #define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 |
445 | #define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 |
446 | #define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 |
447 | #define mmXDMA_MSTR_HEIGHT 0x403 |
448 | #define mmMDMA_PIPE0_XDMA_MSTR_HEIGHT 0x403 |
449 | #define mmMDMA_PIPE1_XDMA_MSTR_HEIGHT 0x413 |
450 | #define mmMDMA_PIPE2_XDMA_MSTR_HEIGHT 0x423 |
451 | #define mmMDMA_PIPE3_XDMA_MSTR_HEIGHT 0x433 |
452 | #define mmMDMA_PIPE4_XDMA_MSTR_HEIGHT 0x443 |
453 | #define mmMDMA_PIPE5_XDMA_MSTR_HEIGHT 0x453 |
454 | #define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 |
455 | #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 |
456 | #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 |
457 | #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 |
458 | #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 |
459 | #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 |
460 | #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 |
461 | #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 |
462 | #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 |
463 | #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 |
464 | #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 |
465 | #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 |
466 | #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 |
467 | #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 |
468 | #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 |
469 | #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 |
470 | #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 |
471 | #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 |
472 | #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 |
473 | #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 |
474 | #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 |
475 | #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 |
476 | #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 |
477 | #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 |
478 | #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 |
479 | #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 |
480 | #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 |
481 | #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 |
482 | #define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 |
483 | #define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 |
484 | #define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 |
485 | #define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 |
486 | #define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 |
487 | #define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 |
488 | #define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 |
489 | #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 |
490 | #define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 |
491 | #define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 |
492 | #define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 |
493 | #define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 |
494 | #define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 |
495 | #define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 |
496 | #define mmXDMA_MSTR_CACHE_PITCH 0x40a |
497 | #define mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH 0x40a |
498 | #define mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH 0x41a |
499 | #define mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH 0x42a |
500 | #define mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH 0x43a |
501 | #define mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH 0x44a |
502 | #define mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH 0x45a |
503 | #define mmXDMA_MSTR_CHANNEL_START 0x40b |
504 | #define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b |
505 | #define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b |
506 | #define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b |
507 | #define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b |
508 | #define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b |
509 | #define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b |
510 | #define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c |
511 | #define mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c |
512 | #define mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x41c |
513 | #define mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x42c |
514 | #define mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x43c |
515 | #define mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x44c |
516 | #define mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x45c |
517 | #define mmXDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d |
518 | #define mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d |
519 | #define mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x41d |
520 | #define mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x42d |
521 | #define mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x43d |
522 | #define mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x44d |
523 | #define mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x45d |
524 | #define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e |
525 | #define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e |
526 | #define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e |
527 | #define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e |
528 | #define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e |
529 | #define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e |
530 | #define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e |
531 | #define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f |
532 | #define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f |
533 | #define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f |
534 | #define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f |
535 | #define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f |
536 | #define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f |
537 | #define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f |
538 | #define mmXDMA_MSTR_CNTL 0x3ec |
539 | #define mmXDMA_MSTR_STATUS 0x3ed |
540 | #define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee |
541 | #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef |
542 | #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 |
543 | #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 |
544 | #define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 |
545 | #define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 |
546 | #define mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG 0x3f4 |
547 | #define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 |
548 | #define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 |
549 | #define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 |
550 | #define mmHDP_HOST_PATH_CNTL 0xb00 |
551 | #define mmHDP_NONSURFACE_BASE 0xb01 |
552 | #define mmHDP_NONSURFACE_INFO 0xb02 |
553 | #define mmHDP_NONSURFACE_SIZE 0xb03 |
554 | #define mmHDP_NONSURF_FLAGS 0xbc9 |
555 | #define mmHDP_NONSURF_FLAGS_CLR 0xbca |
556 | #define mmHDP_SW_SEMAPHORE 0xbcb |
557 | #define mmHDP_DEBUG0 0xbcc |
558 | #define mmHDP_DEBUG1 0xbcd |
559 | #define mmHDP_LAST_SURFACE_HIT 0xbce |
560 | #define mmHDP_TILING_CONFIG 0xbcf |
561 | #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 |
562 | #define mmHDP_OUTSTANDING_REQ 0xbd1 |
563 | #define mmHDP_ADDR_CONFIG 0xbd2 |
564 | #define mmHDP_MISC_CNTL 0xbd3 |
565 | #define mmHDP_MEM_POWER_LS 0xbd4 |
566 | #define mmHDP_NONSURFACE_PREFETCH 0xbd5 |
567 | #define mmHDP_MEMIO_CNTL 0xbf6 |
568 | #define mmHDP_MEMIO_ADDR 0xbf7 |
569 | #define mmHDP_MEMIO_STATUS 0xbf8 |
570 | #define mmHDP_MEMIO_WR_DATA 0xbf9 |
571 | #define mmHDP_MEMIO_RD_DATA 0xbfa |
572 | #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 |
573 | #define mmHDP_XDP_D2H_FLUSH 0xc01 |
574 | #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 |
575 | #define mmHDP_XDP_D2H_RSVD_3 0xc03 |
576 | #define mmHDP_XDP_D2H_RSVD_4 0xc04 |
577 | #define mmHDP_XDP_D2H_RSVD_5 0xc05 |
578 | #define mmHDP_XDP_D2H_RSVD_6 0xc06 |
579 | #define mmHDP_XDP_D2H_RSVD_7 0xc07 |
580 | #define mmHDP_XDP_D2H_RSVD_8 0xc08 |
581 | #define mmHDP_XDP_D2H_RSVD_9 0xc09 |
582 | #define mmHDP_XDP_D2H_RSVD_10 0xc0a |
583 | #define mmHDP_XDP_D2H_RSVD_11 0xc0b |
584 | #define mmHDP_XDP_D2H_RSVD_12 0xc0c |
585 | #define mmHDP_XDP_D2H_RSVD_13 0xc0d |
586 | #define mmHDP_XDP_D2H_RSVD_14 0xc0e |
587 | #define mmHDP_XDP_D2H_RSVD_15 0xc0f |
588 | #define mmHDP_XDP_D2H_RSVD_16 0xc10 |
589 | #define mmHDP_XDP_D2H_RSVD_17 0xc11 |
590 | #define mmHDP_XDP_D2H_RSVD_18 0xc12 |
591 | #define mmHDP_XDP_D2H_RSVD_19 0xc13 |
592 | #define mmHDP_XDP_D2H_RSVD_20 0xc14 |
593 | #define mmHDP_XDP_D2H_RSVD_21 0xc15 |
594 | #define mmHDP_XDP_D2H_RSVD_22 0xc16 |
595 | #define mmHDP_XDP_D2H_RSVD_23 0xc17 |
596 | #define mmHDP_XDP_D2H_RSVD_24 0xc18 |
597 | #define mmHDP_XDP_D2H_RSVD_25 0xc19 |
598 | #define mmHDP_XDP_D2H_RSVD_26 0xc1a |
599 | #define mmHDP_XDP_D2H_RSVD_27 0xc1b |
600 | #define mmHDP_XDP_D2H_RSVD_28 0xc1c |
601 | #define mmHDP_XDP_D2H_RSVD_29 0xc1d |
602 | #define mmHDP_XDP_D2H_RSVD_30 0xc1e |
603 | #define mmHDP_XDP_D2H_RSVD_31 0xc1f |
604 | #define mmHDP_XDP_D2H_RSVD_32 0xc20 |
605 | #define mmHDP_XDP_D2H_RSVD_33 0xc21 |
606 | #define mmHDP_XDP_D2H_RSVD_34 0xc22 |
607 | #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 |
608 | #define mmHDP_XDP_P2P_BAR_CFG 0xc24 |
609 | #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 |
610 | #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 |
611 | #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 |
612 | #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 |
613 | #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 |
614 | #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a |
615 | #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b |
616 | #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c |
617 | #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d |
618 | #define mmHDP_XDP_HDP_MC_CFG 0xc2e |
619 | #define mmHDP_XDP_HST_CFG 0xc2f |
620 | #define mmHDP_XDP_SID_CFG 0xc30 |
621 | #define mmHDP_XDP_HDP_IPH_CFG 0xc31 |
622 | #define mmHDP_XDP_SRBM_CFG 0xc32 |
623 | #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 |
624 | #define mmHDP_XDP_P2P_BAR0 0xc34 |
625 | #define mmHDP_XDP_P2P_BAR1 0xc35 |
626 | #define mmHDP_XDP_P2P_BAR2 0xc36 |
627 | #define mmHDP_XDP_P2P_BAR3 0xc37 |
628 | #define mmHDP_XDP_P2P_BAR4 0xc38 |
629 | #define mmHDP_XDP_P2P_BAR5 0xc39 |
630 | #define mmHDP_XDP_P2P_BAR6 0xc3a |
631 | #define mmHDP_XDP_P2P_BAR7 0xc3b |
632 | #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c |
633 | #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d |
634 | #define mmHDP_XDP_BUSY_STS 0xc3e |
635 | #define mmHDP_XDP_STICKY 0xc3f |
636 | #define mmHDP_XDP_CHKN 0xc40 |
637 | #define mmHDP_XDP_DBG_ADDR 0xc41 |
638 | #define mmHDP_XDP_DBG_DATA 0xc42 |
639 | #define mmHDP_XDP_DBG_MASK 0xc43 |
640 | #define mmHDP_XDP_BARS_ADDR_39_36 0xc44 |
641 | |
642 | #endif /* OSS_2_0_D_H */ |
643 | |