1 | /* |
2 | * Copyright 2022 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _osssys_4_4_2_SH_MASK_HEADER |
24 | #define |
25 | |
26 | |
27 | // addressBlock: aid_osssys_osssysdec |
28 | //IH_VMID_0_LUT |
29 | #define IH_VMID_0_LUT__PASID__SHIFT 0x0 |
30 | #define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL |
31 | //IH_VMID_1_LUT |
32 | #define IH_VMID_1_LUT__PASID__SHIFT 0x0 |
33 | #define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL |
34 | //IH_VMID_2_LUT |
35 | #define IH_VMID_2_LUT__PASID__SHIFT 0x0 |
36 | #define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL |
37 | //IH_VMID_3_LUT |
38 | #define IH_VMID_3_LUT__PASID__SHIFT 0x0 |
39 | #define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL |
40 | //IH_VMID_4_LUT |
41 | #define IH_VMID_4_LUT__PASID__SHIFT 0x0 |
42 | #define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL |
43 | //IH_VMID_5_LUT |
44 | #define IH_VMID_5_LUT__PASID__SHIFT 0x0 |
45 | #define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL |
46 | //IH_VMID_6_LUT |
47 | #define IH_VMID_6_LUT__PASID__SHIFT 0x0 |
48 | #define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL |
49 | //IH_VMID_7_LUT |
50 | #define IH_VMID_7_LUT__PASID__SHIFT 0x0 |
51 | #define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL |
52 | //IH_VMID_8_LUT |
53 | #define IH_VMID_8_LUT__PASID__SHIFT 0x0 |
54 | #define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL |
55 | //IH_VMID_9_LUT |
56 | #define IH_VMID_9_LUT__PASID__SHIFT 0x0 |
57 | #define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL |
58 | //IH_VMID_10_LUT |
59 | #define IH_VMID_10_LUT__PASID__SHIFT 0x0 |
60 | #define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL |
61 | //IH_VMID_11_LUT |
62 | #define IH_VMID_11_LUT__PASID__SHIFT 0x0 |
63 | #define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL |
64 | //IH_VMID_12_LUT |
65 | #define IH_VMID_12_LUT__PASID__SHIFT 0x0 |
66 | #define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL |
67 | //IH_VMID_13_LUT |
68 | #define IH_VMID_13_LUT__PASID__SHIFT 0x0 |
69 | #define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL |
70 | //IH_VMID_14_LUT |
71 | #define IH_VMID_14_LUT__PASID__SHIFT 0x0 |
72 | #define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL |
73 | //IH_VMID_15_LUT |
74 | #define IH_VMID_15_LUT__PASID__SHIFT 0x0 |
75 | #define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL |
76 | //IH_VMID_0_LUT_MM |
77 | #define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 |
78 | #define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL |
79 | //IH_VMID_1_LUT_MM |
80 | #define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 |
81 | #define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL |
82 | //IH_VMID_2_LUT_MM |
83 | #define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 |
84 | #define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL |
85 | //IH_VMID_3_LUT_MM |
86 | #define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 |
87 | #define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL |
88 | //IH_VMID_4_LUT_MM |
89 | #define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 |
90 | #define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL |
91 | //IH_VMID_5_LUT_MM |
92 | #define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 |
93 | #define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL |
94 | //IH_VMID_6_LUT_MM |
95 | #define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 |
96 | #define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL |
97 | //IH_VMID_7_LUT_MM |
98 | #define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 |
99 | #define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL |
100 | //IH_VMID_8_LUT_MM |
101 | #define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 |
102 | #define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL |
103 | //IH_VMID_9_LUT_MM |
104 | #define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 |
105 | #define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL |
106 | //IH_VMID_10_LUT_MM |
107 | #define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 |
108 | #define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL |
109 | //IH_VMID_11_LUT_MM |
110 | #define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 |
111 | #define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL |
112 | //IH_VMID_12_LUT_MM |
113 | #define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 |
114 | #define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL |
115 | //IH_VMID_13_LUT_MM |
116 | #define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 |
117 | #define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL |
118 | //IH_VMID_14_LUT_MM |
119 | #define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 |
120 | #define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL |
121 | //IH_VMID_15_LUT_MM |
122 | #define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 |
123 | #define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL |
124 | //IH_COOKIE_0 |
125 | #define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 |
126 | #define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 |
127 | #define IH_COOKIE_0__RING_ID__SHIFT 0x10 |
128 | #define IH_COOKIE_0__VM_ID__SHIFT 0x18 |
129 | #define IH_COOKIE_0__RESERVED__SHIFT 0x1c |
130 | #define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f |
131 | #define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL |
132 | #define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L |
133 | #define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L |
134 | #define IH_COOKIE_0__VM_ID_MASK 0x0F000000L |
135 | #define IH_COOKIE_0__RESERVED_MASK 0x70000000L |
136 | #define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L |
137 | //IH_COOKIE_1 |
138 | #define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 |
139 | #define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL |
140 | //IH_COOKIE_2 |
141 | #define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 |
142 | #define IH_COOKIE_2__RESERVED__SHIFT 0x10 |
143 | #define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f |
144 | #define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL |
145 | #define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L |
146 | #define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L |
147 | //IH_COOKIE_3 |
148 | #define IH_COOKIE_3__PAS_ID__SHIFT 0x0 |
149 | #define IH_COOKIE_3__RESERVED__SHIFT 0x10 |
150 | #define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f |
151 | #define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL |
152 | #define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L |
153 | #define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L |
154 | //IH_COOKIE_4 |
155 | #define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 |
156 | #define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL |
157 | //IH_COOKIE_5 |
158 | #define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 |
159 | #define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL |
160 | //IH_COOKIE_6 |
161 | #define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 |
162 | #define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL |
163 | //IH_COOKIE_7 |
164 | #define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 |
165 | #define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL |
166 | //IH_REGISTER_LAST_PART0 |
167 | #define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 |
168 | #define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL |
169 | //IH_RB_CNTL |
170 | #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
171 | #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 |
172 | #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 |
173 | #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
174 | #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 |
175 | #define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa |
176 | #define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb |
177 | #define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc |
178 | #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 |
179 | #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 |
180 | #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 |
181 | #define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 |
182 | #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 |
183 | #define IH_RB_CNTL__MC_RO__SHIFT 0x16 |
184 | #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 |
185 | #define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c |
186 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
187 | #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
188 | #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
189 | #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L |
190 | #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
191 | #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L |
192 | #define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L |
193 | #define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L |
194 | #define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L |
195 | #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L |
196 | #define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L |
197 | #define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L |
198 | #define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L |
199 | #define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L |
200 | #define IH_RB_CNTL__MC_RO_MASK 0x00400000L |
201 | #define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L |
202 | #define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L |
203 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
204 | //IH_RB_BASE |
205 | #define IH_RB_BASE__ADDR__SHIFT 0x0 |
206 | #define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
207 | //IH_RB_BASE_HI |
208 | #define IH_RB_BASE_HI__ADDR__SHIFT 0x0 |
209 | #define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL |
210 | //IH_RB_RPTR |
211 | #define IH_RB_RPTR__OFFSET__SHIFT 0x2 |
212 | #define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
213 | //IH_RB_WPTR |
214 | #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 |
215 | #define IH_RB_WPTR__OFFSET__SHIFT 0x2 |
216 | #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 |
217 | #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 |
218 | #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L |
219 | #define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
220 | #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L |
221 | #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L |
222 | //IH_RB_WPTR_ADDR_HI |
223 | #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
224 | #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL |
225 | //IH_RB_WPTR_ADDR_LO |
226 | #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
227 | #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
228 | //IH_DOORBELL_RPTR |
229 | #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 |
230 | #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c |
231 | #define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL |
232 | #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L |
233 | //IH_DOORBELL_RETRY_CAM |
234 | #define IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT 0x0 |
235 | #define IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT 0x1c |
236 | #define IH_DOORBELL_RETRY_CAM__OFFSET_MASK 0x03FFFFFFL |
237 | #define IH_DOORBELL_RETRY_CAM__ENABLE_MASK 0x10000000L |
238 | //IH_RB_CNTL_RING1 |
239 | #define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 |
240 | #define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 |
241 | #define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7 |
242 | #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 |
243 | #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa |
244 | #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb |
245 | #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc |
246 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 |
247 | #define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 |
248 | #define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 |
249 | #define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 |
250 | #define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 |
251 | #define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c |
252 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
253 | #define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L |
254 | #define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL |
255 | #define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L |
256 | #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L |
257 | #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L |
258 | #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L |
259 | #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L |
260 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L |
261 | #define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L |
262 | #define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L |
263 | #define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L |
264 | #define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L |
265 | #define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L |
266 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
267 | //IH_RB_BASE_RING1 |
268 | #define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 |
269 | #define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL |
270 | //IH_RB_BASE_HI_RING1 |
271 | #define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 |
272 | #define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL |
273 | //IH_RB_RPTR_RING1 |
274 | #define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 |
275 | #define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL |
276 | //IH_RB_WPTR_RING1 |
277 | #define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 |
278 | #define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 |
279 | #define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 |
280 | #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 |
281 | #define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L |
282 | #define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL |
283 | #define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L |
284 | #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L |
285 | //IH_DOORBELL_RPTR_RING1 |
286 | #define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 |
287 | #define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c |
288 | #define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL |
289 | #define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L |
290 | //IH_RETRY_CAM_ACK |
291 | #define IH_RETRY_CAM_ACK__INDEX__SHIFT 0x0 |
292 | #define IH_RETRY_CAM_ACK__INDEX_MASK 0x000003FFL |
293 | //IH_VERSION |
294 | #define IH_VERSION__MINVER__SHIFT 0x0 |
295 | #define IH_VERSION__MAJVER__SHIFT 0x8 |
296 | #define IH_VERSION__REV__SHIFT 0x10 |
297 | #define IH_VERSION__MINVER_MASK 0x0000007FL |
298 | #define IH_VERSION__MAJVER_MASK 0x00007F00L |
299 | #define IH_VERSION__REV_MASK 0x003F0000L |
300 | //IH_CNTL |
301 | #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 |
302 | #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 |
303 | #define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 |
304 | #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 |
305 | #define IH_CNTL__SRAM_ECC_ENABLE__SHIFT 0x19 |
306 | #define IH_CNTL__FED_ENABLE__SHIFT 0x1a |
307 | #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL |
308 | #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L |
309 | #define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L |
310 | #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L |
311 | #define IH_CNTL__SRAM_ECC_ENABLE_MASK 0x02000000L |
312 | #define IH_CNTL__FED_ENABLE_MASK 0x04000000L |
313 | //IH_CNTL2 |
314 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 |
315 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 |
316 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL |
317 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L |
318 | //IH_STATUS |
319 | #define IH_STATUS__IDLE__SHIFT 0x0 |
320 | #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 |
321 | #define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 |
322 | #define IH_STATUS__RB_FULL__SHIFT 0x3 |
323 | #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 |
324 | #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 |
325 | #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 |
326 | #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 |
327 | #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 |
328 | #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 |
329 | #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa |
330 | #define IH_STATUS__SWITCH_READY__SHIFT 0xb |
331 | #define IH_STATUS__RB1_FULL__SHIFT 0xc |
332 | #define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd |
333 | #define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe |
334 | #define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 |
335 | #define IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT 0x13 |
336 | #define IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT 0x14 |
337 | #define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT 0x15 |
338 | #define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT 0x16 |
339 | #define IH_STATUS__IDLE_MASK 0x00000001L |
340 | #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L |
341 | #define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L |
342 | #define IH_STATUS__RB_FULL_MASK 0x00000008L |
343 | #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L |
344 | #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L |
345 | #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L |
346 | #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L |
347 | #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L |
348 | #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L |
349 | #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L |
350 | #define IH_STATUS__SWITCH_READY_MASK 0x00000800L |
351 | #define IH_STATUS__RB1_FULL_MASK 0x00001000L |
352 | #define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L |
353 | #define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L |
354 | #define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L |
355 | #define IH_STATUS__RETRY_INT_CAM_IDLE_MASK 0x00080000L |
356 | #define IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK 0x00100000L |
357 | #define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK 0x00200000L |
358 | #define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK 0x00400000L |
359 | //IH_PERFMON_CNTL |
360 | #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 |
361 | #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 |
362 | #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 |
363 | #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 |
364 | #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 |
365 | #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 |
366 | #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L |
367 | #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L |
368 | #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL |
369 | #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L |
370 | #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L |
371 | #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L |
372 | //IH_PERFCOUNTER0_RESULT |
373 | #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 |
374 | #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
375 | //IH_PERFCOUNTER1_RESULT |
376 | #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 |
377 | #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
378 | //IH_DSM_MATCH_VALUE_BIT_31_0 |
379 | #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 |
380 | #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL |
381 | //IH_DSM_MATCH_VALUE_BIT_63_32 |
382 | #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 |
383 | #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL |
384 | //IH_DSM_MATCH_VALUE_BIT_95_64 |
385 | #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 |
386 | #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL |
387 | //IH_DSM_MATCH_FIELD_CONTROL |
388 | #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 |
389 | #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 |
390 | #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 |
391 | #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 |
392 | #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 |
393 | #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 |
394 | #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 |
395 | #define IH_DSM_MATCH_FIELD_CONTROL__DIEID_EN__SHIFT 0x7 |
396 | #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L |
397 | #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L |
398 | #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L |
399 | #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L |
400 | #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L |
401 | #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L |
402 | #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L |
403 | #define IH_DSM_MATCH_FIELD_CONTROL__DIEID_EN_MASK 0x00000080L |
404 | //IH_DSM_MATCH_DATA_CONTROL |
405 | #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 |
406 | #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL |
407 | //IH_DSM_MATCH_FCN_ID |
408 | #define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0 |
409 | #define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1 |
410 | #define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L |
411 | #define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000000EL |
412 | //IH_LIMIT_INT_RATE_CNTL |
413 | #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 |
414 | #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 |
415 | #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 |
416 | #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 |
417 | #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 |
418 | #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L |
419 | #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL |
420 | #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L |
421 | #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L |
422 | #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L |
423 | //IH_VF_RB_STATUS |
424 | #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 |
425 | #define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 |
426 | #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x000000FFL |
427 | #define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0x00FF0000L |
428 | //IH_VF_RB_STATUS2 |
429 | #define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 |
430 | #define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 |
431 | #define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x000000FFL |
432 | #define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0x00FF0000L |
433 | //IH_VF_RB1_STATUS |
434 | #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 |
435 | #define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 |
436 | #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x000000FFL |
437 | #define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0x00FF0000L |
438 | //IH_VF_RB1_STATUS2 |
439 | #define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 |
440 | #define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x000000FFL |
441 | //IH_INT_FLOOD_CNTL |
442 | #define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 |
443 | #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 |
444 | #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 |
445 | #define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L |
446 | #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L |
447 | #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L |
448 | //IH_RB0_INT_FLOOD_STATUS |
449 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 |
450 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f |
451 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x000000FFL |
452 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L |
453 | //IH_RB1_INT_FLOOD_STATUS |
454 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 |
455 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f |
456 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x000000FFL |
457 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L |
458 | //IH_INT_FLOOD_STATUS |
459 | #define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 |
460 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 |
461 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 |
462 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 |
463 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c |
464 | #define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e |
465 | #define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL |
466 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L |
467 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L |
468 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x07000000L |
469 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L |
470 | #define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L |
471 | //IH_STORM_CLIENT_LIST_CNTL |
472 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 |
473 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 |
474 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 |
475 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 |
476 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 |
477 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 |
478 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 |
479 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 |
480 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 |
481 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa |
482 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb |
483 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc |
484 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd |
485 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe |
486 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf |
487 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 |
488 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 |
489 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 |
490 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 |
491 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 |
492 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 |
493 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 |
494 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 |
495 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 |
496 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 |
497 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a |
498 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b |
499 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c |
500 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d |
501 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e |
502 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f |
503 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L |
504 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L |
505 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L |
506 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L |
507 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L |
508 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L |
509 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L |
510 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L |
511 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L |
512 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L |
513 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L |
514 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L |
515 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L |
516 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L |
517 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L |
518 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L |
519 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L |
520 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L |
521 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L |
522 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L |
523 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L |
524 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L |
525 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L |
526 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L |
527 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L |
528 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L |
529 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L |
530 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L |
531 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L |
532 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L |
533 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L |
534 | //IH_CLK_CTRL |
535 | #define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x17 |
536 | #define IH_CLK_CTRL__IH_RAS_CLK_SOFT_OVERRIDE__SHIFT 0x18 |
537 | #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 |
538 | #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a |
539 | #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b |
540 | #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c |
541 | #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d |
542 | #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e |
543 | #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f |
544 | #define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK 0x00800000L |
545 | #define IH_CLK_CTRL__IH_RAS_CLK_SOFT_OVERRIDE_MASK 0x01000000L |
546 | #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L |
547 | #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L |
548 | #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L |
549 | #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L |
550 | #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L |
551 | #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L |
552 | #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L |
553 | //IH_INT_FLAGS |
554 | #define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 |
555 | #define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 |
556 | #define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 |
557 | #define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 |
558 | #define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 |
559 | #define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 |
560 | #define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 |
561 | #define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 |
562 | #define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 |
563 | #define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 |
564 | #define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa |
565 | #define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb |
566 | #define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc |
567 | #define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd |
568 | #define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe |
569 | #define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf |
570 | #define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 |
571 | #define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 |
572 | #define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 |
573 | #define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 |
574 | #define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 |
575 | #define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 |
576 | #define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 |
577 | #define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 |
578 | #define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 |
579 | #define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 |
580 | #define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a |
581 | #define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b |
582 | #define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c |
583 | #define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d |
584 | #define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e |
585 | #define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f |
586 | #define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L |
587 | #define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L |
588 | #define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L |
589 | #define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L |
590 | #define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L |
591 | #define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L |
592 | #define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L |
593 | #define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L |
594 | #define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L |
595 | #define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L |
596 | #define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L |
597 | #define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L |
598 | #define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L |
599 | #define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L |
600 | #define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L |
601 | #define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L |
602 | #define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L |
603 | #define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L |
604 | #define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L |
605 | #define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L |
606 | #define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L |
607 | #define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L |
608 | #define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L |
609 | #define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L |
610 | #define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L |
611 | #define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L |
612 | #define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L |
613 | #define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L |
614 | #define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L |
615 | #define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L |
616 | #define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L |
617 | #define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L |
618 | //IH_LAST_INT_INFO0 |
619 | #define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 |
620 | #define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 |
621 | #define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 |
622 | #define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 |
623 | #define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f |
624 | #define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL |
625 | #define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L |
626 | #define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L |
627 | #define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L |
628 | #define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L |
629 | //IH_LAST_INT_INFO1 |
630 | #define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 |
631 | #define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL |
632 | //IH_LAST_INT_INFO2 |
633 | #define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 |
634 | #define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 |
635 | #define IH_LAST_INT_INFO2__VF__SHIFT 0x14 |
636 | #define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL |
637 | #define IH_LAST_INT_INFO2__VF_ID_MASK 0x00070000L |
638 | #define IH_LAST_INT_INFO2__VF_MASK 0x00100000L |
639 | //IH_SCRATCH |
640 | #define IH_SCRATCH__DATA__SHIFT 0x0 |
641 | #define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL |
642 | //IH_CLIENT_CREDIT_ERROR |
643 | #define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 |
644 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 |
645 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 |
646 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 |
647 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 |
648 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 |
649 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 |
650 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 |
651 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 |
652 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 |
653 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa |
654 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb |
655 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc |
656 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd |
657 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe |
658 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf |
659 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 |
660 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 |
661 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 |
662 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 |
663 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 |
664 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 |
665 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 |
666 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 |
667 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 |
668 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 |
669 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a |
670 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b |
671 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c |
672 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d |
673 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e |
674 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f |
675 | #define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L |
676 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L |
677 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L |
678 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L |
679 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L |
680 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L |
681 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L |
682 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L |
683 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L |
684 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L |
685 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L |
686 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L |
687 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L |
688 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L |
689 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L |
690 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L |
691 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L |
692 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L |
693 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L |
694 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L |
695 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L |
696 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L |
697 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L |
698 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L |
699 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L |
700 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L |
701 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L |
702 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L |
703 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L |
704 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L |
705 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L |
706 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L |
707 | //IH_GPU_IOV_VIOLATION_LOG |
708 | #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 |
709 | #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 |
710 | #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 |
711 | #define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 |
712 | #define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 |
713 | #define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 |
714 | #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L |
715 | #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L |
716 | #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL |
717 | #define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L |
718 | #define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L |
719 | #define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00700000L |
720 | //IH_GPU_IOV_VIOLATION_LOG2 |
721 | #define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 |
722 | #define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL |
723 | //IH_COOKIE_REC_VIOLATION_LOG |
724 | #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 |
725 | #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8 |
726 | #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10 |
727 | #define IH_COOKIE_REC_VIOLATION_LOG__DIE_ID__SHIFT 0x1a |
728 | #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L |
729 | #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L |
730 | #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L |
731 | #define IH_COOKIE_REC_VIOLATION_LOG__DIE_ID_MASK 0x3C000000L |
732 | //IH_CREDIT_STATUS |
733 | #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 |
734 | #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 |
735 | #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 |
736 | #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 |
737 | #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 |
738 | #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 |
739 | #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 |
740 | #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 |
741 | #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 |
742 | #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa |
743 | #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb |
744 | #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc |
745 | #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd |
746 | #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe |
747 | #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf |
748 | #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 |
749 | #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 |
750 | #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 |
751 | #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 |
752 | #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 |
753 | #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 |
754 | #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 |
755 | #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 |
756 | #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 |
757 | #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 |
758 | #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a |
759 | #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b |
760 | #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c |
761 | #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d |
762 | #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e |
763 | #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f |
764 | #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L |
765 | #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L |
766 | #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L |
767 | #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L |
768 | #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L |
769 | #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L |
770 | #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L |
771 | #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L |
772 | #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L |
773 | #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L |
774 | #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L |
775 | #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L |
776 | #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L |
777 | #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L |
778 | #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L |
779 | #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L |
780 | #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L |
781 | #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L |
782 | #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L |
783 | #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L |
784 | #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L |
785 | #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L |
786 | #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L |
787 | #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L |
788 | #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L |
789 | #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L |
790 | #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L |
791 | #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L |
792 | #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L |
793 | #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L |
794 | #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L |
795 | //IH_MMHUB_ERROR |
796 | #define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 |
797 | #define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 |
798 | #define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 |
799 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 |
800 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 |
801 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 |
802 | #define IH_MMHUB_ERROR__IH_BUSER_FED__SHIFT 0x8 |
803 | #define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L |
804 | #define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L |
805 | #define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L |
806 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L |
807 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L |
808 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L |
809 | #define IH_MMHUB_ERROR__IH_BUSER_FED_MASK 0x00000100L |
810 | //IH_MEM_POWER_CTRL |
811 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 |
812 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 |
813 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 |
814 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 |
815 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 |
816 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 |
817 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe |
818 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT 0x10 |
819 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT 0x11 |
820 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT 0x12 |
821 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT 0x13 |
822 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT 0x14 |
823 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 |
824 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0x1e |
825 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L |
826 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L |
827 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L |
828 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L |
829 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L |
830 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L |
831 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L |
832 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK 0x00010000L |
833 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK 0x00020000L |
834 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK 0x00040000L |
835 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK 0x00080000L |
836 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK 0x00700000L |
837 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L |
838 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0xC0000000L |
839 | //IH_RETRY_INT_CAM_CNTL |
840 | #define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0 |
841 | #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8 |
842 | #define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10 |
843 | #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_ENABLE__SHIFT 0x11 |
844 | #define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14 |
845 | #define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL |
846 | #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00007F00L |
847 | #define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L |
848 | #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_ENABLE_MASK 0x00020000L |
849 | #define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L |
850 | //IH_VMID_LUT_INDEX |
851 | #define IH_VMID_LUT_INDEX__INDEX__SHIFT 0x0 |
852 | #define IH_VMID_LUT_INDEX__INDEX_MASK 0x0000000FL |
853 | //IH_MEM_POWER_CTRL2 |
854 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT 0x0 |
855 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT 0x1 |
856 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT 0x2 |
857 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT 0x3 |
858 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT 0x4 |
859 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 |
860 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe |
861 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK 0x00000001L |
862 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK 0x00000002L |
863 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK 0x00000004L |
864 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK 0x00000008L |
865 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK 0x00000070L |
866 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L |
867 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L |
868 | //IH_REGISTER_LAST_PART2 |
869 | #define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 |
870 | #define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL |
871 | //SEM_MAILBOX |
872 | #define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 |
873 | #define SEM_MAILBOX__RESERVED__SHIFT 0x10 |
874 | #define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL |
875 | #define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L |
876 | //SEM_MAILBOX_CLEAR |
877 | #define SEM_MAILBOX_CLEAR__CLEAR__SHIFT 0x0 |
878 | #define SEM_MAILBOX_CLEAR__RESERVED__SHIFT 0x10 |
879 | #define SEM_MAILBOX_CLEAR__CLEAR_MASK 0x0000FFFFL |
880 | #define SEM_MAILBOX_CLEAR__RESERVED_MASK 0xFFFF0000L |
881 | //SEM_REGISTER_LAST_PART2 |
882 | #define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 |
883 | #define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL |
884 | //IH_ACTIVE_FCN_ID |
885 | #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 |
886 | #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x3 |
887 | #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f |
888 | #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x00000007L |
889 | #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF8L |
890 | #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L |
891 | //IH_VIRT_RESET_REQ |
892 | #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 |
893 | #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f |
894 | #define IH_VIRT_RESET_REQ__VF_MASK 0x000000FFL |
895 | #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L |
896 | //IH_CLIENT_CFG |
897 | #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 |
898 | #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000007FL |
899 | //IH_CLIENT_CFG_INDEX |
900 | #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 |
901 | #define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL |
902 | //IH_CLIENT_CFG_DATA |
903 | #define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x13 |
904 | #define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14 |
905 | #define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 |
906 | #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 |
907 | #define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19 |
908 | #define IH_CLIENT_CFG_DATA__DIE_TYPE__SHIFT 0x1a |
909 | #define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x00080000L |
910 | #define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L |
911 | #define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L |
912 | #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L |
913 | #define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L |
914 | #define IH_CLIENT_CFG_DATA__DIE_TYPE_MASK 0x04000000L |
915 | //IH_CLIENT_CFG_DATA2 |
916 | #define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR__SHIFT 0x0 |
917 | #define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR_MASK 0xFFFFFFFFL |
918 | //IH_CID_REMAP_INDEX |
919 | #define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 |
920 | #define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000007L |
921 | //IH_CID_REMAP_DATA |
922 | #define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 |
923 | #define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 |
924 | #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 |
925 | #define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL |
926 | #define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L |
927 | #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L |
928 | //IH_CHICKEN |
929 | #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 |
930 | #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 |
931 | #define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 |
932 | #define IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT 0x5 |
933 | #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L |
934 | #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L |
935 | #define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L |
936 | #define IH_CHICKEN__REG_FIREWALL_ENABLE_MASK 0x00000020L |
937 | //IH_INT_DROP_CNTL |
938 | #define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 |
939 | #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 |
940 | #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 |
941 | #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 |
942 | #define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 |
943 | #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 |
944 | #define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 |
945 | #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 |
946 | #define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 |
947 | #define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L |
948 | #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L |
949 | #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L |
950 | #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L |
951 | #define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L |
952 | #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L |
953 | #define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L |
954 | #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L |
955 | #define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L |
956 | //IH_INT_DROP_MATCH_VALUE0 |
957 | #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 |
958 | #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 |
959 | #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 |
960 | #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 |
961 | #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 |
962 | #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL |
963 | #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L |
964 | #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x000F0000L |
965 | #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L |
966 | #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L |
967 | //IH_INT_DROP_MATCH_VALUE1 |
968 | #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 |
969 | #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL |
970 | //IH_INT_DROP_MATCH_MASK0 |
971 | #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 |
972 | #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 |
973 | #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 |
974 | #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 |
975 | #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 |
976 | #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL |
977 | #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L |
978 | #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x000F0000L |
979 | #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L |
980 | #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L |
981 | //IH_INT_DROP_MATCH_MASK1 |
982 | #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 |
983 | #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL |
984 | //IH_MMHUB_CNTL |
985 | #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 |
986 | #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 |
987 | #define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc |
988 | #define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL |
989 | #define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000F00L |
990 | #define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x0000F000L |
991 | //IH_REGISTER_LAST_PART1 |
992 | #define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 |
993 | #define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL |
994 | |
995 | #endif |
996 | |