| 1 | /* |
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| 2 | * Copyright 2020 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef _sdma_4_4_0_OFFSET_HEADER |
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| 24 | #define |
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| 25 | |
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| 26 | |
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| 27 | // addressBlock: sdma0_sdma0dec |
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| 28 | // base address: 0x4980 |
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| 29 | #define regSDMA0_UCODE_ADDR 0x0000 |
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| 30 | #define regSDMA0_UCODE_ADDR_BASE_IDX 0 |
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| 31 | #define regSDMA0_UCODE_DATA 0x0001 |
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| 32 | #define regSDMA0_UCODE_DATA_BASE_IDX 0 |
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| 33 | #define regSDMA0_VF_ENABLE 0x000a |
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| 34 | #define regSDMA0_VF_ENABLE_BASE_IDX 0 |
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| 35 | #define regSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 |
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| 36 | #define regSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
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| 37 | #define regSDMA0_POWER_CNTL 0x001a |
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| 38 | #define regSDMA0_POWER_CNTL_BASE_IDX 0 |
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| 39 | #define regSDMA0_CLK_CTRL 0x001b |
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| 40 | #define regSDMA0_CLK_CTRL_BASE_IDX 0 |
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| 41 | #define regSDMA0_CNTL 0x001c |
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| 42 | #define regSDMA0_CNTL_BASE_IDX 0 |
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| 43 | #define regSDMA0_CHICKEN_BITS 0x001d |
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| 44 | #define regSDMA0_CHICKEN_BITS_BASE_IDX 0 |
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| 45 | #define regSDMA0_GB_ADDR_CONFIG 0x001e |
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| 46 | #define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 |
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| 47 | #define regSDMA0_GB_ADDR_CONFIG_READ 0x001f |
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| 48 | #define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
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| 49 | #define regSDMA0_RB_RPTR_FETCH_HI 0x0020 |
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| 50 | #define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 |
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| 51 | #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 |
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| 52 | #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
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| 53 | #define regSDMA0_RB_RPTR_FETCH 0x0022 |
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| 54 | #define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0 |
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| 55 | #define regSDMA0_IB_OFFSET_FETCH 0x0023 |
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| 56 | #define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 |
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| 57 | #define regSDMA0_PROGRAM 0x0024 |
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| 58 | #define regSDMA0_PROGRAM_BASE_IDX 0 |
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| 59 | #define regSDMA0_STATUS_REG 0x0025 |
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| 60 | #define regSDMA0_STATUS_REG_BASE_IDX 0 |
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| 61 | #define regSDMA0_STATUS1_REG 0x0026 |
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| 62 | #define regSDMA0_STATUS1_REG_BASE_IDX 0 |
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| 63 | #define regSDMA0_RD_BURST_CNTL 0x0027 |
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| 64 | #define regSDMA0_RD_BURST_CNTL_BASE_IDX 0 |
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| 65 | #define regSDMA0_HBM_PAGE_CONFIG 0x0028 |
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| 66 | #define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 |
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| 67 | #define regSDMA0_UCODE_CHECKSUM 0x0029 |
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| 68 | #define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0 |
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| 69 | #define regSDMA0_F32_CNTL 0x002a |
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| 70 | #define regSDMA0_F32_CNTL_BASE_IDX 0 |
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| 71 | #define regSDMA0_FREEZE 0x002b |
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| 72 | #define regSDMA0_FREEZE_BASE_IDX 0 |
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| 73 | #define regSDMA0_PHASE0_QUANTUM 0x002c |
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| 74 | #define regSDMA0_PHASE0_QUANTUM_BASE_IDX 0 |
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| 75 | #define regSDMA0_PHASE1_QUANTUM 0x002d |
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| 76 | #define regSDMA0_PHASE1_QUANTUM_BASE_IDX 0 |
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| 77 | #define regSDMA_POWER_GATING 0x002e |
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| 78 | #define regSDMA_POWER_GATING_BASE_IDX 0 |
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| 79 | #define regSDMA_PGFSM_CONFIG 0x002f |
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| 80 | #define regSDMA_PGFSM_CONFIG_BASE_IDX 0 |
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| 81 | #define regSDMA_PGFSM_WRITE 0x0030 |
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| 82 | #define regSDMA_PGFSM_WRITE_BASE_IDX 0 |
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| 83 | #define regSDMA_PGFSM_READ 0x0031 |
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| 84 | #define regSDMA_PGFSM_READ_BASE_IDX 0 |
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| 85 | #define regCC_SDMA0_EDC_CONFIG 0x0032 |
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| 86 | #define regCC_SDMA0_EDC_CONFIG_BASE_IDX 0 |
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| 87 | #define regSDMA0_BA_THRESHOLD 0x0033 |
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| 88 | #define regSDMA0_BA_THRESHOLD_BASE_IDX 0 |
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| 89 | #define regSDMA0_ID 0x0034 |
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| 90 | #define regSDMA0_ID_BASE_IDX 0 |
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| 91 | #define regSDMA0_VERSION 0x0035 |
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| 92 | #define regSDMA0_VERSION_BASE_IDX 0 |
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| 93 | #define regSDMA0_EDC_COUNTER 0x0036 |
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| 94 | #define regSDMA0_EDC_COUNTER_BASE_IDX 0 |
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| 95 | #define regSDMA0_EDC_COUNTER2 0x0037 |
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| 96 | #define regSDMA0_EDC_COUNTER2_BASE_IDX 0 |
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| 97 | #define regSDMA0_STATUS2_REG 0x0038 |
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| 98 | #define regSDMA0_STATUS2_REG_BASE_IDX 0 |
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| 99 | #define regSDMA0_ATOMIC_CNTL 0x0039 |
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| 100 | #define regSDMA0_ATOMIC_CNTL_BASE_IDX 0 |
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| 101 | #define regSDMA0_ATOMIC_PREOP_LO 0x003a |
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| 102 | #define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 |
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| 103 | #define regSDMA0_ATOMIC_PREOP_HI 0x003b |
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| 104 | #define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 |
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| 105 | #define regSDMA0_UTCL1_CNTL 0x003c |
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| 106 | #define regSDMA0_UTCL1_CNTL_BASE_IDX 0 |
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| 107 | #define regSDMA0_UTCL1_WATERMK 0x003d |
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| 108 | #define regSDMA0_UTCL1_WATERMK_BASE_IDX 0 |
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| 109 | #define regSDMA0_UTCL1_RD_STATUS 0x003e |
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| 110 | #define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 |
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| 111 | #define regSDMA0_UTCL1_WR_STATUS 0x003f |
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| 112 | #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 |
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| 113 | #define regSDMA0_UTCL1_INV0 0x0040 |
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| 114 | #define regSDMA0_UTCL1_INV0_BASE_IDX 0 |
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| 115 | #define regSDMA0_UTCL1_INV1 0x0041 |
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| 116 | #define regSDMA0_UTCL1_INV1_BASE_IDX 0 |
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| 117 | #define regSDMA0_UTCL1_INV2 0x0042 |
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| 118 | #define regSDMA0_UTCL1_INV2_BASE_IDX 0 |
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| 119 | #define regSDMA0_UTCL1_RD_XNACK0 0x0043 |
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| 120 | #define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 |
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| 121 | #define regSDMA0_UTCL1_RD_XNACK1 0x0044 |
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| 122 | #define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 |
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| 123 | #define regSDMA0_UTCL1_WR_XNACK0 0x0045 |
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| 124 | #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 |
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| 125 | #define regSDMA0_UTCL1_WR_XNACK1 0x0046 |
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| 126 | #define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 |
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| 127 | #define regSDMA0_UTCL1_TIMEOUT 0x0047 |
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| 128 | #define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 |
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| 129 | #define regSDMA0_UTCL1_PAGE 0x0048 |
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| 130 | #define regSDMA0_UTCL1_PAGE_BASE_IDX 0 |
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| 131 | #define regSDMA0_POWER_CNTL_IDLE 0x0049 |
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| 132 | #define regSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 |
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| 133 | #define regSDMA0_RELAX_ORDERING_LUT 0x004a |
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| 134 | #define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 |
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| 135 | #define regSDMA0_CHICKEN_BITS_2 0x004b |
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| 136 | #define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0 |
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| 137 | #define regSDMA0_STATUS3_REG 0x004c |
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| 138 | #define regSDMA0_STATUS3_REG_BASE_IDX 0 |
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| 139 | #define regSDMA0_PHYSICAL_ADDR_LO 0x004d |
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| 140 | #define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 |
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| 141 | #define regSDMA0_PHYSICAL_ADDR_HI 0x004e |
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| 142 | #define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 |
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| 143 | #define regSDMA0_PHASE2_QUANTUM 0x004f |
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| 144 | #define regSDMA0_PHASE2_QUANTUM_BASE_IDX 0 |
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| 145 | #define regSDMA0_ERROR_LOG 0x0050 |
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| 146 | #define regSDMA0_ERROR_LOG_BASE_IDX 0 |
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| 147 | #define regSDMA0_PUB_DUMMY_REG0 0x0051 |
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| 148 | #define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 |
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| 149 | #define regSDMA0_PUB_DUMMY_REG1 0x0052 |
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| 150 | #define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 |
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| 151 | #define regSDMA0_PUB_DUMMY_REG2 0x0053 |
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| 152 | #define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 |
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| 153 | #define regSDMA0_PUB_DUMMY_REG3 0x0054 |
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| 154 | #define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 |
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| 155 | #define regSDMA0_F32_COUNTER 0x0055 |
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| 156 | #define regSDMA0_F32_COUNTER_BASE_IDX 0 |
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| 157 | #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x0057 |
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| 158 | #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 |
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| 159 | #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x0058 |
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| 160 | #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 |
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| 161 | #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0059 |
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| 162 | #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
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| 163 | #define regSDMA0_PERFCNT_MISC_CNTL 0x005a |
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| 164 | #define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 0 |
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| 165 | #define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x005b |
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| 166 | #define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 |
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| 167 | #define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x005c |
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| 168 | #define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 |
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| 169 | #define regSDMA0_CRD_CNTL 0x005d |
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| 170 | #define regSDMA0_CRD_CNTL_BASE_IDX 0 |
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| 171 | #define regSDMA0_ULV_CNTL 0x005f |
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| 172 | #define regSDMA0_ULV_CNTL_BASE_IDX 0 |
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| 173 | #define regSDMA0_EA_DBIT_ADDR_DATA 0x0060 |
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| 174 | #define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
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| 175 | #define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061 |
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| 176 | #define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
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| 177 | #define regSDMA0_STATUS4_REG 0x0063 |
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| 178 | #define regSDMA0_STATUS4_REG_BASE_IDX 0 |
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| 179 | #define regSDMA0_SCRATCH_RAM_DATA 0x0064 |
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| 180 | #define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 |
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| 181 | #define regSDMA0_SCRATCH_RAM_ADDR 0x0065 |
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| 182 | #define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 |
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| 183 | #define regSDMA0_CE_CTRL 0x0066 |
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| 184 | #define regSDMA0_CE_CTRL_BASE_IDX 0 |
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| 185 | #define regSDMA0_RAS_STATUS 0x0067 |
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| 186 | #define regSDMA0_RAS_STATUS_BASE_IDX 0 |
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| 187 | #define regSDMA0_CLK_STATUS 0x0068 |
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| 188 | #define regSDMA0_CLK_STATUS_BASE_IDX 0 |
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| 189 | #define regSDMA0_GFX_RB_CNTL 0x0080 |
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| 190 | #define regSDMA0_GFX_RB_CNTL_BASE_IDX 0 |
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| 191 | #define regSDMA0_GFX_RB_BASE 0x0081 |
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| 192 | #define regSDMA0_GFX_RB_BASE_BASE_IDX 0 |
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| 193 | #define regSDMA0_GFX_RB_BASE_HI 0x0082 |
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| 194 | #define regSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 |
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| 195 | #define regSDMA0_GFX_RB_RPTR 0x0083 |
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| 196 | #define regSDMA0_GFX_RB_RPTR_BASE_IDX 0 |
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| 197 | #define regSDMA0_GFX_RB_RPTR_HI 0x0084 |
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| 198 | #define regSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 |
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| 199 | #define regSDMA0_GFX_RB_WPTR 0x0085 |
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| 200 | #define regSDMA0_GFX_RB_WPTR_BASE_IDX 0 |
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| 201 | #define regSDMA0_GFX_RB_WPTR_HI 0x0086 |
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| 202 | #define regSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 |
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| 203 | #define regSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 |
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| 204 | #define regSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
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| 205 | #define regSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 |
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| 206 | #define regSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
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| 207 | #define regSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 |
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| 208 | #define regSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
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| 209 | #define regSDMA0_GFX_IB_CNTL 0x008a |
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| 210 | #define regSDMA0_GFX_IB_CNTL_BASE_IDX 0 |
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| 211 | #define regSDMA0_GFX_IB_RPTR 0x008b |
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| 212 | #define regSDMA0_GFX_IB_RPTR_BASE_IDX 0 |
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| 213 | #define regSDMA0_GFX_IB_OFFSET 0x008c |
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| 214 | #define regSDMA0_GFX_IB_OFFSET_BASE_IDX 0 |
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| 215 | #define regSDMA0_GFX_IB_BASE_LO 0x008d |
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| 216 | #define regSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 |
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| 217 | #define regSDMA0_GFX_IB_BASE_HI 0x008e |
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| 218 | #define regSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 |
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| 219 | #define regSDMA0_GFX_IB_SIZE 0x008f |
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| 220 | #define regSDMA0_GFX_IB_SIZE_BASE_IDX 0 |
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| 221 | #define regSDMA0_GFX_SKIP_CNTL 0x0090 |
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| 222 | #define regSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 |
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| 223 | #define regSDMA0_GFX_CONTEXT_STATUS 0x0091 |
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| 224 | #define regSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 |
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| 225 | #define regSDMA0_GFX_DOORBELL 0x0092 |
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| 226 | #define regSDMA0_GFX_DOORBELL_BASE_IDX 0 |
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| 227 | #define regSDMA0_GFX_CONTEXT_CNTL 0x0093 |
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| 228 | #define regSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 |
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| 229 | #define regSDMA0_GFX_STATUS 0x00a8 |
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| 230 | #define regSDMA0_GFX_STATUS_BASE_IDX 0 |
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| 231 | #define regSDMA0_GFX_DOORBELL_LOG 0x00a9 |
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| 232 | #define regSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 |
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| 233 | #define regSDMA0_GFX_WATERMARK 0x00aa |
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| 234 | #define regSDMA0_GFX_WATERMARK_BASE_IDX 0 |
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| 235 | #define regSDMA0_GFX_DOORBELL_OFFSET 0x00ab |
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| 236 | #define regSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
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| 237 | #define regSDMA0_GFX_CSA_ADDR_LO 0x00ac |
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| 238 | #define regSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 |
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| 239 | #define regSDMA0_GFX_CSA_ADDR_HI 0x00ad |
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| 240 | #define regSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 |
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| 241 | #define regSDMA0_GFX_IB_SUB_REMAIN 0x00af |
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| 242 | #define regSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
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| 243 | #define regSDMA0_GFX_PREEMPT 0x00b0 |
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| 244 | #define regSDMA0_GFX_PREEMPT_BASE_IDX 0 |
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| 245 | #define regSDMA0_GFX_DUMMY_REG 0x00b1 |
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| 246 | #define regSDMA0_GFX_DUMMY_REG_BASE_IDX 0 |
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| 247 | #define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 |
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| 248 | #define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
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| 249 | #define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 |
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| 250 | #define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
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| 251 | #define regSDMA0_GFX_RB_AQL_CNTL 0x00b4 |
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| 252 | #define regSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 |
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| 253 | #define regSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 |
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| 254 | #define regSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
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| 255 | #define regSDMA0_GFX_MIDCMD_DATA0 0x00c0 |
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| 256 | #define regSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 |
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| 257 | #define regSDMA0_GFX_MIDCMD_DATA1 0x00c1 |
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| 258 | #define regSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 |
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| 259 | #define regSDMA0_GFX_MIDCMD_DATA2 0x00c2 |
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| 260 | #define regSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 |
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| 261 | #define regSDMA0_GFX_MIDCMD_DATA3 0x00c3 |
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| 262 | #define regSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 |
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| 263 | #define regSDMA0_GFX_MIDCMD_DATA4 0x00c4 |
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| 264 | #define regSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 |
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| 265 | #define regSDMA0_GFX_MIDCMD_DATA5 0x00c5 |
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| 266 | #define regSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 |
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| 267 | #define regSDMA0_GFX_MIDCMD_DATA6 0x00c6 |
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| 268 | #define regSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 |
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| 269 | #define regSDMA0_GFX_MIDCMD_DATA7 0x00c7 |
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| 270 | #define regSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 |
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| 271 | #define regSDMA0_GFX_MIDCMD_DATA8 0x00c8 |
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| 272 | #define regSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 |
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| 273 | #define regSDMA0_GFX_MIDCMD_DATA9 0x00c9 |
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| 274 | #define regSDMA0_GFX_MIDCMD_DATA9_BASE_IDX 0 |
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| 275 | #define regSDMA0_GFX_MIDCMD_DATA10 0x00ca |
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| 276 | #define regSDMA0_GFX_MIDCMD_DATA10_BASE_IDX 0 |
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| 277 | #define regSDMA0_GFX_MIDCMD_CNTL 0x00cb |
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| 278 | #define regSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 |
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| 279 | #define regSDMA0_PAGE_RB_CNTL 0x00d8 |
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| 280 | #define regSDMA0_PAGE_RB_CNTL_BASE_IDX 0 |
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| 281 | #define regSDMA0_PAGE_RB_BASE 0x00d9 |
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| 282 | #define regSDMA0_PAGE_RB_BASE_BASE_IDX 0 |
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| 283 | #define regSDMA0_PAGE_RB_BASE_HI 0x00da |
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| 284 | #define regSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 |
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| 285 | #define regSDMA0_PAGE_RB_RPTR 0x00db |
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| 286 | #define regSDMA0_PAGE_RB_RPTR_BASE_IDX 0 |
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| 287 | #define regSDMA0_PAGE_RB_RPTR_HI 0x00dc |
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| 288 | #define regSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 |
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| 289 | #define regSDMA0_PAGE_RB_WPTR 0x00dd |
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| 290 | #define regSDMA0_PAGE_RB_WPTR_BASE_IDX 0 |
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| 291 | #define regSDMA0_PAGE_RB_WPTR_HI 0x00de |
|---|
| 292 | #define regSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 |
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| 293 | #define regSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df |
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| 294 | #define regSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 295 | #define regSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0 |
|---|
| 296 | #define regSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 297 | #define regSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1 |
|---|
| 298 | #define regSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
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| 299 | #define regSDMA0_PAGE_IB_CNTL 0x00e2 |
|---|
| 300 | #define regSDMA0_PAGE_IB_CNTL_BASE_IDX 0 |
|---|
| 301 | #define regSDMA0_PAGE_IB_RPTR 0x00e3 |
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| 302 | #define regSDMA0_PAGE_IB_RPTR_BASE_IDX 0 |
|---|
| 303 | #define regSDMA0_PAGE_IB_OFFSET 0x00e4 |
|---|
| 304 | #define regSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 |
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| 305 | #define regSDMA0_PAGE_IB_BASE_LO 0x00e5 |
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| 306 | #define regSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 |
|---|
| 307 | #define regSDMA0_PAGE_IB_BASE_HI 0x00e6 |
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| 308 | #define regSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 |
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| 309 | #define regSDMA0_PAGE_IB_SIZE 0x00e7 |
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| 310 | #define regSDMA0_PAGE_IB_SIZE_BASE_IDX 0 |
|---|
| 311 | #define regSDMA0_PAGE_SKIP_CNTL 0x00e8 |
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| 312 | #define regSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 |
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| 313 | #define regSDMA0_PAGE_CONTEXT_STATUS 0x00e9 |
|---|
| 314 | #define regSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
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| 315 | #define regSDMA0_PAGE_DOORBELL 0x00ea |
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| 316 | #define regSDMA0_PAGE_DOORBELL_BASE_IDX 0 |
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| 317 | #define regSDMA0_PAGE_STATUS 0x0100 |
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| 318 | #define regSDMA0_PAGE_STATUS_BASE_IDX 0 |
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| 319 | #define regSDMA0_PAGE_DOORBELL_LOG 0x0101 |
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| 320 | #define regSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 |
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| 321 | #define regSDMA0_PAGE_WATERMARK 0x0102 |
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| 322 | #define regSDMA0_PAGE_WATERMARK_BASE_IDX 0 |
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| 323 | #define regSDMA0_PAGE_DOORBELL_OFFSET 0x0103 |
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| 324 | #define regSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
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| 325 | #define regSDMA0_PAGE_CSA_ADDR_LO 0x0104 |
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| 326 | #define regSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
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| 327 | #define regSDMA0_PAGE_CSA_ADDR_HI 0x0105 |
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| 328 | #define regSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
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| 329 | #define regSDMA0_PAGE_IB_SUB_REMAIN 0x0107 |
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| 330 | #define regSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
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| 331 | #define regSDMA0_PAGE_PREEMPT 0x0108 |
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| 332 | #define regSDMA0_PAGE_PREEMPT_BASE_IDX 0 |
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| 333 | #define regSDMA0_PAGE_DUMMY_REG 0x0109 |
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| 334 | #define regSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 |
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| 335 | #define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a |
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| 336 | #define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 337 | #define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b |
|---|
| 338 | #define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 339 | #define regSDMA0_PAGE_RB_AQL_CNTL 0x010c |
|---|
| 340 | #define regSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
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| 341 | #define regSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d |
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| 342 | #define regSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 343 | #define regSDMA0_PAGE_MIDCMD_DATA0 0x0118 |
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| 344 | #define regSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
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| 345 | #define regSDMA0_PAGE_MIDCMD_DATA1 0x0119 |
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| 346 | #define regSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
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| 347 | #define regSDMA0_PAGE_MIDCMD_DATA2 0x011a |
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| 348 | #define regSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 349 | #define regSDMA0_PAGE_MIDCMD_DATA3 0x011b |
|---|
| 350 | #define regSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 351 | #define regSDMA0_PAGE_MIDCMD_DATA4 0x011c |
|---|
| 352 | #define regSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 353 | #define regSDMA0_PAGE_MIDCMD_DATA5 0x011d |
|---|
| 354 | #define regSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 355 | #define regSDMA0_PAGE_MIDCMD_DATA6 0x011e |
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| 356 | #define regSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 357 | #define regSDMA0_PAGE_MIDCMD_DATA7 0x011f |
|---|
| 358 | #define regSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 359 | #define regSDMA0_PAGE_MIDCMD_DATA8 0x0120 |
|---|
| 360 | #define regSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 361 | #define regSDMA0_PAGE_MIDCMD_DATA9 0x0121 |
|---|
| 362 | #define regSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 363 | #define regSDMA0_PAGE_MIDCMD_DATA10 0x0122 |
|---|
| 364 | #define regSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 365 | #define regSDMA0_PAGE_MIDCMD_CNTL 0x0123 |
|---|
| 366 | #define regSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 367 | #define regSDMA0_RLC0_RB_CNTL 0x0130 |
|---|
| 368 | #define regSDMA0_RLC0_RB_CNTL_BASE_IDX 0 |
|---|
| 369 | #define regSDMA0_RLC0_RB_BASE 0x0131 |
|---|
| 370 | #define regSDMA0_RLC0_RB_BASE_BASE_IDX 0 |
|---|
| 371 | #define regSDMA0_RLC0_RB_BASE_HI 0x0132 |
|---|
| 372 | #define regSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 |
|---|
| 373 | #define regSDMA0_RLC0_RB_RPTR 0x0133 |
|---|
| 374 | #define regSDMA0_RLC0_RB_RPTR_BASE_IDX 0 |
|---|
| 375 | #define regSDMA0_RLC0_RB_RPTR_HI 0x0134 |
|---|
| 376 | #define regSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 377 | #define regSDMA0_RLC0_RB_WPTR 0x0135 |
|---|
| 378 | #define regSDMA0_RLC0_RB_WPTR_BASE_IDX 0 |
|---|
| 379 | #define regSDMA0_RLC0_RB_WPTR_HI 0x0136 |
|---|
| 380 | #define regSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 381 | #define regSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137 |
|---|
| 382 | #define regSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 383 | #define regSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138 |
|---|
| 384 | #define regSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 385 | #define regSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139 |
|---|
| 386 | #define regSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 387 | #define regSDMA0_RLC0_IB_CNTL 0x013a |
|---|
| 388 | #define regSDMA0_RLC0_IB_CNTL_BASE_IDX 0 |
|---|
| 389 | #define regSDMA0_RLC0_IB_RPTR 0x013b |
|---|
| 390 | #define regSDMA0_RLC0_IB_RPTR_BASE_IDX 0 |
|---|
| 391 | #define regSDMA0_RLC0_IB_OFFSET 0x013c |
|---|
| 392 | #define regSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 |
|---|
| 393 | #define regSDMA0_RLC0_IB_BASE_LO 0x013d |
|---|
| 394 | #define regSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 |
|---|
| 395 | #define regSDMA0_RLC0_IB_BASE_HI 0x013e |
|---|
| 396 | #define regSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 |
|---|
| 397 | #define regSDMA0_RLC0_IB_SIZE 0x013f |
|---|
| 398 | #define regSDMA0_RLC0_IB_SIZE_BASE_IDX 0 |
|---|
| 399 | #define regSDMA0_RLC0_SKIP_CNTL 0x0140 |
|---|
| 400 | #define regSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 |
|---|
| 401 | #define regSDMA0_RLC0_CONTEXT_STATUS 0x0141 |
|---|
| 402 | #define regSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 403 | #define regSDMA0_RLC0_DOORBELL 0x0142 |
|---|
| 404 | #define regSDMA0_RLC0_DOORBELL_BASE_IDX 0 |
|---|
| 405 | #define regSDMA0_RLC0_STATUS 0x0158 |
|---|
| 406 | #define regSDMA0_RLC0_STATUS_BASE_IDX 0 |
|---|
| 407 | #define regSDMA0_RLC0_DOORBELL_LOG 0x0159 |
|---|
| 408 | #define regSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 409 | #define regSDMA0_RLC0_WATERMARK 0x015a |
|---|
| 410 | #define regSDMA0_RLC0_WATERMARK_BASE_IDX 0 |
|---|
| 411 | #define regSDMA0_RLC0_DOORBELL_OFFSET 0x015b |
|---|
| 412 | #define regSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 413 | #define regSDMA0_RLC0_CSA_ADDR_LO 0x015c |
|---|
| 414 | #define regSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 415 | #define regSDMA0_RLC0_CSA_ADDR_HI 0x015d |
|---|
| 416 | #define regSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 417 | #define regSDMA0_RLC0_IB_SUB_REMAIN 0x015f |
|---|
| 418 | #define regSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 419 | #define regSDMA0_RLC0_PREEMPT 0x0160 |
|---|
| 420 | #define regSDMA0_RLC0_PREEMPT_BASE_IDX 0 |
|---|
| 421 | #define regSDMA0_RLC0_DUMMY_REG 0x0161 |
|---|
| 422 | #define regSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 |
|---|
| 423 | #define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 |
|---|
| 424 | #define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 425 | #define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 |
|---|
| 426 | #define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 427 | #define regSDMA0_RLC0_RB_AQL_CNTL 0x0164 |
|---|
| 428 | #define regSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 429 | #define regSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165 |
|---|
| 430 | #define regSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 431 | #define regSDMA0_RLC0_MIDCMD_DATA0 0x0170 |
|---|
| 432 | #define regSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 433 | #define regSDMA0_RLC0_MIDCMD_DATA1 0x0171 |
|---|
| 434 | #define regSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 435 | #define regSDMA0_RLC0_MIDCMD_DATA2 0x0172 |
|---|
| 436 | #define regSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 437 | #define regSDMA0_RLC0_MIDCMD_DATA3 0x0173 |
|---|
| 438 | #define regSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 439 | #define regSDMA0_RLC0_MIDCMD_DATA4 0x0174 |
|---|
| 440 | #define regSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 441 | #define regSDMA0_RLC0_MIDCMD_DATA5 0x0175 |
|---|
| 442 | #define regSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 443 | #define regSDMA0_RLC0_MIDCMD_DATA6 0x0176 |
|---|
| 444 | #define regSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 445 | #define regSDMA0_RLC0_MIDCMD_DATA7 0x0177 |
|---|
| 446 | #define regSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 447 | #define regSDMA0_RLC0_MIDCMD_DATA8 0x0178 |
|---|
| 448 | #define regSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 449 | #define regSDMA0_RLC0_MIDCMD_DATA9 0x0179 |
|---|
| 450 | #define regSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 451 | #define regSDMA0_RLC0_MIDCMD_DATA10 0x017a |
|---|
| 452 | #define regSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 453 | #define regSDMA0_RLC0_MIDCMD_CNTL 0x017b |
|---|
| 454 | #define regSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 455 | #define regSDMA0_RLC1_RB_CNTL 0x0188 |
|---|
| 456 | #define regSDMA0_RLC1_RB_CNTL_BASE_IDX 0 |
|---|
| 457 | #define regSDMA0_RLC1_RB_BASE 0x0189 |
|---|
| 458 | #define regSDMA0_RLC1_RB_BASE_BASE_IDX 0 |
|---|
| 459 | #define regSDMA0_RLC1_RB_BASE_HI 0x018a |
|---|
| 460 | #define regSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 |
|---|
| 461 | #define regSDMA0_RLC1_RB_RPTR 0x018b |
|---|
| 462 | #define regSDMA0_RLC1_RB_RPTR_BASE_IDX 0 |
|---|
| 463 | #define regSDMA0_RLC1_RB_RPTR_HI 0x018c |
|---|
| 464 | #define regSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 465 | #define regSDMA0_RLC1_RB_WPTR 0x018d |
|---|
| 466 | #define regSDMA0_RLC1_RB_WPTR_BASE_IDX 0 |
|---|
| 467 | #define regSDMA0_RLC1_RB_WPTR_HI 0x018e |
|---|
| 468 | #define regSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 469 | #define regSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f |
|---|
| 470 | #define regSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 471 | #define regSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190 |
|---|
| 472 | #define regSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 473 | #define regSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191 |
|---|
| 474 | #define regSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 475 | #define regSDMA0_RLC1_IB_CNTL 0x0192 |
|---|
| 476 | #define regSDMA0_RLC1_IB_CNTL_BASE_IDX 0 |
|---|
| 477 | #define regSDMA0_RLC1_IB_RPTR 0x0193 |
|---|
| 478 | #define regSDMA0_RLC1_IB_RPTR_BASE_IDX 0 |
|---|
| 479 | #define regSDMA0_RLC1_IB_OFFSET 0x0194 |
|---|
| 480 | #define regSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 |
|---|
| 481 | #define regSDMA0_RLC1_IB_BASE_LO 0x0195 |
|---|
| 482 | #define regSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 |
|---|
| 483 | #define regSDMA0_RLC1_IB_BASE_HI 0x0196 |
|---|
| 484 | #define regSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 |
|---|
| 485 | #define regSDMA0_RLC1_IB_SIZE 0x0197 |
|---|
| 486 | #define regSDMA0_RLC1_IB_SIZE_BASE_IDX 0 |
|---|
| 487 | #define regSDMA0_RLC1_SKIP_CNTL 0x0198 |
|---|
| 488 | #define regSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 |
|---|
| 489 | #define regSDMA0_RLC1_CONTEXT_STATUS 0x0199 |
|---|
| 490 | #define regSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 491 | #define regSDMA0_RLC1_DOORBELL 0x019a |
|---|
| 492 | #define regSDMA0_RLC1_DOORBELL_BASE_IDX 0 |
|---|
| 493 | #define regSDMA0_RLC1_STATUS 0x01b0 |
|---|
| 494 | #define regSDMA0_RLC1_STATUS_BASE_IDX 0 |
|---|
| 495 | #define regSDMA0_RLC1_DOORBELL_LOG 0x01b1 |
|---|
| 496 | #define regSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 497 | #define regSDMA0_RLC1_WATERMARK 0x01b2 |
|---|
| 498 | #define regSDMA0_RLC1_WATERMARK_BASE_IDX 0 |
|---|
| 499 | #define regSDMA0_RLC1_DOORBELL_OFFSET 0x01b3 |
|---|
| 500 | #define regSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 501 | #define regSDMA0_RLC1_CSA_ADDR_LO 0x01b4 |
|---|
| 502 | #define regSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 503 | #define regSDMA0_RLC1_CSA_ADDR_HI 0x01b5 |
|---|
| 504 | #define regSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 505 | #define regSDMA0_RLC1_IB_SUB_REMAIN 0x01b7 |
|---|
| 506 | #define regSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 507 | #define regSDMA0_RLC1_PREEMPT 0x01b8 |
|---|
| 508 | #define regSDMA0_RLC1_PREEMPT_BASE_IDX 0 |
|---|
| 509 | #define regSDMA0_RLC1_DUMMY_REG 0x01b9 |
|---|
| 510 | #define regSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 |
|---|
| 511 | #define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba |
|---|
| 512 | #define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 513 | #define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb |
|---|
| 514 | #define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 515 | #define regSDMA0_RLC1_RB_AQL_CNTL 0x01bc |
|---|
| 516 | #define regSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 517 | #define regSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd |
|---|
| 518 | #define regSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 519 | #define regSDMA0_RLC1_MIDCMD_DATA0 0x01c8 |
|---|
| 520 | #define regSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 521 | #define regSDMA0_RLC1_MIDCMD_DATA1 0x01c9 |
|---|
| 522 | #define regSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 523 | #define regSDMA0_RLC1_MIDCMD_DATA2 0x01ca |
|---|
| 524 | #define regSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 525 | #define regSDMA0_RLC1_MIDCMD_DATA3 0x01cb |
|---|
| 526 | #define regSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 527 | #define regSDMA0_RLC1_MIDCMD_DATA4 0x01cc |
|---|
| 528 | #define regSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 529 | #define regSDMA0_RLC1_MIDCMD_DATA5 0x01cd |
|---|
| 530 | #define regSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 531 | #define regSDMA0_RLC1_MIDCMD_DATA6 0x01ce |
|---|
| 532 | #define regSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 533 | #define regSDMA0_RLC1_MIDCMD_DATA7 0x01cf |
|---|
| 534 | #define regSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 535 | #define regSDMA0_RLC1_MIDCMD_DATA8 0x01d0 |
|---|
| 536 | #define regSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 537 | #define regSDMA0_RLC1_MIDCMD_DATA9 0x01d1 |
|---|
| 538 | #define regSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 539 | #define regSDMA0_RLC1_MIDCMD_DATA10 0x01d2 |
|---|
| 540 | #define regSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 541 | #define regSDMA0_RLC1_MIDCMD_CNTL 0x01d3 |
|---|
| 542 | #define regSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 543 | #define regSDMA0_RLC2_RB_CNTL 0x01e0 |
|---|
| 544 | #define regSDMA0_RLC2_RB_CNTL_BASE_IDX 0 |
|---|
| 545 | #define regSDMA0_RLC2_RB_BASE 0x01e1 |
|---|
| 546 | #define regSDMA0_RLC2_RB_BASE_BASE_IDX 0 |
|---|
| 547 | #define regSDMA0_RLC2_RB_BASE_HI 0x01e2 |
|---|
| 548 | #define regSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 |
|---|
| 549 | #define regSDMA0_RLC2_RB_RPTR 0x01e3 |
|---|
| 550 | #define regSDMA0_RLC2_RB_RPTR_BASE_IDX 0 |
|---|
| 551 | #define regSDMA0_RLC2_RB_RPTR_HI 0x01e4 |
|---|
| 552 | #define regSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 553 | #define regSDMA0_RLC2_RB_WPTR 0x01e5 |
|---|
| 554 | #define regSDMA0_RLC2_RB_WPTR_BASE_IDX 0 |
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| 555 | #define regSDMA0_RLC2_RB_WPTR_HI 0x01e6 |
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| 556 | #define regSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 |
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| 557 | #define regSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 |
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| 558 | #define regSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
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| 559 | #define regSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8 |
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| 560 | #define regSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 |
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| 561 | #define regSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9 |
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| 562 | #define regSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 |
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| 563 | #define regSDMA0_RLC2_IB_CNTL 0x01ea |
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| 564 | #define regSDMA0_RLC2_IB_CNTL_BASE_IDX 0 |
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| 565 | #define regSDMA0_RLC2_IB_RPTR 0x01eb |
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| 566 | #define regSDMA0_RLC2_IB_RPTR_BASE_IDX 0 |
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| 567 | #define regSDMA0_RLC2_IB_OFFSET 0x01ec |
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| 568 | #define regSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 |
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| 569 | #define regSDMA0_RLC2_IB_BASE_LO 0x01ed |
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| 570 | #define regSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 |
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| 571 | #define regSDMA0_RLC2_IB_BASE_HI 0x01ee |
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| 572 | #define regSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 |
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| 573 | #define regSDMA0_RLC2_IB_SIZE 0x01ef |
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| 574 | #define regSDMA0_RLC2_IB_SIZE_BASE_IDX 0 |
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| 575 | #define regSDMA0_RLC2_SKIP_CNTL 0x01f0 |
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| 576 | #define regSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 |
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| 577 | #define regSDMA0_RLC2_CONTEXT_STATUS 0x01f1 |
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| 578 | #define regSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 |
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| 579 | #define regSDMA0_RLC2_DOORBELL 0x01f2 |
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| 580 | #define regSDMA0_RLC2_DOORBELL_BASE_IDX 0 |
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| 581 | #define regSDMA0_RLC2_STATUS 0x0208 |
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| 582 | #define regSDMA0_RLC2_STATUS_BASE_IDX 0 |
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| 583 | #define regSDMA0_RLC2_DOORBELL_LOG 0x0209 |
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| 584 | #define regSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 |
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| 585 | #define regSDMA0_RLC2_WATERMARK 0x020a |
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| 586 | #define regSDMA0_RLC2_WATERMARK_BASE_IDX 0 |
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| 587 | #define regSDMA0_RLC2_DOORBELL_OFFSET 0x020b |
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| 588 | #define regSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 |
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| 589 | #define regSDMA0_RLC2_CSA_ADDR_LO 0x020c |
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| 590 | #define regSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 |
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| 591 | #define regSDMA0_RLC2_CSA_ADDR_HI 0x020d |
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| 592 | #define regSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 |
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| 593 | #define regSDMA0_RLC2_IB_SUB_REMAIN 0x020f |
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| 594 | #define regSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 |
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| 595 | #define regSDMA0_RLC2_PREEMPT 0x0210 |
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| 596 | #define regSDMA0_RLC2_PREEMPT_BASE_IDX 0 |
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| 597 | #define regSDMA0_RLC2_DUMMY_REG 0x0211 |
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| 598 | #define regSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 |
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| 599 | #define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 |
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| 600 | #define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
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| 601 | #define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 |
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| 602 | #define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
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| 603 | #define regSDMA0_RLC2_RB_AQL_CNTL 0x0214 |
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| 604 | #define regSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 |
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| 605 | #define regSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215 |
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| 606 | #define regSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 |
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| 607 | #define regSDMA0_RLC2_MIDCMD_DATA0 0x0220 |
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| 608 | #define regSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 |
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| 609 | #define regSDMA0_RLC2_MIDCMD_DATA1 0x0221 |
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| 610 | #define regSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 |
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| 611 | #define regSDMA0_RLC2_MIDCMD_DATA2 0x0222 |
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| 612 | #define regSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 |
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| 613 | #define regSDMA0_RLC2_MIDCMD_DATA3 0x0223 |
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| 614 | #define regSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 |
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| 615 | #define regSDMA0_RLC2_MIDCMD_DATA4 0x0224 |
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| 616 | #define regSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 |
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| 617 | #define regSDMA0_RLC2_MIDCMD_DATA5 0x0225 |
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| 618 | #define regSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 |
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| 619 | #define regSDMA0_RLC2_MIDCMD_DATA6 0x0226 |
|---|
| 620 | #define regSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 621 | #define regSDMA0_RLC2_MIDCMD_DATA7 0x0227 |
|---|
| 622 | #define regSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 623 | #define regSDMA0_RLC2_MIDCMD_DATA8 0x0228 |
|---|
| 624 | #define regSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 625 | #define regSDMA0_RLC2_MIDCMD_DATA9 0x0229 |
|---|
| 626 | #define regSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 627 | #define regSDMA0_RLC2_MIDCMD_DATA10 0x022a |
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| 628 | #define regSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX 0 |
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| 629 | #define regSDMA0_RLC2_MIDCMD_CNTL 0x022b |
|---|
| 630 | #define regSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 631 | #define regSDMA0_RLC3_RB_CNTL 0x0238 |
|---|
| 632 | #define regSDMA0_RLC3_RB_CNTL_BASE_IDX 0 |
|---|
| 633 | #define regSDMA0_RLC3_RB_BASE 0x0239 |
|---|
| 634 | #define regSDMA0_RLC3_RB_BASE_BASE_IDX 0 |
|---|
| 635 | #define regSDMA0_RLC3_RB_BASE_HI 0x023a |
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| 636 | #define regSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 |
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| 637 | #define regSDMA0_RLC3_RB_RPTR 0x023b |
|---|
| 638 | #define regSDMA0_RLC3_RB_RPTR_BASE_IDX 0 |
|---|
| 639 | #define regSDMA0_RLC3_RB_RPTR_HI 0x023c |
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| 640 | #define regSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 |
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| 641 | #define regSDMA0_RLC3_RB_WPTR 0x023d |
|---|
| 642 | #define regSDMA0_RLC3_RB_WPTR_BASE_IDX 0 |
|---|
| 643 | #define regSDMA0_RLC3_RB_WPTR_HI 0x023e |
|---|
| 644 | #define regSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 645 | #define regSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f |
|---|
| 646 | #define regSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 647 | #define regSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240 |
|---|
| 648 | #define regSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 649 | #define regSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241 |
|---|
| 650 | #define regSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 651 | #define regSDMA0_RLC3_IB_CNTL 0x0242 |
|---|
| 652 | #define regSDMA0_RLC3_IB_CNTL_BASE_IDX 0 |
|---|
| 653 | #define regSDMA0_RLC3_IB_RPTR 0x0243 |
|---|
| 654 | #define regSDMA0_RLC3_IB_RPTR_BASE_IDX 0 |
|---|
| 655 | #define regSDMA0_RLC3_IB_OFFSET 0x0244 |
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| 656 | #define regSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 |
|---|
| 657 | #define regSDMA0_RLC3_IB_BASE_LO 0x0245 |
|---|
| 658 | #define regSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 |
|---|
| 659 | #define regSDMA0_RLC3_IB_BASE_HI 0x0246 |
|---|
| 660 | #define regSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 |
|---|
| 661 | #define regSDMA0_RLC3_IB_SIZE 0x0247 |
|---|
| 662 | #define regSDMA0_RLC3_IB_SIZE_BASE_IDX 0 |
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| 663 | #define regSDMA0_RLC3_SKIP_CNTL 0x0248 |
|---|
| 664 | #define regSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 |
|---|
| 665 | #define regSDMA0_RLC3_CONTEXT_STATUS 0x0249 |
|---|
| 666 | #define regSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 667 | #define regSDMA0_RLC3_DOORBELL 0x024a |
|---|
| 668 | #define regSDMA0_RLC3_DOORBELL_BASE_IDX 0 |
|---|
| 669 | #define regSDMA0_RLC3_STATUS 0x0260 |
|---|
| 670 | #define regSDMA0_RLC3_STATUS_BASE_IDX 0 |
|---|
| 671 | #define regSDMA0_RLC3_DOORBELL_LOG 0x0261 |
|---|
| 672 | #define regSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 673 | #define regSDMA0_RLC3_WATERMARK 0x0262 |
|---|
| 674 | #define regSDMA0_RLC3_WATERMARK_BASE_IDX 0 |
|---|
| 675 | #define regSDMA0_RLC3_DOORBELL_OFFSET 0x0263 |
|---|
| 676 | #define regSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 677 | #define regSDMA0_RLC3_CSA_ADDR_LO 0x0264 |
|---|
| 678 | #define regSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 679 | #define regSDMA0_RLC3_CSA_ADDR_HI 0x0265 |
|---|
| 680 | #define regSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 681 | #define regSDMA0_RLC3_IB_SUB_REMAIN 0x0267 |
|---|
| 682 | #define regSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 683 | #define regSDMA0_RLC3_PREEMPT 0x0268 |
|---|
| 684 | #define regSDMA0_RLC3_PREEMPT_BASE_IDX 0 |
|---|
| 685 | #define regSDMA0_RLC3_DUMMY_REG 0x0269 |
|---|
| 686 | #define regSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 |
|---|
| 687 | #define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a |
|---|
| 688 | #define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 689 | #define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b |
|---|
| 690 | #define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 691 | #define regSDMA0_RLC3_RB_AQL_CNTL 0x026c |
|---|
| 692 | #define regSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 693 | #define regSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d |
|---|
| 694 | #define regSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 695 | #define regSDMA0_RLC3_MIDCMD_DATA0 0x0278 |
|---|
| 696 | #define regSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 697 | #define regSDMA0_RLC3_MIDCMD_DATA1 0x0279 |
|---|
| 698 | #define regSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 699 | #define regSDMA0_RLC3_MIDCMD_DATA2 0x027a |
|---|
| 700 | #define regSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 701 | #define regSDMA0_RLC3_MIDCMD_DATA3 0x027b |
|---|
| 702 | #define regSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 703 | #define regSDMA0_RLC3_MIDCMD_DATA4 0x027c |
|---|
| 704 | #define regSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 705 | #define regSDMA0_RLC3_MIDCMD_DATA5 0x027d |
|---|
| 706 | #define regSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 707 | #define regSDMA0_RLC3_MIDCMD_DATA6 0x027e |
|---|
| 708 | #define regSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 709 | #define regSDMA0_RLC3_MIDCMD_DATA7 0x027f |
|---|
| 710 | #define regSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 711 | #define regSDMA0_RLC3_MIDCMD_DATA8 0x0280 |
|---|
| 712 | #define regSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 713 | #define regSDMA0_RLC3_MIDCMD_DATA9 0x0281 |
|---|
| 714 | #define regSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 715 | #define regSDMA0_RLC3_MIDCMD_DATA10 0x0282 |
|---|
| 716 | #define regSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 717 | #define regSDMA0_RLC3_MIDCMD_CNTL 0x0283 |
|---|
| 718 | #define regSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 719 | #define regSDMA0_RLC4_RB_CNTL 0x0290 |
|---|
| 720 | #define regSDMA0_RLC4_RB_CNTL_BASE_IDX 0 |
|---|
| 721 | #define regSDMA0_RLC4_RB_BASE 0x0291 |
|---|
| 722 | #define regSDMA0_RLC4_RB_BASE_BASE_IDX 0 |
|---|
| 723 | #define regSDMA0_RLC4_RB_BASE_HI 0x0292 |
|---|
| 724 | #define regSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 |
|---|
| 725 | #define regSDMA0_RLC4_RB_RPTR 0x0293 |
|---|
| 726 | #define regSDMA0_RLC4_RB_RPTR_BASE_IDX 0 |
|---|
| 727 | #define regSDMA0_RLC4_RB_RPTR_HI 0x0294 |
|---|
| 728 | #define regSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 729 | #define regSDMA0_RLC4_RB_WPTR 0x0295 |
|---|
| 730 | #define regSDMA0_RLC4_RB_WPTR_BASE_IDX 0 |
|---|
| 731 | #define regSDMA0_RLC4_RB_WPTR_HI 0x0296 |
|---|
| 732 | #define regSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 733 | #define regSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 |
|---|
| 734 | #define regSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 735 | #define regSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298 |
|---|
| 736 | #define regSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 737 | #define regSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299 |
|---|
| 738 | #define regSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 739 | #define regSDMA0_RLC4_IB_CNTL 0x029a |
|---|
| 740 | #define regSDMA0_RLC4_IB_CNTL_BASE_IDX 0 |
|---|
| 741 | #define regSDMA0_RLC4_IB_RPTR 0x029b |
|---|
| 742 | #define regSDMA0_RLC4_IB_RPTR_BASE_IDX 0 |
|---|
| 743 | #define regSDMA0_RLC4_IB_OFFSET 0x029c |
|---|
| 744 | #define regSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 |
|---|
| 745 | #define regSDMA0_RLC4_IB_BASE_LO 0x029d |
|---|
| 746 | #define regSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 |
|---|
| 747 | #define regSDMA0_RLC4_IB_BASE_HI 0x029e |
|---|
| 748 | #define regSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 |
|---|
| 749 | #define regSDMA0_RLC4_IB_SIZE 0x029f |
|---|
| 750 | #define regSDMA0_RLC4_IB_SIZE_BASE_IDX 0 |
|---|
| 751 | #define regSDMA0_RLC4_SKIP_CNTL 0x02a0 |
|---|
| 752 | #define regSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 |
|---|
| 753 | #define regSDMA0_RLC4_CONTEXT_STATUS 0x02a1 |
|---|
| 754 | #define regSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 755 | #define regSDMA0_RLC4_DOORBELL 0x02a2 |
|---|
| 756 | #define regSDMA0_RLC4_DOORBELL_BASE_IDX 0 |
|---|
| 757 | #define regSDMA0_RLC4_STATUS 0x02b8 |
|---|
| 758 | #define regSDMA0_RLC4_STATUS_BASE_IDX 0 |
|---|
| 759 | #define regSDMA0_RLC4_DOORBELL_LOG 0x02b9 |
|---|
| 760 | #define regSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 761 | #define regSDMA0_RLC4_WATERMARK 0x02ba |
|---|
| 762 | #define regSDMA0_RLC4_WATERMARK_BASE_IDX 0 |
|---|
| 763 | #define regSDMA0_RLC4_DOORBELL_OFFSET 0x02bb |
|---|
| 764 | #define regSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 765 | #define regSDMA0_RLC4_CSA_ADDR_LO 0x02bc |
|---|
| 766 | #define regSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 767 | #define regSDMA0_RLC4_CSA_ADDR_HI 0x02bd |
|---|
| 768 | #define regSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 769 | #define regSDMA0_RLC4_IB_SUB_REMAIN 0x02bf |
|---|
| 770 | #define regSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 771 | #define regSDMA0_RLC4_PREEMPT 0x02c0 |
|---|
| 772 | #define regSDMA0_RLC4_PREEMPT_BASE_IDX 0 |
|---|
| 773 | #define regSDMA0_RLC4_DUMMY_REG 0x02c1 |
|---|
| 774 | #define regSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 |
|---|
| 775 | #define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 |
|---|
| 776 | #define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 777 | #define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 |
|---|
| 778 | #define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 779 | #define regSDMA0_RLC4_RB_AQL_CNTL 0x02c4 |
|---|
| 780 | #define regSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 781 | #define regSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5 |
|---|
| 782 | #define regSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 783 | #define regSDMA0_RLC4_MIDCMD_DATA0 0x02d0 |
|---|
| 784 | #define regSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 785 | #define regSDMA0_RLC4_MIDCMD_DATA1 0x02d1 |
|---|
| 786 | #define regSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 787 | #define regSDMA0_RLC4_MIDCMD_DATA2 0x02d2 |
|---|
| 788 | #define regSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 789 | #define regSDMA0_RLC4_MIDCMD_DATA3 0x02d3 |
|---|
| 790 | #define regSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 791 | #define regSDMA0_RLC4_MIDCMD_DATA4 0x02d4 |
|---|
| 792 | #define regSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 793 | #define regSDMA0_RLC4_MIDCMD_DATA5 0x02d5 |
|---|
| 794 | #define regSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 795 | #define regSDMA0_RLC4_MIDCMD_DATA6 0x02d6 |
|---|
| 796 | #define regSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 797 | #define regSDMA0_RLC4_MIDCMD_DATA7 0x02d7 |
|---|
| 798 | #define regSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 799 | #define regSDMA0_RLC4_MIDCMD_DATA8 0x02d8 |
|---|
| 800 | #define regSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 801 | #define regSDMA0_RLC4_MIDCMD_DATA9 0x02d9 |
|---|
| 802 | #define regSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 803 | #define regSDMA0_RLC4_MIDCMD_DATA10 0x02da |
|---|
| 804 | #define regSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 805 | #define regSDMA0_RLC4_MIDCMD_CNTL 0x02db |
|---|
| 806 | #define regSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 807 | #define regSDMA0_RLC5_RB_CNTL 0x02e8 |
|---|
| 808 | #define regSDMA0_RLC5_RB_CNTL_BASE_IDX 0 |
|---|
| 809 | #define regSDMA0_RLC5_RB_BASE 0x02e9 |
|---|
| 810 | #define regSDMA0_RLC5_RB_BASE_BASE_IDX 0 |
|---|
| 811 | #define regSDMA0_RLC5_RB_BASE_HI 0x02ea |
|---|
| 812 | #define regSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 |
|---|
| 813 | #define regSDMA0_RLC5_RB_RPTR 0x02eb |
|---|
| 814 | #define regSDMA0_RLC5_RB_RPTR_BASE_IDX 0 |
|---|
| 815 | #define regSDMA0_RLC5_RB_RPTR_HI 0x02ec |
|---|
| 816 | #define regSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 817 | #define regSDMA0_RLC5_RB_WPTR 0x02ed |
|---|
| 818 | #define regSDMA0_RLC5_RB_WPTR_BASE_IDX 0 |
|---|
| 819 | #define regSDMA0_RLC5_RB_WPTR_HI 0x02ee |
|---|
| 820 | #define regSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 821 | #define regSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef |
|---|
| 822 | #define regSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 823 | #define regSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0 |
|---|
| 824 | #define regSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 825 | #define regSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1 |
|---|
| 826 | #define regSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 827 | #define regSDMA0_RLC5_IB_CNTL 0x02f2 |
|---|
| 828 | #define regSDMA0_RLC5_IB_CNTL_BASE_IDX 0 |
|---|
| 829 | #define regSDMA0_RLC5_IB_RPTR 0x02f3 |
|---|
| 830 | #define regSDMA0_RLC5_IB_RPTR_BASE_IDX 0 |
|---|
| 831 | #define regSDMA0_RLC5_IB_OFFSET 0x02f4 |
|---|
| 832 | #define regSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 |
|---|
| 833 | #define regSDMA0_RLC5_IB_BASE_LO 0x02f5 |
|---|
| 834 | #define regSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 |
|---|
| 835 | #define regSDMA0_RLC5_IB_BASE_HI 0x02f6 |
|---|
| 836 | #define regSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 |
|---|
| 837 | #define regSDMA0_RLC5_IB_SIZE 0x02f7 |
|---|
| 838 | #define regSDMA0_RLC5_IB_SIZE_BASE_IDX 0 |
|---|
| 839 | #define regSDMA0_RLC5_SKIP_CNTL 0x02f8 |
|---|
| 840 | #define regSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 |
|---|
| 841 | #define regSDMA0_RLC5_CONTEXT_STATUS 0x02f9 |
|---|
| 842 | #define regSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 843 | #define regSDMA0_RLC5_DOORBELL 0x02fa |
|---|
| 844 | #define regSDMA0_RLC5_DOORBELL_BASE_IDX 0 |
|---|
| 845 | #define regSDMA0_RLC5_STATUS 0x0310 |
|---|
| 846 | #define regSDMA0_RLC5_STATUS_BASE_IDX 0 |
|---|
| 847 | #define regSDMA0_RLC5_DOORBELL_LOG 0x0311 |
|---|
| 848 | #define regSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 849 | #define regSDMA0_RLC5_WATERMARK 0x0312 |
|---|
| 850 | #define regSDMA0_RLC5_WATERMARK_BASE_IDX 0 |
|---|
| 851 | #define regSDMA0_RLC5_DOORBELL_OFFSET 0x0313 |
|---|
| 852 | #define regSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 853 | #define regSDMA0_RLC5_CSA_ADDR_LO 0x0314 |
|---|
| 854 | #define regSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 855 | #define regSDMA0_RLC5_CSA_ADDR_HI 0x0315 |
|---|
| 856 | #define regSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 857 | #define regSDMA0_RLC5_IB_SUB_REMAIN 0x0317 |
|---|
| 858 | #define regSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 859 | #define regSDMA0_RLC5_PREEMPT 0x0318 |
|---|
| 860 | #define regSDMA0_RLC5_PREEMPT_BASE_IDX 0 |
|---|
| 861 | #define regSDMA0_RLC5_DUMMY_REG 0x0319 |
|---|
| 862 | #define regSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 |
|---|
| 863 | #define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a |
|---|
| 864 | #define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 865 | #define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b |
|---|
| 866 | #define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 867 | #define regSDMA0_RLC5_RB_AQL_CNTL 0x031c |
|---|
| 868 | #define regSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 869 | #define regSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d |
|---|
| 870 | #define regSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 871 | #define regSDMA0_RLC5_MIDCMD_DATA0 0x0328 |
|---|
| 872 | #define regSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 873 | #define regSDMA0_RLC5_MIDCMD_DATA1 0x0329 |
|---|
| 874 | #define regSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 875 | #define regSDMA0_RLC5_MIDCMD_DATA2 0x032a |
|---|
| 876 | #define regSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 877 | #define regSDMA0_RLC5_MIDCMD_DATA3 0x032b |
|---|
| 878 | #define regSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 879 | #define regSDMA0_RLC5_MIDCMD_DATA4 0x032c |
|---|
| 880 | #define regSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 881 | #define regSDMA0_RLC5_MIDCMD_DATA5 0x032d |
|---|
| 882 | #define regSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 883 | #define regSDMA0_RLC5_MIDCMD_DATA6 0x032e |
|---|
| 884 | #define regSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 885 | #define regSDMA0_RLC5_MIDCMD_DATA7 0x032f |
|---|
| 886 | #define regSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 887 | #define regSDMA0_RLC5_MIDCMD_DATA8 0x0330 |
|---|
| 888 | #define regSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 889 | #define regSDMA0_RLC5_MIDCMD_DATA9 0x0331 |
|---|
| 890 | #define regSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 891 | #define regSDMA0_RLC5_MIDCMD_DATA10 0x0332 |
|---|
| 892 | #define regSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 893 | #define regSDMA0_RLC5_MIDCMD_CNTL 0x0333 |
|---|
| 894 | #define regSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 895 | #define regSDMA0_RLC6_RB_CNTL 0x0340 |
|---|
| 896 | #define regSDMA0_RLC6_RB_CNTL_BASE_IDX 0 |
|---|
| 897 | #define regSDMA0_RLC6_RB_BASE 0x0341 |
|---|
| 898 | #define regSDMA0_RLC6_RB_BASE_BASE_IDX 0 |
|---|
| 899 | #define regSDMA0_RLC6_RB_BASE_HI 0x0342 |
|---|
| 900 | #define regSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 |
|---|
| 901 | #define regSDMA0_RLC6_RB_RPTR 0x0343 |
|---|
| 902 | #define regSDMA0_RLC6_RB_RPTR_BASE_IDX 0 |
|---|
| 903 | #define regSDMA0_RLC6_RB_RPTR_HI 0x0344 |
|---|
| 904 | #define regSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 905 | #define regSDMA0_RLC6_RB_WPTR 0x0345 |
|---|
| 906 | #define regSDMA0_RLC6_RB_WPTR_BASE_IDX 0 |
|---|
| 907 | #define regSDMA0_RLC6_RB_WPTR_HI 0x0346 |
|---|
| 908 | #define regSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 909 | #define regSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347 |
|---|
| 910 | #define regSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 911 | #define regSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348 |
|---|
| 912 | #define regSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 913 | #define regSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349 |
|---|
| 914 | #define regSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 915 | #define regSDMA0_RLC6_IB_CNTL 0x034a |
|---|
| 916 | #define regSDMA0_RLC6_IB_CNTL_BASE_IDX 0 |
|---|
| 917 | #define regSDMA0_RLC6_IB_RPTR 0x034b |
|---|
| 918 | #define regSDMA0_RLC6_IB_RPTR_BASE_IDX 0 |
|---|
| 919 | #define regSDMA0_RLC6_IB_OFFSET 0x034c |
|---|
| 920 | #define regSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 |
|---|
| 921 | #define regSDMA0_RLC6_IB_BASE_LO 0x034d |
|---|
| 922 | #define regSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 |
|---|
| 923 | #define regSDMA0_RLC6_IB_BASE_HI 0x034e |
|---|
| 924 | #define regSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 |
|---|
| 925 | #define regSDMA0_RLC6_IB_SIZE 0x034f |
|---|
| 926 | #define regSDMA0_RLC6_IB_SIZE_BASE_IDX 0 |
|---|
| 927 | #define regSDMA0_RLC6_SKIP_CNTL 0x0350 |
|---|
| 928 | #define regSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 |
|---|
| 929 | #define regSDMA0_RLC6_CONTEXT_STATUS 0x0351 |
|---|
| 930 | #define regSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 931 | #define regSDMA0_RLC6_DOORBELL 0x0352 |
|---|
| 932 | #define regSDMA0_RLC6_DOORBELL_BASE_IDX 0 |
|---|
| 933 | #define regSDMA0_RLC6_STATUS 0x0368 |
|---|
| 934 | #define regSDMA0_RLC6_STATUS_BASE_IDX 0 |
|---|
| 935 | #define regSDMA0_RLC6_DOORBELL_LOG 0x0369 |
|---|
| 936 | #define regSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 937 | #define regSDMA0_RLC6_WATERMARK 0x036a |
|---|
| 938 | #define regSDMA0_RLC6_WATERMARK_BASE_IDX 0 |
|---|
| 939 | #define regSDMA0_RLC6_DOORBELL_OFFSET 0x036b |
|---|
| 940 | #define regSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 941 | #define regSDMA0_RLC6_CSA_ADDR_LO 0x036c |
|---|
| 942 | #define regSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 943 | #define regSDMA0_RLC6_CSA_ADDR_HI 0x036d |
|---|
| 944 | #define regSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 945 | #define regSDMA0_RLC6_IB_SUB_REMAIN 0x036f |
|---|
| 946 | #define regSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 947 | #define regSDMA0_RLC6_PREEMPT 0x0370 |
|---|
| 948 | #define regSDMA0_RLC6_PREEMPT_BASE_IDX 0 |
|---|
| 949 | #define regSDMA0_RLC6_DUMMY_REG 0x0371 |
|---|
| 950 | #define regSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 |
|---|
| 951 | #define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 |
|---|
| 952 | #define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 953 | #define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 |
|---|
| 954 | #define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 955 | #define regSDMA0_RLC6_RB_AQL_CNTL 0x0374 |
|---|
| 956 | #define regSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 957 | #define regSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375 |
|---|
| 958 | #define regSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 959 | #define regSDMA0_RLC6_MIDCMD_DATA0 0x0380 |
|---|
| 960 | #define regSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 961 | #define regSDMA0_RLC6_MIDCMD_DATA1 0x0381 |
|---|
| 962 | #define regSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 963 | #define regSDMA0_RLC6_MIDCMD_DATA2 0x0382 |
|---|
| 964 | #define regSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 965 | #define regSDMA0_RLC6_MIDCMD_DATA3 0x0383 |
|---|
| 966 | #define regSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 967 | #define regSDMA0_RLC6_MIDCMD_DATA4 0x0384 |
|---|
| 968 | #define regSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 969 | #define regSDMA0_RLC6_MIDCMD_DATA5 0x0385 |
|---|
| 970 | #define regSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 971 | #define regSDMA0_RLC6_MIDCMD_DATA6 0x0386 |
|---|
| 972 | #define regSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 973 | #define regSDMA0_RLC6_MIDCMD_DATA7 0x0387 |
|---|
| 974 | #define regSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 975 | #define regSDMA0_RLC6_MIDCMD_DATA8 0x0388 |
|---|
| 976 | #define regSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 977 | #define regSDMA0_RLC6_MIDCMD_DATA9 0x0389 |
|---|
| 978 | #define regSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 979 | #define regSDMA0_RLC6_MIDCMD_DATA10 0x038a |
|---|
| 980 | #define regSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 981 | #define regSDMA0_RLC6_MIDCMD_CNTL 0x038b |
|---|
| 982 | #define regSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 983 | #define regSDMA0_RLC7_RB_CNTL 0x0398 |
|---|
| 984 | #define regSDMA0_RLC7_RB_CNTL_BASE_IDX 0 |
|---|
| 985 | #define regSDMA0_RLC7_RB_BASE 0x0399 |
|---|
| 986 | #define regSDMA0_RLC7_RB_BASE_BASE_IDX 0 |
|---|
| 987 | #define regSDMA0_RLC7_RB_BASE_HI 0x039a |
|---|
| 988 | #define regSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 |
|---|
| 989 | #define regSDMA0_RLC7_RB_RPTR 0x039b |
|---|
| 990 | #define regSDMA0_RLC7_RB_RPTR_BASE_IDX 0 |
|---|
| 991 | #define regSDMA0_RLC7_RB_RPTR_HI 0x039c |
|---|
| 992 | #define regSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 993 | #define regSDMA0_RLC7_RB_WPTR 0x039d |
|---|
| 994 | #define regSDMA0_RLC7_RB_WPTR_BASE_IDX 0 |
|---|
| 995 | #define regSDMA0_RLC7_RB_WPTR_HI 0x039e |
|---|
| 996 | #define regSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 997 | #define regSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f |
|---|
| 998 | #define regSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 999 | #define regSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0 |
|---|
| 1000 | #define regSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1001 | #define regSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1 |
|---|
| 1002 | #define regSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1003 | #define regSDMA0_RLC7_IB_CNTL 0x03a2 |
|---|
| 1004 | #define regSDMA0_RLC7_IB_CNTL_BASE_IDX 0 |
|---|
| 1005 | #define regSDMA0_RLC7_IB_RPTR 0x03a3 |
|---|
| 1006 | #define regSDMA0_RLC7_IB_RPTR_BASE_IDX 0 |
|---|
| 1007 | #define regSDMA0_RLC7_IB_OFFSET 0x03a4 |
|---|
| 1008 | #define regSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 |
|---|
| 1009 | #define regSDMA0_RLC7_IB_BASE_LO 0x03a5 |
|---|
| 1010 | #define regSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1011 | #define regSDMA0_RLC7_IB_BASE_HI 0x03a6 |
|---|
| 1012 | #define regSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1013 | #define regSDMA0_RLC7_IB_SIZE 0x03a7 |
|---|
| 1014 | #define regSDMA0_RLC7_IB_SIZE_BASE_IDX 0 |
|---|
| 1015 | #define regSDMA0_RLC7_SKIP_CNTL 0x03a8 |
|---|
| 1016 | #define regSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1017 | #define regSDMA0_RLC7_CONTEXT_STATUS 0x03a9 |
|---|
| 1018 | #define regSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1019 | #define regSDMA0_RLC7_DOORBELL 0x03aa |
|---|
| 1020 | #define regSDMA0_RLC7_DOORBELL_BASE_IDX 0 |
|---|
| 1021 | #define regSDMA0_RLC7_STATUS 0x03c0 |
|---|
| 1022 | #define regSDMA0_RLC7_STATUS_BASE_IDX 0 |
|---|
| 1023 | #define regSDMA0_RLC7_DOORBELL_LOG 0x03c1 |
|---|
| 1024 | #define regSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1025 | #define regSDMA0_RLC7_WATERMARK 0x03c2 |
|---|
| 1026 | #define regSDMA0_RLC7_WATERMARK_BASE_IDX 0 |
|---|
| 1027 | #define regSDMA0_RLC7_DOORBELL_OFFSET 0x03c3 |
|---|
| 1028 | #define regSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1029 | #define regSDMA0_RLC7_CSA_ADDR_LO 0x03c4 |
|---|
| 1030 | #define regSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1031 | #define regSDMA0_RLC7_CSA_ADDR_HI 0x03c5 |
|---|
| 1032 | #define regSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1033 | #define regSDMA0_RLC7_IB_SUB_REMAIN 0x03c7 |
|---|
| 1034 | #define regSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1035 | #define regSDMA0_RLC7_PREEMPT 0x03c8 |
|---|
| 1036 | #define regSDMA0_RLC7_PREEMPT_BASE_IDX 0 |
|---|
| 1037 | #define regSDMA0_RLC7_DUMMY_REG 0x03c9 |
|---|
| 1038 | #define regSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 |
|---|
| 1039 | #define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca |
|---|
| 1040 | #define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1041 | #define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb |
|---|
| 1042 | #define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1043 | #define regSDMA0_RLC7_RB_AQL_CNTL 0x03cc |
|---|
| 1044 | #define regSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1045 | #define regSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd |
|---|
| 1046 | #define regSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1047 | #define regSDMA0_RLC7_MIDCMD_DATA0 0x03d8 |
|---|
| 1048 | #define regSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1049 | #define regSDMA0_RLC7_MIDCMD_DATA1 0x03d9 |
|---|
| 1050 | #define regSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1051 | #define regSDMA0_RLC7_MIDCMD_DATA2 0x03da |
|---|
| 1052 | #define regSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1053 | #define regSDMA0_RLC7_MIDCMD_DATA3 0x03db |
|---|
| 1054 | #define regSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1055 | #define regSDMA0_RLC7_MIDCMD_DATA4 0x03dc |
|---|
| 1056 | #define regSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1057 | #define regSDMA0_RLC7_MIDCMD_DATA5 0x03dd |
|---|
| 1058 | #define regSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1059 | #define regSDMA0_RLC7_MIDCMD_DATA6 0x03de |
|---|
| 1060 | #define regSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1061 | #define regSDMA0_RLC7_MIDCMD_DATA7 0x03df |
|---|
| 1062 | #define regSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1063 | #define regSDMA0_RLC7_MIDCMD_DATA8 0x03e0 |
|---|
| 1064 | #define regSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1065 | #define regSDMA0_RLC7_MIDCMD_DATA9 0x03e1 |
|---|
| 1066 | #define regSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1067 | #define regSDMA0_RLC7_MIDCMD_DATA10 0x03e2 |
|---|
| 1068 | #define regSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1069 | #define regSDMA0_RLC7_MIDCMD_CNTL 0x03e3 |
|---|
| 1070 | #define regSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1071 | |
|---|
| 1072 | |
|---|
| 1073 | // addressBlock: sdma0_sdma1dec |
|---|
| 1074 | // base address: 0x6180 |
|---|
| 1075 | #define regSDMA1_UCODE_ADDR 0x0600 |
|---|
| 1076 | #define regSDMA1_UCODE_ADDR_BASE_IDX 0 |
|---|
| 1077 | #define regSDMA1_UCODE_DATA 0x0601 |
|---|
| 1078 | #define regSDMA1_UCODE_DATA_BASE_IDX 0 |
|---|
| 1079 | #define regSDMA1_VF_ENABLE 0x060a |
|---|
| 1080 | #define regSDMA1_VF_ENABLE_BASE_IDX 0 |
|---|
| 1081 | #define regSDMA1_CONTEXT_GROUP_BOUNDARY 0x0619 |
|---|
| 1082 | #define regSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
|---|
| 1083 | #define regSDMA1_POWER_CNTL 0x061a |
|---|
| 1084 | #define regSDMA1_POWER_CNTL_BASE_IDX 0 |
|---|
| 1085 | #define regSDMA1_CLK_CTRL 0x061b |
|---|
| 1086 | #define regSDMA1_CLK_CTRL_BASE_IDX 0 |
|---|
| 1087 | #define regSDMA1_CNTL 0x061c |
|---|
| 1088 | #define regSDMA1_CNTL_BASE_IDX 0 |
|---|
| 1089 | #define regSDMA1_CHICKEN_BITS 0x061d |
|---|
| 1090 | #define regSDMA1_CHICKEN_BITS_BASE_IDX 0 |
|---|
| 1091 | #define regSDMA1_GB_ADDR_CONFIG 0x061e |
|---|
| 1092 | #define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 |
|---|
| 1093 | #define regSDMA1_GB_ADDR_CONFIG_READ 0x061f |
|---|
| 1094 | #define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
|---|
| 1095 | #define regSDMA1_RB_RPTR_FETCH_HI 0x0620 |
|---|
| 1096 | #define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 |
|---|
| 1097 | #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0621 |
|---|
| 1098 | #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
|---|
| 1099 | #define regSDMA1_RB_RPTR_FETCH 0x0622 |
|---|
| 1100 | #define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0 |
|---|
| 1101 | #define regSDMA1_IB_OFFSET_FETCH 0x0623 |
|---|
| 1102 | #define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 |
|---|
| 1103 | #define regSDMA1_PROGRAM 0x0624 |
|---|
| 1104 | #define regSDMA1_PROGRAM_BASE_IDX 0 |
|---|
| 1105 | #define regSDMA1_STATUS_REG 0x0625 |
|---|
| 1106 | #define regSDMA1_STATUS_REG_BASE_IDX 0 |
|---|
| 1107 | #define regSDMA1_STATUS1_REG 0x0626 |
|---|
| 1108 | #define regSDMA1_STATUS1_REG_BASE_IDX 0 |
|---|
| 1109 | #define regSDMA1_RD_BURST_CNTL 0x0627 |
|---|
| 1110 | #define regSDMA1_RD_BURST_CNTL_BASE_IDX 0 |
|---|
| 1111 | #define regSDMA1_HBM_PAGE_CONFIG 0x0628 |
|---|
| 1112 | #define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 |
|---|
| 1113 | #define regSDMA1_UCODE_CHECKSUM 0x0629 |
|---|
| 1114 | #define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0 |
|---|
| 1115 | #define regSDMA1_F32_CNTL 0x062a |
|---|
| 1116 | #define regSDMA1_F32_CNTL_BASE_IDX 0 |
|---|
| 1117 | #define regSDMA1_FREEZE 0x062b |
|---|
| 1118 | #define regSDMA1_FREEZE_BASE_IDX 0 |
|---|
| 1119 | #define regSDMA1_PHASE0_QUANTUM 0x062c |
|---|
| 1120 | #define regSDMA1_PHASE0_QUANTUM_BASE_IDX 0 |
|---|
| 1121 | #define regSDMA1_PHASE1_QUANTUM 0x062d |
|---|
| 1122 | #define regSDMA1_PHASE1_QUANTUM_BASE_IDX 0 |
|---|
| 1123 | #define regCC_SDMA1_EDC_CONFIG 0x0632 |
|---|
| 1124 | #define regCC_SDMA1_EDC_CONFIG_BASE_IDX 0 |
|---|
| 1125 | #define regSDMA1_BA_THRESHOLD 0x0633 |
|---|
| 1126 | #define regSDMA1_BA_THRESHOLD_BASE_IDX 0 |
|---|
| 1127 | #define regSDMA1_ID 0x0634 |
|---|
| 1128 | #define regSDMA1_ID_BASE_IDX 0 |
|---|
| 1129 | #define regSDMA1_VERSION 0x0635 |
|---|
| 1130 | #define regSDMA1_VERSION_BASE_IDX 0 |
|---|
| 1131 | #define regSDMA1_EDC_COUNTER 0x0636 |
|---|
| 1132 | #define regSDMA1_EDC_COUNTER_BASE_IDX 0 |
|---|
| 1133 | #define regSDMA1_EDC_COUNTER2 0x0637 |
|---|
| 1134 | #define regSDMA1_EDC_COUNTER2_BASE_IDX 0 |
|---|
| 1135 | #define regSDMA1_STATUS2_REG 0x0638 |
|---|
| 1136 | #define regSDMA1_STATUS2_REG_BASE_IDX 0 |
|---|
| 1137 | #define regSDMA1_ATOMIC_CNTL 0x0639 |
|---|
| 1138 | #define regSDMA1_ATOMIC_CNTL_BASE_IDX 0 |
|---|
| 1139 | #define regSDMA1_ATOMIC_PREOP_LO 0x063a |
|---|
| 1140 | #define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 |
|---|
| 1141 | #define regSDMA1_ATOMIC_PREOP_HI 0x063b |
|---|
| 1142 | #define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 |
|---|
| 1143 | #define regSDMA1_UTCL1_CNTL 0x063c |
|---|
| 1144 | #define regSDMA1_UTCL1_CNTL_BASE_IDX 0 |
|---|
| 1145 | #define regSDMA1_UTCL1_WATERMK 0x063d |
|---|
| 1146 | #define regSDMA1_UTCL1_WATERMK_BASE_IDX 0 |
|---|
| 1147 | #define regSDMA1_UTCL1_RD_STATUS 0x063e |
|---|
| 1148 | #define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 |
|---|
| 1149 | #define regSDMA1_UTCL1_WR_STATUS 0x063f |
|---|
| 1150 | #define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 |
|---|
| 1151 | #define regSDMA1_UTCL1_INV0 0x0640 |
|---|
| 1152 | #define regSDMA1_UTCL1_INV0_BASE_IDX 0 |
|---|
| 1153 | #define regSDMA1_UTCL1_INV1 0x0641 |
|---|
| 1154 | #define regSDMA1_UTCL1_INV1_BASE_IDX 0 |
|---|
| 1155 | #define regSDMA1_UTCL1_INV2 0x0642 |
|---|
| 1156 | #define regSDMA1_UTCL1_INV2_BASE_IDX 0 |
|---|
| 1157 | #define regSDMA1_UTCL1_RD_XNACK0 0x0643 |
|---|
| 1158 | #define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 |
|---|
| 1159 | #define regSDMA1_UTCL1_RD_XNACK1 0x0644 |
|---|
| 1160 | #define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 |
|---|
| 1161 | #define regSDMA1_UTCL1_WR_XNACK0 0x0645 |
|---|
| 1162 | #define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 |
|---|
| 1163 | #define regSDMA1_UTCL1_WR_XNACK1 0x0646 |
|---|
| 1164 | #define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 |
|---|
| 1165 | #define regSDMA1_UTCL1_TIMEOUT 0x0647 |
|---|
| 1166 | #define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 |
|---|
| 1167 | #define regSDMA1_UTCL1_PAGE 0x0648 |
|---|
| 1168 | #define regSDMA1_UTCL1_PAGE_BASE_IDX 0 |
|---|
| 1169 | #define regSDMA1_POWER_CNTL_IDLE 0x0649 |
|---|
| 1170 | #define regSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 |
|---|
| 1171 | #define regSDMA1_RELAX_ORDERING_LUT 0x064a |
|---|
| 1172 | #define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 |
|---|
| 1173 | #define regSDMA1_CHICKEN_BITS_2 0x064b |
|---|
| 1174 | #define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0 |
|---|
| 1175 | #define regSDMA1_STATUS3_REG 0x064c |
|---|
| 1176 | #define regSDMA1_STATUS3_REG_BASE_IDX 0 |
|---|
| 1177 | #define regSDMA1_PHYSICAL_ADDR_LO 0x064d |
|---|
| 1178 | #define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 |
|---|
| 1179 | #define regSDMA1_PHYSICAL_ADDR_HI 0x064e |
|---|
| 1180 | #define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 |
|---|
| 1181 | #define regSDMA1_PHASE2_QUANTUM 0x064f |
|---|
| 1182 | #define regSDMA1_PHASE2_QUANTUM_BASE_IDX 0 |
|---|
| 1183 | #define regSDMA1_ERROR_LOG 0x0650 |
|---|
| 1184 | #define regSDMA1_ERROR_LOG_BASE_IDX 0 |
|---|
| 1185 | #define regSDMA1_PUB_DUMMY_REG0 0x0651 |
|---|
| 1186 | #define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 |
|---|
| 1187 | #define regSDMA1_PUB_DUMMY_REG1 0x0652 |
|---|
| 1188 | #define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 |
|---|
| 1189 | #define regSDMA1_PUB_DUMMY_REG2 0x0653 |
|---|
| 1190 | #define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 |
|---|
| 1191 | #define regSDMA1_PUB_DUMMY_REG3 0x0654 |
|---|
| 1192 | #define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 |
|---|
| 1193 | #define regSDMA1_F32_COUNTER 0x0655 |
|---|
| 1194 | #define regSDMA1_F32_COUNTER_BASE_IDX 0 |
|---|
| 1195 | #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x0657 |
|---|
| 1196 | #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 |
|---|
| 1197 | #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x0658 |
|---|
| 1198 | #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 |
|---|
| 1199 | #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0659 |
|---|
| 1200 | #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
|---|
| 1201 | #define regSDMA1_PERFCNT_MISC_CNTL 0x065a |
|---|
| 1202 | #define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 0 |
|---|
| 1203 | #define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x065b |
|---|
| 1204 | #define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 |
|---|
| 1205 | #define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x065c |
|---|
| 1206 | #define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 |
|---|
| 1207 | #define regSDMA1_CRD_CNTL 0x065d |
|---|
| 1208 | #define regSDMA1_CRD_CNTL_BASE_IDX 0 |
|---|
| 1209 | #define regSDMA1_ULV_CNTL 0x065f |
|---|
| 1210 | #define regSDMA1_ULV_CNTL_BASE_IDX 0 |
|---|
| 1211 | #define regSDMA1_EA_DBIT_ADDR_DATA 0x0660 |
|---|
| 1212 | #define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
|---|
| 1213 | #define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661 |
|---|
| 1214 | #define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
|---|
| 1215 | #define regSDMA1_STATUS4_REG 0x0663 |
|---|
| 1216 | #define regSDMA1_STATUS4_REG_BASE_IDX 0 |
|---|
| 1217 | #define regSDMA1_SCRATCH_RAM_DATA 0x0664 |
|---|
| 1218 | #define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 |
|---|
| 1219 | #define regSDMA1_SCRATCH_RAM_ADDR 0x0665 |
|---|
| 1220 | #define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 |
|---|
| 1221 | #define regSDMA1_CE_CTRL 0x0666 |
|---|
| 1222 | #define regSDMA1_CE_CTRL_BASE_IDX 0 |
|---|
| 1223 | #define regSDMA1_RAS_STATUS 0x0667 |
|---|
| 1224 | #define regSDMA1_RAS_STATUS_BASE_IDX 0 |
|---|
| 1225 | #define regSDMA1_CLK_STATUS 0x0668 |
|---|
| 1226 | #define regSDMA1_CLK_STATUS_BASE_IDX 0 |
|---|
| 1227 | #define regSDMA1_GFX_RB_CNTL 0x0680 |
|---|
| 1228 | #define regSDMA1_GFX_RB_CNTL_BASE_IDX 0 |
|---|
| 1229 | #define regSDMA1_GFX_RB_BASE 0x0681 |
|---|
| 1230 | #define regSDMA1_GFX_RB_BASE_BASE_IDX 0 |
|---|
| 1231 | #define regSDMA1_GFX_RB_BASE_HI 0x0682 |
|---|
| 1232 | #define regSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1233 | #define regSDMA1_GFX_RB_RPTR 0x0683 |
|---|
| 1234 | #define regSDMA1_GFX_RB_RPTR_BASE_IDX 0 |
|---|
| 1235 | #define regSDMA1_GFX_RB_RPTR_HI 0x0684 |
|---|
| 1236 | #define regSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1237 | #define regSDMA1_GFX_RB_WPTR 0x0685 |
|---|
| 1238 | #define regSDMA1_GFX_RB_WPTR_BASE_IDX 0 |
|---|
| 1239 | #define regSDMA1_GFX_RB_WPTR_HI 0x0686 |
|---|
| 1240 | #define regSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1241 | #define regSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687 |
|---|
| 1242 | #define regSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1243 | #define regSDMA1_GFX_RB_RPTR_ADDR_HI 0x0688 |
|---|
| 1244 | #define regSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1245 | #define regSDMA1_GFX_RB_RPTR_ADDR_LO 0x0689 |
|---|
| 1246 | #define regSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1247 | #define regSDMA1_GFX_IB_CNTL 0x068a |
|---|
| 1248 | #define regSDMA1_GFX_IB_CNTL_BASE_IDX 0 |
|---|
| 1249 | #define regSDMA1_GFX_IB_RPTR 0x068b |
|---|
| 1250 | #define regSDMA1_GFX_IB_RPTR_BASE_IDX 0 |
|---|
| 1251 | #define regSDMA1_GFX_IB_OFFSET 0x068c |
|---|
| 1252 | #define regSDMA1_GFX_IB_OFFSET_BASE_IDX 0 |
|---|
| 1253 | #define regSDMA1_GFX_IB_BASE_LO 0x068d |
|---|
| 1254 | #define regSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1255 | #define regSDMA1_GFX_IB_BASE_HI 0x068e |
|---|
| 1256 | #define regSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1257 | #define regSDMA1_GFX_IB_SIZE 0x068f |
|---|
| 1258 | #define regSDMA1_GFX_IB_SIZE_BASE_IDX 0 |
|---|
| 1259 | #define regSDMA1_GFX_SKIP_CNTL 0x0690 |
|---|
| 1260 | #define regSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1261 | #define regSDMA1_GFX_CONTEXT_STATUS 0x0691 |
|---|
| 1262 | #define regSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1263 | #define regSDMA1_GFX_DOORBELL 0x0692 |
|---|
| 1264 | #define regSDMA1_GFX_DOORBELL_BASE_IDX 0 |
|---|
| 1265 | #define regSDMA1_GFX_CONTEXT_CNTL 0x0693 |
|---|
| 1266 | #define regSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 |
|---|
| 1267 | #define regSDMA1_GFX_STATUS 0x06a8 |
|---|
| 1268 | #define regSDMA1_GFX_STATUS_BASE_IDX 0 |
|---|
| 1269 | #define regSDMA1_GFX_DOORBELL_LOG 0x06a9 |
|---|
| 1270 | #define regSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1271 | #define regSDMA1_GFX_WATERMARK 0x06aa |
|---|
| 1272 | #define regSDMA1_GFX_WATERMARK_BASE_IDX 0 |
|---|
| 1273 | #define regSDMA1_GFX_DOORBELL_OFFSET 0x06ab |
|---|
| 1274 | #define regSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1275 | #define regSDMA1_GFX_CSA_ADDR_LO 0x06ac |
|---|
| 1276 | #define regSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1277 | #define regSDMA1_GFX_CSA_ADDR_HI 0x06ad |
|---|
| 1278 | #define regSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1279 | #define regSDMA1_GFX_IB_SUB_REMAIN 0x06af |
|---|
| 1280 | #define regSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1281 | #define regSDMA1_GFX_PREEMPT 0x06b0 |
|---|
| 1282 | #define regSDMA1_GFX_PREEMPT_BASE_IDX 0 |
|---|
| 1283 | #define regSDMA1_GFX_DUMMY_REG 0x06b1 |
|---|
| 1284 | #define regSDMA1_GFX_DUMMY_REG_BASE_IDX 0 |
|---|
| 1285 | #define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x06b2 |
|---|
| 1286 | #define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1287 | #define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x06b3 |
|---|
| 1288 | #define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1289 | #define regSDMA1_GFX_RB_AQL_CNTL 0x06b4 |
|---|
| 1290 | #define regSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1291 | #define regSDMA1_GFX_MINOR_PTR_UPDATE 0x06b5 |
|---|
| 1292 | #define regSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1293 | #define regSDMA1_GFX_MIDCMD_DATA0 0x06c0 |
|---|
| 1294 | #define regSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1295 | #define regSDMA1_GFX_MIDCMD_DATA1 0x06c1 |
|---|
| 1296 | #define regSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1297 | #define regSDMA1_GFX_MIDCMD_DATA2 0x06c2 |
|---|
| 1298 | #define regSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1299 | #define regSDMA1_GFX_MIDCMD_DATA3 0x06c3 |
|---|
| 1300 | #define regSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1301 | #define regSDMA1_GFX_MIDCMD_DATA4 0x06c4 |
|---|
| 1302 | #define regSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1303 | #define regSDMA1_GFX_MIDCMD_DATA5 0x06c5 |
|---|
| 1304 | #define regSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1305 | #define regSDMA1_GFX_MIDCMD_DATA6 0x06c6 |
|---|
| 1306 | #define regSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1307 | #define regSDMA1_GFX_MIDCMD_DATA7 0x06c7 |
|---|
| 1308 | #define regSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1309 | #define regSDMA1_GFX_MIDCMD_DATA8 0x06c8 |
|---|
| 1310 | #define regSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1311 | #define regSDMA1_GFX_MIDCMD_DATA9 0x06c9 |
|---|
| 1312 | #define regSDMA1_GFX_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1313 | #define regSDMA1_GFX_MIDCMD_DATA10 0x06ca |
|---|
| 1314 | #define regSDMA1_GFX_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1315 | #define regSDMA1_GFX_MIDCMD_CNTL 0x06cb |
|---|
| 1316 | #define regSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1317 | #define regSDMA1_PAGE_RB_CNTL 0x06d8 |
|---|
| 1318 | #define regSDMA1_PAGE_RB_CNTL_BASE_IDX 0 |
|---|
| 1319 | #define regSDMA1_PAGE_RB_BASE 0x06d9 |
|---|
| 1320 | #define regSDMA1_PAGE_RB_BASE_BASE_IDX 0 |
|---|
| 1321 | #define regSDMA1_PAGE_RB_BASE_HI 0x06da |
|---|
| 1322 | #define regSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1323 | #define regSDMA1_PAGE_RB_RPTR 0x06db |
|---|
| 1324 | #define regSDMA1_PAGE_RB_RPTR_BASE_IDX 0 |
|---|
| 1325 | #define regSDMA1_PAGE_RB_RPTR_HI 0x06dc |
|---|
| 1326 | #define regSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1327 | #define regSDMA1_PAGE_RB_WPTR 0x06dd |
|---|
| 1328 | #define regSDMA1_PAGE_RB_WPTR_BASE_IDX 0 |
|---|
| 1329 | #define regSDMA1_PAGE_RB_WPTR_HI 0x06de |
|---|
| 1330 | #define regSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1331 | #define regSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x06df |
|---|
| 1332 | #define regSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1333 | #define regSDMA1_PAGE_RB_RPTR_ADDR_HI 0x06e0 |
|---|
| 1334 | #define regSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1335 | #define regSDMA1_PAGE_RB_RPTR_ADDR_LO 0x06e1 |
|---|
| 1336 | #define regSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1337 | #define regSDMA1_PAGE_IB_CNTL 0x06e2 |
|---|
| 1338 | #define regSDMA1_PAGE_IB_CNTL_BASE_IDX 0 |
|---|
| 1339 | #define regSDMA1_PAGE_IB_RPTR 0x06e3 |
|---|
| 1340 | #define regSDMA1_PAGE_IB_RPTR_BASE_IDX 0 |
|---|
| 1341 | #define regSDMA1_PAGE_IB_OFFSET 0x06e4 |
|---|
| 1342 | #define regSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 |
|---|
| 1343 | #define regSDMA1_PAGE_IB_BASE_LO 0x06e5 |
|---|
| 1344 | #define regSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1345 | #define regSDMA1_PAGE_IB_BASE_HI 0x06e6 |
|---|
| 1346 | #define regSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1347 | #define regSDMA1_PAGE_IB_SIZE 0x06e7 |
|---|
| 1348 | #define regSDMA1_PAGE_IB_SIZE_BASE_IDX 0 |
|---|
| 1349 | #define regSDMA1_PAGE_SKIP_CNTL 0x06e8 |
|---|
| 1350 | #define regSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1351 | #define regSDMA1_PAGE_CONTEXT_STATUS 0x06e9 |
|---|
| 1352 | #define regSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1353 | #define regSDMA1_PAGE_DOORBELL 0x06ea |
|---|
| 1354 | #define regSDMA1_PAGE_DOORBELL_BASE_IDX 0 |
|---|
| 1355 | #define regSDMA1_PAGE_STATUS 0x0700 |
|---|
| 1356 | #define regSDMA1_PAGE_STATUS_BASE_IDX 0 |
|---|
| 1357 | #define regSDMA1_PAGE_DOORBELL_LOG 0x0701 |
|---|
| 1358 | #define regSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1359 | #define regSDMA1_PAGE_WATERMARK 0x0702 |
|---|
| 1360 | #define regSDMA1_PAGE_WATERMARK_BASE_IDX 0 |
|---|
| 1361 | #define regSDMA1_PAGE_DOORBELL_OFFSET 0x0703 |
|---|
| 1362 | #define regSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1363 | #define regSDMA1_PAGE_CSA_ADDR_LO 0x0704 |
|---|
| 1364 | #define regSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1365 | #define regSDMA1_PAGE_CSA_ADDR_HI 0x0705 |
|---|
| 1366 | #define regSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1367 | #define regSDMA1_PAGE_IB_SUB_REMAIN 0x0707 |
|---|
| 1368 | #define regSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1369 | #define regSDMA1_PAGE_PREEMPT 0x0708 |
|---|
| 1370 | #define regSDMA1_PAGE_PREEMPT_BASE_IDX 0 |
|---|
| 1371 | #define regSDMA1_PAGE_DUMMY_REG 0x0709 |
|---|
| 1372 | #define regSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 |
|---|
| 1373 | #define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x070a |
|---|
| 1374 | #define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1375 | #define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x070b |
|---|
| 1376 | #define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1377 | #define regSDMA1_PAGE_RB_AQL_CNTL 0x070c |
|---|
| 1378 | #define regSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1379 | #define regSDMA1_PAGE_MINOR_PTR_UPDATE 0x070d |
|---|
| 1380 | #define regSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1381 | #define regSDMA1_PAGE_MIDCMD_DATA0 0x0718 |
|---|
| 1382 | #define regSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1383 | #define regSDMA1_PAGE_MIDCMD_DATA1 0x0719 |
|---|
| 1384 | #define regSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1385 | #define regSDMA1_PAGE_MIDCMD_DATA2 0x071a |
|---|
| 1386 | #define regSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1387 | #define regSDMA1_PAGE_MIDCMD_DATA3 0x071b |
|---|
| 1388 | #define regSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1389 | #define regSDMA1_PAGE_MIDCMD_DATA4 0x071c |
|---|
| 1390 | #define regSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1391 | #define regSDMA1_PAGE_MIDCMD_DATA5 0x071d |
|---|
| 1392 | #define regSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1393 | #define regSDMA1_PAGE_MIDCMD_DATA6 0x071e |
|---|
| 1394 | #define regSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1395 | #define regSDMA1_PAGE_MIDCMD_DATA7 0x071f |
|---|
| 1396 | #define regSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1397 | #define regSDMA1_PAGE_MIDCMD_DATA8 0x0720 |
|---|
| 1398 | #define regSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1399 | #define regSDMA1_PAGE_MIDCMD_DATA9 0x0721 |
|---|
| 1400 | #define regSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1401 | #define regSDMA1_PAGE_MIDCMD_DATA10 0x0722 |
|---|
| 1402 | #define regSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1403 | #define regSDMA1_PAGE_MIDCMD_CNTL 0x0723 |
|---|
| 1404 | #define regSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1405 | #define regSDMA1_RLC0_RB_CNTL 0x0730 |
|---|
| 1406 | #define regSDMA1_RLC0_RB_CNTL_BASE_IDX 0 |
|---|
| 1407 | #define regSDMA1_RLC0_RB_BASE 0x0731 |
|---|
| 1408 | #define regSDMA1_RLC0_RB_BASE_BASE_IDX 0 |
|---|
| 1409 | #define regSDMA1_RLC0_RB_BASE_HI 0x0732 |
|---|
| 1410 | #define regSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1411 | #define regSDMA1_RLC0_RB_RPTR 0x0733 |
|---|
| 1412 | #define regSDMA1_RLC0_RB_RPTR_BASE_IDX 0 |
|---|
| 1413 | #define regSDMA1_RLC0_RB_RPTR_HI 0x0734 |
|---|
| 1414 | #define regSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1415 | #define regSDMA1_RLC0_RB_WPTR 0x0735 |
|---|
| 1416 | #define regSDMA1_RLC0_RB_WPTR_BASE_IDX 0 |
|---|
| 1417 | #define regSDMA1_RLC0_RB_WPTR_HI 0x0736 |
|---|
| 1418 | #define regSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1419 | #define regSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0737 |
|---|
| 1420 | #define regSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1421 | #define regSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0738 |
|---|
| 1422 | #define regSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1423 | #define regSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0739 |
|---|
| 1424 | #define regSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1425 | #define regSDMA1_RLC0_IB_CNTL 0x073a |
|---|
| 1426 | #define regSDMA1_RLC0_IB_CNTL_BASE_IDX 0 |
|---|
| 1427 | #define regSDMA1_RLC0_IB_RPTR 0x073b |
|---|
| 1428 | #define regSDMA1_RLC0_IB_RPTR_BASE_IDX 0 |
|---|
| 1429 | #define regSDMA1_RLC0_IB_OFFSET 0x073c |
|---|
| 1430 | #define regSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 |
|---|
| 1431 | #define regSDMA1_RLC0_IB_BASE_LO 0x073d |
|---|
| 1432 | #define regSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1433 | #define regSDMA1_RLC0_IB_BASE_HI 0x073e |
|---|
| 1434 | #define regSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1435 | #define regSDMA1_RLC0_IB_SIZE 0x073f |
|---|
| 1436 | #define regSDMA1_RLC0_IB_SIZE_BASE_IDX 0 |
|---|
| 1437 | #define regSDMA1_RLC0_SKIP_CNTL 0x0740 |
|---|
| 1438 | #define regSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1439 | #define regSDMA1_RLC0_CONTEXT_STATUS 0x0741 |
|---|
| 1440 | #define regSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1441 | #define regSDMA1_RLC0_DOORBELL 0x0742 |
|---|
| 1442 | #define regSDMA1_RLC0_DOORBELL_BASE_IDX 0 |
|---|
| 1443 | #define regSDMA1_RLC0_STATUS 0x0758 |
|---|
| 1444 | #define regSDMA1_RLC0_STATUS_BASE_IDX 0 |
|---|
| 1445 | #define regSDMA1_RLC0_DOORBELL_LOG 0x0759 |
|---|
| 1446 | #define regSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1447 | #define regSDMA1_RLC0_WATERMARK 0x075a |
|---|
| 1448 | #define regSDMA1_RLC0_WATERMARK_BASE_IDX 0 |
|---|
| 1449 | #define regSDMA1_RLC0_DOORBELL_OFFSET 0x075b |
|---|
| 1450 | #define regSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1451 | #define regSDMA1_RLC0_CSA_ADDR_LO 0x075c |
|---|
| 1452 | #define regSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1453 | #define regSDMA1_RLC0_CSA_ADDR_HI 0x075d |
|---|
| 1454 | #define regSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1455 | #define regSDMA1_RLC0_IB_SUB_REMAIN 0x075f |
|---|
| 1456 | #define regSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1457 | #define regSDMA1_RLC0_PREEMPT 0x0760 |
|---|
| 1458 | #define regSDMA1_RLC0_PREEMPT_BASE_IDX 0 |
|---|
| 1459 | #define regSDMA1_RLC0_DUMMY_REG 0x0761 |
|---|
| 1460 | #define regSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 |
|---|
| 1461 | #define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0762 |
|---|
| 1462 | #define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1463 | #define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0763 |
|---|
| 1464 | #define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1465 | #define regSDMA1_RLC0_RB_AQL_CNTL 0x0764 |
|---|
| 1466 | #define regSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1467 | #define regSDMA1_RLC0_MINOR_PTR_UPDATE 0x0765 |
|---|
| 1468 | #define regSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1469 | #define regSDMA1_RLC0_MIDCMD_DATA0 0x0770 |
|---|
| 1470 | #define regSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1471 | #define regSDMA1_RLC0_MIDCMD_DATA1 0x0771 |
|---|
| 1472 | #define regSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1473 | #define regSDMA1_RLC0_MIDCMD_DATA2 0x0772 |
|---|
| 1474 | #define regSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1475 | #define regSDMA1_RLC0_MIDCMD_DATA3 0x0773 |
|---|
| 1476 | #define regSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1477 | #define regSDMA1_RLC0_MIDCMD_DATA4 0x0774 |
|---|
| 1478 | #define regSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1479 | #define regSDMA1_RLC0_MIDCMD_DATA5 0x0775 |
|---|
| 1480 | #define regSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1481 | #define regSDMA1_RLC0_MIDCMD_DATA6 0x0776 |
|---|
| 1482 | #define regSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1483 | #define regSDMA1_RLC0_MIDCMD_DATA7 0x0777 |
|---|
| 1484 | #define regSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1485 | #define regSDMA1_RLC0_MIDCMD_DATA8 0x0778 |
|---|
| 1486 | #define regSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1487 | #define regSDMA1_RLC0_MIDCMD_DATA9 0x0779 |
|---|
| 1488 | #define regSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1489 | #define regSDMA1_RLC0_MIDCMD_DATA10 0x077a |
|---|
| 1490 | #define regSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1491 | #define regSDMA1_RLC0_MIDCMD_CNTL 0x077b |
|---|
| 1492 | #define regSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1493 | #define regSDMA1_RLC1_RB_CNTL 0x0788 |
|---|
| 1494 | #define regSDMA1_RLC1_RB_CNTL_BASE_IDX 0 |
|---|
| 1495 | #define regSDMA1_RLC1_RB_BASE 0x0789 |
|---|
| 1496 | #define regSDMA1_RLC1_RB_BASE_BASE_IDX 0 |
|---|
| 1497 | #define regSDMA1_RLC1_RB_BASE_HI 0x078a |
|---|
| 1498 | #define regSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1499 | #define regSDMA1_RLC1_RB_RPTR 0x078b |
|---|
| 1500 | #define regSDMA1_RLC1_RB_RPTR_BASE_IDX 0 |
|---|
| 1501 | #define regSDMA1_RLC1_RB_RPTR_HI 0x078c |
|---|
| 1502 | #define regSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1503 | #define regSDMA1_RLC1_RB_WPTR 0x078d |
|---|
| 1504 | #define regSDMA1_RLC1_RB_WPTR_BASE_IDX 0 |
|---|
| 1505 | #define regSDMA1_RLC1_RB_WPTR_HI 0x078e |
|---|
| 1506 | #define regSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1507 | #define regSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x078f |
|---|
| 1508 | #define regSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1509 | #define regSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0790 |
|---|
| 1510 | #define regSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1511 | #define regSDMA1_RLC1_RB_RPTR_ADDR_LO 0x0791 |
|---|
| 1512 | #define regSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1513 | #define regSDMA1_RLC1_IB_CNTL 0x0792 |
|---|
| 1514 | #define regSDMA1_RLC1_IB_CNTL_BASE_IDX 0 |
|---|
| 1515 | #define regSDMA1_RLC1_IB_RPTR 0x0793 |
|---|
| 1516 | #define regSDMA1_RLC1_IB_RPTR_BASE_IDX 0 |
|---|
| 1517 | #define regSDMA1_RLC1_IB_OFFSET 0x0794 |
|---|
| 1518 | #define regSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 |
|---|
| 1519 | #define regSDMA1_RLC1_IB_BASE_LO 0x0795 |
|---|
| 1520 | #define regSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1521 | #define regSDMA1_RLC1_IB_BASE_HI 0x0796 |
|---|
| 1522 | #define regSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1523 | #define regSDMA1_RLC1_IB_SIZE 0x0797 |
|---|
| 1524 | #define regSDMA1_RLC1_IB_SIZE_BASE_IDX 0 |
|---|
| 1525 | #define regSDMA1_RLC1_SKIP_CNTL 0x0798 |
|---|
| 1526 | #define regSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1527 | #define regSDMA1_RLC1_CONTEXT_STATUS 0x0799 |
|---|
| 1528 | #define regSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1529 | #define regSDMA1_RLC1_DOORBELL 0x079a |
|---|
| 1530 | #define regSDMA1_RLC1_DOORBELL_BASE_IDX 0 |
|---|
| 1531 | #define regSDMA1_RLC1_STATUS 0x07b0 |
|---|
| 1532 | #define regSDMA1_RLC1_STATUS_BASE_IDX 0 |
|---|
| 1533 | #define regSDMA1_RLC1_DOORBELL_LOG 0x07b1 |
|---|
| 1534 | #define regSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1535 | #define regSDMA1_RLC1_WATERMARK 0x07b2 |
|---|
| 1536 | #define regSDMA1_RLC1_WATERMARK_BASE_IDX 0 |
|---|
| 1537 | #define regSDMA1_RLC1_DOORBELL_OFFSET 0x07b3 |
|---|
| 1538 | #define regSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1539 | #define regSDMA1_RLC1_CSA_ADDR_LO 0x07b4 |
|---|
| 1540 | #define regSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1541 | #define regSDMA1_RLC1_CSA_ADDR_HI 0x07b5 |
|---|
| 1542 | #define regSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1543 | #define regSDMA1_RLC1_IB_SUB_REMAIN 0x07b7 |
|---|
| 1544 | #define regSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1545 | #define regSDMA1_RLC1_PREEMPT 0x07b8 |
|---|
| 1546 | #define regSDMA1_RLC1_PREEMPT_BASE_IDX 0 |
|---|
| 1547 | #define regSDMA1_RLC1_DUMMY_REG 0x07b9 |
|---|
| 1548 | #define regSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 |
|---|
| 1549 | #define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x07ba |
|---|
| 1550 | #define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1551 | #define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x07bb |
|---|
| 1552 | #define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1553 | #define regSDMA1_RLC1_RB_AQL_CNTL 0x07bc |
|---|
| 1554 | #define regSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1555 | #define regSDMA1_RLC1_MINOR_PTR_UPDATE 0x07bd |
|---|
| 1556 | #define regSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1557 | #define regSDMA1_RLC1_MIDCMD_DATA0 0x07c8 |
|---|
| 1558 | #define regSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1559 | #define regSDMA1_RLC1_MIDCMD_DATA1 0x07c9 |
|---|
| 1560 | #define regSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1561 | #define regSDMA1_RLC1_MIDCMD_DATA2 0x07ca |
|---|
| 1562 | #define regSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1563 | #define regSDMA1_RLC1_MIDCMD_DATA3 0x07cb |
|---|
| 1564 | #define regSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1565 | #define regSDMA1_RLC1_MIDCMD_DATA4 0x07cc |
|---|
| 1566 | #define regSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1567 | #define regSDMA1_RLC1_MIDCMD_DATA5 0x07cd |
|---|
| 1568 | #define regSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1569 | #define regSDMA1_RLC1_MIDCMD_DATA6 0x07ce |
|---|
| 1570 | #define regSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1571 | #define regSDMA1_RLC1_MIDCMD_DATA7 0x07cf |
|---|
| 1572 | #define regSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1573 | #define regSDMA1_RLC1_MIDCMD_DATA8 0x07d0 |
|---|
| 1574 | #define regSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1575 | #define regSDMA1_RLC1_MIDCMD_DATA9 0x07d1 |
|---|
| 1576 | #define regSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1577 | #define regSDMA1_RLC1_MIDCMD_DATA10 0x07d2 |
|---|
| 1578 | #define regSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1579 | #define regSDMA1_RLC1_MIDCMD_CNTL 0x07d3 |
|---|
| 1580 | #define regSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1581 | #define regSDMA1_RLC2_RB_CNTL 0x07e0 |
|---|
| 1582 | #define regSDMA1_RLC2_RB_CNTL_BASE_IDX 0 |
|---|
| 1583 | #define regSDMA1_RLC2_RB_BASE 0x07e1 |
|---|
| 1584 | #define regSDMA1_RLC2_RB_BASE_BASE_IDX 0 |
|---|
| 1585 | #define regSDMA1_RLC2_RB_BASE_HI 0x07e2 |
|---|
| 1586 | #define regSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1587 | #define regSDMA1_RLC2_RB_RPTR 0x07e3 |
|---|
| 1588 | #define regSDMA1_RLC2_RB_RPTR_BASE_IDX 0 |
|---|
| 1589 | #define regSDMA1_RLC2_RB_RPTR_HI 0x07e4 |
|---|
| 1590 | #define regSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1591 | #define regSDMA1_RLC2_RB_WPTR 0x07e5 |
|---|
| 1592 | #define regSDMA1_RLC2_RB_WPTR_BASE_IDX 0 |
|---|
| 1593 | #define regSDMA1_RLC2_RB_WPTR_HI 0x07e6 |
|---|
| 1594 | #define regSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1595 | #define regSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x07e7 |
|---|
| 1596 | #define regSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1597 | #define regSDMA1_RLC2_RB_RPTR_ADDR_HI 0x07e8 |
|---|
| 1598 | #define regSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1599 | #define regSDMA1_RLC2_RB_RPTR_ADDR_LO 0x07e9 |
|---|
| 1600 | #define regSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1601 | #define regSDMA1_RLC2_IB_CNTL 0x07ea |
|---|
| 1602 | #define regSDMA1_RLC2_IB_CNTL_BASE_IDX 0 |
|---|
| 1603 | #define regSDMA1_RLC2_IB_RPTR 0x07eb |
|---|
| 1604 | #define regSDMA1_RLC2_IB_RPTR_BASE_IDX 0 |
|---|
| 1605 | #define regSDMA1_RLC2_IB_OFFSET 0x07ec |
|---|
| 1606 | #define regSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 |
|---|
| 1607 | #define regSDMA1_RLC2_IB_BASE_LO 0x07ed |
|---|
| 1608 | #define regSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1609 | #define regSDMA1_RLC2_IB_BASE_HI 0x07ee |
|---|
| 1610 | #define regSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1611 | #define regSDMA1_RLC2_IB_SIZE 0x07ef |
|---|
| 1612 | #define regSDMA1_RLC2_IB_SIZE_BASE_IDX 0 |
|---|
| 1613 | #define regSDMA1_RLC2_SKIP_CNTL 0x07f0 |
|---|
| 1614 | #define regSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1615 | #define regSDMA1_RLC2_CONTEXT_STATUS 0x07f1 |
|---|
| 1616 | #define regSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1617 | #define regSDMA1_RLC2_DOORBELL 0x07f2 |
|---|
| 1618 | #define regSDMA1_RLC2_DOORBELL_BASE_IDX 0 |
|---|
| 1619 | #define regSDMA1_RLC2_STATUS 0x0808 |
|---|
| 1620 | #define regSDMA1_RLC2_STATUS_BASE_IDX 0 |
|---|
| 1621 | #define regSDMA1_RLC2_DOORBELL_LOG 0x0809 |
|---|
| 1622 | #define regSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1623 | #define regSDMA1_RLC2_WATERMARK 0x080a |
|---|
| 1624 | #define regSDMA1_RLC2_WATERMARK_BASE_IDX 0 |
|---|
| 1625 | #define regSDMA1_RLC2_DOORBELL_OFFSET 0x080b |
|---|
| 1626 | #define regSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1627 | #define regSDMA1_RLC2_CSA_ADDR_LO 0x080c |
|---|
| 1628 | #define regSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1629 | #define regSDMA1_RLC2_CSA_ADDR_HI 0x080d |
|---|
| 1630 | #define regSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1631 | #define regSDMA1_RLC2_IB_SUB_REMAIN 0x080f |
|---|
| 1632 | #define regSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1633 | #define regSDMA1_RLC2_PREEMPT 0x0810 |
|---|
| 1634 | #define regSDMA1_RLC2_PREEMPT_BASE_IDX 0 |
|---|
| 1635 | #define regSDMA1_RLC2_DUMMY_REG 0x0811 |
|---|
| 1636 | #define regSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 |
|---|
| 1637 | #define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0812 |
|---|
| 1638 | #define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1639 | #define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0813 |
|---|
| 1640 | #define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1641 | #define regSDMA1_RLC2_RB_AQL_CNTL 0x0814 |
|---|
| 1642 | #define regSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1643 | #define regSDMA1_RLC2_MINOR_PTR_UPDATE 0x0815 |
|---|
| 1644 | #define regSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1645 | #define regSDMA1_RLC2_MIDCMD_DATA0 0x0820 |
|---|
| 1646 | #define regSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1647 | #define regSDMA1_RLC2_MIDCMD_DATA1 0x0821 |
|---|
| 1648 | #define regSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1649 | #define regSDMA1_RLC2_MIDCMD_DATA2 0x0822 |
|---|
| 1650 | #define regSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1651 | #define regSDMA1_RLC2_MIDCMD_DATA3 0x0823 |
|---|
| 1652 | #define regSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1653 | #define regSDMA1_RLC2_MIDCMD_DATA4 0x0824 |
|---|
| 1654 | #define regSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1655 | #define regSDMA1_RLC2_MIDCMD_DATA5 0x0825 |
|---|
| 1656 | #define regSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1657 | #define regSDMA1_RLC2_MIDCMD_DATA6 0x0826 |
|---|
| 1658 | #define regSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1659 | #define regSDMA1_RLC2_MIDCMD_DATA7 0x0827 |
|---|
| 1660 | #define regSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1661 | #define regSDMA1_RLC2_MIDCMD_DATA8 0x0828 |
|---|
| 1662 | #define regSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1663 | #define regSDMA1_RLC2_MIDCMD_DATA9 0x0829 |
|---|
| 1664 | #define regSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1665 | #define regSDMA1_RLC2_MIDCMD_DATA10 0x082a |
|---|
| 1666 | #define regSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1667 | #define regSDMA1_RLC2_MIDCMD_CNTL 0x082b |
|---|
| 1668 | #define regSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1669 | #define regSDMA1_RLC3_RB_CNTL 0x0838 |
|---|
| 1670 | #define regSDMA1_RLC3_RB_CNTL_BASE_IDX 0 |
|---|
| 1671 | #define regSDMA1_RLC3_RB_BASE 0x0839 |
|---|
| 1672 | #define regSDMA1_RLC3_RB_BASE_BASE_IDX 0 |
|---|
| 1673 | #define regSDMA1_RLC3_RB_BASE_HI 0x083a |
|---|
| 1674 | #define regSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1675 | #define regSDMA1_RLC3_RB_RPTR 0x083b |
|---|
| 1676 | #define regSDMA1_RLC3_RB_RPTR_BASE_IDX 0 |
|---|
| 1677 | #define regSDMA1_RLC3_RB_RPTR_HI 0x083c |
|---|
| 1678 | #define regSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1679 | #define regSDMA1_RLC3_RB_WPTR 0x083d |
|---|
| 1680 | #define regSDMA1_RLC3_RB_WPTR_BASE_IDX 0 |
|---|
| 1681 | #define regSDMA1_RLC3_RB_WPTR_HI 0x083e |
|---|
| 1682 | #define regSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1683 | #define regSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x083f |
|---|
| 1684 | #define regSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1685 | #define regSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0840 |
|---|
| 1686 | #define regSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1687 | #define regSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0841 |
|---|
| 1688 | #define regSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1689 | #define regSDMA1_RLC3_IB_CNTL 0x0842 |
|---|
| 1690 | #define regSDMA1_RLC3_IB_CNTL_BASE_IDX 0 |
|---|
| 1691 | #define regSDMA1_RLC3_IB_RPTR 0x0843 |
|---|
| 1692 | #define regSDMA1_RLC3_IB_RPTR_BASE_IDX 0 |
|---|
| 1693 | #define regSDMA1_RLC3_IB_OFFSET 0x0844 |
|---|
| 1694 | #define regSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 |
|---|
| 1695 | #define regSDMA1_RLC3_IB_BASE_LO 0x0845 |
|---|
| 1696 | #define regSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1697 | #define regSDMA1_RLC3_IB_BASE_HI 0x0846 |
|---|
| 1698 | #define regSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1699 | #define regSDMA1_RLC3_IB_SIZE 0x0847 |
|---|
| 1700 | #define regSDMA1_RLC3_IB_SIZE_BASE_IDX 0 |
|---|
| 1701 | #define regSDMA1_RLC3_SKIP_CNTL 0x0848 |
|---|
| 1702 | #define regSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1703 | #define regSDMA1_RLC3_CONTEXT_STATUS 0x0849 |
|---|
| 1704 | #define regSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1705 | #define regSDMA1_RLC3_DOORBELL 0x084a |
|---|
| 1706 | #define regSDMA1_RLC3_DOORBELL_BASE_IDX 0 |
|---|
| 1707 | #define regSDMA1_RLC3_STATUS 0x0860 |
|---|
| 1708 | #define regSDMA1_RLC3_STATUS_BASE_IDX 0 |
|---|
| 1709 | #define regSDMA1_RLC3_DOORBELL_LOG 0x0861 |
|---|
| 1710 | #define regSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1711 | #define regSDMA1_RLC3_WATERMARK 0x0862 |
|---|
| 1712 | #define regSDMA1_RLC3_WATERMARK_BASE_IDX 0 |
|---|
| 1713 | #define regSDMA1_RLC3_DOORBELL_OFFSET 0x0863 |
|---|
| 1714 | #define regSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1715 | #define regSDMA1_RLC3_CSA_ADDR_LO 0x0864 |
|---|
| 1716 | #define regSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1717 | #define regSDMA1_RLC3_CSA_ADDR_HI 0x0865 |
|---|
| 1718 | #define regSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1719 | #define regSDMA1_RLC3_IB_SUB_REMAIN 0x0867 |
|---|
| 1720 | #define regSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1721 | #define regSDMA1_RLC3_PREEMPT 0x0868 |
|---|
| 1722 | #define regSDMA1_RLC3_PREEMPT_BASE_IDX 0 |
|---|
| 1723 | #define regSDMA1_RLC3_DUMMY_REG 0x0869 |
|---|
| 1724 | #define regSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 |
|---|
| 1725 | #define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x086a |
|---|
| 1726 | #define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1727 | #define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x086b |
|---|
| 1728 | #define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1729 | #define regSDMA1_RLC3_RB_AQL_CNTL 0x086c |
|---|
| 1730 | #define regSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1731 | #define regSDMA1_RLC3_MINOR_PTR_UPDATE 0x086d |
|---|
| 1732 | #define regSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1733 | #define regSDMA1_RLC3_MIDCMD_DATA0 0x0878 |
|---|
| 1734 | #define regSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1735 | #define regSDMA1_RLC3_MIDCMD_DATA1 0x0879 |
|---|
| 1736 | #define regSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1737 | #define regSDMA1_RLC3_MIDCMD_DATA2 0x087a |
|---|
| 1738 | #define regSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1739 | #define regSDMA1_RLC3_MIDCMD_DATA3 0x087b |
|---|
| 1740 | #define regSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1741 | #define regSDMA1_RLC3_MIDCMD_DATA4 0x087c |
|---|
| 1742 | #define regSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 1743 | #define regSDMA1_RLC3_MIDCMD_DATA5 0x087d |
|---|
| 1744 | #define regSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 1745 | #define regSDMA1_RLC3_MIDCMD_DATA6 0x087e |
|---|
| 1746 | #define regSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 1747 | #define regSDMA1_RLC3_MIDCMD_DATA7 0x087f |
|---|
| 1748 | #define regSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 1749 | #define regSDMA1_RLC3_MIDCMD_DATA8 0x0880 |
|---|
| 1750 | #define regSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 1751 | #define regSDMA1_RLC3_MIDCMD_DATA9 0x0881 |
|---|
| 1752 | #define regSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 1753 | #define regSDMA1_RLC3_MIDCMD_DATA10 0x0882 |
|---|
| 1754 | #define regSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 1755 | #define regSDMA1_RLC3_MIDCMD_CNTL 0x0883 |
|---|
| 1756 | #define regSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 1757 | #define regSDMA1_RLC4_RB_CNTL 0x0890 |
|---|
| 1758 | #define regSDMA1_RLC4_RB_CNTL_BASE_IDX 0 |
|---|
| 1759 | #define regSDMA1_RLC4_RB_BASE 0x0891 |
|---|
| 1760 | #define regSDMA1_RLC4_RB_BASE_BASE_IDX 0 |
|---|
| 1761 | #define regSDMA1_RLC4_RB_BASE_HI 0x0892 |
|---|
| 1762 | #define regSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 |
|---|
| 1763 | #define regSDMA1_RLC4_RB_RPTR 0x0893 |
|---|
| 1764 | #define regSDMA1_RLC4_RB_RPTR_BASE_IDX 0 |
|---|
| 1765 | #define regSDMA1_RLC4_RB_RPTR_HI 0x0894 |
|---|
| 1766 | #define regSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 1767 | #define regSDMA1_RLC4_RB_WPTR 0x0895 |
|---|
| 1768 | #define regSDMA1_RLC4_RB_WPTR_BASE_IDX 0 |
|---|
| 1769 | #define regSDMA1_RLC4_RB_WPTR_HI 0x0896 |
|---|
| 1770 | #define regSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 1771 | #define regSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x0897 |
|---|
| 1772 | #define regSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 1773 | #define regSDMA1_RLC4_RB_RPTR_ADDR_HI 0x0898 |
|---|
| 1774 | #define regSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 1775 | #define regSDMA1_RLC4_RB_RPTR_ADDR_LO 0x0899 |
|---|
| 1776 | #define regSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 1777 | #define regSDMA1_RLC4_IB_CNTL 0x089a |
|---|
| 1778 | #define regSDMA1_RLC4_IB_CNTL_BASE_IDX 0 |
|---|
| 1779 | #define regSDMA1_RLC4_IB_RPTR 0x089b |
|---|
| 1780 | #define regSDMA1_RLC4_IB_RPTR_BASE_IDX 0 |
|---|
| 1781 | #define regSDMA1_RLC4_IB_OFFSET 0x089c |
|---|
| 1782 | #define regSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 |
|---|
| 1783 | #define regSDMA1_RLC4_IB_BASE_LO 0x089d |
|---|
| 1784 | #define regSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 |
|---|
| 1785 | #define regSDMA1_RLC4_IB_BASE_HI 0x089e |
|---|
| 1786 | #define regSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 |
|---|
| 1787 | #define regSDMA1_RLC4_IB_SIZE 0x089f |
|---|
| 1788 | #define regSDMA1_RLC4_IB_SIZE_BASE_IDX 0 |
|---|
| 1789 | #define regSDMA1_RLC4_SKIP_CNTL 0x08a0 |
|---|
| 1790 | #define regSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 |
|---|
| 1791 | #define regSDMA1_RLC4_CONTEXT_STATUS 0x08a1 |
|---|
| 1792 | #define regSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 1793 | #define regSDMA1_RLC4_DOORBELL 0x08a2 |
|---|
| 1794 | #define regSDMA1_RLC4_DOORBELL_BASE_IDX 0 |
|---|
| 1795 | #define regSDMA1_RLC4_STATUS 0x08b8 |
|---|
| 1796 | #define regSDMA1_RLC4_STATUS_BASE_IDX 0 |
|---|
| 1797 | #define regSDMA1_RLC4_DOORBELL_LOG 0x08b9 |
|---|
| 1798 | #define regSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 1799 | #define regSDMA1_RLC4_WATERMARK 0x08ba |
|---|
| 1800 | #define regSDMA1_RLC4_WATERMARK_BASE_IDX 0 |
|---|
| 1801 | #define regSDMA1_RLC4_DOORBELL_OFFSET 0x08bb |
|---|
| 1802 | #define regSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 1803 | #define regSDMA1_RLC4_CSA_ADDR_LO 0x08bc |
|---|
| 1804 | #define regSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 1805 | #define regSDMA1_RLC4_CSA_ADDR_HI 0x08bd |
|---|
| 1806 | #define regSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 1807 | #define regSDMA1_RLC4_IB_SUB_REMAIN 0x08bf |
|---|
| 1808 | #define regSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 1809 | #define regSDMA1_RLC4_PREEMPT 0x08c0 |
|---|
| 1810 | #define regSDMA1_RLC4_PREEMPT_BASE_IDX 0 |
|---|
| 1811 | #define regSDMA1_RLC4_DUMMY_REG 0x08c1 |
|---|
| 1812 | #define regSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 |
|---|
| 1813 | #define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x08c2 |
|---|
| 1814 | #define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1815 | #define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x08c3 |
|---|
| 1816 | #define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1817 | #define regSDMA1_RLC4_RB_AQL_CNTL 0x08c4 |
|---|
| 1818 | #define regSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1819 | #define regSDMA1_RLC4_MINOR_PTR_UPDATE 0x08c5 |
|---|
| 1820 | #define regSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1821 | #define regSDMA1_RLC4_MIDCMD_DATA0 0x08d0 |
|---|
| 1822 | #define regSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1823 | #define regSDMA1_RLC4_MIDCMD_DATA1 0x08d1 |
|---|
| 1824 | #define regSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 1825 | #define regSDMA1_RLC4_MIDCMD_DATA2 0x08d2 |
|---|
| 1826 | #define regSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 1827 | #define regSDMA1_RLC4_MIDCMD_DATA3 0x08d3 |
|---|
| 1828 | #define regSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 1829 | #define regSDMA1_RLC4_MIDCMD_DATA4 0x08d4 |
|---|
| 1830 | #define regSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 |
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| 1831 | #define regSDMA1_RLC4_MIDCMD_DATA5 0x08d5 |
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| 1832 | #define regSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 |
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| 1833 | #define regSDMA1_RLC4_MIDCMD_DATA6 0x08d6 |
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| 1834 | #define regSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 |
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| 1835 | #define regSDMA1_RLC4_MIDCMD_DATA7 0x08d7 |
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| 1836 | #define regSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 |
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| 1837 | #define regSDMA1_RLC4_MIDCMD_DATA8 0x08d8 |
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| 1838 | #define regSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 |
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| 1839 | #define regSDMA1_RLC4_MIDCMD_DATA9 0x08d9 |
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| 1840 | #define regSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX 0 |
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| 1841 | #define regSDMA1_RLC4_MIDCMD_DATA10 0x08da |
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| 1842 | #define regSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX 0 |
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| 1843 | #define regSDMA1_RLC4_MIDCMD_CNTL 0x08db |
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| 1844 | #define regSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 |
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| 1845 | #define regSDMA1_RLC5_RB_CNTL 0x08e8 |
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| 1846 | #define regSDMA1_RLC5_RB_CNTL_BASE_IDX 0 |
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| 1847 | #define regSDMA1_RLC5_RB_BASE 0x08e9 |
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| 1848 | #define regSDMA1_RLC5_RB_BASE_BASE_IDX 0 |
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| 1849 | #define regSDMA1_RLC5_RB_BASE_HI 0x08ea |
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| 1850 | #define regSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 |
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| 1851 | #define regSDMA1_RLC5_RB_RPTR 0x08eb |
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| 1852 | #define regSDMA1_RLC5_RB_RPTR_BASE_IDX 0 |
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| 1853 | #define regSDMA1_RLC5_RB_RPTR_HI 0x08ec |
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| 1854 | #define regSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 |
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| 1855 | #define regSDMA1_RLC5_RB_WPTR 0x08ed |
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| 1856 | #define regSDMA1_RLC5_RB_WPTR_BASE_IDX 0 |
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| 1857 | #define regSDMA1_RLC5_RB_WPTR_HI 0x08ee |
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| 1858 | #define regSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 |
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| 1859 | #define regSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x08ef |
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| 1860 | #define regSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
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| 1861 | #define regSDMA1_RLC5_RB_RPTR_ADDR_HI 0x08f0 |
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| 1862 | #define regSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 |
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| 1863 | #define regSDMA1_RLC5_RB_RPTR_ADDR_LO 0x08f1 |
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| 1864 | #define regSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 |
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| 1865 | #define regSDMA1_RLC5_IB_CNTL 0x08f2 |
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| 1866 | #define regSDMA1_RLC5_IB_CNTL_BASE_IDX 0 |
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| 1867 | #define regSDMA1_RLC5_IB_RPTR 0x08f3 |
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| 1868 | #define regSDMA1_RLC5_IB_RPTR_BASE_IDX 0 |
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| 1869 | #define regSDMA1_RLC5_IB_OFFSET 0x08f4 |
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| 1870 | #define regSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 |
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| 1871 | #define regSDMA1_RLC5_IB_BASE_LO 0x08f5 |
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| 1872 | #define regSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 |
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| 1873 | #define regSDMA1_RLC5_IB_BASE_HI 0x08f6 |
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| 1874 | #define regSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 |
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| 1875 | #define regSDMA1_RLC5_IB_SIZE 0x08f7 |
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| 1876 | #define regSDMA1_RLC5_IB_SIZE_BASE_IDX 0 |
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| 1877 | #define regSDMA1_RLC5_SKIP_CNTL 0x08f8 |
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| 1878 | #define regSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 |
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| 1879 | #define regSDMA1_RLC5_CONTEXT_STATUS 0x08f9 |
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| 1880 | #define regSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 |
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| 1881 | #define regSDMA1_RLC5_DOORBELL 0x08fa |
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| 1882 | #define regSDMA1_RLC5_DOORBELL_BASE_IDX 0 |
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| 1883 | #define regSDMA1_RLC5_STATUS 0x0910 |
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| 1884 | #define regSDMA1_RLC5_STATUS_BASE_IDX 0 |
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| 1885 | #define regSDMA1_RLC5_DOORBELL_LOG 0x0911 |
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| 1886 | #define regSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 |
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| 1887 | #define regSDMA1_RLC5_WATERMARK 0x0912 |
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| 1888 | #define regSDMA1_RLC5_WATERMARK_BASE_IDX 0 |
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| 1889 | #define regSDMA1_RLC5_DOORBELL_OFFSET 0x0913 |
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| 1890 | #define regSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 |
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| 1891 | #define regSDMA1_RLC5_CSA_ADDR_LO 0x0914 |
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| 1892 | #define regSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 |
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| 1893 | #define regSDMA1_RLC5_CSA_ADDR_HI 0x0915 |
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| 1894 | #define regSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 |
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| 1895 | #define regSDMA1_RLC5_IB_SUB_REMAIN 0x0917 |
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| 1896 | #define regSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 |
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| 1897 | #define regSDMA1_RLC5_PREEMPT 0x0918 |
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| 1898 | #define regSDMA1_RLC5_PREEMPT_BASE_IDX 0 |
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| 1899 | #define regSDMA1_RLC5_DUMMY_REG 0x0919 |
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| 1900 | #define regSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 |
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| 1901 | #define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x091a |
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| 1902 | #define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
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| 1903 | #define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x091b |
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| 1904 | #define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
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| 1905 | #define regSDMA1_RLC5_RB_AQL_CNTL 0x091c |
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| 1906 | #define regSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 |
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| 1907 | #define regSDMA1_RLC5_MINOR_PTR_UPDATE 0x091d |
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| 1908 | #define regSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 |
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| 1909 | #define regSDMA1_RLC5_MIDCMD_DATA0 0x0928 |
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| 1910 | #define regSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 |
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| 1911 | #define regSDMA1_RLC5_MIDCMD_DATA1 0x0929 |
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| 1912 | #define regSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 |
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| 1913 | #define regSDMA1_RLC5_MIDCMD_DATA2 0x092a |
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| 1914 | #define regSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 |
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| 1915 | #define regSDMA1_RLC5_MIDCMD_DATA3 0x092b |
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| 1916 | #define regSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 |
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| 1917 | #define regSDMA1_RLC5_MIDCMD_DATA4 0x092c |
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| 1918 | #define regSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 |
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| 1919 | #define regSDMA1_RLC5_MIDCMD_DATA5 0x092d |
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| 1920 | #define regSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 |
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| 1921 | #define regSDMA1_RLC5_MIDCMD_DATA6 0x092e |
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| 1922 | #define regSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 |
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| 1923 | #define regSDMA1_RLC5_MIDCMD_DATA7 0x092f |
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| 1924 | #define regSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 |
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| 1925 | #define regSDMA1_RLC5_MIDCMD_DATA8 0x0930 |
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| 1926 | #define regSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 |
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| 1927 | #define regSDMA1_RLC5_MIDCMD_DATA9 0x0931 |
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| 1928 | #define regSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX 0 |
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| 1929 | #define regSDMA1_RLC5_MIDCMD_DATA10 0x0932 |
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| 1930 | #define regSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX 0 |
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| 1931 | #define regSDMA1_RLC5_MIDCMD_CNTL 0x0933 |
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| 1932 | #define regSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 |
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| 1933 | #define regSDMA1_RLC6_RB_CNTL 0x0940 |
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| 1934 | #define regSDMA1_RLC6_RB_CNTL_BASE_IDX 0 |
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| 1935 | #define regSDMA1_RLC6_RB_BASE 0x0941 |
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| 1936 | #define regSDMA1_RLC6_RB_BASE_BASE_IDX 0 |
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| 1937 | #define regSDMA1_RLC6_RB_BASE_HI 0x0942 |
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| 1938 | #define regSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 |
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| 1939 | #define regSDMA1_RLC6_RB_RPTR 0x0943 |
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| 1940 | #define regSDMA1_RLC6_RB_RPTR_BASE_IDX 0 |
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| 1941 | #define regSDMA1_RLC6_RB_RPTR_HI 0x0944 |
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| 1942 | #define regSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 |
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| 1943 | #define regSDMA1_RLC6_RB_WPTR 0x0945 |
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| 1944 | #define regSDMA1_RLC6_RB_WPTR_BASE_IDX 0 |
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| 1945 | #define regSDMA1_RLC6_RB_WPTR_HI 0x0946 |
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| 1946 | #define regSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 |
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| 1947 | #define regSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0947 |
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| 1948 | #define regSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
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| 1949 | #define regSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0948 |
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| 1950 | #define regSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 |
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| 1951 | #define regSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0949 |
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| 1952 | #define regSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 |
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| 1953 | #define regSDMA1_RLC6_IB_CNTL 0x094a |
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| 1954 | #define regSDMA1_RLC6_IB_CNTL_BASE_IDX 0 |
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| 1955 | #define regSDMA1_RLC6_IB_RPTR 0x094b |
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| 1956 | #define regSDMA1_RLC6_IB_RPTR_BASE_IDX 0 |
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| 1957 | #define regSDMA1_RLC6_IB_OFFSET 0x094c |
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| 1958 | #define regSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 |
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| 1959 | #define regSDMA1_RLC6_IB_BASE_LO 0x094d |
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| 1960 | #define regSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 |
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| 1961 | #define regSDMA1_RLC6_IB_BASE_HI 0x094e |
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| 1962 | #define regSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 |
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| 1963 | #define regSDMA1_RLC6_IB_SIZE 0x094f |
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| 1964 | #define regSDMA1_RLC6_IB_SIZE_BASE_IDX 0 |
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| 1965 | #define regSDMA1_RLC6_SKIP_CNTL 0x0950 |
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| 1966 | #define regSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 |
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| 1967 | #define regSDMA1_RLC6_CONTEXT_STATUS 0x0951 |
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| 1968 | #define regSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 |
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| 1969 | #define regSDMA1_RLC6_DOORBELL 0x0952 |
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| 1970 | #define regSDMA1_RLC6_DOORBELL_BASE_IDX 0 |
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| 1971 | #define regSDMA1_RLC6_STATUS 0x0968 |
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| 1972 | #define regSDMA1_RLC6_STATUS_BASE_IDX 0 |
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| 1973 | #define regSDMA1_RLC6_DOORBELL_LOG 0x0969 |
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| 1974 | #define regSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 |
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| 1975 | #define regSDMA1_RLC6_WATERMARK 0x096a |
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| 1976 | #define regSDMA1_RLC6_WATERMARK_BASE_IDX 0 |
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| 1977 | #define regSDMA1_RLC6_DOORBELL_OFFSET 0x096b |
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| 1978 | #define regSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 |
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| 1979 | #define regSDMA1_RLC6_CSA_ADDR_LO 0x096c |
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| 1980 | #define regSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 |
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| 1981 | #define regSDMA1_RLC6_CSA_ADDR_HI 0x096d |
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| 1982 | #define regSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 |
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| 1983 | #define regSDMA1_RLC6_IB_SUB_REMAIN 0x096f |
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| 1984 | #define regSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 |
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| 1985 | #define regSDMA1_RLC6_PREEMPT 0x0970 |
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| 1986 | #define regSDMA1_RLC6_PREEMPT_BASE_IDX 0 |
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| 1987 | #define regSDMA1_RLC6_DUMMY_REG 0x0971 |
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| 1988 | #define regSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 |
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| 1989 | #define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x0972 |
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| 1990 | #define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 1991 | #define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x0973 |
|---|
| 1992 | #define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 1993 | #define regSDMA1_RLC6_RB_AQL_CNTL 0x0974 |
|---|
| 1994 | #define regSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 1995 | #define regSDMA1_RLC6_MINOR_PTR_UPDATE 0x0975 |
|---|
| 1996 | #define regSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 1997 | #define regSDMA1_RLC6_MIDCMD_DATA0 0x0980 |
|---|
| 1998 | #define regSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 1999 | #define regSDMA1_RLC6_MIDCMD_DATA1 0x0981 |
|---|
| 2000 | #define regSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2001 | #define regSDMA1_RLC6_MIDCMD_DATA2 0x0982 |
|---|
| 2002 | #define regSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2003 | #define regSDMA1_RLC6_MIDCMD_DATA3 0x0983 |
|---|
| 2004 | #define regSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2005 | #define regSDMA1_RLC6_MIDCMD_DATA4 0x0984 |
|---|
| 2006 | #define regSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2007 | #define regSDMA1_RLC6_MIDCMD_DATA5 0x0985 |
|---|
| 2008 | #define regSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2009 | #define regSDMA1_RLC6_MIDCMD_DATA6 0x0986 |
|---|
| 2010 | #define regSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2011 | #define regSDMA1_RLC6_MIDCMD_DATA7 0x0987 |
|---|
| 2012 | #define regSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2013 | #define regSDMA1_RLC6_MIDCMD_DATA8 0x0988 |
|---|
| 2014 | #define regSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2015 | #define regSDMA1_RLC6_MIDCMD_DATA9 0x0989 |
|---|
| 2016 | #define regSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2017 | #define regSDMA1_RLC6_MIDCMD_DATA10 0x098a |
|---|
| 2018 | #define regSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2019 | #define regSDMA1_RLC6_MIDCMD_CNTL 0x098b |
|---|
| 2020 | #define regSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2021 | #define regSDMA1_RLC7_RB_CNTL 0x0998 |
|---|
| 2022 | #define regSDMA1_RLC7_RB_CNTL_BASE_IDX 0 |
|---|
| 2023 | #define regSDMA1_RLC7_RB_BASE 0x0999 |
|---|
| 2024 | #define regSDMA1_RLC7_RB_BASE_BASE_IDX 0 |
|---|
| 2025 | #define regSDMA1_RLC7_RB_BASE_HI 0x099a |
|---|
| 2026 | #define regSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2027 | #define regSDMA1_RLC7_RB_RPTR 0x099b |
|---|
| 2028 | #define regSDMA1_RLC7_RB_RPTR_BASE_IDX 0 |
|---|
| 2029 | #define regSDMA1_RLC7_RB_RPTR_HI 0x099c |
|---|
| 2030 | #define regSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2031 | #define regSDMA1_RLC7_RB_WPTR 0x099d |
|---|
| 2032 | #define regSDMA1_RLC7_RB_WPTR_BASE_IDX 0 |
|---|
| 2033 | #define regSDMA1_RLC7_RB_WPTR_HI 0x099e |
|---|
| 2034 | #define regSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2035 | #define regSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x099f |
|---|
| 2036 | #define regSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2037 | #define regSDMA1_RLC7_RB_RPTR_ADDR_HI 0x09a0 |
|---|
| 2038 | #define regSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2039 | #define regSDMA1_RLC7_RB_RPTR_ADDR_LO 0x09a1 |
|---|
| 2040 | #define regSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2041 | #define regSDMA1_RLC7_IB_CNTL 0x09a2 |
|---|
| 2042 | #define regSDMA1_RLC7_IB_CNTL_BASE_IDX 0 |
|---|
| 2043 | #define regSDMA1_RLC7_IB_RPTR 0x09a3 |
|---|
| 2044 | #define regSDMA1_RLC7_IB_RPTR_BASE_IDX 0 |
|---|
| 2045 | #define regSDMA1_RLC7_IB_OFFSET 0x09a4 |
|---|
| 2046 | #define regSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 |
|---|
| 2047 | #define regSDMA1_RLC7_IB_BASE_LO 0x09a5 |
|---|
| 2048 | #define regSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2049 | #define regSDMA1_RLC7_IB_BASE_HI 0x09a6 |
|---|
| 2050 | #define regSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2051 | #define regSDMA1_RLC7_IB_SIZE 0x09a7 |
|---|
| 2052 | #define regSDMA1_RLC7_IB_SIZE_BASE_IDX 0 |
|---|
| 2053 | #define regSDMA1_RLC7_SKIP_CNTL 0x09a8 |
|---|
| 2054 | #define regSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2055 | #define regSDMA1_RLC7_CONTEXT_STATUS 0x09a9 |
|---|
| 2056 | #define regSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2057 | #define regSDMA1_RLC7_DOORBELL 0x09aa |
|---|
| 2058 | #define regSDMA1_RLC7_DOORBELL_BASE_IDX 0 |
|---|
| 2059 | #define regSDMA1_RLC7_STATUS 0x09c0 |
|---|
| 2060 | #define regSDMA1_RLC7_STATUS_BASE_IDX 0 |
|---|
| 2061 | #define regSDMA1_RLC7_DOORBELL_LOG 0x09c1 |
|---|
| 2062 | #define regSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2063 | #define regSDMA1_RLC7_WATERMARK 0x09c2 |
|---|
| 2064 | #define regSDMA1_RLC7_WATERMARK_BASE_IDX 0 |
|---|
| 2065 | #define regSDMA1_RLC7_DOORBELL_OFFSET 0x09c3 |
|---|
| 2066 | #define regSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2067 | #define regSDMA1_RLC7_CSA_ADDR_LO 0x09c4 |
|---|
| 2068 | #define regSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2069 | #define regSDMA1_RLC7_CSA_ADDR_HI 0x09c5 |
|---|
| 2070 | #define regSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2071 | #define regSDMA1_RLC7_IB_SUB_REMAIN 0x09c7 |
|---|
| 2072 | #define regSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2073 | #define regSDMA1_RLC7_PREEMPT 0x09c8 |
|---|
| 2074 | #define regSDMA1_RLC7_PREEMPT_BASE_IDX 0 |
|---|
| 2075 | #define regSDMA1_RLC7_DUMMY_REG 0x09c9 |
|---|
| 2076 | #define regSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 |
|---|
| 2077 | #define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x09ca |
|---|
| 2078 | #define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2079 | #define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x09cb |
|---|
| 2080 | #define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2081 | #define regSDMA1_RLC7_RB_AQL_CNTL 0x09cc |
|---|
| 2082 | #define regSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2083 | #define regSDMA1_RLC7_MINOR_PTR_UPDATE 0x09cd |
|---|
| 2084 | #define regSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2085 | #define regSDMA1_RLC7_MIDCMD_DATA0 0x09d8 |
|---|
| 2086 | #define regSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2087 | #define regSDMA1_RLC7_MIDCMD_DATA1 0x09d9 |
|---|
| 2088 | #define regSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2089 | #define regSDMA1_RLC7_MIDCMD_DATA2 0x09da |
|---|
| 2090 | #define regSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2091 | #define regSDMA1_RLC7_MIDCMD_DATA3 0x09db |
|---|
| 2092 | #define regSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2093 | #define regSDMA1_RLC7_MIDCMD_DATA4 0x09dc |
|---|
| 2094 | #define regSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2095 | #define regSDMA1_RLC7_MIDCMD_DATA5 0x09dd |
|---|
| 2096 | #define regSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2097 | #define regSDMA1_RLC7_MIDCMD_DATA6 0x09de |
|---|
| 2098 | #define regSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2099 | #define regSDMA1_RLC7_MIDCMD_DATA7 0x09df |
|---|
| 2100 | #define regSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2101 | #define regSDMA1_RLC7_MIDCMD_DATA8 0x09e0 |
|---|
| 2102 | #define regSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2103 | #define regSDMA1_RLC7_MIDCMD_DATA9 0x09e1 |
|---|
| 2104 | #define regSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2105 | #define regSDMA1_RLC7_MIDCMD_DATA10 0x09e2 |
|---|
| 2106 | #define regSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2107 | #define regSDMA1_RLC7_MIDCMD_CNTL 0x09e3 |
|---|
| 2108 | #define regSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2109 | |
|---|
| 2110 | |
|---|
| 2111 | // addressBlock: sdma0_sdma2dec |
|---|
| 2112 | // base address: 0x78000 |
|---|
| 2113 | #define regSDMA2_UCODE_ADDR 0x1cda0 |
|---|
| 2114 | #define regSDMA2_UCODE_ADDR_BASE_IDX 0 |
|---|
| 2115 | #define regSDMA2_UCODE_DATA 0x1cda1 |
|---|
| 2116 | #define regSDMA2_UCODE_DATA_BASE_IDX 0 |
|---|
| 2117 | #define regSDMA2_VF_ENABLE 0x1cdaa |
|---|
| 2118 | #define regSDMA2_VF_ENABLE_BASE_IDX 0 |
|---|
| 2119 | #define regSDMA2_CONTEXT_GROUP_BOUNDARY 0x1cdb9 |
|---|
| 2120 | #define regSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
|---|
| 2121 | #define regSDMA2_POWER_CNTL 0x1cdba |
|---|
| 2122 | #define regSDMA2_POWER_CNTL_BASE_IDX 0 |
|---|
| 2123 | #define regSDMA2_CLK_CTRL 0x1cdbb |
|---|
| 2124 | #define regSDMA2_CLK_CTRL_BASE_IDX 0 |
|---|
| 2125 | #define regSDMA2_CNTL 0x1cdbc |
|---|
| 2126 | #define regSDMA2_CNTL_BASE_IDX 0 |
|---|
| 2127 | #define regSDMA2_CHICKEN_BITS 0x1cdbd |
|---|
| 2128 | #define regSDMA2_CHICKEN_BITS_BASE_IDX 0 |
|---|
| 2129 | #define regSDMA2_GB_ADDR_CONFIG 0x1cdbe |
|---|
| 2130 | #define regSDMA2_GB_ADDR_CONFIG_BASE_IDX 0 |
|---|
| 2131 | #define regSDMA2_GB_ADDR_CONFIG_READ 0x1cdbf |
|---|
| 2132 | #define regSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
|---|
| 2133 | #define regSDMA2_RB_RPTR_FETCH_HI 0x1cdc0 |
|---|
| 2134 | #define regSDMA2_RB_RPTR_FETCH_HI_BASE_IDX 0 |
|---|
| 2135 | #define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0x1cdc1 |
|---|
| 2136 | #define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
|---|
| 2137 | #define regSDMA2_RB_RPTR_FETCH 0x1cdc2 |
|---|
| 2138 | #define regSDMA2_RB_RPTR_FETCH_BASE_IDX 0 |
|---|
| 2139 | #define regSDMA2_IB_OFFSET_FETCH 0x1cdc3 |
|---|
| 2140 | #define regSDMA2_IB_OFFSET_FETCH_BASE_IDX 0 |
|---|
| 2141 | #define regSDMA2_PROGRAM 0x1cdc4 |
|---|
| 2142 | #define regSDMA2_PROGRAM_BASE_IDX 0 |
|---|
| 2143 | #define regSDMA2_STATUS_REG 0x1cdc5 |
|---|
| 2144 | #define regSDMA2_STATUS_REG_BASE_IDX 0 |
|---|
| 2145 | #define regSDMA2_STATUS1_REG 0x1cdc6 |
|---|
| 2146 | #define regSDMA2_STATUS1_REG_BASE_IDX 0 |
|---|
| 2147 | #define regSDMA2_RD_BURST_CNTL 0x1cdc7 |
|---|
| 2148 | #define regSDMA2_RD_BURST_CNTL_BASE_IDX 0 |
|---|
| 2149 | #define regSDMA2_HBM_PAGE_CONFIG 0x1cdc8 |
|---|
| 2150 | #define regSDMA2_HBM_PAGE_CONFIG_BASE_IDX 0 |
|---|
| 2151 | #define regSDMA2_UCODE_CHECKSUM 0x1cdc9 |
|---|
| 2152 | #define regSDMA2_UCODE_CHECKSUM_BASE_IDX 0 |
|---|
| 2153 | #define regSDMA2_F32_CNTL 0x1cdca |
|---|
| 2154 | #define regSDMA2_F32_CNTL_BASE_IDX 0 |
|---|
| 2155 | #define regSDMA2_FREEZE 0x1cdcb |
|---|
| 2156 | #define regSDMA2_FREEZE_BASE_IDX 0 |
|---|
| 2157 | #define regSDMA2_PHASE0_QUANTUM 0x1cdcc |
|---|
| 2158 | #define regSDMA2_PHASE0_QUANTUM_BASE_IDX 0 |
|---|
| 2159 | #define regSDMA2_PHASE1_QUANTUM 0x1cdcd |
|---|
| 2160 | #define regSDMA2_PHASE1_QUANTUM_BASE_IDX 0 |
|---|
| 2161 | #define regCC_SDMA2_EDC_CONFIG 0x1cdd2 |
|---|
| 2162 | #define regCC_SDMA2_EDC_CONFIG_BASE_IDX 0 |
|---|
| 2163 | #define regSDMA2_BA_THRESHOLD 0x1cdd3 |
|---|
| 2164 | #define regSDMA2_BA_THRESHOLD_BASE_IDX 0 |
|---|
| 2165 | #define regSDMA2_ID 0x1cdd4 |
|---|
| 2166 | #define regSDMA2_ID_BASE_IDX 0 |
|---|
| 2167 | #define regSDMA2_VERSION 0x1cdd5 |
|---|
| 2168 | #define regSDMA2_VERSION_BASE_IDX 0 |
|---|
| 2169 | #define regSDMA2_EDC_COUNTER 0x1cdd6 |
|---|
| 2170 | #define regSDMA2_EDC_COUNTER_BASE_IDX 0 |
|---|
| 2171 | #define regSDMA2_EDC_COUNTER2 0x1cdd7 |
|---|
| 2172 | #define regSDMA2_EDC_COUNTER2_BASE_IDX 0 |
|---|
| 2173 | #define regSDMA2_STATUS2_REG 0x1cdd8 |
|---|
| 2174 | #define regSDMA2_STATUS2_REG_BASE_IDX 0 |
|---|
| 2175 | #define regSDMA2_ATOMIC_CNTL 0x1cdd9 |
|---|
| 2176 | #define regSDMA2_ATOMIC_CNTL_BASE_IDX 0 |
|---|
| 2177 | #define regSDMA2_ATOMIC_PREOP_LO 0x1cdda |
|---|
| 2178 | #define regSDMA2_ATOMIC_PREOP_LO_BASE_IDX 0 |
|---|
| 2179 | #define regSDMA2_ATOMIC_PREOP_HI 0x1cddb |
|---|
| 2180 | #define regSDMA2_ATOMIC_PREOP_HI_BASE_IDX 0 |
|---|
| 2181 | #define regSDMA2_UTCL1_CNTL 0x1cddc |
|---|
| 2182 | #define regSDMA2_UTCL1_CNTL_BASE_IDX 0 |
|---|
| 2183 | #define regSDMA2_UTCL1_WATERMK 0x1cddd |
|---|
| 2184 | #define regSDMA2_UTCL1_WATERMK_BASE_IDX 0 |
|---|
| 2185 | #define regSDMA2_UTCL1_RD_STATUS 0x1cdde |
|---|
| 2186 | #define regSDMA2_UTCL1_RD_STATUS_BASE_IDX 0 |
|---|
| 2187 | #define regSDMA2_UTCL1_WR_STATUS 0x1cddf |
|---|
| 2188 | #define regSDMA2_UTCL1_WR_STATUS_BASE_IDX 0 |
|---|
| 2189 | #define regSDMA2_UTCL1_INV0 0x1cde0 |
|---|
| 2190 | #define regSDMA2_UTCL1_INV0_BASE_IDX 0 |
|---|
| 2191 | #define regSDMA2_UTCL1_INV1 0x1cde1 |
|---|
| 2192 | #define regSDMA2_UTCL1_INV1_BASE_IDX 0 |
|---|
| 2193 | #define regSDMA2_UTCL1_INV2 0x1cde2 |
|---|
| 2194 | #define regSDMA2_UTCL1_INV2_BASE_IDX 0 |
|---|
| 2195 | #define regSDMA2_UTCL1_RD_XNACK0 0x1cde3 |
|---|
| 2196 | #define regSDMA2_UTCL1_RD_XNACK0_BASE_IDX 0 |
|---|
| 2197 | #define regSDMA2_UTCL1_RD_XNACK1 0x1cde4 |
|---|
| 2198 | #define regSDMA2_UTCL1_RD_XNACK1_BASE_IDX 0 |
|---|
| 2199 | #define regSDMA2_UTCL1_WR_XNACK0 0x1cde5 |
|---|
| 2200 | #define regSDMA2_UTCL1_WR_XNACK0_BASE_IDX 0 |
|---|
| 2201 | #define regSDMA2_UTCL1_WR_XNACK1 0x1cde6 |
|---|
| 2202 | #define regSDMA2_UTCL1_WR_XNACK1_BASE_IDX 0 |
|---|
| 2203 | #define regSDMA2_UTCL1_TIMEOUT 0x1cde7 |
|---|
| 2204 | #define regSDMA2_UTCL1_TIMEOUT_BASE_IDX 0 |
|---|
| 2205 | #define regSDMA2_UTCL1_PAGE 0x1cde8 |
|---|
| 2206 | #define regSDMA2_UTCL1_PAGE_BASE_IDX 0 |
|---|
| 2207 | #define regSDMA2_POWER_CNTL_IDLE 0x1cde9 |
|---|
| 2208 | #define regSDMA2_POWER_CNTL_IDLE_BASE_IDX 0 |
|---|
| 2209 | #define regSDMA2_RELAX_ORDERING_LUT 0x1cdea |
|---|
| 2210 | #define regSDMA2_RELAX_ORDERING_LUT_BASE_IDX 0 |
|---|
| 2211 | #define regSDMA2_CHICKEN_BITS_2 0x1cdeb |
|---|
| 2212 | #define regSDMA2_CHICKEN_BITS_2_BASE_IDX 0 |
|---|
| 2213 | #define regSDMA2_STATUS3_REG 0x1cdec |
|---|
| 2214 | #define regSDMA2_STATUS3_REG_BASE_IDX 0 |
|---|
| 2215 | #define regSDMA2_PHYSICAL_ADDR_LO 0x1cded |
|---|
| 2216 | #define regSDMA2_PHYSICAL_ADDR_LO_BASE_IDX 0 |
|---|
| 2217 | #define regSDMA2_PHYSICAL_ADDR_HI 0x1cdee |
|---|
| 2218 | #define regSDMA2_PHYSICAL_ADDR_HI_BASE_IDX 0 |
|---|
| 2219 | #define regSDMA2_PHASE2_QUANTUM 0x1cdef |
|---|
| 2220 | #define regSDMA2_PHASE2_QUANTUM_BASE_IDX 0 |
|---|
| 2221 | #define regSDMA2_ERROR_LOG 0x1cdf0 |
|---|
| 2222 | #define regSDMA2_ERROR_LOG_BASE_IDX 0 |
|---|
| 2223 | #define regSDMA2_PUB_DUMMY_REG0 0x1cdf1 |
|---|
| 2224 | #define regSDMA2_PUB_DUMMY_REG0_BASE_IDX 0 |
|---|
| 2225 | #define regSDMA2_PUB_DUMMY_REG1 0x1cdf2 |
|---|
| 2226 | #define regSDMA2_PUB_DUMMY_REG1_BASE_IDX 0 |
|---|
| 2227 | #define regSDMA2_PUB_DUMMY_REG2 0x1cdf3 |
|---|
| 2228 | #define regSDMA2_PUB_DUMMY_REG2_BASE_IDX 0 |
|---|
| 2229 | #define regSDMA2_PUB_DUMMY_REG3 0x1cdf4 |
|---|
| 2230 | #define regSDMA2_PUB_DUMMY_REG3_BASE_IDX 0 |
|---|
| 2231 | #define regSDMA2_F32_COUNTER 0x1cdf5 |
|---|
| 2232 | #define regSDMA2_F32_COUNTER_BASE_IDX 0 |
|---|
| 2233 | #define regSDMA2_PERFCNT_PERFCOUNTER0_CFG 0x1cdf7 |
|---|
| 2234 | #define regSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 |
|---|
| 2235 | #define regSDMA2_PERFCNT_PERFCOUNTER1_CFG 0x1cdf8 |
|---|
| 2236 | #define regSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 |
|---|
| 2237 | #define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1cdf9 |
|---|
| 2238 | #define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
|---|
| 2239 | #define regSDMA2_PERFCNT_MISC_CNTL 0x1cdfa |
|---|
| 2240 | #define regSDMA2_PERFCNT_MISC_CNTL_BASE_IDX 0 |
|---|
| 2241 | #define regSDMA2_PERFCNT_PERFCOUNTER_LO 0x1cdfb |
|---|
| 2242 | #define regSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 |
|---|
| 2243 | #define regSDMA2_PERFCNT_PERFCOUNTER_HI 0x1cdfc |
|---|
| 2244 | #define regSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 |
|---|
| 2245 | #define regSDMA2_CRD_CNTL 0x1cdfd |
|---|
| 2246 | #define regSDMA2_CRD_CNTL_BASE_IDX 0 |
|---|
| 2247 | #define regSDMA2_ULV_CNTL 0x1cdff |
|---|
| 2248 | #define regSDMA2_ULV_CNTL_BASE_IDX 0 |
|---|
| 2249 | #define regSDMA2_EA_DBIT_ADDR_DATA 0x1ce00 |
|---|
| 2250 | #define regSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
|---|
| 2251 | #define regSDMA2_EA_DBIT_ADDR_INDEX 0x1ce01 |
|---|
| 2252 | #define regSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
|---|
| 2253 | #define regSDMA2_STATUS4_REG 0x1ce03 |
|---|
| 2254 | #define regSDMA2_STATUS4_REG_BASE_IDX 0 |
|---|
| 2255 | #define regSDMA2_SCRATCH_RAM_DATA 0x1ce04 |
|---|
| 2256 | #define regSDMA2_SCRATCH_RAM_DATA_BASE_IDX 0 |
|---|
| 2257 | #define regSDMA2_SCRATCH_RAM_ADDR 0x1ce05 |
|---|
| 2258 | #define regSDMA2_SCRATCH_RAM_ADDR_BASE_IDX 0 |
|---|
| 2259 | #define regSDMA2_CE_CTRL 0x1ce06 |
|---|
| 2260 | #define regSDMA2_CE_CTRL_BASE_IDX 0 |
|---|
| 2261 | #define regSDMA2_RAS_STATUS 0x1ce07 |
|---|
| 2262 | #define regSDMA2_RAS_STATUS_BASE_IDX 0 |
|---|
| 2263 | #define regSDMA2_CLK_STATUS 0x1ce08 |
|---|
| 2264 | #define regSDMA2_CLK_STATUS_BASE_IDX 0 |
|---|
| 2265 | #define regSDMA2_GFX_RB_CNTL 0x1ce20 |
|---|
| 2266 | #define regSDMA2_GFX_RB_CNTL_BASE_IDX 0 |
|---|
| 2267 | #define regSDMA2_GFX_RB_BASE 0x1ce21 |
|---|
| 2268 | #define regSDMA2_GFX_RB_BASE_BASE_IDX 0 |
|---|
| 2269 | #define regSDMA2_GFX_RB_BASE_HI 0x1ce22 |
|---|
| 2270 | #define regSDMA2_GFX_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2271 | #define regSDMA2_GFX_RB_RPTR 0x1ce23 |
|---|
| 2272 | #define regSDMA2_GFX_RB_RPTR_BASE_IDX 0 |
|---|
| 2273 | #define regSDMA2_GFX_RB_RPTR_HI 0x1ce24 |
|---|
| 2274 | #define regSDMA2_GFX_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2275 | #define regSDMA2_GFX_RB_WPTR 0x1ce25 |
|---|
| 2276 | #define regSDMA2_GFX_RB_WPTR_BASE_IDX 0 |
|---|
| 2277 | #define regSDMA2_GFX_RB_WPTR_HI 0x1ce26 |
|---|
| 2278 | #define regSDMA2_GFX_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2279 | #define regSDMA2_GFX_RB_WPTR_POLL_CNTL 0x1ce27 |
|---|
| 2280 | #define regSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2281 | #define regSDMA2_GFX_RB_RPTR_ADDR_HI 0x1ce28 |
|---|
| 2282 | #define regSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2283 | #define regSDMA2_GFX_RB_RPTR_ADDR_LO 0x1ce29 |
|---|
| 2284 | #define regSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2285 | #define regSDMA2_GFX_IB_CNTL 0x1ce2a |
|---|
| 2286 | #define regSDMA2_GFX_IB_CNTL_BASE_IDX 0 |
|---|
| 2287 | #define regSDMA2_GFX_IB_RPTR 0x1ce2b |
|---|
| 2288 | #define regSDMA2_GFX_IB_RPTR_BASE_IDX 0 |
|---|
| 2289 | #define regSDMA2_GFX_IB_OFFSET 0x1ce2c |
|---|
| 2290 | #define regSDMA2_GFX_IB_OFFSET_BASE_IDX 0 |
|---|
| 2291 | #define regSDMA2_GFX_IB_BASE_LO 0x1ce2d |
|---|
| 2292 | #define regSDMA2_GFX_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2293 | #define regSDMA2_GFX_IB_BASE_HI 0x1ce2e |
|---|
| 2294 | #define regSDMA2_GFX_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2295 | #define regSDMA2_GFX_IB_SIZE 0x1ce2f |
|---|
| 2296 | #define regSDMA2_GFX_IB_SIZE_BASE_IDX 0 |
|---|
| 2297 | #define regSDMA2_GFX_SKIP_CNTL 0x1ce30 |
|---|
| 2298 | #define regSDMA2_GFX_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2299 | #define regSDMA2_GFX_CONTEXT_STATUS 0x1ce31 |
|---|
| 2300 | #define regSDMA2_GFX_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2301 | #define regSDMA2_GFX_DOORBELL 0x1ce32 |
|---|
| 2302 | #define regSDMA2_GFX_DOORBELL_BASE_IDX 0 |
|---|
| 2303 | #define regSDMA2_GFX_CONTEXT_CNTL 0x1ce33 |
|---|
| 2304 | #define regSDMA2_GFX_CONTEXT_CNTL_BASE_IDX 0 |
|---|
| 2305 | #define regSDMA2_GFX_STATUS 0x1ce48 |
|---|
| 2306 | #define regSDMA2_GFX_STATUS_BASE_IDX 0 |
|---|
| 2307 | #define regSDMA2_GFX_DOORBELL_LOG 0x1ce49 |
|---|
| 2308 | #define regSDMA2_GFX_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2309 | #define regSDMA2_GFX_WATERMARK 0x1ce4a |
|---|
| 2310 | #define regSDMA2_GFX_WATERMARK_BASE_IDX 0 |
|---|
| 2311 | #define regSDMA2_GFX_DOORBELL_OFFSET 0x1ce4b |
|---|
| 2312 | #define regSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2313 | #define regSDMA2_GFX_CSA_ADDR_LO 0x1ce4c |
|---|
| 2314 | #define regSDMA2_GFX_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2315 | #define regSDMA2_GFX_CSA_ADDR_HI 0x1ce4d |
|---|
| 2316 | #define regSDMA2_GFX_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2317 | #define regSDMA2_GFX_IB_SUB_REMAIN 0x1ce4f |
|---|
| 2318 | #define regSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2319 | #define regSDMA2_GFX_PREEMPT 0x1ce50 |
|---|
| 2320 | #define regSDMA2_GFX_PREEMPT_BASE_IDX 0 |
|---|
| 2321 | #define regSDMA2_GFX_DUMMY_REG 0x1ce51 |
|---|
| 2322 | #define regSDMA2_GFX_DUMMY_REG_BASE_IDX 0 |
|---|
| 2323 | #define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0x1ce52 |
|---|
| 2324 | #define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2325 | #define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0x1ce53 |
|---|
| 2326 | #define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2327 | #define regSDMA2_GFX_RB_AQL_CNTL 0x1ce54 |
|---|
| 2328 | #define regSDMA2_GFX_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2329 | #define regSDMA2_GFX_MINOR_PTR_UPDATE 0x1ce55 |
|---|
| 2330 | #define regSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2331 | #define regSDMA2_GFX_MIDCMD_DATA0 0x1ce60 |
|---|
| 2332 | #define regSDMA2_GFX_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2333 | #define regSDMA2_GFX_MIDCMD_DATA1 0x1ce61 |
|---|
| 2334 | #define regSDMA2_GFX_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2335 | #define regSDMA2_GFX_MIDCMD_DATA2 0x1ce62 |
|---|
| 2336 | #define regSDMA2_GFX_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2337 | #define regSDMA2_GFX_MIDCMD_DATA3 0x1ce63 |
|---|
| 2338 | #define regSDMA2_GFX_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2339 | #define regSDMA2_GFX_MIDCMD_DATA4 0x1ce64 |
|---|
| 2340 | #define regSDMA2_GFX_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2341 | #define regSDMA2_GFX_MIDCMD_DATA5 0x1ce65 |
|---|
| 2342 | #define regSDMA2_GFX_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2343 | #define regSDMA2_GFX_MIDCMD_DATA6 0x1ce66 |
|---|
| 2344 | #define regSDMA2_GFX_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2345 | #define regSDMA2_GFX_MIDCMD_DATA7 0x1ce67 |
|---|
| 2346 | #define regSDMA2_GFX_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2347 | #define regSDMA2_GFX_MIDCMD_DATA8 0x1ce68 |
|---|
| 2348 | #define regSDMA2_GFX_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2349 | #define regSDMA2_GFX_MIDCMD_DATA9 0x1ce69 |
|---|
| 2350 | #define regSDMA2_GFX_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2351 | #define regSDMA2_GFX_MIDCMD_DATA10 0x1ce6a |
|---|
| 2352 | #define regSDMA2_GFX_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2353 | #define regSDMA2_GFX_MIDCMD_CNTL 0x1ce6b |
|---|
| 2354 | #define regSDMA2_GFX_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2355 | #define regSDMA2_PAGE_RB_CNTL 0x1ce78 |
|---|
| 2356 | #define regSDMA2_PAGE_RB_CNTL_BASE_IDX 0 |
|---|
| 2357 | #define regSDMA2_PAGE_RB_BASE 0x1ce79 |
|---|
| 2358 | #define regSDMA2_PAGE_RB_BASE_BASE_IDX 0 |
|---|
| 2359 | #define regSDMA2_PAGE_RB_BASE_HI 0x1ce7a |
|---|
| 2360 | #define regSDMA2_PAGE_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2361 | #define regSDMA2_PAGE_RB_RPTR 0x1ce7b |
|---|
| 2362 | #define regSDMA2_PAGE_RB_RPTR_BASE_IDX 0 |
|---|
| 2363 | #define regSDMA2_PAGE_RB_RPTR_HI 0x1ce7c |
|---|
| 2364 | #define regSDMA2_PAGE_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2365 | #define regSDMA2_PAGE_RB_WPTR 0x1ce7d |
|---|
| 2366 | #define regSDMA2_PAGE_RB_WPTR_BASE_IDX 0 |
|---|
| 2367 | #define regSDMA2_PAGE_RB_WPTR_HI 0x1ce7e |
|---|
| 2368 | #define regSDMA2_PAGE_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2369 | #define regSDMA2_PAGE_RB_WPTR_POLL_CNTL 0x1ce7f |
|---|
| 2370 | #define regSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2371 | #define regSDMA2_PAGE_RB_RPTR_ADDR_HI 0x1ce80 |
|---|
| 2372 | #define regSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2373 | #define regSDMA2_PAGE_RB_RPTR_ADDR_LO 0x1ce81 |
|---|
| 2374 | #define regSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2375 | #define regSDMA2_PAGE_IB_CNTL 0x1ce82 |
|---|
| 2376 | #define regSDMA2_PAGE_IB_CNTL_BASE_IDX 0 |
|---|
| 2377 | #define regSDMA2_PAGE_IB_RPTR 0x1ce83 |
|---|
| 2378 | #define regSDMA2_PAGE_IB_RPTR_BASE_IDX 0 |
|---|
| 2379 | #define regSDMA2_PAGE_IB_OFFSET 0x1ce84 |
|---|
| 2380 | #define regSDMA2_PAGE_IB_OFFSET_BASE_IDX 0 |
|---|
| 2381 | #define regSDMA2_PAGE_IB_BASE_LO 0x1ce85 |
|---|
| 2382 | #define regSDMA2_PAGE_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2383 | #define regSDMA2_PAGE_IB_BASE_HI 0x1ce86 |
|---|
| 2384 | #define regSDMA2_PAGE_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2385 | #define regSDMA2_PAGE_IB_SIZE 0x1ce87 |
|---|
| 2386 | #define regSDMA2_PAGE_IB_SIZE_BASE_IDX 0 |
|---|
| 2387 | #define regSDMA2_PAGE_SKIP_CNTL 0x1ce88 |
|---|
| 2388 | #define regSDMA2_PAGE_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2389 | #define regSDMA2_PAGE_CONTEXT_STATUS 0x1ce89 |
|---|
| 2390 | #define regSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2391 | #define regSDMA2_PAGE_DOORBELL 0x1ce8a |
|---|
| 2392 | #define regSDMA2_PAGE_DOORBELL_BASE_IDX 0 |
|---|
| 2393 | #define regSDMA2_PAGE_STATUS 0x1cea0 |
|---|
| 2394 | #define regSDMA2_PAGE_STATUS_BASE_IDX 0 |
|---|
| 2395 | #define regSDMA2_PAGE_DOORBELL_LOG 0x1cea1 |
|---|
| 2396 | #define regSDMA2_PAGE_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2397 | #define regSDMA2_PAGE_WATERMARK 0x1cea2 |
|---|
| 2398 | #define regSDMA2_PAGE_WATERMARK_BASE_IDX 0 |
|---|
| 2399 | #define regSDMA2_PAGE_DOORBELL_OFFSET 0x1cea3 |
|---|
| 2400 | #define regSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2401 | #define regSDMA2_PAGE_CSA_ADDR_LO 0x1cea4 |
|---|
| 2402 | #define regSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2403 | #define regSDMA2_PAGE_CSA_ADDR_HI 0x1cea5 |
|---|
| 2404 | #define regSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2405 | #define regSDMA2_PAGE_IB_SUB_REMAIN 0x1cea7 |
|---|
| 2406 | #define regSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2407 | #define regSDMA2_PAGE_PREEMPT 0x1cea8 |
|---|
| 2408 | #define regSDMA2_PAGE_PREEMPT_BASE_IDX 0 |
|---|
| 2409 | #define regSDMA2_PAGE_DUMMY_REG 0x1cea9 |
|---|
| 2410 | #define regSDMA2_PAGE_DUMMY_REG_BASE_IDX 0 |
|---|
| 2411 | #define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0x1ceaa |
|---|
| 2412 | #define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2413 | #define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0x1ceab |
|---|
| 2414 | #define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2415 | #define regSDMA2_PAGE_RB_AQL_CNTL 0x1ceac |
|---|
| 2416 | #define regSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2417 | #define regSDMA2_PAGE_MINOR_PTR_UPDATE 0x1cead |
|---|
| 2418 | #define regSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2419 | #define regSDMA2_PAGE_MIDCMD_DATA0 0x1ceb8 |
|---|
| 2420 | #define regSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2421 | #define regSDMA2_PAGE_MIDCMD_DATA1 0x1ceb9 |
|---|
| 2422 | #define regSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2423 | #define regSDMA2_PAGE_MIDCMD_DATA2 0x1ceba |
|---|
| 2424 | #define regSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2425 | #define regSDMA2_PAGE_MIDCMD_DATA3 0x1cebb |
|---|
| 2426 | #define regSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2427 | #define regSDMA2_PAGE_MIDCMD_DATA4 0x1cebc |
|---|
| 2428 | #define regSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2429 | #define regSDMA2_PAGE_MIDCMD_DATA5 0x1cebd |
|---|
| 2430 | #define regSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2431 | #define regSDMA2_PAGE_MIDCMD_DATA6 0x1cebe |
|---|
| 2432 | #define regSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2433 | #define regSDMA2_PAGE_MIDCMD_DATA7 0x1cebf |
|---|
| 2434 | #define regSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2435 | #define regSDMA2_PAGE_MIDCMD_DATA8 0x1cec0 |
|---|
| 2436 | #define regSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2437 | #define regSDMA2_PAGE_MIDCMD_DATA9 0x1cec1 |
|---|
| 2438 | #define regSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2439 | #define regSDMA2_PAGE_MIDCMD_DATA10 0x1cec2 |
|---|
| 2440 | #define regSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2441 | #define regSDMA2_PAGE_MIDCMD_CNTL 0x1cec3 |
|---|
| 2442 | #define regSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2443 | #define regSDMA2_RLC0_RB_CNTL 0x1ced0 |
|---|
| 2444 | #define regSDMA2_RLC0_RB_CNTL_BASE_IDX 0 |
|---|
| 2445 | #define regSDMA2_RLC0_RB_BASE 0x1ced1 |
|---|
| 2446 | #define regSDMA2_RLC0_RB_BASE_BASE_IDX 0 |
|---|
| 2447 | #define regSDMA2_RLC0_RB_BASE_HI 0x1ced2 |
|---|
| 2448 | #define regSDMA2_RLC0_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2449 | #define regSDMA2_RLC0_RB_RPTR 0x1ced3 |
|---|
| 2450 | #define regSDMA2_RLC0_RB_RPTR_BASE_IDX 0 |
|---|
| 2451 | #define regSDMA2_RLC0_RB_RPTR_HI 0x1ced4 |
|---|
| 2452 | #define regSDMA2_RLC0_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2453 | #define regSDMA2_RLC0_RB_WPTR 0x1ced5 |
|---|
| 2454 | #define regSDMA2_RLC0_RB_WPTR_BASE_IDX 0 |
|---|
| 2455 | #define regSDMA2_RLC0_RB_WPTR_HI 0x1ced6 |
|---|
| 2456 | #define regSDMA2_RLC0_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2457 | #define regSDMA2_RLC0_RB_WPTR_POLL_CNTL 0x1ced7 |
|---|
| 2458 | #define regSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2459 | #define regSDMA2_RLC0_RB_RPTR_ADDR_HI 0x1ced8 |
|---|
| 2460 | #define regSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2461 | #define regSDMA2_RLC0_RB_RPTR_ADDR_LO 0x1ced9 |
|---|
| 2462 | #define regSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2463 | #define regSDMA2_RLC0_IB_CNTL 0x1ceda |
|---|
| 2464 | #define regSDMA2_RLC0_IB_CNTL_BASE_IDX 0 |
|---|
| 2465 | #define regSDMA2_RLC0_IB_RPTR 0x1cedb |
|---|
| 2466 | #define regSDMA2_RLC0_IB_RPTR_BASE_IDX 0 |
|---|
| 2467 | #define regSDMA2_RLC0_IB_OFFSET 0x1cedc |
|---|
| 2468 | #define regSDMA2_RLC0_IB_OFFSET_BASE_IDX 0 |
|---|
| 2469 | #define regSDMA2_RLC0_IB_BASE_LO 0x1cedd |
|---|
| 2470 | #define regSDMA2_RLC0_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2471 | #define regSDMA2_RLC0_IB_BASE_HI 0x1cede |
|---|
| 2472 | #define regSDMA2_RLC0_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2473 | #define regSDMA2_RLC0_IB_SIZE 0x1cedf |
|---|
| 2474 | #define regSDMA2_RLC0_IB_SIZE_BASE_IDX 0 |
|---|
| 2475 | #define regSDMA2_RLC0_SKIP_CNTL 0x1cee0 |
|---|
| 2476 | #define regSDMA2_RLC0_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2477 | #define regSDMA2_RLC0_CONTEXT_STATUS 0x1cee1 |
|---|
| 2478 | #define regSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2479 | #define regSDMA2_RLC0_DOORBELL 0x1cee2 |
|---|
| 2480 | #define regSDMA2_RLC0_DOORBELL_BASE_IDX 0 |
|---|
| 2481 | #define regSDMA2_RLC0_STATUS 0x1cef8 |
|---|
| 2482 | #define regSDMA2_RLC0_STATUS_BASE_IDX 0 |
|---|
| 2483 | #define regSDMA2_RLC0_DOORBELL_LOG 0x1cef9 |
|---|
| 2484 | #define regSDMA2_RLC0_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2485 | #define regSDMA2_RLC0_WATERMARK 0x1cefa |
|---|
| 2486 | #define regSDMA2_RLC0_WATERMARK_BASE_IDX 0 |
|---|
| 2487 | #define regSDMA2_RLC0_DOORBELL_OFFSET 0x1cefb |
|---|
| 2488 | #define regSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2489 | #define regSDMA2_RLC0_CSA_ADDR_LO 0x1cefc |
|---|
| 2490 | #define regSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2491 | #define regSDMA2_RLC0_CSA_ADDR_HI 0x1cefd |
|---|
| 2492 | #define regSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2493 | #define regSDMA2_RLC0_IB_SUB_REMAIN 0x1ceff |
|---|
| 2494 | #define regSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2495 | #define regSDMA2_RLC0_PREEMPT 0x1cf00 |
|---|
| 2496 | #define regSDMA2_RLC0_PREEMPT_BASE_IDX 0 |
|---|
| 2497 | #define regSDMA2_RLC0_DUMMY_REG 0x1cf01 |
|---|
| 2498 | #define regSDMA2_RLC0_DUMMY_REG_BASE_IDX 0 |
|---|
| 2499 | #define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0x1cf02 |
|---|
| 2500 | #define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2501 | #define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0x1cf03 |
|---|
| 2502 | #define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2503 | #define regSDMA2_RLC0_RB_AQL_CNTL 0x1cf04 |
|---|
| 2504 | #define regSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2505 | #define regSDMA2_RLC0_MINOR_PTR_UPDATE 0x1cf05 |
|---|
| 2506 | #define regSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2507 | #define regSDMA2_RLC0_MIDCMD_DATA0 0x1cf10 |
|---|
| 2508 | #define regSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2509 | #define regSDMA2_RLC0_MIDCMD_DATA1 0x1cf11 |
|---|
| 2510 | #define regSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2511 | #define regSDMA2_RLC0_MIDCMD_DATA2 0x1cf12 |
|---|
| 2512 | #define regSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2513 | #define regSDMA2_RLC0_MIDCMD_DATA3 0x1cf13 |
|---|
| 2514 | #define regSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2515 | #define regSDMA2_RLC0_MIDCMD_DATA4 0x1cf14 |
|---|
| 2516 | #define regSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2517 | #define regSDMA2_RLC0_MIDCMD_DATA5 0x1cf15 |
|---|
| 2518 | #define regSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2519 | #define regSDMA2_RLC0_MIDCMD_DATA6 0x1cf16 |
|---|
| 2520 | #define regSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2521 | #define regSDMA2_RLC0_MIDCMD_DATA7 0x1cf17 |
|---|
| 2522 | #define regSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2523 | #define regSDMA2_RLC0_MIDCMD_DATA8 0x1cf18 |
|---|
| 2524 | #define regSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2525 | #define regSDMA2_RLC0_MIDCMD_DATA9 0x1cf19 |
|---|
| 2526 | #define regSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2527 | #define regSDMA2_RLC0_MIDCMD_DATA10 0x1cf1a |
|---|
| 2528 | #define regSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2529 | #define regSDMA2_RLC0_MIDCMD_CNTL 0x1cf1b |
|---|
| 2530 | #define regSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2531 | #define regSDMA2_RLC1_RB_CNTL 0x1cf28 |
|---|
| 2532 | #define regSDMA2_RLC1_RB_CNTL_BASE_IDX 0 |
|---|
| 2533 | #define regSDMA2_RLC1_RB_BASE 0x1cf29 |
|---|
| 2534 | #define regSDMA2_RLC1_RB_BASE_BASE_IDX 0 |
|---|
| 2535 | #define regSDMA2_RLC1_RB_BASE_HI 0x1cf2a |
|---|
| 2536 | #define regSDMA2_RLC1_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2537 | #define regSDMA2_RLC1_RB_RPTR 0x1cf2b |
|---|
| 2538 | #define regSDMA2_RLC1_RB_RPTR_BASE_IDX 0 |
|---|
| 2539 | #define regSDMA2_RLC1_RB_RPTR_HI 0x1cf2c |
|---|
| 2540 | #define regSDMA2_RLC1_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2541 | #define regSDMA2_RLC1_RB_WPTR 0x1cf2d |
|---|
| 2542 | #define regSDMA2_RLC1_RB_WPTR_BASE_IDX 0 |
|---|
| 2543 | #define regSDMA2_RLC1_RB_WPTR_HI 0x1cf2e |
|---|
| 2544 | #define regSDMA2_RLC1_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2545 | #define regSDMA2_RLC1_RB_WPTR_POLL_CNTL 0x1cf2f |
|---|
| 2546 | #define regSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2547 | #define regSDMA2_RLC1_RB_RPTR_ADDR_HI 0x1cf30 |
|---|
| 2548 | #define regSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2549 | #define regSDMA2_RLC1_RB_RPTR_ADDR_LO 0x1cf31 |
|---|
| 2550 | #define regSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2551 | #define regSDMA2_RLC1_IB_CNTL 0x1cf32 |
|---|
| 2552 | #define regSDMA2_RLC1_IB_CNTL_BASE_IDX 0 |
|---|
| 2553 | #define regSDMA2_RLC1_IB_RPTR 0x1cf33 |
|---|
| 2554 | #define regSDMA2_RLC1_IB_RPTR_BASE_IDX 0 |
|---|
| 2555 | #define regSDMA2_RLC1_IB_OFFSET 0x1cf34 |
|---|
| 2556 | #define regSDMA2_RLC1_IB_OFFSET_BASE_IDX 0 |
|---|
| 2557 | #define regSDMA2_RLC1_IB_BASE_LO 0x1cf35 |
|---|
| 2558 | #define regSDMA2_RLC1_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2559 | #define regSDMA2_RLC1_IB_BASE_HI 0x1cf36 |
|---|
| 2560 | #define regSDMA2_RLC1_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2561 | #define regSDMA2_RLC1_IB_SIZE 0x1cf37 |
|---|
| 2562 | #define regSDMA2_RLC1_IB_SIZE_BASE_IDX 0 |
|---|
| 2563 | #define regSDMA2_RLC1_SKIP_CNTL 0x1cf38 |
|---|
| 2564 | #define regSDMA2_RLC1_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2565 | #define regSDMA2_RLC1_CONTEXT_STATUS 0x1cf39 |
|---|
| 2566 | #define regSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2567 | #define regSDMA2_RLC1_DOORBELL 0x1cf3a |
|---|
| 2568 | #define regSDMA2_RLC1_DOORBELL_BASE_IDX 0 |
|---|
| 2569 | #define regSDMA2_RLC1_STATUS 0x1cf50 |
|---|
| 2570 | #define regSDMA2_RLC1_STATUS_BASE_IDX 0 |
|---|
| 2571 | #define regSDMA2_RLC1_DOORBELL_LOG 0x1cf51 |
|---|
| 2572 | #define regSDMA2_RLC1_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2573 | #define regSDMA2_RLC1_WATERMARK 0x1cf52 |
|---|
| 2574 | #define regSDMA2_RLC1_WATERMARK_BASE_IDX 0 |
|---|
| 2575 | #define regSDMA2_RLC1_DOORBELL_OFFSET 0x1cf53 |
|---|
| 2576 | #define regSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2577 | #define regSDMA2_RLC1_CSA_ADDR_LO 0x1cf54 |
|---|
| 2578 | #define regSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2579 | #define regSDMA2_RLC1_CSA_ADDR_HI 0x1cf55 |
|---|
| 2580 | #define regSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2581 | #define regSDMA2_RLC1_IB_SUB_REMAIN 0x1cf57 |
|---|
| 2582 | #define regSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2583 | #define regSDMA2_RLC1_PREEMPT 0x1cf58 |
|---|
| 2584 | #define regSDMA2_RLC1_PREEMPT_BASE_IDX 0 |
|---|
| 2585 | #define regSDMA2_RLC1_DUMMY_REG 0x1cf59 |
|---|
| 2586 | #define regSDMA2_RLC1_DUMMY_REG_BASE_IDX 0 |
|---|
| 2587 | #define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0x1cf5a |
|---|
| 2588 | #define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2589 | #define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0x1cf5b |
|---|
| 2590 | #define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2591 | #define regSDMA2_RLC1_RB_AQL_CNTL 0x1cf5c |
|---|
| 2592 | #define regSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2593 | #define regSDMA2_RLC1_MINOR_PTR_UPDATE 0x1cf5d |
|---|
| 2594 | #define regSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2595 | #define regSDMA2_RLC1_MIDCMD_DATA0 0x1cf68 |
|---|
| 2596 | #define regSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2597 | #define regSDMA2_RLC1_MIDCMD_DATA1 0x1cf69 |
|---|
| 2598 | #define regSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2599 | #define regSDMA2_RLC1_MIDCMD_DATA2 0x1cf6a |
|---|
| 2600 | #define regSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2601 | #define regSDMA2_RLC1_MIDCMD_DATA3 0x1cf6b |
|---|
| 2602 | #define regSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2603 | #define regSDMA2_RLC1_MIDCMD_DATA4 0x1cf6c |
|---|
| 2604 | #define regSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2605 | #define regSDMA2_RLC1_MIDCMD_DATA5 0x1cf6d |
|---|
| 2606 | #define regSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2607 | #define regSDMA2_RLC1_MIDCMD_DATA6 0x1cf6e |
|---|
| 2608 | #define regSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2609 | #define regSDMA2_RLC1_MIDCMD_DATA7 0x1cf6f |
|---|
| 2610 | #define regSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2611 | #define regSDMA2_RLC1_MIDCMD_DATA8 0x1cf70 |
|---|
| 2612 | #define regSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2613 | #define regSDMA2_RLC1_MIDCMD_DATA9 0x1cf71 |
|---|
| 2614 | #define regSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2615 | #define regSDMA2_RLC1_MIDCMD_DATA10 0x1cf72 |
|---|
| 2616 | #define regSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2617 | #define regSDMA2_RLC1_MIDCMD_CNTL 0x1cf73 |
|---|
| 2618 | #define regSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2619 | #define regSDMA2_RLC2_RB_CNTL 0x1cf80 |
|---|
| 2620 | #define regSDMA2_RLC2_RB_CNTL_BASE_IDX 0 |
|---|
| 2621 | #define regSDMA2_RLC2_RB_BASE 0x1cf81 |
|---|
| 2622 | #define regSDMA2_RLC2_RB_BASE_BASE_IDX 0 |
|---|
| 2623 | #define regSDMA2_RLC2_RB_BASE_HI 0x1cf82 |
|---|
| 2624 | #define regSDMA2_RLC2_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2625 | #define regSDMA2_RLC2_RB_RPTR 0x1cf83 |
|---|
| 2626 | #define regSDMA2_RLC2_RB_RPTR_BASE_IDX 0 |
|---|
| 2627 | #define regSDMA2_RLC2_RB_RPTR_HI 0x1cf84 |
|---|
| 2628 | #define regSDMA2_RLC2_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2629 | #define regSDMA2_RLC2_RB_WPTR 0x1cf85 |
|---|
| 2630 | #define regSDMA2_RLC2_RB_WPTR_BASE_IDX 0 |
|---|
| 2631 | #define regSDMA2_RLC2_RB_WPTR_HI 0x1cf86 |
|---|
| 2632 | #define regSDMA2_RLC2_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2633 | #define regSDMA2_RLC2_RB_WPTR_POLL_CNTL 0x1cf87 |
|---|
| 2634 | #define regSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2635 | #define regSDMA2_RLC2_RB_RPTR_ADDR_HI 0x1cf88 |
|---|
| 2636 | #define regSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2637 | #define regSDMA2_RLC2_RB_RPTR_ADDR_LO 0x1cf89 |
|---|
| 2638 | #define regSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2639 | #define regSDMA2_RLC2_IB_CNTL 0x1cf8a |
|---|
| 2640 | #define regSDMA2_RLC2_IB_CNTL_BASE_IDX 0 |
|---|
| 2641 | #define regSDMA2_RLC2_IB_RPTR 0x1cf8b |
|---|
| 2642 | #define regSDMA2_RLC2_IB_RPTR_BASE_IDX 0 |
|---|
| 2643 | #define regSDMA2_RLC2_IB_OFFSET 0x1cf8c |
|---|
| 2644 | #define regSDMA2_RLC2_IB_OFFSET_BASE_IDX 0 |
|---|
| 2645 | #define regSDMA2_RLC2_IB_BASE_LO 0x1cf8d |
|---|
| 2646 | #define regSDMA2_RLC2_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2647 | #define regSDMA2_RLC2_IB_BASE_HI 0x1cf8e |
|---|
| 2648 | #define regSDMA2_RLC2_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2649 | #define regSDMA2_RLC2_IB_SIZE 0x1cf8f |
|---|
| 2650 | #define regSDMA2_RLC2_IB_SIZE_BASE_IDX 0 |
|---|
| 2651 | #define regSDMA2_RLC2_SKIP_CNTL 0x1cf90 |
|---|
| 2652 | #define regSDMA2_RLC2_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2653 | #define regSDMA2_RLC2_CONTEXT_STATUS 0x1cf91 |
|---|
| 2654 | #define regSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2655 | #define regSDMA2_RLC2_DOORBELL 0x1cf92 |
|---|
| 2656 | #define regSDMA2_RLC2_DOORBELL_BASE_IDX 0 |
|---|
| 2657 | #define regSDMA2_RLC2_STATUS 0x1cfa8 |
|---|
| 2658 | #define regSDMA2_RLC2_STATUS_BASE_IDX 0 |
|---|
| 2659 | #define regSDMA2_RLC2_DOORBELL_LOG 0x1cfa9 |
|---|
| 2660 | #define regSDMA2_RLC2_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2661 | #define regSDMA2_RLC2_WATERMARK 0x1cfaa |
|---|
| 2662 | #define regSDMA2_RLC2_WATERMARK_BASE_IDX 0 |
|---|
| 2663 | #define regSDMA2_RLC2_DOORBELL_OFFSET 0x1cfab |
|---|
| 2664 | #define regSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2665 | #define regSDMA2_RLC2_CSA_ADDR_LO 0x1cfac |
|---|
| 2666 | #define regSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2667 | #define regSDMA2_RLC2_CSA_ADDR_HI 0x1cfad |
|---|
| 2668 | #define regSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2669 | #define regSDMA2_RLC2_IB_SUB_REMAIN 0x1cfaf |
|---|
| 2670 | #define regSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2671 | #define regSDMA2_RLC2_PREEMPT 0x1cfb0 |
|---|
| 2672 | #define regSDMA2_RLC2_PREEMPT_BASE_IDX 0 |
|---|
| 2673 | #define regSDMA2_RLC2_DUMMY_REG 0x1cfb1 |
|---|
| 2674 | #define regSDMA2_RLC2_DUMMY_REG_BASE_IDX 0 |
|---|
| 2675 | #define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0x1cfb2 |
|---|
| 2676 | #define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2677 | #define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0x1cfb3 |
|---|
| 2678 | #define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2679 | #define regSDMA2_RLC2_RB_AQL_CNTL 0x1cfb4 |
|---|
| 2680 | #define regSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2681 | #define regSDMA2_RLC2_MINOR_PTR_UPDATE 0x1cfb5 |
|---|
| 2682 | #define regSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2683 | #define regSDMA2_RLC2_MIDCMD_DATA0 0x1cfc0 |
|---|
| 2684 | #define regSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2685 | #define regSDMA2_RLC2_MIDCMD_DATA1 0x1cfc1 |
|---|
| 2686 | #define regSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2687 | #define regSDMA2_RLC2_MIDCMD_DATA2 0x1cfc2 |
|---|
| 2688 | #define regSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2689 | #define regSDMA2_RLC2_MIDCMD_DATA3 0x1cfc3 |
|---|
| 2690 | #define regSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2691 | #define regSDMA2_RLC2_MIDCMD_DATA4 0x1cfc4 |
|---|
| 2692 | #define regSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2693 | #define regSDMA2_RLC2_MIDCMD_DATA5 0x1cfc5 |
|---|
| 2694 | #define regSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2695 | #define regSDMA2_RLC2_MIDCMD_DATA6 0x1cfc6 |
|---|
| 2696 | #define regSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2697 | #define regSDMA2_RLC2_MIDCMD_DATA7 0x1cfc7 |
|---|
| 2698 | #define regSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2699 | #define regSDMA2_RLC2_MIDCMD_DATA8 0x1cfc8 |
|---|
| 2700 | #define regSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2701 | #define regSDMA2_RLC2_MIDCMD_DATA9 0x1cfc9 |
|---|
| 2702 | #define regSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2703 | #define regSDMA2_RLC2_MIDCMD_DATA10 0x1cfca |
|---|
| 2704 | #define regSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2705 | #define regSDMA2_RLC2_MIDCMD_CNTL 0x1cfcb |
|---|
| 2706 | #define regSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2707 | #define regSDMA2_RLC3_RB_CNTL 0x1cfd8 |
|---|
| 2708 | #define regSDMA2_RLC3_RB_CNTL_BASE_IDX 0 |
|---|
| 2709 | #define regSDMA2_RLC3_RB_BASE 0x1cfd9 |
|---|
| 2710 | #define regSDMA2_RLC3_RB_BASE_BASE_IDX 0 |
|---|
| 2711 | #define regSDMA2_RLC3_RB_BASE_HI 0x1cfda |
|---|
| 2712 | #define regSDMA2_RLC3_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2713 | #define regSDMA2_RLC3_RB_RPTR 0x1cfdb |
|---|
| 2714 | #define regSDMA2_RLC3_RB_RPTR_BASE_IDX 0 |
|---|
| 2715 | #define regSDMA2_RLC3_RB_RPTR_HI 0x1cfdc |
|---|
| 2716 | #define regSDMA2_RLC3_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2717 | #define regSDMA2_RLC3_RB_WPTR 0x1cfdd |
|---|
| 2718 | #define regSDMA2_RLC3_RB_WPTR_BASE_IDX 0 |
|---|
| 2719 | #define regSDMA2_RLC3_RB_WPTR_HI 0x1cfde |
|---|
| 2720 | #define regSDMA2_RLC3_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2721 | #define regSDMA2_RLC3_RB_WPTR_POLL_CNTL 0x1cfdf |
|---|
| 2722 | #define regSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2723 | #define regSDMA2_RLC3_RB_RPTR_ADDR_HI 0x1cfe0 |
|---|
| 2724 | #define regSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2725 | #define regSDMA2_RLC3_RB_RPTR_ADDR_LO 0x1cfe1 |
|---|
| 2726 | #define regSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2727 | #define regSDMA2_RLC3_IB_CNTL 0x1cfe2 |
|---|
| 2728 | #define regSDMA2_RLC3_IB_CNTL_BASE_IDX 0 |
|---|
| 2729 | #define regSDMA2_RLC3_IB_RPTR 0x1cfe3 |
|---|
| 2730 | #define regSDMA2_RLC3_IB_RPTR_BASE_IDX 0 |
|---|
| 2731 | #define regSDMA2_RLC3_IB_OFFSET 0x1cfe4 |
|---|
| 2732 | #define regSDMA2_RLC3_IB_OFFSET_BASE_IDX 0 |
|---|
| 2733 | #define regSDMA2_RLC3_IB_BASE_LO 0x1cfe5 |
|---|
| 2734 | #define regSDMA2_RLC3_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2735 | #define regSDMA2_RLC3_IB_BASE_HI 0x1cfe6 |
|---|
| 2736 | #define regSDMA2_RLC3_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2737 | #define regSDMA2_RLC3_IB_SIZE 0x1cfe7 |
|---|
| 2738 | #define regSDMA2_RLC3_IB_SIZE_BASE_IDX 0 |
|---|
| 2739 | #define regSDMA2_RLC3_SKIP_CNTL 0x1cfe8 |
|---|
| 2740 | #define regSDMA2_RLC3_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2741 | #define regSDMA2_RLC3_CONTEXT_STATUS 0x1cfe9 |
|---|
| 2742 | #define regSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2743 | #define regSDMA2_RLC3_DOORBELL 0x1cfea |
|---|
| 2744 | #define regSDMA2_RLC3_DOORBELL_BASE_IDX 0 |
|---|
| 2745 | #define regSDMA2_RLC3_STATUS 0x1d000 |
|---|
| 2746 | #define regSDMA2_RLC3_STATUS_BASE_IDX 0 |
|---|
| 2747 | #define regSDMA2_RLC3_DOORBELL_LOG 0x1d001 |
|---|
| 2748 | #define regSDMA2_RLC3_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2749 | #define regSDMA2_RLC3_WATERMARK 0x1d002 |
|---|
| 2750 | #define regSDMA2_RLC3_WATERMARK_BASE_IDX 0 |
|---|
| 2751 | #define regSDMA2_RLC3_DOORBELL_OFFSET 0x1d003 |
|---|
| 2752 | #define regSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2753 | #define regSDMA2_RLC3_CSA_ADDR_LO 0x1d004 |
|---|
| 2754 | #define regSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2755 | #define regSDMA2_RLC3_CSA_ADDR_HI 0x1d005 |
|---|
| 2756 | #define regSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2757 | #define regSDMA2_RLC3_IB_SUB_REMAIN 0x1d007 |
|---|
| 2758 | #define regSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2759 | #define regSDMA2_RLC3_PREEMPT 0x1d008 |
|---|
| 2760 | #define regSDMA2_RLC3_PREEMPT_BASE_IDX 0 |
|---|
| 2761 | #define regSDMA2_RLC3_DUMMY_REG 0x1d009 |
|---|
| 2762 | #define regSDMA2_RLC3_DUMMY_REG_BASE_IDX 0 |
|---|
| 2763 | #define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d00a |
|---|
| 2764 | #define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2765 | #define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d00b |
|---|
| 2766 | #define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2767 | #define regSDMA2_RLC3_RB_AQL_CNTL 0x1d00c |
|---|
| 2768 | #define regSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2769 | #define regSDMA2_RLC3_MINOR_PTR_UPDATE 0x1d00d |
|---|
| 2770 | #define regSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2771 | #define regSDMA2_RLC3_MIDCMD_DATA0 0x1d018 |
|---|
| 2772 | #define regSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2773 | #define regSDMA2_RLC3_MIDCMD_DATA1 0x1d019 |
|---|
| 2774 | #define regSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2775 | #define regSDMA2_RLC3_MIDCMD_DATA2 0x1d01a |
|---|
| 2776 | #define regSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2777 | #define regSDMA2_RLC3_MIDCMD_DATA3 0x1d01b |
|---|
| 2778 | #define regSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2779 | #define regSDMA2_RLC3_MIDCMD_DATA4 0x1d01c |
|---|
| 2780 | #define regSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2781 | #define regSDMA2_RLC3_MIDCMD_DATA5 0x1d01d |
|---|
| 2782 | #define regSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2783 | #define regSDMA2_RLC3_MIDCMD_DATA6 0x1d01e |
|---|
| 2784 | #define regSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2785 | #define regSDMA2_RLC3_MIDCMD_DATA7 0x1d01f |
|---|
| 2786 | #define regSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2787 | #define regSDMA2_RLC3_MIDCMD_DATA8 0x1d020 |
|---|
| 2788 | #define regSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2789 | #define regSDMA2_RLC3_MIDCMD_DATA9 0x1d021 |
|---|
| 2790 | #define regSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2791 | #define regSDMA2_RLC3_MIDCMD_DATA10 0x1d022 |
|---|
| 2792 | #define regSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2793 | #define regSDMA2_RLC3_MIDCMD_CNTL 0x1d023 |
|---|
| 2794 | #define regSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2795 | #define regSDMA2_RLC4_RB_CNTL 0x1d030 |
|---|
| 2796 | #define regSDMA2_RLC4_RB_CNTL_BASE_IDX 0 |
|---|
| 2797 | #define regSDMA2_RLC4_RB_BASE 0x1d031 |
|---|
| 2798 | #define regSDMA2_RLC4_RB_BASE_BASE_IDX 0 |
|---|
| 2799 | #define regSDMA2_RLC4_RB_BASE_HI 0x1d032 |
|---|
| 2800 | #define regSDMA2_RLC4_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2801 | #define regSDMA2_RLC4_RB_RPTR 0x1d033 |
|---|
| 2802 | #define regSDMA2_RLC4_RB_RPTR_BASE_IDX 0 |
|---|
| 2803 | #define regSDMA2_RLC4_RB_RPTR_HI 0x1d034 |
|---|
| 2804 | #define regSDMA2_RLC4_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2805 | #define regSDMA2_RLC4_RB_WPTR 0x1d035 |
|---|
| 2806 | #define regSDMA2_RLC4_RB_WPTR_BASE_IDX 0 |
|---|
| 2807 | #define regSDMA2_RLC4_RB_WPTR_HI 0x1d036 |
|---|
| 2808 | #define regSDMA2_RLC4_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2809 | #define regSDMA2_RLC4_RB_WPTR_POLL_CNTL 0x1d037 |
|---|
| 2810 | #define regSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2811 | #define regSDMA2_RLC4_RB_RPTR_ADDR_HI 0x1d038 |
|---|
| 2812 | #define regSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2813 | #define regSDMA2_RLC4_RB_RPTR_ADDR_LO 0x1d039 |
|---|
| 2814 | #define regSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2815 | #define regSDMA2_RLC4_IB_CNTL 0x1d03a |
|---|
| 2816 | #define regSDMA2_RLC4_IB_CNTL_BASE_IDX 0 |
|---|
| 2817 | #define regSDMA2_RLC4_IB_RPTR 0x1d03b |
|---|
| 2818 | #define regSDMA2_RLC4_IB_RPTR_BASE_IDX 0 |
|---|
| 2819 | #define regSDMA2_RLC4_IB_OFFSET 0x1d03c |
|---|
| 2820 | #define regSDMA2_RLC4_IB_OFFSET_BASE_IDX 0 |
|---|
| 2821 | #define regSDMA2_RLC4_IB_BASE_LO 0x1d03d |
|---|
| 2822 | #define regSDMA2_RLC4_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2823 | #define regSDMA2_RLC4_IB_BASE_HI 0x1d03e |
|---|
| 2824 | #define regSDMA2_RLC4_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2825 | #define regSDMA2_RLC4_IB_SIZE 0x1d03f |
|---|
| 2826 | #define regSDMA2_RLC4_IB_SIZE_BASE_IDX 0 |
|---|
| 2827 | #define regSDMA2_RLC4_SKIP_CNTL 0x1d040 |
|---|
| 2828 | #define regSDMA2_RLC4_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2829 | #define regSDMA2_RLC4_CONTEXT_STATUS 0x1d041 |
|---|
| 2830 | #define regSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2831 | #define regSDMA2_RLC4_DOORBELL 0x1d042 |
|---|
| 2832 | #define regSDMA2_RLC4_DOORBELL_BASE_IDX 0 |
|---|
| 2833 | #define regSDMA2_RLC4_STATUS 0x1d058 |
|---|
| 2834 | #define regSDMA2_RLC4_STATUS_BASE_IDX 0 |
|---|
| 2835 | #define regSDMA2_RLC4_DOORBELL_LOG 0x1d059 |
|---|
| 2836 | #define regSDMA2_RLC4_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2837 | #define regSDMA2_RLC4_WATERMARK 0x1d05a |
|---|
| 2838 | #define regSDMA2_RLC4_WATERMARK_BASE_IDX 0 |
|---|
| 2839 | #define regSDMA2_RLC4_DOORBELL_OFFSET 0x1d05b |
|---|
| 2840 | #define regSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2841 | #define regSDMA2_RLC4_CSA_ADDR_LO 0x1d05c |
|---|
| 2842 | #define regSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2843 | #define regSDMA2_RLC4_CSA_ADDR_HI 0x1d05d |
|---|
| 2844 | #define regSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2845 | #define regSDMA2_RLC4_IB_SUB_REMAIN 0x1d05f |
|---|
| 2846 | #define regSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2847 | #define regSDMA2_RLC4_PREEMPT 0x1d060 |
|---|
| 2848 | #define regSDMA2_RLC4_PREEMPT_BASE_IDX 0 |
|---|
| 2849 | #define regSDMA2_RLC4_DUMMY_REG 0x1d061 |
|---|
| 2850 | #define regSDMA2_RLC4_DUMMY_REG_BASE_IDX 0 |
|---|
| 2851 | #define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d062 |
|---|
| 2852 | #define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2853 | #define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d063 |
|---|
| 2854 | #define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2855 | #define regSDMA2_RLC4_RB_AQL_CNTL 0x1d064 |
|---|
| 2856 | #define regSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2857 | #define regSDMA2_RLC4_MINOR_PTR_UPDATE 0x1d065 |
|---|
| 2858 | #define regSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2859 | #define regSDMA2_RLC4_MIDCMD_DATA0 0x1d070 |
|---|
| 2860 | #define regSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2861 | #define regSDMA2_RLC4_MIDCMD_DATA1 0x1d071 |
|---|
| 2862 | #define regSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2863 | #define regSDMA2_RLC4_MIDCMD_DATA2 0x1d072 |
|---|
| 2864 | #define regSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2865 | #define regSDMA2_RLC4_MIDCMD_DATA3 0x1d073 |
|---|
| 2866 | #define regSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2867 | #define regSDMA2_RLC4_MIDCMD_DATA4 0x1d074 |
|---|
| 2868 | #define regSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2869 | #define regSDMA2_RLC4_MIDCMD_DATA5 0x1d075 |
|---|
| 2870 | #define regSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2871 | #define regSDMA2_RLC4_MIDCMD_DATA6 0x1d076 |
|---|
| 2872 | #define regSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2873 | #define regSDMA2_RLC4_MIDCMD_DATA7 0x1d077 |
|---|
| 2874 | #define regSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2875 | #define regSDMA2_RLC4_MIDCMD_DATA8 0x1d078 |
|---|
| 2876 | #define regSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2877 | #define regSDMA2_RLC4_MIDCMD_DATA9 0x1d079 |
|---|
| 2878 | #define regSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2879 | #define regSDMA2_RLC4_MIDCMD_DATA10 0x1d07a |
|---|
| 2880 | #define regSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2881 | #define regSDMA2_RLC4_MIDCMD_CNTL 0x1d07b |
|---|
| 2882 | #define regSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2883 | #define regSDMA2_RLC5_RB_CNTL 0x1d088 |
|---|
| 2884 | #define regSDMA2_RLC5_RB_CNTL_BASE_IDX 0 |
|---|
| 2885 | #define regSDMA2_RLC5_RB_BASE 0x1d089 |
|---|
| 2886 | #define regSDMA2_RLC5_RB_BASE_BASE_IDX 0 |
|---|
| 2887 | #define regSDMA2_RLC5_RB_BASE_HI 0x1d08a |
|---|
| 2888 | #define regSDMA2_RLC5_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2889 | #define regSDMA2_RLC5_RB_RPTR 0x1d08b |
|---|
| 2890 | #define regSDMA2_RLC5_RB_RPTR_BASE_IDX 0 |
|---|
| 2891 | #define regSDMA2_RLC5_RB_RPTR_HI 0x1d08c |
|---|
| 2892 | #define regSDMA2_RLC5_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2893 | #define regSDMA2_RLC5_RB_WPTR 0x1d08d |
|---|
| 2894 | #define regSDMA2_RLC5_RB_WPTR_BASE_IDX 0 |
|---|
| 2895 | #define regSDMA2_RLC5_RB_WPTR_HI 0x1d08e |
|---|
| 2896 | #define regSDMA2_RLC5_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2897 | #define regSDMA2_RLC5_RB_WPTR_POLL_CNTL 0x1d08f |
|---|
| 2898 | #define regSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2899 | #define regSDMA2_RLC5_RB_RPTR_ADDR_HI 0x1d090 |
|---|
| 2900 | #define regSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2901 | #define regSDMA2_RLC5_RB_RPTR_ADDR_LO 0x1d091 |
|---|
| 2902 | #define regSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2903 | #define regSDMA2_RLC5_IB_CNTL 0x1d092 |
|---|
| 2904 | #define regSDMA2_RLC5_IB_CNTL_BASE_IDX 0 |
|---|
| 2905 | #define regSDMA2_RLC5_IB_RPTR 0x1d093 |
|---|
| 2906 | #define regSDMA2_RLC5_IB_RPTR_BASE_IDX 0 |
|---|
| 2907 | #define regSDMA2_RLC5_IB_OFFSET 0x1d094 |
|---|
| 2908 | #define regSDMA2_RLC5_IB_OFFSET_BASE_IDX 0 |
|---|
| 2909 | #define regSDMA2_RLC5_IB_BASE_LO 0x1d095 |
|---|
| 2910 | #define regSDMA2_RLC5_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2911 | #define regSDMA2_RLC5_IB_BASE_HI 0x1d096 |
|---|
| 2912 | #define regSDMA2_RLC5_IB_BASE_HI_BASE_IDX 0 |
|---|
| 2913 | #define regSDMA2_RLC5_IB_SIZE 0x1d097 |
|---|
| 2914 | #define regSDMA2_RLC5_IB_SIZE_BASE_IDX 0 |
|---|
| 2915 | #define regSDMA2_RLC5_SKIP_CNTL 0x1d098 |
|---|
| 2916 | #define regSDMA2_RLC5_SKIP_CNTL_BASE_IDX 0 |
|---|
| 2917 | #define regSDMA2_RLC5_CONTEXT_STATUS 0x1d099 |
|---|
| 2918 | #define regSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 2919 | #define regSDMA2_RLC5_DOORBELL 0x1d09a |
|---|
| 2920 | #define regSDMA2_RLC5_DOORBELL_BASE_IDX 0 |
|---|
| 2921 | #define regSDMA2_RLC5_STATUS 0x1d0b0 |
|---|
| 2922 | #define regSDMA2_RLC5_STATUS_BASE_IDX 0 |
|---|
| 2923 | #define regSDMA2_RLC5_DOORBELL_LOG 0x1d0b1 |
|---|
| 2924 | #define regSDMA2_RLC5_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 2925 | #define regSDMA2_RLC5_WATERMARK 0x1d0b2 |
|---|
| 2926 | #define regSDMA2_RLC5_WATERMARK_BASE_IDX 0 |
|---|
| 2927 | #define regSDMA2_RLC5_DOORBELL_OFFSET 0x1d0b3 |
|---|
| 2928 | #define regSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 2929 | #define regSDMA2_RLC5_CSA_ADDR_LO 0x1d0b4 |
|---|
| 2930 | #define regSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 2931 | #define regSDMA2_RLC5_CSA_ADDR_HI 0x1d0b5 |
|---|
| 2932 | #define regSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 2933 | #define regSDMA2_RLC5_IB_SUB_REMAIN 0x1d0b7 |
|---|
| 2934 | #define regSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 2935 | #define regSDMA2_RLC5_PREEMPT 0x1d0b8 |
|---|
| 2936 | #define regSDMA2_RLC5_PREEMPT_BASE_IDX 0 |
|---|
| 2937 | #define regSDMA2_RLC5_DUMMY_REG 0x1d0b9 |
|---|
| 2938 | #define regSDMA2_RLC5_DUMMY_REG_BASE_IDX 0 |
|---|
| 2939 | #define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d0ba |
|---|
| 2940 | #define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 2941 | #define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d0bb |
|---|
| 2942 | #define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 2943 | #define regSDMA2_RLC5_RB_AQL_CNTL 0x1d0bc |
|---|
| 2944 | #define regSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 2945 | #define regSDMA2_RLC5_MINOR_PTR_UPDATE 0x1d0bd |
|---|
| 2946 | #define regSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 2947 | #define regSDMA2_RLC5_MIDCMD_DATA0 0x1d0c8 |
|---|
| 2948 | #define regSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 2949 | #define regSDMA2_RLC5_MIDCMD_DATA1 0x1d0c9 |
|---|
| 2950 | #define regSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 2951 | #define regSDMA2_RLC5_MIDCMD_DATA2 0x1d0ca |
|---|
| 2952 | #define regSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 2953 | #define regSDMA2_RLC5_MIDCMD_DATA3 0x1d0cb |
|---|
| 2954 | #define regSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 2955 | #define regSDMA2_RLC5_MIDCMD_DATA4 0x1d0cc |
|---|
| 2956 | #define regSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 2957 | #define regSDMA2_RLC5_MIDCMD_DATA5 0x1d0cd |
|---|
| 2958 | #define regSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 2959 | #define regSDMA2_RLC5_MIDCMD_DATA6 0x1d0ce |
|---|
| 2960 | #define regSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 2961 | #define regSDMA2_RLC5_MIDCMD_DATA7 0x1d0cf |
|---|
| 2962 | #define regSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 2963 | #define regSDMA2_RLC5_MIDCMD_DATA8 0x1d0d0 |
|---|
| 2964 | #define regSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 2965 | #define regSDMA2_RLC5_MIDCMD_DATA9 0x1d0d1 |
|---|
| 2966 | #define regSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 2967 | #define regSDMA2_RLC5_MIDCMD_DATA10 0x1d0d2 |
|---|
| 2968 | #define regSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 2969 | #define regSDMA2_RLC5_MIDCMD_CNTL 0x1d0d3 |
|---|
| 2970 | #define regSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 2971 | #define regSDMA2_RLC6_RB_CNTL 0x1d0e0 |
|---|
| 2972 | #define regSDMA2_RLC6_RB_CNTL_BASE_IDX 0 |
|---|
| 2973 | #define regSDMA2_RLC6_RB_BASE 0x1d0e1 |
|---|
| 2974 | #define regSDMA2_RLC6_RB_BASE_BASE_IDX 0 |
|---|
| 2975 | #define regSDMA2_RLC6_RB_BASE_HI 0x1d0e2 |
|---|
| 2976 | #define regSDMA2_RLC6_RB_BASE_HI_BASE_IDX 0 |
|---|
| 2977 | #define regSDMA2_RLC6_RB_RPTR 0x1d0e3 |
|---|
| 2978 | #define regSDMA2_RLC6_RB_RPTR_BASE_IDX 0 |
|---|
| 2979 | #define regSDMA2_RLC6_RB_RPTR_HI 0x1d0e4 |
|---|
| 2980 | #define regSDMA2_RLC6_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 2981 | #define regSDMA2_RLC6_RB_WPTR 0x1d0e5 |
|---|
| 2982 | #define regSDMA2_RLC6_RB_WPTR_BASE_IDX 0 |
|---|
| 2983 | #define regSDMA2_RLC6_RB_WPTR_HI 0x1d0e6 |
|---|
| 2984 | #define regSDMA2_RLC6_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 2985 | #define regSDMA2_RLC6_RB_WPTR_POLL_CNTL 0x1d0e7 |
|---|
| 2986 | #define regSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 2987 | #define regSDMA2_RLC6_RB_RPTR_ADDR_HI 0x1d0e8 |
|---|
| 2988 | #define regSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 2989 | #define regSDMA2_RLC6_RB_RPTR_ADDR_LO 0x1d0e9 |
|---|
| 2990 | #define regSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 2991 | #define regSDMA2_RLC6_IB_CNTL 0x1d0ea |
|---|
| 2992 | #define regSDMA2_RLC6_IB_CNTL_BASE_IDX 0 |
|---|
| 2993 | #define regSDMA2_RLC6_IB_RPTR 0x1d0eb |
|---|
| 2994 | #define regSDMA2_RLC6_IB_RPTR_BASE_IDX 0 |
|---|
| 2995 | #define regSDMA2_RLC6_IB_OFFSET 0x1d0ec |
|---|
| 2996 | #define regSDMA2_RLC6_IB_OFFSET_BASE_IDX 0 |
|---|
| 2997 | #define regSDMA2_RLC6_IB_BASE_LO 0x1d0ed |
|---|
| 2998 | #define regSDMA2_RLC6_IB_BASE_LO_BASE_IDX 0 |
|---|
| 2999 | #define regSDMA2_RLC6_IB_BASE_HI 0x1d0ee |
|---|
| 3000 | #define regSDMA2_RLC6_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3001 | #define regSDMA2_RLC6_IB_SIZE 0x1d0ef |
|---|
| 3002 | #define regSDMA2_RLC6_IB_SIZE_BASE_IDX 0 |
|---|
| 3003 | #define regSDMA2_RLC6_SKIP_CNTL 0x1d0f0 |
|---|
| 3004 | #define regSDMA2_RLC6_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3005 | #define regSDMA2_RLC6_CONTEXT_STATUS 0x1d0f1 |
|---|
| 3006 | #define regSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3007 | #define regSDMA2_RLC6_DOORBELL 0x1d0f2 |
|---|
| 3008 | #define regSDMA2_RLC6_DOORBELL_BASE_IDX 0 |
|---|
| 3009 | #define regSDMA2_RLC6_STATUS 0x1d108 |
|---|
| 3010 | #define regSDMA2_RLC6_STATUS_BASE_IDX 0 |
|---|
| 3011 | #define regSDMA2_RLC6_DOORBELL_LOG 0x1d109 |
|---|
| 3012 | #define regSDMA2_RLC6_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3013 | #define regSDMA2_RLC6_WATERMARK 0x1d10a |
|---|
| 3014 | #define regSDMA2_RLC6_WATERMARK_BASE_IDX 0 |
|---|
| 3015 | #define regSDMA2_RLC6_DOORBELL_OFFSET 0x1d10b |
|---|
| 3016 | #define regSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3017 | #define regSDMA2_RLC6_CSA_ADDR_LO 0x1d10c |
|---|
| 3018 | #define regSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3019 | #define regSDMA2_RLC6_CSA_ADDR_HI 0x1d10d |
|---|
| 3020 | #define regSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3021 | #define regSDMA2_RLC6_IB_SUB_REMAIN 0x1d10f |
|---|
| 3022 | #define regSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3023 | #define regSDMA2_RLC6_PREEMPT 0x1d110 |
|---|
| 3024 | #define regSDMA2_RLC6_PREEMPT_BASE_IDX 0 |
|---|
| 3025 | #define regSDMA2_RLC6_DUMMY_REG 0x1d111 |
|---|
| 3026 | #define regSDMA2_RLC6_DUMMY_REG_BASE_IDX 0 |
|---|
| 3027 | #define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d112 |
|---|
| 3028 | #define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3029 | #define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d113 |
|---|
| 3030 | #define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3031 | #define regSDMA2_RLC6_RB_AQL_CNTL 0x1d114 |
|---|
| 3032 | #define regSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3033 | #define regSDMA2_RLC6_MINOR_PTR_UPDATE 0x1d115 |
|---|
| 3034 | #define regSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3035 | #define regSDMA2_RLC6_MIDCMD_DATA0 0x1d120 |
|---|
| 3036 | #define regSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3037 | #define regSDMA2_RLC6_MIDCMD_DATA1 0x1d121 |
|---|
| 3038 | #define regSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3039 | #define regSDMA2_RLC6_MIDCMD_DATA2 0x1d122 |
|---|
| 3040 | #define regSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3041 | #define regSDMA2_RLC6_MIDCMD_DATA3 0x1d123 |
|---|
| 3042 | #define regSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3043 | #define regSDMA2_RLC6_MIDCMD_DATA4 0x1d124 |
|---|
| 3044 | #define regSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3045 | #define regSDMA2_RLC6_MIDCMD_DATA5 0x1d125 |
|---|
| 3046 | #define regSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3047 | #define regSDMA2_RLC6_MIDCMD_DATA6 0x1d126 |
|---|
| 3048 | #define regSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3049 | #define regSDMA2_RLC6_MIDCMD_DATA7 0x1d127 |
|---|
| 3050 | #define regSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3051 | #define regSDMA2_RLC6_MIDCMD_DATA8 0x1d128 |
|---|
| 3052 | #define regSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3053 | #define regSDMA2_RLC6_MIDCMD_DATA9 0x1d129 |
|---|
| 3054 | #define regSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3055 | #define regSDMA2_RLC6_MIDCMD_DATA10 0x1d12a |
|---|
| 3056 | #define regSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3057 | #define regSDMA2_RLC6_MIDCMD_CNTL 0x1d12b |
|---|
| 3058 | #define regSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3059 | #define regSDMA2_RLC7_RB_CNTL 0x1d138 |
|---|
| 3060 | #define regSDMA2_RLC7_RB_CNTL_BASE_IDX 0 |
|---|
| 3061 | #define regSDMA2_RLC7_RB_BASE 0x1d139 |
|---|
| 3062 | #define regSDMA2_RLC7_RB_BASE_BASE_IDX 0 |
|---|
| 3063 | #define regSDMA2_RLC7_RB_BASE_HI 0x1d13a |
|---|
| 3064 | #define regSDMA2_RLC7_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3065 | #define regSDMA2_RLC7_RB_RPTR 0x1d13b |
|---|
| 3066 | #define regSDMA2_RLC7_RB_RPTR_BASE_IDX 0 |
|---|
| 3067 | #define regSDMA2_RLC7_RB_RPTR_HI 0x1d13c |
|---|
| 3068 | #define regSDMA2_RLC7_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3069 | #define regSDMA2_RLC7_RB_WPTR 0x1d13d |
|---|
| 3070 | #define regSDMA2_RLC7_RB_WPTR_BASE_IDX 0 |
|---|
| 3071 | #define regSDMA2_RLC7_RB_WPTR_HI 0x1d13e |
|---|
| 3072 | #define regSDMA2_RLC7_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3073 | #define regSDMA2_RLC7_RB_WPTR_POLL_CNTL 0x1d13f |
|---|
| 3074 | #define regSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3075 | #define regSDMA2_RLC7_RB_RPTR_ADDR_HI 0x1d140 |
|---|
| 3076 | #define regSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3077 | #define regSDMA2_RLC7_RB_RPTR_ADDR_LO 0x1d141 |
|---|
| 3078 | #define regSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3079 | #define regSDMA2_RLC7_IB_CNTL 0x1d142 |
|---|
| 3080 | #define regSDMA2_RLC7_IB_CNTL_BASE_IDX 0 |
|---|
| 3081 | #define regSDMA2_RLC7_IB_RPTR 0x1d143 |
|---|
| 3082 | #define regSDMA2_RLC7_IB_RPTR_BASE_IDX 0 |
|---|
| 3083 | #define regSDMA2_RLC7_IB_OFFSET 0x1d144 |
|---|
| 3084 | #define regSDMA2_RLC7_IB_OFFSET_BASE_IDX 0 |
|---|
| 3085 | #define regSDMA2_RLC7_IB_BASE_LO 0x1d145 |
|---|
| 3086 | #define regSDMA2_RLC7_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3087 | #define regSDMA2_RLC7_IB_BASE_HI 0x1d146 |
|---|
| 3088 | #define regSDMA2_RLC7_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3089 | #define regSDMA2_RLC7_IB_SIZE 0x1d147 |
|---|
| 3090 | #define regSDMA2_RLC7_IB_SIZE_BASE_IDX 0 |
|---|
| 3091 | #define regSDMA2_RLC7_SKIP_CNTL 0x1d148 |
|---|
| 3092 | #define regSDMA2_RLC7_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3093 | #define regSDMA2_RLC7_CONTEXT_STATUS 0x1d149 |
|---|
| 3094 | #define regSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3095 | #define regSDMA2_RLC7_DOORBELL 0x1d14a |
|---|
| 3096 | #define regSDMA2_RLC7_DOORBELL_BASE_IDX 0 |
|---|
| 3097 | #define regSDMA2_RLC7_STATUS 0x1d160 |
|---|
| 3098 | #define regSDMA2_RLC7_STATUS_BASE_IDX 0 |
|---|
| 3099 | #define regSDMA2_RLC7_DOORBELL_LOG 0x1d161 |
|---|
| 3100 | #define regSDMA2_RLC7_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3101 | #define regSDMA2_RLC7_WATERMARK 0x1d162 |
|---|
| 3102 | #define regSDMA2_RLC7_WATERMARK_BASE_IDX 0 |
|---|
| 3103 | #define regSDMA2_RLC7_DOORBELL_OFFSET 0x1d163 |
|---|
| 3104 | #define regSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3105 | #define regSDMA2_RLC7_CSA_ADDR_LO 0x1d164 |
|---|
| 3106 | #define regSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3107 | #define regSDMA2_RLC7_CSA_ADDR_HI 0x1d165 |
|---|
| 3108 | #define regSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3109 | #define regSDMA2_RLC7_IB_SUB_REMAIN 0x1d167 |
|---|
| 3110 | #define regSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3111 | #define regSDMA2_RLC7_PREEMPT 0x1d168 |
|---|
| 3112 | #define regSDMA2_RLC7_PREEMPT_BASE_IDX 0 |
|---|
| 3113 | #define regSDMA2_RLC7_DUMMY_REG 0x1d169 |
|---|
| 3114 | #define regSDMA2_RLC7_DUMMY_REG_BASE_IDX 0 |
|---|
| 3115 | #define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d16a |
|---|
| 3116 | #define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3117 | #define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d16b |
|---|
| 3118 | #define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3119 | #define regSDMA2_RLC7_RB_AQL_CNTL 0x1d16c |
|---|
| 3120 | #define regSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3121 | #define regSDMA2_RLC7_MINOR_PTR_UPDATE 0x1d16d |
|---|
| 3122 | #define regSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3123 | #define regSDMA2_RLC7_MIDCMD_DATA0 0x1d178 |
|---|
| 3124 | #define regSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3125 | #define regSDMA2_RLC7_MIDCMD_DATA1 0x1d179 |
|---|
| 3126 | #define regSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3127 | #define regSDMA2_RLC7_MIDCMD_DATA2 0x1d17a |
|---|
| 3128 | #define regSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3129 | #define regSDMA2_RLC7_MIDCMD_DATA3 0x1d17b |
|---|
| 3130 | #define regSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3131 | #define regSDMA2_RLC7_MIDCMD_DATA4 0x1d17c |
|---|
| 3132 | #define regSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3133 | #define regSDMA2_RLC7_MIDCMD_DATA5 0x1d17d |
|---|
| 3134 | #define regSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3135 | #define regSDMA2_RLC7_MIDCMD_DATA6 0x1d17e |
|---|
| 3136 | #define regSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3137 | #define regSDMA2_RLC7_MIDCMD_DATA7 0x1d17f |
|---|
| 3138 | #define regSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3139 | #define regSDMA2_RLC7_MIDCMD_DATA8 0x1d180 |
|---|
| 3140 | #define regSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3141 | #define regSDMA2_RLC7_MIDCMD_DATA9 0x1d181 |
|---|
| 3142 | #define regSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3143 | #define regSDMA2_RLC7_MIDCMD_DATA10 0x1d182 |
|---|
| 3144 | #define regSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3145 | #define regSDMA2_RLC7_MIDCMD_CNTL 0x1d183 |
|---|
| 3146 | #define regSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3147 | |
|---|
| 3148 | |
|---|
| 3149 | // addressBlock: sdma0_sdma3dec |
|---|
| 3150 | // base address: 0x79000 |
|---|
| 3151 | #define regSDMA3_UCODE_ADDR 0x1d1a0 |
|---|
| 3152 | #define regSDMA3_UCODE_ADDR_BASE_IDX 0 |
|---|
| 3153 | #define regSDMA3_UCODE_DATA 0x1d1a1 |
|---|
| 3154 | #define regSDMA3_UCODE_DATA_BASE_IDX 0 |
|---|
| 3155 | #define regSDMA3_VF_ENABLE 0x1d1aa |
|---|
| 3156 | #define regSDMA3_VF_ENABLE_BASE_IDX 0 |
|---|
| 3157 | #define regSDMA3_CONTEXT_GROUP_BOUNDARY 0x1d1b9 |
|---|
| 3158 | #define regSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
|---|
| 3159 | #define regSDMA3_POWER_CNTL 0x1d1ba |
|---|
| 3160 | #define regSDMA3_POWER_CNTL_BASE_IDX 0 |
|---|
| 3161 | #define regSDMA3_CLK_CTRL 0x1d1bb |
|---|
| 3162 | #define regSDMA3_CLK_CTRL_BASE_IDX 0 |
|---|
| 3163 | #define regSDMA3_CNTL 0x1d1bc |
|---|
| 3164 | #define regSDMA3_CNTL_BASE_IDX 0 |
|---|
| 3165 | #define regSDMA3_CHICKEN_BITS 0x1d1bd |
|---|
| 3166 | #define regSDMA3_CHICKEN_BITS_BASE_IDX 0 |
|---|
| 3167 | #define regSDMA3_GB_ADDR_CONFIG 0x1d1be |
|---|
| 3168 | #define regSDMA3_GB_ADDR_CONFIG_BASE_IDX 0 |
|---|
| 3169 | #define regSDMA3_GB_ADDR_CONFIG_READ 0x1d1bf |
|---|
| 3170 | #define regSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
|---|
| 3171 | #define regSDMA3_RB_RPTR_FETCH_HI 0x1d1c0 |
|---|
| 3172 | #define regSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 0 |
|---|
| 3173 | #define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x1d1c1 |
|---|
| 3174 | #define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
|---|
| 3175 | #define regSDMA3_RB_RPTR_FETCH 0x1d1c2 |
|---|
| 3176 | #define regSDMA3_RB_RPTR_FETCH_BASE_IDX 0 |
|---|
| 3177 | #define regSDMA3_IB_OFFSET_FETCH 0x1d1c3 |
|---|
| 3178 | #define regSDMA3_IB_OFFSET_FETCH_BASE_IDX 0 |
|---|
| 3179 | #define regSDMA3_PROGRAM 0x1d1c4 |
|---|
| 3180 | #define regSDMA3_PROGRAM_BASE_IDX 0 |
|---|
| 3181 | #define regSDMA3_STATUS_REG 0x1d1c5 |
|---|
| 3182 | #define regSDMA3_STATUS_REG_BASE_IDX 0 |
|---|
| 3183 | #define regSDMA3_STATUS1_REG 0x1d1c6 |
|---|
| 3184 | #define regSDMA3_STATUS1_REG_BASE_IDX 0 |
|---|
| 3185 | #define regSDMA3_RD_BURST_CNTL 0x1d1c7 |
|---|
| 3186 | #define regSDMA3_RD_BURST_CNTL_BASE_IDX 0 |
|---|
| 3187 | #define regSDMA3_HBM_PAGE_CONFIG 0x1d1c8 |
|---|
| 3188 | #define regSDMA3_HBM_PAGE_CONFIG_BASE_IDX 0 |
|---|
| 3189 | #define regSDMA3_UCODE_CHECKSUM 0x1d1c9 |
|---|
| 3190 | #define regSDMA3_UCODE_CHECKSUM_BASE_IDX 0 |
|---|
| 3191 | #define regSDMA3_F32_CNTL 0x1d1ca |
|---|
| 3192 | #define regSDMA3_F32_CNTL_BASE_IDX 0 |
|---|
| 3193 | #define regSDMA3_FREEZE 0x1d1cb |
|---|
| 3194 | #define regSDMA3_FREEZE_BASE_IDX 0 |
|---|
| 3195 | #define regSDMA3_PHASE0_QUANTUM 0x1d1cc |
|---|
| 3196 | #define regSDMA3_PHASE0_QUANTUM_BASE_IDX 0 |
|---|
| 3197 | #define regSDMA3_PHASE1_QUANTUM 0x1d1cd |
|---|
| 3198 | #define regSDMA3_PHASE1_QUANTUM_BASE_IDX 0 |
|---|
| 3199 | #define regCC_SDMA3_EDC_CONFIG 0x1d1d2 |
|---|
| 3200 | #define regCC_SDMA3_EDC_CONFIG_BASE_IDX 0 |
|---|
| 3201 | #define regSDMA3_BA_THRESHOLD 0x1d1d3 |
|---|
| 3202 | #define regSDMA3_BA_THRESHOLD_BASE_IDX 0 |
|---|
| 3203 | #define regSDMA3_ID 0x1d1d4 |
|---|
| 3204 | #define regSDMA3_ID_BASE_IDX 0 |
|---|
| 3205 | #define regSDMA3_VERSION 0x1d1d5 |
|---|
| 3206 | #define regSDMA3_VERSION_BASE_IDX 0 |
|---|
| 3207 | #define regSDMA3_EDC_COUNTER 0x1d1d6 |
|---|
| 3208 | #define regSDMA3_EDC_COUNTER_BASE_IDX 0 |
|---|
| 3209 | #define regSDMA3_EDC_COUNTER2 0x1d1d7 |
|---|
| 3210 | #define regSDMA3_EDC_COUNTER2_BASE_IDX 0 |
|---|
| 3211 | #define regSDMA3_STATUS2_REG 0x1d1d8 |
|---|
| 3212 | #define regSDMA3_STATUS2_REG_BASE_IDX 0 |
|---|
| 3213 | #define regSDMA3_ATOMIC_CNTL 0x1d1d9 |
|---|
| 3214 | #define regSDMA3_ATOMIC_CNTL_BASE_IDX 0 |
|---|
| 3215 | #define regSDMA3_ATOMIC_PREOP_LO 0x1d1da |
|---|
| 3216 | #define regSDMA3_ATOMIC_PREOP_LO_BASE_IDX 0 |
|---|
| 3217 | #define regSDMA3_ATOMIC_PREOP_HI 0x1d1db |
|---|
| 3218 | #define regSDMA3_ATOMIC_PREOP_HI_BASE_IDX 0 |
|---|
| 3219 | #define regSDMA3_UTCL1_CNTL 0x1d1dc |
|---|
| 3220 | #define regSDMA3_UTCL1_CNTL_BASE_IDX 0 |
|---|
| 3221 | #define regSDMA3_UTCL1_WATERMK 0x1d1dd |
|---|
| 3222 | #define regSDMA3_UTCL1_WATERMK_BASE_IDX 0 |
|---|
| 3223 | #define regSDMA3_UTCL1_RD_STATUS 0x1d1de |
|---|
| 3224 | #define regSDMA3_UTCL1_RD_STATUS_BASE_IDX 0 |
|---|
| 3225 | #define regSDMA3_UTCL1_WR_STATUS 0x1d1df |
|---|
| 3226 | #define regSDMA3_UTCL1_WR_STATUS_BASE_IDX 0 |
|---|
| 3227 | #define regSDMA3_UTCL1_INV0 0x1d1e0 |
|---|
| 3228 | #define regSDMA3_UTCL1_INV0_BASE_IDX 0 |
|---|
| 3229 | #define regSDMA3_UTCL1_INV1 0x1d1e1 |
|---|
| 3230 | #define regSDMA3_UTCL1_INV1_BASE_IDX 0 |
|---|
| 3231 | #define regSDMA3_UTCL1_INV2 0x1d1e2 |
|---|
| 3232 | #define regSDMA3_UTCL1_INV2_BASE_IDX 0 |
|---|
| 3233 | #define regSDMA3_UTCL1_RD_XNACK0 0x1d1e3 |
|---|
| 3234 | #define regSDMA3_UTCL1_RD_XNACK0_BASE_IDX 0 |
|---|
| 3235 | #define regSDMA3_UTCL1_RD_XNACK1 0x1d1e4 |
|---|
| 3236 | #define regSDMA3_UTCL1_RD_XNACK1_BASE_IDX 0 |
|---|
| 3237 | #define regSDMA3_UTCL1_WR_XNACK0 0x1d1e5 |
|---|
| 3238 | #define regSDMA3_UTCL1_WR_XNACK0_BASE_IDX 0 |
|---|
| 3239 | #define regSDMA3_UTCL1_WR_XNACK1 0x1d1e6 |
|---|
| 3240 | #define regSDMA3_UTCL1_WR_XNACK1_BASE_IDX 0 |
|---|
| 3241 | #define regSDMA3_UTCL1_TIMEOUT 0x1d1e7 |
|---|
| 3242 | #define regSDMA3_UTCL1_TIMEOUT_BASE_IDX 0 |
|---|
| 3243 | #define regSDMA3_UTCL1_PAGE 0x1d1e8 |
|---|
| 3244 | #define regSDMA3_UTCL1_PAGE_BASE_IDX 0 |
|---|
| 3245 | #define regSDMA3_POWER_CNTL_IDLE 0x1d1e9 |
|---|
| 3246 | #define regSDMA3_POWER_CNTL_IDLE_BASE_IDX 0 |
|---|
| 3247 | #define regSDMA3_RELAX_ORDERING_LUT 0x1d1ea |
|---|
| 3248 | #define regSDMA3_RELAX_ORDERING_LUT_BASE_IDX 0 |
|---|
| 3249 | #define regSDMA3_CHICKEN_BITS_2 0x1d1eb |
|---|
| 3250 | #define regSDMA3_CHICKEN_BITS_2_BASE_IDX 0 |
|---|
| 3251 | #define regSDMA3_STATUS3_REG 0x1d1ec |
|---|
| 3252 | #define regSDMA3_STATUS3_REG_BASE_IDX 0 |
|---|
| 3253 | #define regSDMA3_PHYSICAL_ADDR_LO 0x1d1ed |
|---|
| 3254 | #define regSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 0 |
|---|
| 3255 | #define regSDMA3_PHYSICAL_ADDR_HI 0x1d1ee |
|---|
| 3256 | #define regSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 0 |
|---|
| 3257 | #define regSDMA3_PHASE2_QUANTUM 0x1d1ef |
|---|
| 3258 | #define regSDMA3_PHASE2_QUANTUM_BASE_IDX 0 |
|---|
| 3259 | #define regSDMA3_ERROR_LOG 0x1d1f0 |
|---|
| 3260 | #define regSDMA3_ERROR_LOG_BASE_IDX 0 |
|---|
| 3261 | #define regSDMA3_PUB_DUMMY_REG0 0x1d1f1 |
|---|
| 3262 | #define regSDMA3_PUB_DUMMY_REG0_BASE_IDX 0 |
|---|
| 3263 | #define regSDMA3_PUB_DUMMY_REG1 0x1d1f2 |
|---|
| 3264 | #define regSDMA3_PUB_DUMMY_REG1_BASE_IDX 0 |
|---|
| 3265 | #define regSDMA3_PUB_DUMMY_REG2 0x1d1f3 |
|---|
| 3266 | #define regSDMA3_PUB_DUMMY_REG2_BASE_IDX 0 |
|---|
| 3267 | #define regSDMA3_PUB_DUMMY_REG3 0x1d1f4 |
|---|
| 3268 | #define regSDMA3_PUB_DUMMY_REG3_BASE_IDX 0 |
|---|
| 3269 | #define regSDMA3_F32_COUNTER 0x1d1f5 |
|---|
| 3270 | #define regSDMA3_F32_COUNTER_BASE_IDX 0 |
|---|
| 3271 | #define regSDMA3_PERFCNT_PERFCOUNTER0_CFG 0x1d1f7 |
|---|
| 3272 | #define regSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 |
|---|
| 3273 | #define regSDMA3_PERFCNT_PERFCOUNTER1_CFG 0x1d1f8 |
|---|
| 3274 | #define regSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 |
|---|
| 3275 | #define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1d1f9 |
|---|
| 3276 | #define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
|---|
| 3277 | #define regSDMA3_PERFCNT_MISC_CNTL 0x1d1fa |
|---|
| 3278 | #define regSDMA3_PERFCNT_MISC_CNTL_BASE_IDX 0 |
|---|
| 3279 | #define regSDMA3_PERFCNT_PERFCOUNTER_LO 0x1d1fb |
|---|
| 3280 | #define regSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 |
|---|
| 3281 | #define regSDMA3_PERFCNT_PERFCOUNTER_HI 0x1d1fc |
|---|
| 3282 | #define regSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 |
|---|
| 3283 | #define regSDMA3_CRD_CNTL 0x1d1fd |
|---|
| 3284 | #define regSDMA3_CRD_CNTL_BASE_IDX 0 |
|---|
| 3285 | #define regSDMA3_ULV_CNTL 0x1d1ff |
|---|
| 3286 | #define regSDMA3_ULV_CNTL_BASE_IDX 0 |
|---|
| 3287 | #define regSDMA3_EA_DBIT_ADDR_DATA 0x1d200 |
|---|
| 3288 | #define regSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
|---|
| 3289 | #define regSDMA3_EA_DBIT_ADDR_INDEX 0x1d201 |
|---|
| 3290 | #define regSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
|---|
| 3291 | #define regSDMA3_STATUS4_REG 0x1d203 |
|---|
| 3292 | #define regSDMA3_STATUS4_REG_BASE_IDX 0 |
|---|
| 3293 | #define regSDMA3_SCRATCH_RAM_DATA 0x1d204 |
|---|
| 3294 | #define regSDMA3_SCRATCH_RAM_DATA_BASE_IDX 0 |
|---|
| 3295 | #define regSDMA3_SCRATCH_RAM_ADDR 0x1d205 |
|---|
| 3296 | #define regSDMA3_SCRATCH_RAM_ADDR_BASE_IDX 0 |
|---|
| 3297 | #define regSDMA3_CE_CTRL 0x1d206 |
|---|
| 3298 | #define regSDMA3_CE_CTRL_BASE_IDX 0 |
|---|
| 3299 | #define regSDMA3_RAS_STATUS 0x1d207 |
|---|
| 3300 | #define regSDMA3_RAS_STATUS_BASE_IDX 0 |
|---|
| 3301 | #define regSDMA3_CLK_STATUS 0x1d208 |
|---|
| 3302 | #define regSDMA3_CLK_STATUS_BASE_IDX 0 |
|---|
| 3303 | #define regSDMA3_GFX_RB_CNTL 0x1d220 |
|---|
| 3304 | #define regSDMA3_GFX_RB_CNTL_BASE_IDX 0 |
|---|
| 3305 | #define regSDMA3_GFX_RB_BASE 0x1d221 |
|---|
| 3306 | #define regSDMA3_GFX_RB_BASE_BASE_IDX 0 |
|---|
| 3307 | #define regSDMA3_GFX_RB_BASE_HI 0x1d222 |
|---|
| 3308 | #define regSDMA3_GFX_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3309 | #define regSDMA3_GFX_RB_RPTR 0x1d223 |
|---|
| 3310 | #define regSDMA3_GFX_RB_RPTR_BASE_IDX 0 |
|---|
| 3311 | #define regSDMA3_GFX_RB_RPTR_HI 0x1d224 |
|---|
| 3312 | #define regSDMA3_GFX_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3313 | #define regSDMA3_GFX_RB_WPTR 0x1d225 |
|---|
| 3314 | #define regSDMA3_GFX_RB_WPTR_BASE_IDX 0 |
|---|
| 3315 | #define regSDMA3_GFX_RB_WPTR_HI 0x1d226 |
|---|
| 3316 | #define regSDMA3_GFX_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3317 | #define regSDMA3_GFX_RB_WPTR_POLL_CNTL 0x1d227 |
|---|
| 3318 | #define regSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3319 | #define regSDMA3_GFX_RB_RPTR_ADDR_HI 0x1d228 |
|---|
| 3320 | #define regSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3321 | #define regSDMA3_GFX_RB_RPTR_ADDR_LO 0x1d229 |
|---|
| 3322 | #define regSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3323 | #define regSDMA3_GFX_IB_CNTL 0x1d22a |
|---|
| 3324 | #define regSDMA3_GFX_IB_CNTL_BASE_IDX 0 |
|---|
| 3325 | #define regSDMA3_GFX_IB_RPTR 0x1d22b |
|---|
| 3326 | #define regSDMA3_GFX_IB_RPTR_BASE_IDX 0 |
|---|
| 3327 | #define regSDMA3_GFX_IB_OFFSET 0x1d22c |
|---|
| 3328 | #define regSDMA3_GFX_IB_OFFSET_BASE_IDX 0 |
|---|
| 3329 | #define regSDMA3_GFX_IB_BASE_LO 0x1d22d |
|---|
| 3330 | #define regSDMA3_GFX_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3331 | #define regSDMA3_GFX_IB_BASE_HI 0x1d22e |
|---|
| 3332 | #define regSDMA3_GFX_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3333 | #define regSDMA3_GFX_IB_SIZE 0x1d22f |
|---|
| 3334 | #define regSDMA3_GFX_IB_SIZE_BASE_IDX 0 |
|---|
| 3335 | #define regSDMA3_GFX_SKIP_CNTL 0x1d230 |
|---|
| 3336 | #define regSDMA3_GFX_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3337 | #define regSDMA3_GFX_CONTEXT_STATUS 0x1d231 |
|---|
| 3338 | #define regSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3339 | #define regSDMA3_GFX_DOORBELL 0x1d232 |
|---|
| 3340 | #define regSDMA3_GFX_DOORBELL_BASE_IDX 0 |
|---|
| 3341 | #define regSDMA3_GFX_CONTEXT_CNTL 0x1d233 |
|---|
| 3342 | #define regSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 0 |
|---|
| 3343 | #define regSDMA3_GFX_STATUS 0x1d248 |
|---|
| 3344 | #define regSDMA3_GFX_STATUS_BASE_IDX 0 |
|---|
| 3345 | #define regSDMA3_GFX_DOORBELL_LOG 0x1d249 |
|---|
| 3346 | #define regSDMA3_GFX_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3347 | #define regSDMA3_GFX_WATERMARK 0x1d24a |
|---|
| 3348 | #define regSDMA3_GFX_WATERMARK_BASE_IDX 0 |
|---|
| 3349 | #define regSDMA3_GFX_DOORBELL_OFFSET 0x1d24b |
|---|
| 3350 | #define regSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3351 | #define regSDMA3_GFX_CSA_ADDR_LO 0x1d24c |
|---|
| 3352 | #define regSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3353 | #define regSDMA3_GFX_CSA_ADDR_HI 0x1d24d |
|---|
| 3354 | #define regSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3355 | #define regSDMA3_GFX_IB_SUB_REMAIN 0x1d24f |
|---|
| 3356 | #define regSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3357 | #define regSDMA3_GFX_PREEMPT 0x1d250 |
|---|
| 3358 | #define regSDMA3_GFX_PREEMPT_BASE_IDX 0 |
|---|
| 3359 | #define regSDMA3_GFX_DUMMY_REG 0x1d251 |
|---|
| 3360 | #define regSDMA3_GFX_DUMMY_REG_BASE_IDX 0 |
|---|
| 3361 | #define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x1d252 |
|---|
| 3362 | #define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3363 | #define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x1d253 |
|---|
| 3364 | #define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3365 | #define regSDMA3_GFX_RB_AQL_CNTL 0x1d254 |
|---|
| 3366 | #define regSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3367 | #define regSDMA3_GFX_MINOR_PTR_UPDATE 0x1d255 |
|---|
| 3368 | #define regSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3369 | #define regSDMA3_GFX_MIDCMD_DATA0 0x1d260 |
|---|
| 3370 | #define regSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3371 | #define regSDMA3_GFX_MIDCMD_DATA1 0x1d261 |
|---|
| 3372 | #define regSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3373 | #define regSDMA3_GFX_MIDCMD_DATA2 0x1d262 |
|---|
| 3374 | #define regSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3375 | #define regSDMA3_GFX_MIDCMD_DATA3 0x1d263 |
|---|
| 3376 | #define regSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3377 | #define regSDMA3_GFX_MIDCMD_DATA4 0x1d264 |
|---|
| 3378 | #define regSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3379 | #define regSDMA3_GFX_MIDCMD_DATA5 0x1d265 |
|---|
| 3380 | #define regSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3381 | #define regSDMA3_GFX_MIDCMD_DATA6 0x1d266 |
|---|
| 3382 | #define regSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3383 | #define regSDMA3_GFX_MIDCMD_DATA7 0x1d267 |
|---|
| 3384 | #define regSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3385 | #define regSDMA3_GFX_MIDCMD_DATA8 0x1d268 |
|---|
| 3386 | #define regSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3387 | #define regSDMA3_GFX_MIDCMD_DATA9 0x1d269 |
|---|
| 3388 | #define regSDMA3_GFX_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3389 | #define regSDMA3_GFX_MIDCMD_DATA10 0x1d26a |
|---|
| 3390 | #define regSDMA3_GFX_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3391 | #define regSDMA3_GFX_MIDCMD_CNTL 0x1d26b |
|---|
| 3392 | #define regSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3393 | #define regSDMA3_PAGE_RB_CNTL 0x1d278 |
|---|
| 3394 | #define regSDMA3_PAGE_RB_CNTL_BASE_IDX 0 |
|---|
| 3395 | #define regSDMA3_PAGE_RB_BASE 0x1d279 |
|---|
| 3396 | #define regSDMA3_PAGE_RB_BASE_BASE_IDX 0 |
|---|
| 3397 | #define regSDMA3_PAGE_RB_BASE_HI 0x1d27a |
|---|
| 3398 | #define regSDMA3_PAGE_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3399 | #define regSDMA3_PAGE_RB_RPTR 0x1d27b |
|---|
| 3400 | #define regSDMA3_PAGE_RB_RPTR_BASE_IDX 0 |
|---|
| 3401 | #define regSDMA3_PAGE_RB_RPTR_HI 0x1d27c |
|---|
| 3402 | #define regSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3403 | #define regSDMA3_PAGE_RB_WPTR 0x1d27d |
|---|
| 3404 | #define regSDMA3_PAGE_RB_WPTR_BASE_IDX 0 |
|---|
| 3405 | #define regSDMA3_PAGE_RB_WPTR_HI 0x1d27e |
|---|
| 3406 | #define regSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3407 | #define regSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x1d27f |
|---|
| 3408 | #define regSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3409 | #define regSDMA3_PAGE_RB_RPTR_ADDR_HI 0x1d280 |
|---|
| 3410 | #define regSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3411 | #define regSDMA3_PAGE_RB_RPTR_ADDR_LO 0x1d281 |
|---|
| 3412 | #define regSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3413 | #define regSDMA3_PAGE_IB_CNTL 0x1d282 |
|---|
| 3414 | #define regSDMA3_PAGE_IB_CNTL_BASE_IDX 0 |
|---|
| 3415 | #define regSDMA3_PAGE_IB_RPTR 0x1d283 |
|---|
| 3416 | #define regSDMA3_PAGE_IB_RPTR_BASE_IDX 0 |
|---|
| 3417 | #define regSDMA3_PAGE_IB_OFFSET 0x1d284 |
|---|
| 3418 | #define regSDMA3_PAGE_IB_OFFSET_BASE_IDX 0 |
|---|
| 3419 | #define regSDMA3_PAGE_IB_BASE_LO 0x1d285 |
|---|
| 3420 | #define regSDMA3_PAGE_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3421 | #define regSDMA3_PAGE_IB_BASE_HI 0x1d286 |
|---|
| 3422 | #define regSDMA3_PAGE_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3423 | #define regSDMA3_PAGE_IB_SIZE 0x1d287 |
|---|
| 3424 | #define regSDMA3_PAGE_IB_SIZE_BASE_IDX 0 |
|---|
| 3425 | #define regSDMA3_PAGE_SKIP_CNTL 0x1d288 |
|---|
| 3426 | #define regSDMA3_PAGE_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3427 | #define regSDMA3_PAGE_CONTEXT_STATUS 0x1d289 |
|---|
| 3428 | #define regSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3429 | #define regSDMA3_PAGE_DOORBELL 0x1d28a |
|---|
| 3430 | #define regSDMA3_PAGE_DOORBELL_BASE_IDX 0 |
|---|
| 3431 | #define regSDMA3_PAGE_STATUS 0x1d2a0 |
|---|
| 3432 | #define regSDMA3_PAGE_STATUS_BASE_IDX 0 |
|---|
| 3433 | #define regSDMA3_PAGE_DOORBELL_LOG 0x1d2a1 |
|---|
| 3434 | #define regSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3435 | #define regSDMA3_PAGE_WATERMARK 0x1d2a2 |
|---|
| 3436 | #define regSDMA3_PAGE_WATERMARK_BASE_IDX 0 |
|---|
| 3437 | #define regSDMA3_PAGE_DOORBELL_OFFSET 0x1d2a3 |
|---|
| 3438 | #define regSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3439 | #define regSDMA3_PAGE_CSA_ADDR_LO 0x1d2a4 |
|---|
| 3440 | #define regSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3441 | #define regSDMA3_PAGE_CSA_ADDR_HI 0x1d2a5 |
|---|
| 3442 | #define regSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3443 | #define regSDMA3_PAGE_IB_SUB_REMAIN 0x1d2a7 |
|---|
| 3444 | #define regSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3445 | #define regSDMA3_PAGE_PREEMPT 0x1d2a8 |
|---|
| 3446 | #define regSDMA3_PAGE_PREEMPT_BASE_IDX 0 |
|---|
| 3447 | #define regSDMA3_PAGE_DUMMY_REG 0x1d2a9 |
|---|
| 3448 | #define regSDMA3_PAGE_DUMMY_REG_BASE_IDX 0 |
|---|
| 3449 | #define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x1d2aa |
|---|
| 3450 | #define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3451 | #define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x1d2ab |
|---|
| 3452 | #define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3453 | #define regSDMA3_PAGE_RB_AQL_CNTL 0x1d2ac |
|---|
| 3454 | #define regSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3455 | #define regSDMA3_PAGE_MINOR_PTR_UPDATE 0x1d2ad |
|---|
| 3456 | #define regSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3457 | #define regSDMA3_PAGE_MIDCMD_DATA0 0x1d2b8 |
|---|
| 3458 | #define regSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3459 | #define regSDMA3_PAGE_MIDCMD_DATA1 0x1d2b9 |
|---|
| 3460 | #define regSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3461 | #define regSDMA3_PAGE_MIDCMD_DATA2 0x1d2ba |
|---|
| 3462 | #define regSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3463 | #define regSDMA3_PAGE_MIDCMD_DATA3 0x1d2bb |
|---|
| 3464 | #define regSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3465 | #define regSDMA3_PAGE_MIDCMD_DATA4 0x1d2bc |
|---|
| 3466 | #define regSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3467 | #define regSDMA3_PAGE_MIDCMD_DATA5 0x1d2bd |
|---|
| 3468 | #define regSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3469 | #define regSDMA3_PAGE_MIDCMD_DATA6 0x1d2be |
|---|
| 3470 | #define regSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3471 | #define regSDMA3_PAGE_MIDCMD_DATA7 0x1d2bf |
|---|
| 3472 | #define regSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3473 | #define regSDMA3_PAGE_MIDCMD_DATA8 0x1d2c0 |
|---|
| 3474 | #define regSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3475 | #define regSDMA3_PAGE_MIDCMD_DATA9 0x1d2c1 |
|---|
| 3476 | #define regSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3477 | #define regSDMA3_PAGE_MIDCMD_DATA10 0x1d2c2 |
|---|
| 3478 | #define regSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3479 | #define regSDMA3_PAGE_MIDCMD_CNTL 0x1d2c3 |
|---|
| 3480 | #define regSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3481 | #define regSDMA3_RLC0_RB_CNTL 0x1d2d0 |
|---|
| 3482 | #define regSDMA3_RLC0_RB_CNTL_BASE_IDX 0 |
|---|
| 3483 | #define regSDMA3_RLC0_RB_BASE 0x1d2d1 |
|---|
| 3484 | #define regSDMA3_RLC0_RB_BASE_BASE_IDX 0 |
|---|
| 3485 | #define regSDMA3_RLC0_RB_BASE_HI 0x1d2d2 |
|---|
| 3486 | #define regSDMA3_RLC0_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3487 | #define regSDMA3_RLC0_RB_RPTR 0x1d2d3 |
|---|
| 3488 | #define regSDMA3_RLC0_RB_RPTR_BASE_IDX 0 |
|---|
| 3489 | #define regSDMA3_RLC0_RB_RPTR_HI 0x1d2d4 |
|---|
| 3490 | #define regSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3491 | #define regSDMA3_RLC0_RB_WPTR 0x1d2d5 |
|---|
| 3492 | #define regSDMA3_RLC0_RB_WPTR_BASE_IDX 0 |
|---|
| 3493 | #define regSDMA3_RLC0_RB_WPTR_HI 0x1d2d6 |
|---|
| 3494 | #define regSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3495 | #define regSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x1d2d7 |
|---|
| 3496 | #define regSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3497 | #define regSDMA3_RLC0_RB_RPTR_ADDR_HI 0x1d2d8 |
|---|
| 3498 | #define regSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3499 | #define regSDMA3_RLC0_RB_RPTR_ADDR_LO 0x1d2d9 |
|---|
| 3500 | #define regSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3501 | #define regSDMA3_RLC0_IB_CNTL 0x1d2da |
|---|
| 3502 | #define regSDMA3_RLC0_IB_CNTL_BASE_IDX 0 |
|---|
| 3503 | #define regSDMA3_RLC0_IB_RPTR 0x1d2db |
|---|
| 3504 | #define regSDMA3_RLC0_IB_RPTR_BASE_IDX 0 |
|---|
| 3505 | #define regSDMA3_RLC0_IB_OFFSET 0x1d2dc |
|---|
| 3506 | #define regSDMA3_RLC0_IB_OFFSET_BASE_IDX 0 |
|---|
| 3507 | #define regSDMA3_RLC0_IB_BASE_LO 0x1d2dd |
|---|
| 3508 | #define regSDMA3_RLC0_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3509 | #define regSDMA3_RLC0_IB_BASE_HI 0x1d2de |
|---|
| 3510 | #define regSDMA3_RLC0_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3511 | #define regSDMA3_RLC0_IB_SIZE 0x1d2df |
|---|
| 3512 | #define regSDMA3_RLC0_IB_SIZE_BASE_IDX 0 |
|---|
| 3513 | #define regSDMA3_RLC0_SKIP_CNTL 0x1d2e0 |
|---|
| 3514 | #define regSDMA3_RLC0_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3515 | #define regSDMA3_RLC0_CONTEXT_STATUS 0x1d2e1 |
|---|
| 3516 | #define regSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3517 | #define regSDMA3_RLC0_DOORBELL 0x1d2e2 |
|---|
| 3518 | #define regSDMA3_RLC0_DOORBELL_BASE_IDX 0 |
|---|
| 3519 | #define regSDMA3_RLC0_STATUS 0x1d2f8 |
|---|
| 3520 | #define regSDMA3_RLC0_STATUS_BASE_IDX 0 |
|---|
| 3521 | #define regSDMA3_RLC0_DOORBELL_LOG 0x1d2f9 |
|---|
| 3522 | #define regSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3523 | #define regSDMA3_RLC0_WATERMARK 0x1d2fa |
|---|
| 3524 | #define regSDMA3_RLC0_WATERMARK_BASE_IDX 0 |
|---|
| 3525 | #define regSDMA3_RLC0_DOORBELL_OFFSET 0x1d2fb |
|---|
| 3526 | #define regSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3527 | #define regSDMA3_RLC0_CSA_ADDR_LO 0x1d2fc |
|---|
| 3528 | #define regSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3529 | #define regSDMA3_RLC0_CSA_ADDR_HI 0x1d2fd |
|---|
| 3530 | #define regSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3531 | #define regSDMA3_RLC0_IB_SUB_REMAIN 0x1d2ff |
|---|
| 3532 | #define regSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3533 | #define regSDMA3_RLC0_PREEMPT 0x1d300 |
|---|
| 3534 | #define regSDMA3_RLC0_PREEMPT_BASE_IDX 0 |
|---|
| 3535 | #define regSDMA3_RLC0_DUMMY_REG 0x1d301 |
|---|
| 3536 | #define regSDMA3_RLC0_DUMMY_REG_BASE_IDX 0 |
|---|
| 3537 | #define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x1d302 |
|---|
| 3538 | #define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3539 | #define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x1d303 |
|---|
| 3540 | #define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3541 | #define regSDMA3_RLC0_RB_AQL_CNTL 0x1d304 |
|---|
| 3542 | #define regSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3543 | #define regSDMA3_RLC0_MINOR_PTR_UPDATE 0x1d305 |
|---|
| 3544 | #define regSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3545 | #define regSDMA3_RLC0_MIDCMD_DATA0 0x1d310 |
|---|
| 3546 | #define regSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3547 | #define regSDMA3_RLC0_MIDCMD_DATA1 0x1d311 |
|---|
| 3548 | #define regSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3549 | #define regSDMA3_RLC0_MIDCMD_DATA2 0x1d312 |
|---|
| 3550 | #define regSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3551 | #define regSDMA3_RLC0_MIDCMD_DATA3 0x1d313 |
|---|
| 3552 | #define regSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3553 | #define regSDMA3_RLC0_MIDCMD_DATA4 0x1d314 |
|---|
| 3554 | #define regSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3555 | #define regSDMA3_RLC0_MIDCMD_DATA5 0x1d315 |
|---|
| 3556 | #define regSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3557 | #define regSDMA3_RLC0_MIDCMD_DATA6 0x1d316 |
|---|
| 3558 | #define regSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3559 | #define regSDMA3_RLC0_MIDCMD_DATA7 0x1d317 |
|---|
| 3560 | #define regSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3561 | #define regSDMA3_RLC0_MIDCMD_DATA8 0x1d318 |
|---|
| 3562 | #define regSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3563 | #define regSDMA3_RLC0_MIDCMD_DATA9 0x1d319 |
|---|
| 3564 | #define regSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3565 | #define regSDMA3_RLC0_MIDCMD_DATA10 0x1d31a |
|---|
| 3566 | #define regSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3567 | #define regSDMA3_RLC0_MIDCMD_CNTL 0x1d31b |
|---|
| 3568 | #define regSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3569 | #define regSDMA3_RLC1_RB_CNTL 0x1d328 |
|---|
| 3570 | #define regSDMA3_RLC1_RB_CNTL_BASE_IDX 0 |
|---|
| 3571 | #define regSDMA3_RLC1_RB_BASE 0x1d329 |
|---|
| 3572 | #define regSDMA3_RLC1_RB_BASE_BASE_IDX 0 |
|---|
| 3573 | #define regSDMA3_RLC1_RB_BASE_HI 0x1d32a |
|---|
| 3574 | #define regSDMA3_RLC1_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3575 | #define regSDMA3_RLC1_RB_RPTR 0x1d32b |
|---|
| 3576 | #define regSDMA3_RLC1_RB_RPTR_BASE_IDX 0 |
|---|
| 3577 | #define regSDMA3_RLC1_RB_RPTR_HI 0x1d32c |
|---|
| 3578 | #define regSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3579 | #define regSDMA3_RLC1_RB_WPTR 0x1d32d |
|---|
| 3580 | #define regSDMA3_RLC1_RB_WPTR_BASE_IDX 0 |
|---|
| 3581 | #define regSDMA3_RLC1_RB_WPTR_HI 0x1d32e |
|---|
| 3582 | #define regSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3583 | #define regSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x1d32f |
|---|
| 3584 | #define regSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3585 | #define regSDMA3_RLC1_RB_RPTR_ADDR_HI 0x1d330 |
|---|
| 3586 | #define regSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3587 | #define regSDMA3_RLC1_RB_RPTR_ADDR_LO 0x1d331 |
|---|
| 3588 | #define regSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3589 | #define regSDMA3_RLC1_IB_CNTL 0x1d332 |
|---|
| 3590 | #define regSDMA3_RLC1_IB_CNTL_BASE_IDX 0 |
|---|
| 3591 | #define regSDMA3_RLC1_IB_RPTR 0x1d333 |
|---|
| 3592 | #define regSDMA3_RLC1_IB_RPTR_BASE_IDX 0 |
|---|
| 3593 | #define regSDMA3_RLC1_IB_OFFSET 0x1d334 |
|---|
| 3594 | #define regSDMA3_RLC1_IB_OFFSET_BASE_IDX 0 |
|---|
| 3595 | #define regSDMA3_RLC1_IB_BASE_LO 0x1d335 |
|---|
| 3596 | #define regSDMA3_RLC1_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3597 | #define regSDMA3_RLC1_IB_BASE_HI 0x1d336 |
|---|
| 3598 | #define regSDMA3_RLC1_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3599 | #define regSDMA3_RLC1_IB_SIZE 0x1d337 |
|---|
| 3600 | #define regSDMA3_RLC1_IB_SIZE_BASE_IDX 0 |
|---|
| 3601 | #define regSDMA3_RLC1_SKIP_CNTL 0x1d338 |
|---|
| 3602 | #define regSDMA3_RLC1_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3603 | #define regSDMA3_RLC1_CONTEXT_STATUS 0x1d339 |
|---|
| 3604 | #define regSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3605 | #define regSDMA3_RLC1_DOORBELL 0x1d33a |
|---|
| 3606 | #define regSDMA3_RLC1_DOORBELL_BASE_IDX 0 |
|---|
| 3607 | #define regSDMA3_RLC1_STATUS 0x1d350 |
|---|
| 3608 | #define regSDMA3_RLC1_STATUS_BASE_IDX 0 |
|---|
| 3609 | #define regSDMA3_RLC1_DOORBELL_LOG 0x1d351 |
|---|
| 3610 | #define regSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3611 | #define regSDMA3_RLC1_WATERMARK 0x1d352 |
|---|
| 3612 | #define regSDMA3_RLC1_WATERMARK_BASE_IDX 0 |
|---|
| 3613 | #define regSDMA3_RLC1_DOORBELL_OFFSET 0x1d353 |
|---|
| 3614 | #define regSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3615 | #define regSDMA3_RLC1_CSA_ADDR_LO 0x1d354 |
|---|
| 3616 | #define regSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3617 | #define regSDMA3_RLC1_CSA_ADDR_HI 0x1d355 |
|---|
| 3618 | #define regSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3619 | #define regSDMA3_RLC1_IB_SUB_REMAIN 0x1d357 |
|---|
| 3620 | #define regSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3621 | #define regSDMA3_RLC1_PREEMPT 0x1d358 |
|---|
| 3622 | #define regSDMA3_RLC1_PREEMPT_BASE_IDX 0 |
|---|
| 3623 | #define regSDMA3_RLC1_DUMMY_REG 0x1d359 |
|---|
| 3624 | #define regSDMA3_RLC1_DUMMY_REG_BASE_IDX 0 |
|---|
| 3625 | #define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x1d35a |
|---|
| 3626 | #define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3627 | #define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x1d35b |
|---|
| 3628 | #define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3629 | #define regSDMA3_RLC1_RB_AQL_CNTL 0x1d35c |
|---|
| 3630 | #define regSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3631 | #define regSDMA3_RLC1_MINOR_PTR_UPDATE 0x1d35d |
|---|
| 3632 | #define regSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3633 | #define regSDMA3_RLC1_MIDCMD_DATA0 0x1d368 |
|---|
| 3634 | #define regSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3635 | #define regSDMA3_RLC1_MIDCMD_DATA1 0x1d369 |
|---|
| 3636 | #define regSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3637 | #define regSDMA3_RLC1_MIDCMD_DATA2 0x1d36a |
|---|
| 3638 | #define regSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3639 | #define regSDMA3_RLC1_MIDCMD_DATA3 0x1d36b |
|---|
| 3640 | #define regSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3641 | #define regSDMA3_RLC1_MIDCMD_DATA4 0x1d36c |
|---|
| 3642 | #define regSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3643 | #define regSDMA3_RLC1_MIDCMD_DATA5 0x1d36d |
|---|
| 3644 | #define regSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3645 | #define regSDMA3_RLC1_MIDCMD_DATA6 0x1d36e |
|---|
| 3646 | #define regSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3647 | #define regSDMA3_RLC1_MIDCMD_DATA7 0x1d36f |
|---|
| 3648 | #define regSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3649 | #define regSDMA3_RLC1_MIDCMD_DATA8 0x1d370 |
|---|
| 3650 | #define regSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3651 | #define regSDMA3_RLC1_MIDCMD_DATA9 0x1d371 |
|---|
| 3652 | #define regSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3653 | #define regSDMA3_RLC1_MIDCMD_DATA10 0x1d372 |
|---|
| 3654 | #define regSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3655 | #define regSDMA3_RLC1_MIDCMD_CNTL 0x1d373 |
|---|
| 3656 | #define regSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3657 | #define regSDMA3_RLC2_RB_CNTL 0x1d380 |
|---|
| 3658 | #define regSDMA3_RLC2_RB_CNTL_BASE_IDX 0 |
|---|
| 3659 | #define regSDMA3_RLC2_RB_BASE 0x1d381 |
|---|
| 3660 | #define regSDMA3_RLC2_RB_BASE_BASE_IDX 0 |
|---|
| 3661 | #define regSDMA3_RLC2_RB_BASE_HI 0x1d382 |
|---|
| 3662 | #define regSDMA3_RLC2_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3663 | #define regSDMA3_RLC2_RB_RPTR 0x1d383 |
|---|
| 3664 | #define regSDMA3_RLC2_RB_RPTR_BASE_IDX 0 |
|---|
| 3665 | #define regSDMA3_RLC2_RB_RPTR_HI 0x1d384 |
|---|
| 3666 | #define regSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3667 | #define regSDMA3_RLC2_RB_WPTR 0x1d385 |
|---|
| 3668 | #define regSDMA3_RLC2_RB_WPTR_BASE_IDX 0 |
|---|
| 3669 | #define regSDMA3_RLC2_RB_WPTR_HI 0x1d386 |
|---|
| 3670 | #define regSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3671 | #define regSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x1d387 |
|---|
| 3672 | #define regSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3673 | #define regSDMA3_RLC2_RB_RPTR_ADDR_HI 0x1d388 |
|---|
| 3674 | #define regSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3675 | #define regSDMA3_RLC2_RB_RPTR_ADDR_LO 0x1d389 |
|---|
| 3676 | #define regSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3677 | #define regSDMA3_RLC2_IB_CNTL 0x1d38a |
|---|
| 3678 | #define regSDMA3_RLC2_IB_CNTL_BASE_IDX 0 |
|---|
| 3679 | #define regSDMA3_RLC2_IB_RPTR 0x1d38b |
|---|
| 3680 | #define regSDMA3_RLC2_IB_RPTR_BASE_IDX 0 |
|---|
| 3681 | #define regSDMA3_RLC2_IB_OFFSET 0x1d38c |
|---|
| 3682 | #define regSDMA3_RLC2_IB_OFFSET_BASE_IDX 0 |
|---|
| 3683 | #define regSDMA3_RLC2_IB_BASE_LO 0x1d38d |
|---|
| 3684 | #define regSDMA3_RLC2_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3685 | #define regSDMA3_RLC2_IB_BASE_HI 0x1d38e |
|---|
| 3686 | #define regSDMA3_RLC2_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3687 | #define regSDMA3_RLC2_IB_SIZE 0x1d38f |
|---|
| 3688 | #define regSDMA3_RLC2_IB_SIZE_BASE_IDX 0 |
|---|
| 3689 | #define regSDMA3_RLC2_SKIP_CNTL 0x1d390 |
|---|
| 3690 | #define regSDMA3_RLC2_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3691 | #define regSDMA3_RLC2_CONTEXT_STATUS 0x1d391 |
|---|
| 3692 | #define regSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3693 | #define regSDMA3_RLC2_DOORBELL 0x1d392 |
|---|
| 3694 | #define regSDMA3_RLC2_DOORBELL_BASE_IDX 0 |
|---|
| 3695 | #define regSDMA3_RLC2_STATUS 0x1d3a8 |
|---|
| 3696 | #define regSDMA3_RLC2_STATUS_BASE_IDX 0 |
|---|
| 3697 | #define regSDMA3_RLC2_DOORBELL_LOG 0x1d3a9 |
|---|
| 3698 | #define regSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3699 | #define regSDMA3_RLC2_WATERMARK 0x1d3aa |
|---|
| 3700 | #define regSDMA3_RLC2_WATERMARK_BASE_IDX 0 |
|---|
| 3701 | #define regSDMA3_RLC2_DOORBELL_OFFSET 0x1d3ab |
|---|
| 3702 | #define regSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3703 | #define regSDMA3_RLC2_CSA_ADDR_LO 0x1d3ac |
|---|
| 3704 | #define regSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3705 | #define regSDMA3_RLC2_CSA_ADDR_HI 0x1d3ad |
|---|
| 3706 | #define regSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3707 | #define regSDMA3_RLC2_IB_SUB_REMAIN 0x1d3af |
|---|
| 3708 | #define regSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3709 | #define regSDMA3_RLC2_PREEMPT 0x1d3b0 |
|---|
| 3710 | #define regSDMA3_RLC2_PREEMPT_BASE_IDX 0 |
|---|
| 3711 | #define regSDMA3_RLC2_DUMMY_REG 0x1d3b1 |
|---|
| 3712 | #define regSDMA3_RLC2_DUMMY_REG_BASE_IDX 0 |
|---|
| 3713 | #define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x1d3b2 |
|---|
| 3714 | #define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3715 | #define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x1d3b3 |
|---|
| 3716 | #define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3717 | #define regSDMA3_RLC2_RB_AQL_CNTL 0x1d3b4 |
|---|
| 3718 | #define regSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3719 | #define regSDMA3_RLC2_MINOR_PTR_UPDATE 0x1d3b5 |
|---|
| 3720 | #define regSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3721 | #define regSDMA3_RLC2_MIDCMD_DATA0 0x1d3c0 |
|---|
| 3722 | #define regSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3723 | #define regSDMA3_RLC2_MIDCMD_DATA1 0x1d3c1 |
|---|
| 3724 | #define regSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3725 | #define regSDMA3_RLC2_MIDCMD_DATA2 0x1d3c2 |
|---|
| 3726 | #define regSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3727 | #define regSDMA3_RLC2_MIDCMD_DATA3 0x1d3c3 |
|---|
| 3728 | #define regSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3729 | #define regSDMA3_RLC2_MIDCMD_DATA4 0x1d3c4 |
|---|
| 3730 | #define regSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3731 | #define regSDMA3_RLC2_MIDCMD_DATA5 0x1d3c5 |
|---|
| 3732 | #define regSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3733 | #define regSDMA3_RLC2_MIDCMD_DATA6 0x1d3c6 |
|---|
| 3734 | #define regSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3735 | #define regSDMA3_RLC2_MIDCMD_DATA7 0x1d3c7 |
|---|
| 3736 | #define regSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3737 | #define regSDMA3_RLC2_MIDCMD_DATA8 0x1d3c8 |
|---|
| 3738 | #define regSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3739 | #define regSDMA3_RLC2_MIDCMD_DATA9 0x1d3c9 |
|---|
| 3740 | #define regSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3741 | #define regSDMA3_RLC2_MIDCMD_DATA10 0x1d3ca |
|---|
| 3742 | #define regSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3743 | #define regSDMA3_RLC2_MIDCMD_CNTL 0x1d3cb |
|---|
| 3744 | #define regSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3745 | #define regSDMA3_RLC3_RB_CNTL 0x1d3d8 |
|---|
| 3746 | #define regSDMA3_RLC3_RB_CNTL_BASE_IDX 0 |
|---|
| 3747 | #define regSDMA3_RLC3_RB_BASE 0x1d3d9 |
|---|
| 3748 | #define regSDMA3_RLC3_RB_BASE_BASE_IDX 0 |
|---|
| 3749 | #define regSDMA3_RLC3_RB_BASE_HI 0x1d3da |
|---|
| 3750 | #define regSDMA3_RLC3_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3751 | #define regSDMA3_RLC3_RB_RPTR 0x1d3db |
|---|
| 3752 | #define regSDMA3_RLC3_RB_RPTR_BASE_IDX 0 |
|---|
| 3753 | #define regSDMA3_RLC3_RB_RPTR_HI 0x1d3dc |
|---|
| 3754 | #define regSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3755 | #define regSDMA3_RLC3_RB_WPTR 0x1d3dd |
|---|
| 3756 | #define regSDMA3_RLC3_RB_WPTR_BASE_IDX 0 |
|---|
| 3757 | #define regSDMA3_RLC3_RB_WPTR_HI 0x1d3de |
|---|
| 3758 | #define regSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3759 | #define regSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x1d3df |
|---|
| 3760 | #define regSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3761 | #define regSDMA3_RLC3_RB_RPTR_ADDR_HI 0x1d3e0 |
|---|
| 3762 | #define regSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3763 | #define regSDMA3_RLC3_RB_RPTR_ADDR_LO 0x1d3e1 |
|---|
| 3764 | #define regSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3765 | #define regSDMA3_RLC3_IB_CNTL 0x1d3e2 |
|---|
| 3766 | #define regSDMA3_RLC3_IB_CNTL_BASE_IDX 0 |
|---|
| 3767 | #define regSDMA3_RLC3_IB_RPTR 0x1d3e3 |
|---|
| 3768 | #define regSDMA3_RLC3_IB_RPTR_BASE_IDX 0 |
|---|
| 3769 | #define regSDMA3_RLC3_IB_OFFSET 0x1d3e4 |
|---|
| 3770 | #define regSDMA3_RLC3_IB_OFFSET_BASE_IDX 0 |
|---|
| 3771 | #define regSDMA3_RLC3_IB_BASE_LO 0x1d3e5 |
|---|
| 3772 | #define regSDMA3_RLC3_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3773 | #define regSDMA3_RLC3_IB_BASE_HI 0x1d3e6 |
|---|
| 3774 | #define regSDMA3_RLC3_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3775 | #define regSDMA3_RLC3_IB_SIZE 0x1d3e7 |
|---|
| 3776 | #define regSDMA3_RLC3_IB_SIZE_BASE_IDX 0 |
|---|
| 3777 | #define regSDMA3_RLC3_SKIP_CNTL 0x1d3e8 |
|---|
| 3778 | #define regSDMA3_RLC3_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3779 | #define regSDMA3_RLC3_CONTEXT_STATUS 0x1d3e9 |
|---|
| 3780 | #define regSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3781 | #define regSDMA3_RLC3_DOORBELL 0x1d3ea |
|---|
| 3782 | #define regSDMA3_RLC3_DOORBELL_BASE_IDX 0 |
|---|
| 3783 | #define regSDMA3_RLC3_STATUS 0x1d400 |
|---|
| 3784 | #define regSDMA3_RLC3_STATUS_BASE_IDX 0 |
|---|
| 3785 | #define regSDMA3_RLC3_DOORBELL_LOG 0x1d401 |
|---|
| 3786 | #define regSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3787 | #define regSDMA3_RLC3_WATERMARK 0x1d402 |
|---|
| 3788 | #define regSDMA3_RLC3_WATERMARK_BASE_IDX 0 |
|---|
| 3789 | #define regSDMA3_RLC3_DOORBELL_OFFSET 0x1d403 |
|---|
| 3790 | #define regSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3791 | #define regSDMA3_RLC3_CSA_ADDR_LO 0x1d404 |
|---|
| 3792 | #define regSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3793 | #define regSDMA3_RLC3_CSA_ADDR_HI 0x1d405 |
|---|
| 3794 | #define regSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3795 | #define regSDMA3_RLC3_IB_SUB_REMAIN 0x1d407 |
|---|
| 3796 | #define regSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3797 | #define regSDMA3_RLC3_PREEMPT 0x1d408 |
|---|
| 3798 | #define regSDMA3_RLC3_PREEMPT_BASE_IDX 0 |
|---|
| 3799 | #define regSDMA3_RLC3_DUMMY_REG 0x1d409 |
|---|
| 3800 | #define regSDMA3_RLC3_DUMMY_REG_BASE_IDX 0 |
|---|
| 3801 | #define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d40a |
|---|
| 3802 | #define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3803 | #define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d40b |
|---|
| 3804 | #define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3805 | #define regSDMA3_RLC3_RB_AQL_CNTL 0x1d40c |
|---|
| 3806 | #define regSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3807 | #define regSDMA3_RLC3_MINOR_PTR_UPDATE 0x1d40d |
|---|
| 3808 | #define regSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3809 | #define regSDMA3_RLC3_MIDCMD_DATA0 0x1d418 |
|---|
| 3810 | #define regSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3811 | #define regSDMA3_RLC3_MIDCMD_DATA1 0x1d419 |
|---|
| 3812 | #define regSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3813 | #define regSDMA3_RLC3_MIDCMD_DATA2 0x1d41a |
|---|
| 3814 | #define regSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3815 | #define regSDMA3_RLC3_MIDCMD_DATA3 0x1d41b |
|---|
| 3816 | #define regSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3817 | #define regSDMA3_RLC3_MIDCMD_DATA4 0x1d41c |
|---|
| 3818 | #define regSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3819 | #define regSDMA3_RLC3_MIDCMD_DATA5 0x1d41d |
|---|
| 3820 | #define regSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3821 | #define regSDMA3_RLC3_MIDCMD_DATA6 0x1d41e |
|---|
| 3822 | #define regSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3823 | #define regSDMA3_RLC3_MIDCMD_DATA7 0x1d41f |
|---|
| 3824 | #define regSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3825 | #define regSDMA3_RLC3_MIDCMD_DATA8 0x1d420 |
|---|
| 3826 | #define regSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3827 | #define regSDMA3_RLC3_MIDCMD_DATA9 0x1d421 |
|---|
| 3828 | #define regSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3829 | #define regSDMA3_RLC3_MIDCMD_DATA10 0x1d422 |
|---|
| 3830 | #define regSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3831 | #define regSDMA3_RLC3_MIDCMD_CNTL 0x1d423 |
|---|
| 3832 | #define regSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3833 | #define regSDMA3_RLC4_RB_CNTL 0x1d430 |
|---|
| 3834 | #define regSDMA3_RLC4_RB_CNTL_BASE_IDX 0 |
|---|
| 3835 | #define regSDMA3_RLC4_RB_BASE 0x1d431 |
|---|
| 3836 | #define regSDMA3_RLC4_RB_BASE_BASE_IDX 0 |
|---|
| 3837 | #define regSDMA3_RLC4_RB_BASE_HI 0x1d432 |
|---|
| 3838 | #define regSDMA3_RLC4_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3839 | #define regSDMA3_RLC4_RB_RPTR 0x1d433 |
|---|
| 3840 | #define regSDMA3_RLC4_RB_RPTR_BASE_IDX 0 |
|---|
| 3841 | #define regSDMA3_RLC4_RB_RPTR_HI 0x1d434 |
|---|
| 3842 | #define regSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3843 | #define regSDMA3_RLC4_RB_WPTR 0x1d435 |
|---|
| 3844 | #define regSDMA3_RLC4_RB_WPTR_BASE_IDX 0 |
|---|
| 3845 | #define regSDMA3_RLC4_RB_WPTR_HI 0x1d436 |
|---|
| 3846 | #define regSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3847 | #define regSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x1d437 |
|---|
| 3848 | #define regSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3849 | #define regSDMA3_RLC4_RB_RPTR_ADDR_HI 0x1d438 |
|---|
| 3850 | #define regSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3851 | #define regSDMA3_RLC4_RB_RPTR_ADDR_LO 0x1d439 |
|---|
| 3852 | #define regSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3853 | #define regSDMA3_RLC4_IB_CNTL 0x1d43a |
|---|
| 3854 | #define regSDMA3_RLC4_IB_CNTL_BASE_IDX 0 |
|---|
| 3855 | #define regSDMA3_RLC4_IB_RPTR 0x1d43b |
|---|
| 3856 | #define regSDMA3_RLC4_IB_RPTR_BASE_IDX 0 |
|---|
| 3857 | #define regSDMA3_RLC4_IB_OFFSET 0x1d43c |
|---|
| 3858 | #define regSDMA3_RLC4_IB_OFFSET_BASE_IDX 0 |
|---|
| 3859 | #define regSDMA3_RLC4_IB_BASE_LO 0x1d43d |
|---|
| 3860 | #define regSDMA3_RLC4_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3861 | #define regSDMA3_RLC4_IB_BASE_HI 0x1d43e |
|---|
| 3862 | #define regSDMA3_RLC4_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3863 | #define regSDMA3_RLC4_IB_SIZE 0x1d43f |
|---|
| 3864 | #define regSDMA3_RLC4_IB_SIZE_BASE_IDX 0 |
|---|
| 3865 | #define regSDMA3_RLC4_SKIP_CNTL 0x1d440 |
|---|
| 3866 | #define regSDMA3_RLC4_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3867 | #define regSDMA3_RLC4_CONTEXT_STATUS 0x1d441 |
|---|
| 3868 | #define regSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3869 | #define regSDMA3_RLC4_DOORBELL 0x1d442 |
|---|
| 3870 | #define regSDMA3_RLC4_DOORBELL_BASE_IDX 0 |
|---|
| 3871 | #define regSDMA3_RLC4_STATUS 0x1d458 |
|---|
| 3872 | #define regSDMA3_RLC4_STATUS_BASE_IDX 0 |
|---|
| 3873 | #define regSDMA3_RLC4_DOORBELL_LOG 0x1d459 |
|---|
| 3874 | #define regSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3875 | #define regSDMA3_RLC4_WATERMARK 0x1d45a |
|---|
| 3876 | #define regSDMA3_RLC4_WATERMARK_BASE_IDX 0 |
|---|
| 3877 | #define regSDMA3_RLC4_DOORBELL_OFFSET 0x1d45b |
|---|
| 3878 | #define regSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3879 | #define regSDMA3_RLC4_CSA_ADDR_LO 0x1d45c |
|---|
| 3880 | #define regSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3881 | #define regSDMA3_RLC4_CSA_ADDR_HI 0x1d45d |
|---|
| 3882 | #define regSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3883 | #define regSDMA3_RLC4_IB_SUB_REMAIN 0x1d45f |
|---|
| 3884 | #define regSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3885 | #define regSDMA3_RLC4_PREEMPT 0x1d460 |
|---|
| 3886 | #define regSDMA3_RLC4_PREEMPT_BASE_IDX 0 |
|---|
| 3887 | #define regSDMA3_RLC4_DUMMY_REG 0x1d461 |
|---|
| 3888 | #define regSDMA3_RLC4_DUMMY_REG_BASE_IDX 0 |
|---|
| 3889 | #define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d462 |
|---|
| 3890 | #define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3891 | #define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d463 |
|---|
| 3892 | #define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3893 | #define regSDMA3_RLC4_RB_AQL_CNTL 0x1d464 |
|---|
| 3894 | #define regSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3895 | #define regSDMA3_RLC4_MINOR_PTR_UPDATE 0x1d465 |
|---|
| 3896 | #define regSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3897 | #define regSDMA3_RLC4_MIDCMD_DATA0 0x1d470 |
|---|
| 3898 | #define regSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3899 | #define regSDMA3_RLC4_MIDCMD_DATA1 0x1d471 |
|---|
| 3900 | #define regSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3901 | #define regSDMA3_RLC4_MIDCMD_DATA2 0x1d472 |
|---|
| 3902 | #define regSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3903 | #define regSDMA3_RLC4_MIDCMD_DATA3 0x1d473 |
|---|
| 3904 | #define regSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3905 | #define regSDMA3_RLC4_MIDCMD_DATA4 0x1d474 |
|---|
| 3906 | #define regSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3907 | #define regSDMA3_RLC4_MIDCMD_DATA5 0x1d475 |
|---|
| 3908 | #define regSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3909 | #define regSDMA3_RLC4_MIDCMD_DATA6 0x1d476 |
|---|
| 3910 | #define regSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3911 | #define regSDMA3_RLC4_MIDCMD_DATA7 0x1d477 |
|---|
| 3912 | #define regSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 3913 | #define regSDMA3_RLC4_MIDCMD_DATA8 0x1d478 |
|---|
| 3914 | #define regSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 3915 | #define regSDMA3_RLC4_MIDCMD_DATA9 0x1d479 |
|---|
| 3916 | #define regSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 3917 | #define regSDMA3_RLC4_MIDCMD_DATA10 0x1d47a |
|---|
| 3918 | #define regSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 3919 | #define regSDMA3_RLC4_MIDCMD_CNTL 0x1d47b |
|---|
| 3920 | #define regSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 3921 | #define regSDMA3_RLC5_RB_CNTL 0x1d488 |
|---|
| 3922 | #define regSDMA3_RLC5_RB_CNTL_BASE_IDX 0 |
|---|
| 3923 | #define regSDMA3_RLC5_RB_BASE 0x1d489 |
|---|
| 3924 | #define regSDMA3_RLC5_RB_BASE_BASE_IDX 0 |
|---|
| 3925 | #define regSDMA3_RLC5_RB_BASE_HI 0x1d48a |
|---|
| 3926 | #define regSDMA3_RLC5_RB_BASE_HI_BASE_IDX 0 |
|---|
| 3927 | #define regSDMA3_RLC5_RB_RPTR 0x1d48b |
|---|
| 3928 | #define regSDMA3_RLC5_RB_RPTR_BASE_IDX 0 |
|---|
| 3929 | #define regSDMA3_RLC5_RB_RPTR_HI 0x1d48c |
|---|
| 3930 | #define regSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 3931 | #define regSDMA3_RLC5_RB_WPTR 0x1d48d |
|---|
| 3932 | #define regSDMA3_RLC5_RB_WPTR_BASE_IDX 0 |
|---|
| 3933 | #define regSDMA3_RLC5_RB_WPTR_HI 0x1d48e |
|---|
| 3934 | #define regSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 3935 | #define regSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x1d48f |
|---|
| 3936 | #define regSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 3937 | #define regSDMA3_RLC5_RB_RPTR_ADDR_HI 0x1d490 |
|---|
| 3938 | #define regSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 3939 | #define regSDMA3_RLC5_RB_RPTR_ADDR_LO 0x1d491 |
|---|
| 3940 | #define regSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 3941 | #define regSDMA3_RLC5_IB_CNTL 0x1d492 |
|---|
| 3942 | #define regSDMA3_RLC5_IB_CNTL_BASE_IDX 0 |
|---|
| 3943 | #define regSDMA3_RLC5_IB_RPTR 0x1d493 |
|---|
| 3944 | #define regSDMA3_RLC5_IB_RPTR_BASE_IDX 0 |
|---|
| 3945 | #define regSDMA3_RLC5_IB_OFFSET 0x1d494 |
|---|
| 3946 | #define regSDMA3_RLC5_IB_OFFSET_BASE_IDX 0 |
|---|
| 3947 | #define regSDMA3_RLC5_IB_BASE_LO 0x1d495 |
|---|
| 3948 | #define regSDMA3_RLC5_IB_BASE_LO_BASE_IDX 0 |
|---|
| 3949 | #define regSDMA3_RLC5_IB_BASE_HI 0x1d496 |
|---|
| 3950 | #define regSDMA3_RLC5_IB_BASE_HI_BASE_IDX 0 |
|---|
| 3951 | #define regSDMA3_RLC5_IB_SIZE 0x1d497 |
|---|
| 3952 | #define regSDMA3_RLC5_IB_SIZE_BASE_IDX 0 |
|---|
| 3953 | #define regSDMA3_RLC5_SKIP_CNTL 0x1d498 |
|---|
| 3954 | #define regSDMA3_RLC5_SKIP_CNTL_BASE_IDX 0 |
|---|
| 3955 | #define regSDMA3_RLC5_CONTEXT_STATUS 0x1d499 |
|---|
| 3956 | #define regSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 3957 | #define regSDMA3_RLC5_DOORBELL 0x1d49a |
|---|
| 3958 | #define regSDMA3_RLC5_DOORBELL_BASE_IDX 0 |
|---|
| 3959 | #define regSDMA3_RLC5_STATUS 0x1d4b0 |
|---|
| 3960 | #define regSDMA3_RLC5_STATUS_BASE_IDX 0 |
|---|
| 3961 | #define regSDMA3_RLC5_DOORBELL_LOG 0x1d4b1 |
|---|
| 3962 | #define regSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 3963 | #define regSDMA3_RLC5_WATERMARK 0x1d4b2 |
|---|
| 3964 | #define regSDMA3_RLC5_WATERMARK_BASE_IDX 0 |
|---|
| 3965 | #define regSDMA3_RLC5_DOORBELL_OFFSET 0x1d4b3 |
|---|
| 3966 | #define regSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 3967 | #define regSDMA3_RLC5_CSA_ADDR_LO 0x1d4b4 |
|---|
| 3968 | #define regSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 3969 | #define regSDMA3_RLC5_CSA_ADDR_HI 0x1d4b5 |
|---|
| 3970 | #define regSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 3971 | #define regSDMA3_RLC5_IB_SUB_REMAIN 0x1d4b7 |
|---|
| 3972 | #define regSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 3973 | #define regSDMA3_RLC5_PREEMPT 0x1d4b8 |
|---|
| 3974 | #define regSDMA3_RLC5_PREEMPT_BASE_IDX 0 |
|---|
| 3975 | #define regSDMA3_RLC5_DUMMY_REG 0x1d4b9 |
|---|
| 3976 | #define regSDMA3_RLC5_DUMMY_REG_BASE_IDX 0 |
|---|
| 3977 | #define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d4ba |
|---|
| 3978 | #define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 3979 | #define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d4bb |
|---|
| 3980 | #define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 3981 | #define regSDMA3_RLC5_RB_AQL_CNTL 0x1d4bc |
|---|
| 3982 | #define regSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 3983 | #define regSDMA3_RLC5_MINOR_PTR_UPDATE 0x1d4bd |
|---|
| 3984 | #define regSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 3985 | #define regSDMA3_RLC5_MIDCMD_DATA0 0x1d4c8 |
|---|
| 3986 | #define regSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 3987 | #define regSDMA3_RLC5_MIDCMD_DATA1 0x1d4c9 |
|---|
| 3988 | #define regSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 3989 | #define regSDMA3_RLC5_MIDCMD_DATA2 0x1d4ca |
|---|
| 3990 | #define regSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 3991 | #define regSDMA3_RLC5_MIDCMD_DATA3 0x1d4cb |
|---|
| 3992 | #define regSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 3993 | #define regSDMA3_RLC5_MIDCMD_DATA4 0x1d4cc |
|---|
| 3994 | #define regSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 3995 | #define regSDMA3_RLC5_MIDCMD_DATA5 0x1d4cd |
|---|
| 3996 | #define regSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 3997 | #define regSDMA3_RLC5_MIDCMD_DATA6 0x1d4ce |
|---|
| 3998 | #define regSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 3999 | #define regSDMA3_RLC5_MIDCMD_DATA7 0x1d4cf |
|---|
| 4000 | #define regSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4001 | #define regSDMA3_RLC5_MIDCMD_DATA8 0x1d4d0 |
|---|
| 4002 | #define regSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4003 | #define regSDMA3_RLC5_MIDCMD_DATA9 0x1d4d1 |
|---|
| 4004 | #define regSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4005 | #define regSDMA3_RLC5_MIDCMD_DATA10 0x1d4d2 |
|---|
| 4006 | #define regSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4007 | #define regSDMA3_RLC5_MIDCMD_CNTL 0x1d4d3 |
|---|
| 4008 | #define regSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4009 | #define regSDMA3_RLC6_RB_CNTL 0x1d4e0 |
|---|
| 4010 | #define regSDMA3_RLC6_RB_CNTL_BASE_IDX 0 |
|---|
| 4011 | #define regSDMA3_RLC6_RB_BASE 0x1d4e1 |
|---|
| 4012 | #define regSDMA3_RLC6_RB_BASE_BASE_IDX 0 |
|---|
| 4013 | #define regSDMA3_RLC6_RB_BASE_HI 0x1d4e2 |
|---|
| 4014 | #define regSDMA3_RLC6_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4015 | #define regSDMA3_RLC6_RB_RPTR 0x1d4e3 |
|---|
| 4016 | #define regSDMA3_RLC6_RB_RPTR_BASE_IDX 0 |
|---|
| 4017 | #define regSDMA3_RLC6_RB_RPTR_HI 0x1d4e4 |
|---|
| 4018 | #define regSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4019 | #define regSDMA3_RLC6_RB_WPTR 0x1d4e5 |
|---|
| 4020 | #define regSDMA3_RLC6_RB_WPTR_BASE_IDX 0 |
|---|
| 4021 | #define regSDMA3_RLC6_RB_WPTR_HI 0x1d4e6 |
|---|
| 4022 | #define regSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4023 | #define regSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x1d4e7 |
|---|
| 4024 | #define regSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4025 | #define regSDMA3_RLC6_RB_RPTR_ADDR_HI 0x1d4e8 |
|---|
| 4026 | #define regSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4027 | #define regSDMA3_RLC6_RB_RPTR_ADDR_LO 0x1d4e9 |
|---|
| 4028 | #define regSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4029 | #define regSDMA3_RLC6_IB_CNTL 0x1d4ea |
|---|
| 4030 | #define regSDMA3_RLC6_IB_CNTL_BASE_IDX 0 |
|---|
| 4031 | #define regSDMA3_RLC6_IB_RPTR 0x1d4eb |
|---|
| 4032 | #define regSDMA3_RLC6_IB_RPTR_BASE_IDX 0 |
|---|
| 4033 | #define regSDMA3_RLC6_IB_OFFSET 0x1d4ec |
|---|
| 4034 | #define regSDMA3_RLC6_IB_OFFSET_BASE_IDX 0 |
|---|
| 4035 | #define regSDMA3_RLC6_IB_BASE_LO 0x1d4ed |
|---|
| 4036 | #define regSDMA3_RLC6_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4037 | #define regSDMA3_RLC6_IB_BASE_HI 0x1d4ee |
|---|
| 4038 | #define regSDMA3_RLC6_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4039 | #define regSDMA3_RLC6_IB_SIZE 0x1d4ef |
|---|
| 4040 | #define regSDMA3_RLC6_IB_SIZE_BASE_IDX 0 |
|---|
| 4041 | #define regSDMA3_RLC6_SKIP_CNTL 0x1d4f0 |
|---|
| 4042 | #define regSDMA3_RLC6_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4043 | #define regSDMA3_RLC6_CONTEXT_STATUS 0x1d4f1 |
|---|
| 4044 | #define regSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4045 | #define regSDMA3_RLC6_DOORBELL 0x1d4f2 |
|---|
| 4046 | #define regSDMA3_RLC6_DOORBELL_BASE_IDX 0 |
|---|
| 4047 | #define regSDMA3_RLC6_STATUS 0x1d508 |
|---|
| 4048 | #define regSDMA3_RLC6_STATUS_BASE_IDX 0 |
|---|
| 4049 | #define regSDMA3_RLC6_DOORBELL_LOG 0x1d509 |
|---|
| 4050 | #define regSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4051 | #define regSDMA3_RLC6_WATERMARK 0x1d50a |
|---|
| 4052 | #define regSDMA3_RLC6_WATERMARK_BASE_IDX 0 |
|---|
| 4053 | #define regSDMA3_RLC6_DOORBELL_OFFSET 0x1d50b |
|---|
| 4054 | #define regSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4055 | #define regSDMA3_RLC6_CSA_ADDR_LO 0x1d50c |
|---|
| 4056 | #define regSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4057 | #define regSDMA3_RLC6_CSA_ADDR_HI 0x1d50d |
|---|
| 4058 | #define regSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4059 | #define regSDMA3_RLC6_IB_SUB_REMAIN 0x1d50f |
|---|
| 4060 | #define regSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4061 | #define regSDMA3_RLC6_PREEMPT 0x1d510 |
|---|
| 4062 | #define regSDMA3_RLC6_PREEMPT_BASE_IDX 0 |
|---|
| 4063 | #define regSDMA3_RLC6_DUMMY_REG 0x1d511 |
|---|
| 4064 | #define regSDMA3_RLC6_DUMMY_REG_BASE_IDX 0 |
|---|
| 4065 | #define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d512 |
|---|
| 4066 | #define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4067 | #define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d513 |
|---|
| 4068 | #define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4069 | #define regSDMA3_RLC6_RB_AQL_CNTL 0x1d514 |
|---|
| 4070 | #define regSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4071 | #define regSDMA3_RLC6_MINOR_PTR_UPDATE 0x1d515 |
|---|
| 4072 | #define regSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4073 | #define regSDMA3_RLC6_MIDCMD_DATA0 0x1d520 |
|---|
| 4074 | #define regSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4075 | #define regSDMA3_RLC6_MIDCMD_DATA1 0x1d521 |
|---|
| 4076 | #define regSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4077 | #define regSDMA3_RLC6_MIDCMD_DATA2 0x1d522 |
|---|
| 4078 | #define regSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4079 | #define regSDMA3_RLC6_MIDCMD_DATA3 0x1d523 |
|---|
| 4080 | #define regSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4081 | #define regSDMA3_RLC6_MIDCMD_DATA4 0x1d524 |
|---|
| 4082 | #define regSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4083 | #define regSDMA3_RLC6_MIDCMD_DATA5 0x1d525 |
|---|
| 4084 | #define regSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4085 | #define regSDMA3_RLC6_MIDCMD_DATA6 0x1d526 |
|---|
| 4086 | #define regSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4087 | #define regSDMA3_RLC6_MIDCMD_DATA7 0x1d527 |
|---|
| 4088 | #define regSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4089 | #define regSDMA3_RLC6_MIDCMD_DATA8 0x1d528 |
|---|
| 4090 | #define regSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4091 | #define regSDMA3_RLC6_MIDCMD_DATA9 0x1d529 |
|---|
| 4092 | #define regSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4093 | #define regSDMA3_RLC6_MIDCMD_DATA10 0x1d52a |
|---|
| 4094 | #define regSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4095 | #define regSDMA3_RLC6_MIDCMD_CNTL 0x1d52b |
|---|
| 4096 | #define regSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4097 | #define regSDMA3_RLC7_RB_CNTL 0x1d538 |
|---|
| 4098 | #define regSDMA3_RLC7_RB_CNTL_BASE_IDX 0 |
|---|
| 4099 | #define regSDMA3_RLC7_RB_BASE 0x1d539 |
|---|
| 4100 | #define regSDMA3_RLC7_RB_BASE_BASE_IDX 0 |
|---|
| 4101 | #define regSDMA3_RLC7_RB_BASE_HI 0x1d53a |
|---|
| 4102 | #define regSDMA3_RLC7_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4103 | #define regSDMA3_RLC7_RB_RPTR 0x1d53b |
|---|
| 4104 | #define regSDMA3_RLC7_RB_RPTR_BASE_IDX 0 |
|---|
| 4105 | #define regSDMA3_RLC7_RB_RPTR_HI 0x1d53c |
|---|
| 4106 | #define regSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4107 | #define regSDMA3_RLC7_RB_WPTR 0x1d53d |
|---|
| 4108 | #define regSDMA3_RLC7_RB_WPTR_BASE_IDX 0 |
|---|
| 4109 | #define regSDMA3_RLC7_RB_WPTR_HI 0x1d53e |
|---|
| 4110 | #define regSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4111 | #define regSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x1d53f |
|---|
| 4112 | #define regSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4113 | #define regSDMA3_RLC7_RB_RPTR_ADDR_HI 0x1d540 |
|---|
| 4114 | #define regSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4115 | #define regSDMA3_RLC7_RB_RPTR_ADDR_LO 0x1d541 |
|---|
| 4116 | #define regSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4117 | #define regSDMA3_RLC7_IB_CNTL 0x1d542 |
|---|
| 4118 | #define regSDMA3_RLC7_IB_CNTL_BASE_IDX 0 |
|---|
| 4119 | #define regSDMA3_RLC7_IB_RPTR 0x1d543 |
|---|
| 4120 | #define regSDMA3_RLC7_IB_RPTR_BASE_IDX 0 |
|---|
| 4121 | #define regSDMA3_RLC7_IB_OFFSET 0x1d544 |
|---|
| 4122 | #define regSDMA3_RLC7_IB_OFFSET_BASE_IDX 0 |
|---|
| 4123 | #define regSDMA3_RLC7_IB_BASE_LO 0x1d545 |
|---|
| 4124 | #define regSDMA3_RLC7_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4125 | #define regSDMA3_RLC7_IB_BASE_HI 0x1d546 |
|---|
| 4126 | #define regSDMA3_RLC7_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4127 | #define regSDMA3_RLC7_IB_SIZE 0x1d547 |
|---|
| 4128 | #define regSDMA3_RLC7_IB_SIZE_BASE_IDX 0 |
|---|
| 4129 | #define regSDMA3_RLC7_SKIP_CNTL 0x1d548 |
|---|
| 4130 | #define regSDMA3_RLC7_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4131 | #define regSDMA3_RLC7_CONTEXT_STATUS 0x1d549 |
|---|
| 4132 | #define regSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4133 | #define regSDMA3_RLC7_DOORBELL 0x1d54a |
|---|
| 4134 | #define regSDMA3_RLC7_DOORBELL_BASE_IDX 0 |
|---|
| 4135 | #define regSDMA3_RLC7_STATUS 0x1d560 |
|---|
| 4136 | #define regSDMA3_RLC7_STATUS_BASE_IDX 0 |
|---|
| 4137 | #define regSDMA3_RLC7_DOORBELL_LOG 0x1d561 |
|---|
| 4138 | #define regSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4139 | #define regSDMA3_RLC7_WATERMARK 0x1d562 |
|---|
| 4140 | #define regSDMA3_RLC7_WATERMARK_BASE_IDX 0 |
|---|
| 4141 | #define regSDMA3_RLC7_DOORBELL_OFFSET 0x1d563 |
|---|
| 4142 | #define regSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4143 | #define regSDMA3_RLC7_CSA_ADDR_LO 0x1d564 |
|---|
| 4144 | #define regSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4145 | #define regSDMA3_RLC7_CSA_ADDR_HI 0x1d565 |
|---|
| 4146 | #define regSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4147 | #define regSDMA3_RLC7_IB_SUB_REMAIN 0x1d567 |
|---|
| 4148 | #define regSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4149 | #define regSDMA3_RLC7_PREEMPT 0x1d568 |
|---|
| 4150 | #define regSDMA3_RLC7_PREEMPT_BASE_IDX 0 |
|---|
| 4151 | #define regSDMA3_RLC7_DUMMY_REG 0x1d569 |
|---|
| 4152 | #define regSDMA3_RLC7_DUMMY_REG_BASE_IDX 0 |
|---|
| 4153 | #define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d56a |
|---|
| 4154 | #define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4155 | #define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d56b |
|---|
| 4156 | #define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4157 | #define regSDMA3_RLC7_RB_AQL_CNTL 0x1d56c |
|---|
| 4158 | #define regSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4159 | #define regSDMA3_RLC7_MINOR_PTR_UPDATE 0x1d56d |
|---|
| 4160 | #define regSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4161 | #define regSDMA3_RLC7_MIDCMD_DATA0 0x1d578 |
|---|
| 4162 | #define regSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4163 | #define regSDMA3_RLC7_MIDCMD_DATA1 0x1d579 |
|---|
| 4164 | #define regSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4165 | #define regSDMA3_RLC7_MIDCMD_DATA2 0x1d57a |
|---|
| 4166 | #define regSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4167 | #define regSDMA3_RLC7_MIDCMD_DATA3 0x1d57b |
|---|
| 4168 | #define regSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4169 | #define regSDMA3_RLC7_MIDCMD_DATA4 0x1d57c |
|---|
| 4170 | #define regSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4171 | #define regSDMA3_RLC7_MIDCMD_DATA5 0x1d57d |
|---|
| 4172 | #define regSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4173 | #define regSDMA3_RLC7_MIDCMD_DATA6 0x1d57e |
|---|
| 4174 | #define regSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4175 | #define regSDMA3_RLC7_MIDCMD_DATA7 0x1d57f |
|---|
| 4176 | #define regSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4177 | #define regSDMA3_RLC7_MIDCMD_DATA8 0x1d580 |
|---|
| 4178 | #define regSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4179 | #define regSDMA3_RLC7_MIDCMD_DATA9 0x1d581 |
|---|
| 4180 | #define regSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4181 | #define regSDMA3_RLC7_MIDCMD_DATA10 0x1d582 |
|---|
| 4182 | #define regSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4183 | #define regSDMA3_RLC7_MIDCMD_CNTL 0x1d583 |
|---|
| 4184 | #define regSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4185 | |
|---|
| 4186 | |
|---|
| 4187 | // addressBlock: sdma0_sdma4dec |
|---|
| 4188 | // base address: 0x7a000 |
|---|
| 4189 | #define regSDMA4_UCODE_ADDR 0x1d5a0 |
|---|
| 4190 | #define regSDMA4_UCODE_ADDR_BASE_IDX 0 |
|---|
| 4191 | #define regSDMA4_UCODE_DATA 0x1d5a1 |
|---|
| 4192 | #define regSDMA4_UCODE_DATA_BASE_IDX 0 |
|---|
| 4193 | #define regSDMA4_VF_ENABLE 0x1d5aa |
|---|
| 4194 | #define regSDMA4_VF_ENABLE_BASE_IDX 0 |
|---|
| 4195 | #define regSDMA4_CONTEXT_GROUP_BOUNDARY 0x1d5b9 |
|---|
| 4196 | #define regSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
|---|
| 4197 | #define regSDMA4_POWER_CNTL 0x1d5ba |
|---|
| 4198 | #define regSDMA4_POWER_CNTL_BASE_IDX 0 |
|---|
| 4199 | #define regSDMA4_CLK_CTRL 0x1d5bb |
|---|
| 4200 | #define regSDMA4_CLK_CTRL_BASE_IDX 0 |
|---|
| 4201 | #define regSDMA4_CNTL 0x1d5bc |
|---|
| 4202 | #define regSDMA4_CNTL_BASE_IDX 0 |
|---|
| 4203 | #define regSDMA4_CHICKEN_BITS 0x1d5bd |
|---|
| 4204 | #define regSDMA4_CHICKEN_BITS_BASE_IDX 0 |
|---|
| 4205 | #define regSDMA4_GB_ADDR_CONFIG 0x1d5be |
|---|
| 4206 | #define regSDMA4_GB_ADDR_CONFIG_BASE_IDX 0 |
|---|
| 4207 | #define regSDMA4_GB_ADDR_CONFIG_READ 0x1d5bf |
|---|
| 4208 | #define regSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
|---|
| 4209 | #define regSDMA4_RB_RPTR_FETCH_HI 0x1d5c0 |
|---|
| 4210 | #define regSDMA4_RB_RPTR_FETCH_HI_BASE_IDX 0 |
|---|
| 4211 | #define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL 0x1d5c1 |
|---|
| 4212 | #define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
|---|
| 4213 | #define regSDMA4_RB_RPTR_FETCH 0x1d5c2 |
|---|
| 4214 | #define regSDMA4_RB_RPTR_FETCH_BASE_IDX 0 |
|---|
| 4215 | #define regSDMA4_IB_OFFSET_FETCH 0x1d5c3 |
|---|
| 4216 | #define regSDMA4_IB_OFFSET_FETCH_BASE_IDX 0 |
|---|
| 4217 | #define regSDMA4_PROGRAM 0x1d5c4 |
|---|
| 4218 | #define regSDMA4_PROGRAM_BASE_IDX 0 |
|---|
| 4219 | #define regSDMA4_STATUS_REG 0x1d5c5 |
|---|
| 4220 | #define regSDMA4_STATUS_REG_BASE_IDX 0 |
|---|
| 4221 | #define regSDMA4_STATUS1_REG 0x1d5c6 |
|---|
| 4222 | #define regSDMA4_STATUS1_REG_BASE_IDX 0 |
|---|
| 4223 | #define regSDMA4_RD_BURST_CNTL 0x1d5c7 |
|---|
| 4224 | #define regSDMA4_RD_BURST_CNTL_BASE_IDX 0 |
|---|
| 4225 | #define regSDMA4_HBM_PAGE_CONFIG 0x1d5c8 |
|---|
| 4226 | #define regSDMA4_HBM_PAGE_CONFIG_BASE_IDX 0 |
|---|
| 4227 | #define regSDMA4_UCODE_CHECKSUM 0x1d5c9 |
|---|
| 4228 | #define regSDMA4_UCODE_CHECKSUM_BASE_IDX 0 |
|---|
| 4229 | #define regSDMA4_F32_CNTL 0x1d5ca |
|---|
| 4230 | #define regSDMA4_F32_CNTL_BASE_IDX 0 |
|---|
| 4231 | #define regSDMA4_FREEZE 0x1d5cb |
|---|
| 4232 | #define regSDMA4_FREEZE_BASE_IDX 0 |
|---|
| 4233 | #define regSDMA4_PHASE0_QUANTUM 0x1d5cc |
|---|
| 4234 | #define regSDMA4_PHASE0_QUANTUM_BASE_IDX 0 |
|---|
| 4235 | #define regSDMA4_PHASE1_QUANTUM 0x1d5cd |
|---|
| 4236 | #define regSDMA4_PHASE1_QUANTUM_BASE_IDX 0 |
|---|
| 4237 | #define regCC_SDMA4_EDC_CONFIG 0x1d5d2 |
|---|
| 4238 | #define regCC_SDMA4_EDC_CONFIG_BASE_IDX 0 |
|---|
| 4239 | #define regSDMA4_BA_THRESHOLD 0x1d5d3 |
|---|
| 4240 | #define regSDMA4_BA_THRESHOLD_BASE_IDX 0 |
|---|
| 4241 | #define regSDMA4_ID 0x1d5d4 |
|---|
| 4242 | #define regSDMA4_ID_BASE_IDX 0 |
|---|
| 4243 | #define regSDMA4_VERSION 0x1d5d5 |
|---|
| 4244 | #define regSDMA4_VERSION_BASE_IDX 0 |
|---|
| 4245 | #define regSDMA4_EDC_COUNTER 0x1d5d6 |
|---|
| 4246 | #define regSDMA4_EDC_COUNTER_BASE_IDX 0 |
|---|
| 4247 | #define regSDMA4_EDC_COUNTER2 0x1d5d7 |
|---|
| 4248 | #define regSDMA4_EDC_COUNTER2_BASE_IDX 0 |
|---|
| 4249 | #define regSDMA4_STATUS2_REG 0x1d5d8 |
|---|
| 4250 | #define regSDMA4_STATUS2_REG_BASE_IDX 0 |
|---|
| 4251 | #define regSDMA4_ATOMIC_CNTL 0x1d5d9 |
|---|
| 4252 | #define regSDMA4_ATOMIC_CNTL_BASE_IDX 0 |
|---|
| 4253 | #define regSDMA4_ATOMIC_PREOP_LO 0x1d5da |
|---|
| 4254 | #define regSDMA4_ATOMIC_PREOP_LO_BASE_IDX 0 |
|---|
| 4255 | #define regSDMA4_ATOMIC_PREOP_HI 0x1d5db |
|---|
| 4256 | #define regSDMA4_ATOMIC_PREOP_HI_BASE_IDX 0 |
|---|
| 4257 | #define regSDMA4_UTCL1_CNTL 0x1d5dc |
|---|
| 4258 | #define regSDMA4_UTCL1_CNTL_BASE_IDX 0 |
|---|
| 4259 | #define regSDMA4_UTCL1_WATERMK 0x1d5dd |
|---|
| 4260 | #define regSDMA4_UTCL1_WATERMK_BASE_IDX 0 |
|---|
| 4261 | #define regSDMA4_UTCL1_RD_STATUS 0x1d5de |
|---|
| 4262 | #define regSDMA4_UTCL1_RD_STATUS_BASE_IDX 0 |
|---|
| 4263 | #define regSDMA4_UTCL1_WR_STATUS 0x1d5df |
|---|
| 4264 | #define regSDMA4_UTCL1_WR_STATUS_BASE_IDX 0 |
|---|
| 4265 | #define regSDMA4_UTCL1_INV0 0x1d5e0 |
|---|
| 4266 | #define regSDMA4_UTCL1_INV0_BASE_IDX 0 |
|---|
| 4267 | #define regSDMA4_UTCL1_INV1 0x1d5e1 |
|---|
| 4268 | #define regSDMA4_UTCL1_INV1_BASE_IDX 0 |
|---|
| 4269 | #define regSDMA4_UTCL1_INV2 0x1d5e2 |
|---|
| 4270 | #define regSDMA4_UTCL1_INV2_BASE_IDX 0 |
|---|
| 4271 | #define regSDMA4_UTCL1_RD_XNACK0 0x1d5e3 |
|---|
| 4272 | #define regSDMA4_UTCL1_RD_XNACK0_BASE_IDX 0 |
|---|
| 4273 | #define regSDMA4_UTCL1_RD_XNACK1 0x1d5e4 |
|---|
| 4274 | #define regSDMA4_UTCL1_RD_XNACK1_BASE_IDX 0 |
|---|
| 4275 | #define regSDMA4_UTCL1_WR_XNACK0 0x1d5e5 |
|---|
| 4276 | #define regSDMA4_UTCL1_WR_XNACK0_BASE_IDX 0 |
|---|
| 4277 | #define regSDMA4_UTCL1_WR_XNACK1 0x1d5e6 |
|---|
| 4278 | #define regSDMA4_UTCL1_WR_XNACK1_BASE_IDX 0 |
|---|
| 4279 | #define regSDMA4_UTCL1_TIMEOUT 0x1d5e7 |
|---|
| 4280 | #define regSDMA4_UTCL1_TIMEOUT_BASE_IDX 0 |
|---|
| 4281 | #define regSDMA4_UTCL1_PAGE 0x1d5e8 |
|---|
| 4282 | #define regSDMA4_UTCL1_PAGE_BASE_IDX 0 |
|---|
| 4283 | #define regSDMA4_POWER_CNTL_IDLE 0x1d5e9 |
|---|
| 4284 | #define regSDMA4_POWER_CNTL_IDLE_BASE_IDX 0 |
|---|
| 4285 | #define regSDMA4_RELAX_ORDERING_LUT 0x1d5ea |
|---|
| 4286 | #define regSDMA4_RELAX_ORDERING_LUT_BASE_IDX 0 |
|---|
| 4287 | #define regSDMA4_CHICKEN_BITS_2 0x1d5eb |
|---|
| 4288 | #define regSDMA4_CHICKEN_BITS_2_BASE_IDX 0 |
|---|
| 4289 | #define regSDMA4_STATUS3_REG 0x1d5ec |
|---|
| 4290 | #define regSDMA4_STATUS3_REG_BASE_IDX 0 |
|---|
| 4291 | #define regSDMA4_PHYSICAL_ADDR_LO 0x1d5ed |
|---|
| 4292 | #define regSDMA4_PHYSICAL_ADDR_LO_BASE_IDX 0 |
|---|
| 4293 | #define regSDMA4_PHYSICAL_ADDR_HI 0x1d5ee |
|---|
| 4294 | #define regSDMA4_PHYSICAL_ADDR_HI_BASE_IDX 0 |
|---|
| 4295 | #define regSDMA4_PHASE2_QUANTUM 0x1d5ef |
|---|
| 4296 | #define regSDMA4_PHASE2_QUANTUM_BASE_IDX 0 |
|---|
| 4297 | #define regSDMA4_ERROR_LOG 0x1d5f0 |
|---|
| 4298 | #define regSDMA4_ERROR_LOG_BASE_IDX 0 |
|---|
| 4299 | #define regSDMA4_PUB_DUMMY_REG0 0x1d5f1 |
|---|
| 4300 | #define regSDMA4_PUB_DUMMY_REG0_BASE_IDX 0 |
|---|
| 4301 | #define regSDMA4_PUB_DUMMY_REG1 0x1d5f2 |
|---|
| 4302 | #define regSDMA4_PUB_DUMMY_REG1_BASE_IDX 0 |
|---|
| 4303 | #define regSDMA4_PUB_DUMMY_REG2 0x1d5f3 |
|---|
| 4304 | #define regSDMA4_PUB_DUMMY_REG2_BASE_IDX 0 |
|---|
| 4305 | #define regSDMA4_PUB_DUMMY_REG3 0x1d5f4 |
|---|
| 4306 | #define regSDMA4_PUB_DUMMY_REG3_BASE_IDX 0 |
|---|
| 4307 | #define regSDMA4_F32_COUNTER 0x1d5f5 |
|---|
| 4308 | #define regSDMA4_F32_COUNTER_BASE_IDX 0 |
|---|
| 4309 | #define regSDMA4_PERFCNT_PERFCOUNTER0_CFG 0x1d5f7 |
|---|
| 4310 | #define regSDMA4_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 |
|---|
| 4311 | #define regSDMA4_PERFCNT_PERFCOUNTER1_CFG 0x1d5f8 |
|---|
| 4312 | #define regSDMA4_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 |
|---|
| 4313 | #define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1d5f9 |
|---|
| 4314 | #define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
|---|
| 4315 | #define regSDMA4_PERFCNT_MISC_CNTL 0x1d5fa |
|---|
| 4316 | #define regSDMA4_PERFCNT_MISC_CNTL_BASE_IDX 0 |
|---|
| 4317 | #define regSDMA4_PERFCNT_PERFCOUNTER_LO 0x1d5fb |
|---|
| 4318 | #define regSDMA4_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 |
|---|
| 4319 | #define regSDMA4_PERFCNT_PERFCOUNTER_HI 0x1d5fc |
|---|
| 4320 | #define regSDMA4_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 |
|---|
| 4321 | #define regSDMA4_CRD_CNTL 0x1d5fd |
|---|
| 4322 | #define regSDMA4_CRD_CNTL_BASE_IDX 0 |
|---|
| 4323 | #define regSDMA4_ULV_CNTL 0x1d5ff |
|---|
| 4324 | #define regSDMA4_ULV_CNTL_BASE_IDX 0 |
|---|
| 4325 | #define regSDMA4_EA_DBIT_ADDR_DATA 0x1d600 |
|---|
| 4326 | #define regSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
|---|
| 4327 | #define regSDMA4_EA_DBIT_ADDR_INDEX 0x1d601 |
|---|
| 4328 | #define regSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
|---|
| 4329 | #define regSDMA4_STATUS4_REG 0x1d603 |
|---|
| 4330 | #define regSDMA4_STATUS4_REG_BASE_IDX 0 |
|---|
| 4331 | #define regSDMA4_SCRATCH_RAM_DATA 0x1d604 |
|---|
| 4332 | #define regSDMA4_SCRATCH_RAM_DATA_BASE_IDX 0 |
|---|
| 4333 | #define regSDMA4_SCRATCH_RAM_ADDR 0x1d605 |
|---|
| 4334 | #define regSDMA4_SCRATCH_RAM_ADDR_BASE_IDX 0 |
|---|
| 4335 | #define regSDMA4_CE_CTRL 0x1d606 |
|---|
| 4336 | #define regSDMA4_CE_CTRL_BASE_IDX 0 |
|---|
| 4337 | #define regSDMA4_RAS_STATUS 0x1d607 |
|---|
| 4338 | #define regSDMA4_RAS_STATUS_BASE_IDX 0 |
|---|
| 4339 | #define regSDMA4_CLK_STATUS 0x1d608 |
|---|
| 4340 | #define regSDMA4_CLK_STATUS_BASE_IDX 0 |
|---|
| 4341 | #define regSDMA4_GFX_RB_CNTL 0x1d620 |
|---|
| 4342 | #define regSDMA4_GFX_RB_CNTL_BASE_IDX 0 |
|---|
| 4343 | #define regSDMA4_GFX_RB_BASE 0x1d621 |
|---|
| 4344 | #define regSDMA4_GFX_RB_BASE_BASE_IDX 0 |
|---|
| 4345 | #define regSDMA4_GFX_RB_BASE_HI 0x1d622 |
|---|
| 4346 | #define regSDMA4_GFX_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4347 | #define regSDMA4_GFX_RB_RPTR 0x1d623 |
|---|
| 4348 | #define regSDMA4_GFX_RB_RPTR_BASE_IDX 0 |
|---|
| 4349 | #define regSDMA4_GFX_RB_RPTR_HI 0x1d624 |
|---|
| 4350 | #define regSDMA4_GFX_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4351 | #define regSDMA4_GFX_RB_WPTR 0x1d625 |
|---|
| 4352 | #define regSDMA4_GFX_RB_WPTR_BASE_IDX 0 |
|---|
| 4353 | #define regSDMA4_GFX_RB_WPTR_HI 0x1d626 |
|---|
| 4354 | #define regSDMA4_GFX_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4355 | #define regSDMA4_GFX_RB_WPTR_POLL_CNTL 0x1d627 |
|---|
| 4356 | #define regSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4357 | #define regSDMA4_GFX_RB_RPTR_ADDR_HI 0x1d628 |
|---|
| 4358 | #define regSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4359 | #define regSDMA4_GFX_RB_RPTR_ADDR_LO 0x1d629 |
|---|
| 4360 | #define regSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4361 | #define regSDMA4_GFX_IB_CNTL 0x1d62a |
|---|
| 4362 | #define regSDMA4_GFX_IB_CNTL_BASE_IDX 0 |
|---|
| 4363 | #define regSDMA4_GFX_IB_RPTR 0x1d62b |
|---|
| 4364 | #define regSDMA4_GFX_IB_RPTR_BASE_IDX 0 |
|---|
| 4365 | #define regSDMA4_GFX_IB_OFFSET 0x1d62c |
|---|
| 4366 | #define regSDMA4_GFX_IB_OFFSET_BASE_IDX 0 |
|---|
| 4367 | #define regSDMA4_GFX_IB_BASE_LO 0x1d62d |
|---|
| 4368 | #define regSDMA4_GFX_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4369 | #define regSDMA4_GFX_IB_BASE_HI 0x1d62e |
|---|
| 4370 | #define regSDMA4_GFX_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4371 | #define regSDMA4_GFX_IB_SIZE 0x1d62f |
|---|
| 4372 | #define regSDMA4_GFX_IB_SIZE_BASE_IDX 0 |
|---|
| 4373 | #define regSDMA4_GFX_SKIP_CNTL 0x1d630 |
|---|
| 4374 | #define regSDMA4_GFX_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4375 | #define regSDMA4_GFX_CONTEXT_STATUS 0x1d631 |
|---|
| 4376 | #define regSDMA4_GFX_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4377 | #define regSDMA4_GFX_DOORBELL 0x1d632 |
|---|
| 4378 | #define regSDMA4_GFX_DOORBELL_BASE_IDX 0 |
|---|
| 4379 | #define regSDMA4_GFX_CONTEXT_CNTL 0x1d633 |
|---|
| 4380 | #define regSDMA4_GFX_CONTEXT_CNTL_BASE_IDX 0 |
|---|
| 4381 | #define regSDMA4_GFX_STATUS 0x1d648 |
|---|
| 4382 | #define regSDMA4_GFX_STATUS_BASE_IDX 0 |
|---|
| 4383 | #define regSDMA4_GFX_DOORBELL_LOG 0x1d649 |
|---|
| 4384 | #define regSDMA4_GFX_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4385 | #define regSDMA4_GFX_WATERMARK 0x1d64a |
|---|
| 4386 | #define regSDMA4_GFX_WATERMARK_BASE_IDX 0 |
|---|
| 4387 | #define regSDMA4_GFX_DOORBELL_OFFSET 0x1d64b |
|---|
| 4388 | #define regSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4389 | #define regSDMA4_GFX_CSA_ADDR_LO 0x1d64c |
|---|
| 4390 | #define regSDMA4_GFX_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4391 | #define regSDMA4_GFX_CSA_ADDR_HI 0x1d64d |
|---|
| 4392 | #define regSDMA4_GFX_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4393 | #define regSDMA4_GFX_IB_SUB_REMAIN 0x1d64f |
|---|
| 4394 | #define regSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4395 | #define regSDMA4_GFX_PREEMPT 0x1d650 |
|---|
| 4396 | #define regSDMA4_GFX_PREEMPT_BASE_IDX 0 |
|---|
| 4397 | #define regSDMA4_GFX_DUMMY_REG 0x1d651 |
|---|
| 4398 | #define regSDMA4_GFX_DUMMY_REG_BASE_IDX 0 |
|---|
| 4399 | #define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI 0x1d652 |
|---|
| 4400 | #define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4401 | #define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO 0x1d653 |
|---|
| 4402 | #define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4403 | #define regSDMA4_GFX_RB_AQL_CNTL 0x1d654 |
|---|
| 4404 | #define regSDMA4_GFX_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4405 | #define regSDMA4_GFX_MINOR_PTR_UPDATE 0x1d655 |
|---|
| 4406 | #define regSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4407 | #define regSDMA4_GFX_MIDCMD_DATA0 0x1d660 |
|---|
| 4408 | #define regSDMA4_GFX_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4409 | #define regSDMA4_GFX_MIDCMD_DATA1 0x1d661 |
|---|
| 4410 | #define regSDMA4_GFX_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4411 | #define regSDMA4_GFX_MIDCMD_DATA2 0x1d662 |
|---|
| 4412 | #define regSDMA4_GFX_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4413 | #define regSDMA4_GFX_MIDCMD_DATA3 0x1d663 |
|---|
| 4414 | #define regSDMA4_GFX_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4415 | #define regSDMA4_GFX_MIDCMD_DATA4 0x1d664 |
|---|
| 4416 | #define regSDMA4_GFX_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4417 | #define regSDMA4_GFX_MIDCMD_DATA5 0x1d665 |
|---|
| 4418 | #define regSDMA4_GFX_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4419 | #define regSDMA4_GFX_MIDCMD_DATA6 0x1d666 |
|---|
| 4420 | #define regSDMA4_GFX_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4421 | #define regSDMA4_GFX_MIDCMD_DATA7 0x1d667 |
|---|
| 4422 | #define regSDMA4_GFX_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4423 | #define regSDMA4_GFX_MIDCMD_DATA8 0x1d668 |
|---|
| 4424 | #define regSDMA4_GFX_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4425 | #define regSDMA4_GFX_MIDCMD_DATA9 0x1d669 |
|---|
| 4426 | #define regSDMA4_GFX_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4427 | #define regSDMA4_GFX_MIDCMD_DATA10 0x1d66a |
|---|
| 4428 | #define regSDMA4_GFX_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4429 | #define regSDMA4_GFX_MIDCMD_CNTL 0x1d66b |
|---|
| 4430 | #define regSDMA4_GFX_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4431 | #define regSDMA4_PAGE_RB_CNTL 0x1d678 |
|---|
| 4432 | #define regSDMA4_PAGE_RB_CNTL_BASE_IDX 0 |
|---|
| 4433 | #define regSDMA4_PAGE_RB_BASE 0x1d679 |
|---|
| 4434 | #define regSDMA4_PAGE_RB_BASE_BASE_IDX 0 |
|---|
| 4435 | #define regSDMA4_PAGE_RB_BASE_HI 0x1d67a |
|---|
| 4436 | #define regSDMA4_PAGE_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4437 | #define regSDMA4_PAGE_RB_RPTR 0x1d67b |
|---|
| 4438 | #define regSDMA4_PAGE_RB_RPTR_BASE_IDX 0 |
|---|
| 4439 | #define regSDMA4_PAGE_RB_RPTR_HI 0x1d67c |
|---|
| 4440 | #define regSDMA4_PAGE_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4441 | #define regSDMA4_PAGE_RB_WPTR 0x1d67d |
|---|
| 4442 | #define regSDMA4_PAGE_RB_WPTR_BASE_IDX 0 |
|---|
| 4443 | #define regSDMA4_PAGE_RB_WPTR_HI 0x1d67e |
|---|
| 4444 | #define regSDMA4_PAGE_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4445 | #define regSDMA4_PAGE_RB_WPTR_POLL_CNTL 0x1d67f |
|---|
| 4446 | #define regSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4447 | #define regSDMA4_PAGE_RB_RPTR_ADDR_HI 0x1d680 |
|---|
| 4448 | #define regSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4449 | #define regSDMA4_PAGE_RB_RPTR_ADDR_LO 0x1d681 |
|---|
| 4450 | #define regSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4451 | #define regSDMA4_PAGE_IB_CNTL 0x1d682 |
|---|
| 4452 | #define regSDMA4_PAGE_IB_CNTL_BASE_IDX 0 |
|---|
| 4453 | #define regSDMA4_PAGE_IB_RPTR 0x1d683 |
|---|
| 4454 | #define regSDMA4_PAGE_IB_RPTR_BASE_IDX 0 |
|---|
| 4455 | #define regSDMA4_PAGE_IB_OFFSET 0x1d684 |
|---|
| 4456 | #define regSDMA4_PAGE_IB_OFFSET_BASE_IDX 0 |
|---|
| 4457 | #define regSDMA4_PAGE_IB_BASE_LO 0x1d685 |
|---|
| 4458 | #define regSDMA4_PAGE_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4459 | #define regSDMA4_PAGE_IB_BASE_HI 0x1d686 |
|---|
| 4460 | #define regSDMA4_PAGE_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4461 | #define regSDMA4_PAGE_IB_SIZE 0x1d687 |
|---|
| 4462 | #define regSDMA4_PAGE_IB_SIZE_BASE_IDX 0 |
|---|
| 4463 | #define regSDMA4_PAGE_SKIP_CNTL 0x1d688 |
|---|
| 4464 | #define regSDMA4_PAGE_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4465 | #define regSDMA4_PAGE_CONTEXT_STATUS 0x1d689 |
|---|
| 4466 | #define regSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4467 | #define regSDMA4_PAGE_DOORBELL 0x1d68a |
|---|
| 4468 | #define regSDMA4_PAGE_DOORBELL_BASE_IDX 0 |
|---|
| 4469 | #define regSDMA4_PAGE_STATUS 0x1d6a0 |
|---|
| 4470 | #define regSDMA4_PAGE_STATUS_BASE_IDX 0 |
|---|
| 4471 | #define regSDMA4_PAGE_DOORBELL_LOG 0x1d6a1 |
|---|
| 4472 | #define regSDMA4_PAGE_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4473 | #define regSDMA4_PAGE_WATERMARK 0x1d6a2 |
|---|
| 4474 | #define regSDMA4_PAGE_WATERMARK_BASE_IDX 0 |
|---|
| 4475 | #define regSDMA4_PAGE_DOORBELL_OFFSET 0x1d6a3 |
|---|
| 4476 | #define regSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4477 | #define regSDMA4_PAGE_CSA_ADDR_LO 0x1d6a4 |
|---|
| 4478 | #define regSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4479 | #define regSDMA4_PAGE_CSA_ADDR_HI 0x1d6a5 |
|---|
| 4480 | #define regSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4481 | #define regSDMA4_PAGE_IB_SUB_REMAIN 0x1d6a7 |
|---|
| 4482 | #define regSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4483 | #define regSDMA4_PAGE_PREEMPT 0x1d6a8 |
|---|
| 4484 | #define regSDMA4_PAGE_PREEMPT_BASE_IDX 0 |
|---|
| 4485 | #define regSDMA4_PAGE_DUMMY_REG 0x1d6a9 |
|---|
| 4486 | #define regSDMA4_PAGE_DUMMY_REG_BASE_IDX 0 |
|---|
| 4487 | #define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 0x1d6aa |
|---|
| 4488 | #define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4489 | #define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 0x1d6ab |
|---|
| 4490 | #define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4491 | #define regSDMA4_PAGE_RB_AQL_CNTL 0x1d6ac |
|---|
| 4492 | #define regSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4493 | #define regSDMA4_PAGE_MINOR_PTR_UPDATE 0x1d6ad |
|---|
| 4494 | #define regSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4495 | #define regSDMA4_PAGE_MIDCMD_DATA0 0x1d6b8 |
|---|
| 4496 | #define regSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4497 | #define regSDMA4_PAGE_MIDCMD_DATA1 0x1d6b9 |
|---|
| 4498 | #define regSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4499 | #define regSDMA4_PAGE_MIDCMD_DATA2 0x1d6ba |
|---|
| 4500 | #define regSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4501 | #define regSDMA4_PAGE_MIDCMD_DATA3 0x1d6bb |
|---|
| 4502 | #define regSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4503 | #define regSDMA4_PAGE_MIDCMD_DATA4 0x1d6bc |
|---|
| 4504 | #define regSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4505 | #define regSDMA4_PAGE_MIDCMD_DATA5 0x1d6bd |
|---|
| 4506 | #define regSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4507 | #define regSDMA4_PAGE_MIDCMD_DATA6 0x1d6be |
|---|
| 4508 | #define regSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4509 | #define regSDMA4_PAGE_MIDCMD_DATA7 0x1d6bf |
|---|
| 4510 | #define regSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4511 | #define regSDMA4_PAGE_MIDCMD_DATA8 0x1d6c0 |
|---|
| 4512 | #define regSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4513 | #define regSDMA4_PAGE_MIDCMD_DATA9 0x1d6c1 |
|---|
| 4514 | #define regSDMA4_PAGE_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4515 | #define regSDMA4_PAGE_MIDCMD_DATA10 0x1d6c2 |
|---|
| 4516 | #define regSDMA4_PAGE_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4517 | #define regSDMA4_PAGE_MIDCMD_CNTL 0x1d6c3 |
|---|
| 4518 | #define regSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4519 | #define regSDMA4_RLC0_RB_CNTL 0x1d6d0 |
|---|
| 4520 | #define regSDMA4_RLC0_RB_CNTL_BASE_IDX 0 |
|---|
| 4521 | #define regSDMA4_RLC0_RB_BASE 0x1d6d1 |
|---|
| 4522 | #define regSDMA4_RLC0_RB_BASE_BASE_IDX 0 |
|---|
| 4523 | #define regSDMA4_RLC0_RB_BASE_HI 0x1d6d2 |
|---|
| 4524 | #define regSDMA4_RLC0_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4525 | #define regSDMA4_RLC0_RB_RPTR 0x1d6d3 |
|---|
| 4526 | #define regSDMA4_RLC0_RB_RPTR_BASE_IDX 0 |
|---|
| 4527 | #define regSDMA4_RLC0_RB_RPTR_HI 0x1d6d4 |
|---|
| 4528 | #define regSDMA4_RLC0_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4529 | #define regSDMA4_RLC0_RB_WPTR 0x1d6d5 |
|---|
| 4530 | #define regSDMA4_RLC0_RB_WPTR_BASE_IDX 0 |
|---|
| 4531 | #define regSDMA4_RLC0_RB_WPTR_HI 0x1d6d6 |
|---|
| 4532 | #define regSDMA4_RLC0_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4533 | #define regSDMA4_RLC0_RB_WPTR_POLL_CNTL 0x1d6d7 |
|---|
| 4534 | #define regSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4535 | #define regSDMA4_RLC0_RB_RPTR_ADDR_HI 0x1d6d8 |
|---|
| 4536 | #define regSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4537 | #define regSDMA4_RLC0_RB_RPTR_ADDR_LO 0x1d6d9 |
|---|
| 4538 | #define regSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4539 | #define regSDMA4_RLC0_IB_CNTL 0x1d6da |
|---|
| 4540 | #define regSDMA4_RLC0_IB_CNTL_BASE_IDX 0 |
|---|
| 4541 | #define regSDMA4_RLC0_IB_RPTR 0x1d6db |
|---|
| 4542 | #define regSDMA4_RLC0_IB_RPTR_BASE_IDX 0 |
|---|
| 4543 | #define regSDMA4_RLC0_IB_OFFSET 0x1d6dc |
|---|
| 4544 | #define regSDMA4_RLC0_IB_OFFSET_BASE_IDX 0 |
|---|
| 4545 | #define regSDMA4_RLC0_IB_BASE_LO 0x1d6dd |
|---|
| 4546 | #define regSDMA4_RLC0_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4547 | #define regSDMA4_RLC0_IB_BASE_HI 0x1d6de |
|---|
| 4548 | #define regSDMA4_RLC0_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4549 | #define regSDMA4_RLC0_IB_SIZE 0x1d6df |
|---|
| 4550 | #define regSDMA4_RLC0_IB_SIZE_BASE_IDX 0 |
|---|
| 4551 | #define regSDMA4_RLC0_SKIP_CNTL 0x1d6e0 |
|---|
| 4552 | #define regSDMA4_RLC0_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4553 | #define regSDMA4_RLC0_CONTEXT_STATUS 0x1d6e1 |
|---|
| 4554 | #define regSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4555 | #define regSDMA4_RLC0_DOORBELL 0x1d6e2 |
|---|
| 4556 | #define regSDMA4_RLC0_DOORBELL_BASE_IDX 0 |
|---|
| 4557 | #define regSDMA4_RLC0_STATUS 0x1d6f8 |
|---|
| 4558 | #define regSDMA4_RLC0_STATUS_BASE_IDX 0 |
|---|
| 4559 | #define regSDMA4_RLC0_DOORBELL_LOG 0x1d6f9 |
|---|
| 4560 | #define regSDMA4_RLC0_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4561 | #define regSDMA4_RLC0_WATERMARK 0x1d6fa |
|---|
| 4562 | #define regSDMA4_RLC0_WATERMARK_BASE_IDX 0 |
|---|
| 4563 | #define regSDMA4_RLC0_DOORBELL_OFFSET 0x1d6fb |
|---|
| 4564 | #define regSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4565 | #define regSDMA4_RLC0_CSA_ADDR_LO 0x1d6fc |
|---|
| 4566 | #define regSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4567 | #define regSDMA4_RLC0_CSA_ADDR_HI 0x1d6fd |
|---|
| 4568 | #define regSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4569 | #define regSDMA4_RLC0_IB_SUB_REMAIN 0x1d6ff |
|---|
| 4570 | #define regSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4571 | #define regSDMA4_RLC0_PREEMPT 0x1d700 |
|---|
| 4572 | #define regSDMA4_RLC0_PREEMPT_BASE_IDX 0 |
|---|
| 4573 | #define regSDMA4_RLC0_DUMMY_REG 0x1d701 |
|---|
| 4574 | #define regSDMA4_RLC0_DUMMY_REG_BASE_IDX 0 |
|---|
| 4575 | #define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 0x1d702 |
|---|
| 4576 | #define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4577 | #define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 0x1d703 |
|---|
| 4578 | #define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4579 | #define regSDMA4_RLC0_RB_AQL_CNTL 0x1d704 |
|---|
| 4580 | #define regSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4581 | #define regSDMA4_RLC0_MINOR_PTR_UPDATE 0x1d705 |
|---|
| 4582 | #define regSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4583 | #define regSDMA4_RLC0_MIDCMD_DATA0 0x1d710 |
|---|
| 4584 | #define regSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4585 | #define regSDMA4_RLC0_MIDCMD_DATA1 0x1d711 |
|---|
| 4586 | #define regSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4587 | #define regSDMA4_RLC0_MIDCMD_DATA2 0x1d712 |
|---|
| 4588 | #define regSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4589 | #define regSDMA4_RLC0_MIDCMD_DATA3 0x1d713 |
|---|
| 4590 | #define regSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4591 | #define regSDMA4_RLC0_MIDCMD_DATA4 0x1d714 |
|---|
| 4592 | #define regSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4593 | #define regSDMA4_RLC0_MIDCMD_DATA5 0x1d715 |
|---|
| 4594 | #define regSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4595 | #define regSDMA4_RLC0_MIDCMD_DATA6 0x1d716 |
|---|
| 4596 | #define regSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4597 | #define regSDMA4_RLC0_MIDCMD_DATA7 0x1d717 |
|---|
| 4598 | #define regSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4599 | #define regSDMA4_RLC0_MIDCMD_DATA8 0x1d718 |
|---|
| 4600 | #define regSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4601 | #define regSDMA4_RLC0_MIDCMD_DATA9 0x1d719 |
|---|
| 4602 | #define regSDMA4_RLC0_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4603 | #define regSDMA4_RLC0_MIDCMD_DATA10 0x1d71a |
|---|
| 4604 | #define regSDMA4_RLC0_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4605 | #define regSDMA4_RLC0_MIDCMD_CNTL 0x1d71b |
|---|
| 4606 | #define regSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4607 | #define regSDMA4_RLC1_RB_CNTL 0x1d728 |
|---|
| 4608 | #define regSDMA4_RLC1_RB_CNTL_BASE_IDX 0 |
|---|
| 4609 | #define regSDMA4_RLC1_RB_BASE 0x1d729 |
|---|
| 4610 | #define regSDMA4_RLC1_RB_BASE_BASE_IDX 0 |
|---|
| 4611 | #define regSDMA4_RLC1_RB_BASE_HI 0x1d72a |
|---|
| 4612 | #define regSDMA4_RLC1_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4613 | #define regSDMA4_RLC1_RB_RPTR 0x1d72b |
|---|
| 4614 | #define regSDMA4_RLC1_RB_RPTR_BASE_IDX 0 |
|---|
| 4615 | #define regSDMA4_RLC1_RB_RPTR_HI 0x1d72c |
|---|
| 4616 | #define regSDMA4_RLC1_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4617 | #define regSDMA4_RLC1_RB_WPTR 0x1d72d |
|---|
| 4618 | #define regSDMA4_RLC1_RB_WPTR_BASE_IDX 0 |
|---|
| 4619 | #define regSDMA4_RLC1_RB_WPTR_HI 0x1d72e |
|---|
| 4620 | #define regSDMA4_RLC1_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4621 | #define regSDMA4_RLC1_RB_WPTR_POLL_CNTL 0x1d72f |
|---|
| 4622 | #define regSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4623 | #define regSDMA4_RLC1_RB_RPTR_ADDR_HI 0x1d730 |
|---|
| 4624 | #define regSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4625 | #define regSDMA4_RLC1_RB_RPTR_ADDR_LO 0x1d731 |
|---|
| 4626 | #define regSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4627 | #define regSDMA4_RLC1_IB_CNTL 0x1d732 |
|---|
| 4628 | #define regSDMA4_RLC1_IB_CNTL_BASE_IDX 0 |
|---|
| 4629 | #define regSDMA4_RLC1_IB_RPTR 0x1d733 |
|---|
| 4630 | #define regSDMA4_RLC1_IB_RPTR_BASE_IDX 0 |
|---|
| 4631 | #define regSDMA4_RLC1_IB_OFFSET 0x1d734 |
|---|
| 4632 | #define regSDMA4_RLC1_IB_OFFSET_BASE_IDX 0 |
|---|
| 4633 | #define regSDMA4_RLC1_IB_BASE_LO 0x1d735 |
|---|
| 4634 | #define regSDMA4_RLC1_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4635 | #define regSDMA4_RLC1_IB_BASE_HI 0x1d736 |
|---|
| 4636 | #define regSDMA4_RLC1_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4637 | #define regSDMA4_RLC1_IB_SIZE 0x1d737 |
|---|
| 4638 | #define regSDMA4_RLC1_IB_SIZE_BASE_IDX 0 |
|---|
| 4639 | #define regSDMA4_RLC1_SKIP_CNTL 0x1d738 |
|---|
| 4640 | #define regSDMA4_RLC1_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4641 | #define regSDMA4_RLC1_CONTEXT_STATUS 0x1d739 |
|---|
| 4642 | #define regSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4643 | #define regSDMA4_RLC1_DOORBELL 0x1d73a |
|---|
| 4644 | #define regSDMA4_RLC1_DOORBELL_BASE_IDX 0 |
|---|
| 4645 | #define regSDMA4_RLC1_STATUS 0x1d750 |
|---|
| 4646 | #define regSDMA4_RLC1_STATUS_BASE_IDX 0 |
|---|
| 4647 | #define regSDMA4_RLC1_DOORBELL_LOG 0x1d751 |
|---|
| 4648 | #define regSDMA4_RLC1_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4649 | #define regSDMA4_RLC1_WATERMARK 0x1d752 |
|---|
| 4650 | #define regSDMA4_RLC1_WATERMARK_BASE_IDX 0 |
|---|
| 4651 | #define regSDMA4_RLC1_DOORBELL_OFFSET 0x1d753 |
|---|
| 4652 | #define regSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4653 | #define regSDMA4_RLC1_CSA_ADDR_LO 0x1d754 |
|---|
| 4654 | #define regSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4655 | #define regSDMA4_RLC1_CSA_ADDR_HI 0x1d755 |
|---|
| 4656 | #define regSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4657 | #define regSDMA4_RLC1_IB_SUB_REMAIN 0x1d757 |
|---|
| 4658 | #define regSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4659 | #define regSDMA4_RLC1_PREEMPT 0x1d758 |
|---|
| 4660 | #define regSDMA4_RLC1_PREEMPT_BASE_IDX 0 |
|---|
| 4661 | #define regSDMA4_RLC1_DUMMY_REG 0x1d759 |
|---|
| 4662 | #define regSDMA4_RLC1_DUMMY_REG_BASE_IDX 0 |
|---|
| 4663 | #define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 0x1d75a |
|---|
| 4664 | #define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4665 | #define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 0x1d75b |
|---|
| 4666 | #define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4667 | #define regSDMA4_RLC1_RB_AQL_CNTL 0x1d75c |
|---|
| 4668 | #define regSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4669 | #define regSDMA4_RLC1_MINOR_PTR_UPDATE 0x1d75d |
|---|
| 4670 | #define regSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4671 | #define regSDMA4_RLC1_MIDCMD_DATA0 0x1d768 |
|---|
| 4672 | #define regSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4673 | #define regSDMA4_RLC1_MIDCMD_DATA1 0x1d769 |
|---|
| 4674 | #define regSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4675 | #define regSDMA4_RLC1_MIDCMD_DATA2 0x1d76a |
|---|
| 4676 | #define regSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4677 | #define regSDMA4_RLC1_MIDCMD_DATA3 0x1d76b |
|---|
| 4678 | #define regSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4679 | #define regSDMA4_RLC1_MIDCMD_DATA4 0x1d76c |
|---|
| 4680 | #define regSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4681 | #define regSDMA4_RLC1_MIDCMD_DATA5 0x1d76d |
|---|
| 4682 | #define regSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4683 | #define regSDMA4_RLC1_MIDCMD_DATA6 0x1d76e |
|---|
| 4684 | #define regSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4685 | #define regSDMA4_RLC1_MIDCMD_DATA7 0x1d76f |
|---|
| 4686 | #define regSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4687 | #define regSDMA4_RLC1_MIDCMD_DATA8 0x1d770 |
|---|
| 4688 | #define regSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4689 | #define regSDMA4_RLC1_MIDCMD_DATA9 0x1d771 |
|---|
| 4690 | #define regSDMA4_RLC1_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4691 | #define regSDMA4_RLC1_MIDCMD_DATA10 0x1d772 |
|---|
| 4692 | #define regSDMA4_RLC1_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4693 | #define regSDMA4_RLC1_MIDCMD_CNTL 0x1d773 |
|---|
| 4694 | #define regSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4695 | #define regSDMA4_RLC2_RB_CNTL 0x1d780 |
|---|
| 4696 | #define regSDMA4_RLC2_RB_CNTL_BASE_IDX 0 |
|---|
| 4697 | #define regSDMA4_RLC2_RB_BASE 0x1d781 |
|---|
| 4698 | #define regSDMA4_RLC2_RB_BASE_BASE_IDX 0 |
|---|
| 4699 | #define regSDMA4_RLC2_RB_BASE_HI 0x1d782 |
|---|
| 4700 | #define regSDMA4_RLC2_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4701 | #define regSDMA4_RLC2_RB_RPTR 0x1d783 |
|---|
| 4702 | #define regSDMA4_RLC2_RB_RPTR_BASE_IDX 0 |
|---|
| 4703 | #define regSDMA4_RLC2_RB_RPTR_HI 0x1d784 |
|---|
| 4704 | #define regSDMA4_RLC2_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4705 | #define regSDMA4_RLC2_RB_WPTR 0x1d785 |
|---|
| 4706 | #define regSDMA4_RLC2_RB_WPTR_BASE_IDX 0 |
|---|
| 4707 | #define regSDMA4_RLC2_RB_WPTR_HI 0x1d786 |
|---|
| 4708 | #define regSDMA4_RLC2_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4709 | #define regSDMA4_RLC2_RB_WPTR_POLL_CNTL 0x1d787 |
|---|
| 4710 | #define regSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4711 | #define regSDMA4_RLC2_RB_RPTR_ADDR_HI 0x1d788 |
|---|
| 4712 | #define regSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4713 | #define regSDMA4_RLC2_RB_RPTR_ADDR_LO 0x1d789 |
|---|
| 4714 | #define regSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4715 | #define regSDMA4_RLC2_IB_CNTL 0x1d78a |
|---|
| 4716 | #define regSDMA4_RLC2_IB_CNTL_BASE_IDX 0 |
|---|
| 4717 | #define regSDMA4_RLC2_IB_RPTR 0x1d78b |
|---|
| 4718 | #define regSDMA4_RLC2_IB_RPTR_BASE_IDX 0 |
|---|
| 4719 | #define regSDMA4_RLC2_IB_OFFSET 0x1d78c |
|---|
| 4720 | #define regSDMA4_RLC2_IB_OFFSET_BASE_IDX 0 |
|---|
| 4721 | #define regSDMA4_RLC2_IB_BASE_LO 0x1d78d |
|---|
| 4722 | #define regSDMA4_RLC2_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4723 | #define regSDMA4_RLC2_IB_BASE_HI 0x1d78e |
|---|
| 4724 | #define regSDMA4_RLC2_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4725 | #define regSDMA4_RLC2_IB_SIZE 0x1d78f |
|---|
| 4726 | #define regSDMA4_RLC2_IB_SIZE_BASE_IDX 0 |
|---|
| 4727 | #define regSDMA4_RLC2_SKIP_CNTL 0x1d790 |
|---|
| 4728 | #define regSDMA4_RLC2_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4729 | #define regSDMA4_RLC2_CONTEXT_STATUS 0x1d791 |
|---|
| 4730 | #define regSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4731 | #define regSDMA4_RLC2_DOORBELL 0x1d792 |
|---|
| 4732 | #define regSDMA4_RLC2_DOORBELL_BASE_IDX 0 |
|---|
| 4733 | #define regSDMA4_RLC2_STATUS 0x1d7a8 |
|---|
| 4734 | #define regSDMA4_RLC2_STATUS_BASE_IDX 0 |
|---|
| 4735 | #define regSDMA4_RLC2_DOORBELL_LOG 0x1d7a9 |
|---|
| 4736 | #define regSDMA4_RLC2_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4737 | #define regSDMA4_RLC2_WATERMARK 0x1d7aa |
|---|
| 4738 | #define regSDMA4_RLC2_WATERMARK_BASE_IDX 0 |
|---|
| 4739 | #define regSDMA4_RLC2_DOORBELL_OFFSET 0x1d7ab |
|---|
| 4740 | #define regSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4741 | #define regSDMA4_RLC2_CSA_ADDR_LO 0x1d7ac |
|---|
| 4742 | #define regSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4743 | #define regSDMA4_RLC2_CSA_ADDR_HI 0x1d7ad |
|---|
| 4744 | #define regSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4745 | #define regSDMA4_RLC2_IB_SUB_REMAIN 0x1d7af |
|---|
| 4746 | #define regSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4747 | #define regSDMA4_RLC2_PREEMPT 0x1d7b0 |
|---|
| 4748 | #define regSDMA4_RLC2_PREEMPT_BASE_IDX 0 |
|---|
| 4749 | #define regSDMA4_RLC2_DUMMY_REG 0x1d7b1 |
|---|
| 4750 | #define regSDMA4_RLC2_DUMMY_REG_BASE_IDX 0 |
|---|
| 4751 | #define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 0x1d7b2 |
|---|
| 4752 | #define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4753 | #define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 0x1d7b3 |
|---|
| 4754 | #define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4755 | #define regSDMA4_RLC2_RB_AQL_CNTL 0x1d7b4 |
|---|
| 4756 | #define regSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4757 | #define regSDMA4_RLC2_MINOR_PTR_UPDATE 0x1d7b5 |
|---|
| 4758 | #define regSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4759 | #define regSDMA4_RLC2_MIDCMD_DATA0 0x1d7c0 |
|---|
| 4760 | #define regSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4761 | #define regSDMA4_RLC2_MIDCMD_DATA1 0x1d7c1 |
|---|
| 4762 | #define regSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4763 | #define regSDMA4_RLC2_MIDCMD_DATA2 0x1d7c2 |
|---|
| 4764 | #define regSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4765 | #define regSDMA4_RLC2_MIDCMD_DATA3 0x1d7c3 |
|---|
| 4766 | #define regSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4767 | #define regSDMA4_RLC2_MIDCMD_DATA4 0x1d7c4 |
|---|
| 4768 | #define regSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4769 | #define regSDMA4_RLC2_MIDCMD_DATA5 0x1d7c5 |
|---|
| 4770 | #define regSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4771 | #define regSDMA4_RLC2_MIDCMD_DATA6 0x1d7c6 |
|---|
| 4772 | #define regSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4773 | #define regSDMA4_RLC2_MIDCMD_DATA7 0x1d7c7 |
|---|
| 4774 | #define regSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4775 | #define regSDMA4_RLC2_MIDCMD_DATA8 0x1d7c8 |
|---|
| 4776 | #define regSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4777 | #define regSDMA4_RLC2_MIDCMD_DATA9 0x1d7c9 |
|---|
| 4778 | #define regSDMA4_RLC2_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4779 | #define regSDMA4_RLC2_MIDCMD_DATA10 0x1d7ca |
|---|
| 4780 | #define regSDMA4_RLC2_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4781 | #define regSDMA4_RLC2_MIDCMD_CNTL 0x1d7cb |
|---|
| 4782 | #define regSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4783 | #define regSDMA4_RLC3_RB_CNTL 0x1d7d8 |
|---|
| 4784 | #define regSDMA4_RLC3_RB_CNTL_BASE_IDX 0 |
|---|
| 4785 | #define regSDMA4_RLC3_RB_BASE 0x1d7d9 |
|---|
| 4786 | #define regSDMA4_RLC3_RB_BASE_BASE_IDX 0 |
|---|
| 4787 | #define regSDMA4_RLC3_RB_BASE_HI 0x1d7da |
|---|
| 4788 | #define regSDMA4_RLC3_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4789 | #define regSDMA4_RLC3_RB_RPTR 0x1d7db |
|---|
| 4790 | #define regSDMA4_RLC3_RB_RPTR_BASE_IDX 0 |
|---|
| 4791 | #define regSDMA4_RLC3_RB_RPTR_HI 0x1d7dc |
|---|
| 4792 | #define regSDMA4_RLC3_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4793 | #define regSDMA4_RLC3_RB_WPTR 0x1d7dd |
|---|
| 4794 | #define regSDMA4_RLC3_RB_WPTR_BASE_IDX 0 |
|---|
| 4795 | #define regSDMA4_RLC3_RB_WPTR_HI 0x1d7de |
|---|
| 4796 | #define regSDMA4_RLC3_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4797 | #define regSDMA4_RLC3_RB_WPTR_POLL_CNTL 0x1d7df |
|---|
| 4798 | #define regSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4799 | #define regSDMA4_RLC3_RB_RPTR_ADDR_HI 0x1d7e0 |
|---|
| 4800 | #define regSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4801 | #define regSDMA4_RLC3_RB_RPTR_ADDR_LO 0x1d7e1 |
|---|
| 4802 | #define regSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4803 | #define regSDMA4_RLC3_IB_CNTL 0x1d7e2 |
|---|
| 4804 | #define regSDMA4_RLC3_IB_CNTL_BASE_IDX 0 |
|---|
| 4805 | #define regSDMA4_RLC3_IB_RPTR 0x1d7e3 |
|---|
| 4806 | #define regSDMA4_RLC3_IB_RPTR_BASE_IDX 0 |
|---|
| 4807 | #define regSDMA4_RLC3_IB_OFFSET 0x1d7e4 |
|---|
| 4808 | #define regSDMA4_RLC3_IB_OFFSET_BASE_IDX 0 |
|---|
| 4809 | #define regSDMA4_RLC3_IB_BASE_LO 0x1d7e5 |
|---|
| 4810 | #define regSDMA4_RLC3_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4811 | #define regSDMA4_RLC3_IB_BASE_HI 0x1d7e6 |
|---|
| 4812 | #define regSDMA4_RLC3_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4813 | #define regSDMA4_RLC3_IB_SIZE 0x1d7e7 |
|---|
| 4814 | #define regSDMA4_RLC3_IB_SIZE_BASE_IDX 0 |
|---|
| 4815 | #define regSDMA4_RLC3_SKIP_CNTL 0x1d7e8 |
|---|
| 4816 | #define regSDMA4_RLC3_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4817 | #define regSDMA4_RLC3_CONTEXT_STATUS 0x1d7e9 |
|---|
| 4818 | #define regSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4819 | #define regSDMA4_RLC3_DOORBELL 0x1d7ea |
|---|
| 4820 | #define regSDMA4_RLC3_DOORBELL_BASE_IDX 0 |
|---|
| 4821 | #define regSDMA4_RLC3_STATUS 0x1d800 |
|---|
| 4822 | #define regSDMA4_RLC3_STATUS_BASE_IDX 0 |
|---|
| 4823 | #define regSDMA4_RLC3_DOORBELL_LOG 0x1d801 |
|---|
| 4824 | #define regSDMA4_RLC3_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4825 | #define regSDMA4_RLC3_WATERMARK 0x1d802 |
|---|
| 4826 | #define regSDMA4_RLC3_WATERMARK_BASE_IDX 0 |
|---|
| 4827 | #define regSDMA4_RLC3_DOORBELL_OFFSET 0x1d803 |
|---|
| 4828 | #define regSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4829 | #define regSDMA4_RLC3_CSA_ADDR_LO 0x1d804 |
|---|
| 4830 | #define regSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4831 | #define regSDMA4_RLC3_CSA_ADDR_HI 0x1d805 |
|---|
| 4832 | #define regSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4833 | #define regSDMA4_RLC3_IB_SUB_REMAIN 0x1d807 |
|---|
| 4834 | #define regSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4835 | #define regSDMA4_RLC3_PREEMPT 0x1d808 |
|---|
| 4836 | #define regSDMA4_RLC3_PREEMPT_BASE_IDX 0 |
|---|
| 4837 | #define regSDMA4_RLC3_DUMMY_REG 0x1d809 |
|---|
| 4838 | #define regSDMA4_RLC3_DUMMY_REG_BASE_IDX 0 |
|---|
| 4839 | #define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d80a |
|---|
| 4840 | #define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4841 | #define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d80b |
|---|
| 4842 | #define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4843 | #define regSDMA4_RLC3_RB_AQL_CNTL 0x1d80c |
|---|
| 4844 | #define regSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4845 | #define regSDMA4_RLC3_MINOR_PTR_UPDATE 0x1d80d |
|---|
| 4846 | #define regSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4847 | #define regSDMA4_RLC3_MIDCMD_DATA0 0x1d818 |
|---|
| 4848 | #define regSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4849 | #define regSDMA4_RLC3_MIDCMD_DATA1 0x1d819 |
|---|
| 4850 | #define regSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4851 | #define regSDMA4_RLC3_MIDCMD_DATA2 0x1d81a |
|---|
| 4852 | #define regSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4853 | #define regSDMA4_RLC3_MIDCMD_DATA3 0x1d81b |
|---|
| 4854 | #define regSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4855 | #define regSDMA4_RLC3_MIDCMD_DATA4 0x1d81c |
|---|
| 4856 | #define regSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4857 | #define regSDMA4_RLC3_MIDCMD_DATA5 0x1d81d |
|---|
| 4858 | #define regSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4859 | #define regSDMA4_RLC3_MIDCMD_DATA6 0x1d81e |
|---|
| 4860 | #define regSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4861 | #define regSDMA4_RLC3_MIDCMD_DATA7 0x1d81f |
|---|
| 4862 | #define regSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4863 | #define regSDMA4_RLC3_MIDCMD_DATA8 0x1d820 |
|---|
| 4864 | #define regSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4865 | #define regSDMA4_RLC3_MIDCMD_DATA9 0x1d821 |
|---|
| 4866 | #define regSDMA4_RLC3_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4867 | #define regSDMA4_RLC3_MIDCMD_DATA10 0x1d822 |
|---|
| 4868 | #define regSDMA4_RLC3_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4869 | #define regSDMA4_RLC3_MIDCMD_CNTL 0x1d823 |
|---|
| 4870 | #define regSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4871 | #define regSDMA4_RLC4_RB_CNTL 0x1d830 |
|---|
| 4872 | #define regSDMA4_RLC4_RB_CNTL_BASE_IDX 0 |
|---|
| 4873 | #define regSDMA4_RLC4_RB_BASE 0x1d831 |
|---|
| 4874 | #define regSDMA4_RLC4_RB_BASE_BASE_IDX 0 |
|---|
| 4875 | #define regSDMA4_RLC4_RB_BASE_HI 0x1d832 |
|---|
| 4876 | #define regSDMA4_RLC4_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4877 | #define regSDMA4_RLC4_RB_RPTR 0x1d833 |
|---|
| 4878 | #define regSDMA4_RLC4_RB_RPTR_BASE_IDX 0 |
|---|
| 4879 | #define regSDMA4_RLC4_RB_RPTR_HI 0x1d834 |
|---|
| 4880 | #define regSDMA4_RLC4_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4881 | #define regSDMA4_RLC4_RB_WPTR 0x1d835 |
|---|
| 4882 | #define regSDMA4_RLC4_RB_WPTR_BASE_IDX 0 |
|---|
| 4883 | #define regSDMA4_RLC4_RB_WPTR_HI 0x1d836 |
|---|
| 4884 | #define regSDMA4_RLC4_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4885 | #define regSDMA4_RLC4_RB_WPTR_POLL_CNTL 0x1d837 |
|---|
| 4886 | #define regSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4887 | #define regSDMA4_RLC4_RB_RPTR_ADDR_HI 0x1d838 |
|---|
| 4888 | #define regSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4889 | #define regSDMA4_RLC4_RB_RPTR_ADDR_LO 0x1d839 |
|---|
| 4890 | #define regSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4891 | #define regSDMA4_RLC4_IB_CNTL 0x1d83a |
|---|
| 4892 | #define regSDMA4_RLC4_IB_CNTL_BASE_IDX 0 |
|---|
| 4893 | #define regSDMA4_RLC4_IB_RPTR 0x1d83b |
|---|
| 4894 | #define regSDMA4_RLC4_IB_RPTR_BASE_IDX 0 |
|---|
| 4895 | #define regSDMA4_RLC4_IB_OFFSET 0x1d83c |
|---|
| 4896 | #define regSDMA4_RLC4_IB_OFFSET_BASE_IDX 0 |
|---|
| 4897 | #define regSDMA4_RLC4_IB_BASE_LO 0x1d83d |
|---|
| 4898 | #define regSDMA4_RLC4_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4899 | #define regSDMA4_RLC4_IB_BASE_HI 0x1d83e |
|---|
| 4900 | #define regSDMA4_RLC4_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4901 | #define regSDMA4_RLC4_IB_SIZE 0x1d83f |
|---|
| 4902 | #define regSDMA4_RLC4_IB_SIZE_BASE_IDX 0 |
|---|
| 4903 | #define regSDMA4_RLC4_SKIP_CNTL 0x1d840 |
|---|
| 4904 | #define regSDMA4_RLC4_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4905 | #define regSDMA4_RLC4_CONTEXT_STATUS 0x1d841 |
|---|
| 4906 | #define regSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4907 | #define regSDMA4_RLC4_DOORBELL 0x1d842 |
|---|
| 4908 | #define regSDMA4_RLC4_DOORBELL_BASE_IDX 0 |
|---|
| 4909 | #define regSDMA4_RLC4_STATUS 0x1d858 |
|---|
| 4910 | #define regSDMA4_RLC4_STATUS_BASE_IDX 0 |
|---|
| 4911 | #define regSDMA4_RLC4_DOORBELL_LOG 0x1d859 |
|---|
| 4912 | #define regSDMA4_RLC4_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 4913 | #define regSDMA4_RLC4_WATERMARK 0x1d85a |
|---|
| 4914 | #define regSDMA4_RLC4_WATERMARK_BASE_IDX 0 |
|---|
| 4915 | #define regSDMA4_RLC4_DOORBELL_OFFSET 0x1d85b |
|---|
| 4916 | #define regSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 4917 | #define regSDMA4_RLC4_CSA_ADDR_LO 0x1d85c |
|---|
| 4918 | #define regSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 4919 | #define regSDMA4_RLC4_CSA_ADDR_HI 0x1d85d |
|---|
| 4920 | #define regSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 4921 | #define regSDMA4_RLC4_IB_SUB_REMAIN 0x1d85f |
|---|
| 4922 | #define regSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 4923 | #define regSDMA4_RLC4_PREEMPT 0x1d860 |
|---|
| 4924 | #define regSDMA4_RLC4_PREEMPT_BASE_IDX 0 |
|---|
| 4925 | #define regSDMA4_RLC4_DUMMY_REG 0x1d861 |
|---|
| 4926 | #define regSDMA4_RLC4_DUMMY_REG_BASE_IDX 0 |
|---|
| 4927 | #define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d862 |
|---|
| 4928 | #define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 4929 | #define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d863 |
|---|
| 4930 | #define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 4931 | #define regSDMA4_RLC4_RB_AQL_CNTL 0x1d864 |
|---|
| 4932 | #define regSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 4933 | #define regSDMA4_RLC4_MINOR_PTR_UPDATE 0x1d865 |
|---|
| 4934 | #define regSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 4935 | #define regSDMA4_RLC4_MIDCMD_DATA0 0x1d870 |
|---|
| 4936 | #define regSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 4937 | #define regSDMA4_RLC4_MIDCMD_DATA1 0x1d871 |
|---|
| 4938 | #define regSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 4939 | #define regSDMA4_RLC4_MIDCMD_DATA2 0x1d872 |
|---|
| 4940 | #define regSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 4941 | #define regSDMA4_RLC4_MIDCMD_DATA3 0x1d873 |
|---|
| 4942 | #define regSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 4943 | #define regSDMA4_RLC4_MIDCMD_DATA4 0x1d874 |
|---|
| 4944 | #define regSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 4945 | #define regSDMA4_RLC4_MIDCMD_DATA5 0x1d875 |
|---|
| 4946 | #define regSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 4947 | #define regSDMA4_RLC4_MIDCMD_DATA6 0x1d876 |
|---|
| 4948 | #define regSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 4949 | #define regSDMA4_RLC4_MIDCMD_DATA7 0x1d877 |
|---|
| 4950 | #define regSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 4951 | #define regSDMA4_RLC4_MIDCMD_DATA8 0x1d878 |
|---|
| 4952 | #define regSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 4953 | #define regSDMA4_RLC4_MIDCMD_DATA9 0x1d879 |
|---|
| 4954 | #define regSDMA4_RLC4_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 4955 | #define regSDMA4_RLC4_MIDCMD_DATA10 0x1d87a |
|---|
| 4956 | #define regSDMA4_RLC4_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 4957 | #define regSDMA4_RLC4_MIDCMD_CNTL 0x1d87b |
|---|
| 4958 | #define regSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 4959 | #define regSDMA4_RLC5_RB_CNTL 0x1d888 |
|---|
| 4960 | #define regSDMA4_RLC5_RB_CNTL_BASE_IDX 0 |
|---|
| 4961 | #define regSDMA4_RLC5_RB_BASE 0x1d889 |
|---|
| 4962 | #define regSDMA4_RLC5_RB_BASE_BASE_IDX 0 |
|---|
| 4963 | #define regSDMA4_RLC5_RB_BASE_HI 0x1d88a |
|---|
| 4964 | #define regSDMA4_RLC5_RB_BASE_HI_BASE_IDX 0 |
|---|
| 4965 | #define regSDMA4_RLC5_RB_RPTR 0x1d88b |
|---|
| 4966 | #define regSDMA4_RLC5_RB_RPTR_BASE_IDX 0 |
|---|
| 4967 | #define regSDMA4_RLC5_RB_RPTR_HI 0x1d88c |
|---|
| 4968 | #define regSDMA4_RLC5_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 4969 | #define regSDMA4_RLC5_RB_WPTR 0x1d88d |
|---|
| 4970 | #define regSDMA4_RLC5_RB_WPTR_BASE_IDX 0 |
|---|
| 4971 | #define regSDMA4_RLC5_RB_WPTR_HI 0x1d88e |
|---|
| 4972 | #define regSDMA4_RLC5_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 4973 | #define regSDMA4_RLC5_RB_WPTR_POLL_CNTL 0x1d88f |
|---|
| 4974 | #define regSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 4975 | #define regSDMA4_RLC5_RB_RPTR_ADDR_HI 0x1d890 |
|---|
| 4976 | #define regSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 4977 | #define regSDMA4_RLC5_RB_RPTR_ADDR_LO 0x1d891 |
|---|
| 4978 | #define regSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 4979 | #define regSDMA4_RLC5_IB_CNTL 0x1d892 |
|---|
| 4980 | #define regSDMA4_RLC5_IB_CNTL_BASE_IDX 0 |
|---|
| 4981 | #define regSDMA4_RLC5_IB_RPTR 0x1d893 |
|---|
| 4982 | #define regSDMA4_RLC5_IB_RPTR_BASE_IDX 0 |
|---|
| 4983 | #define regSDMA4_RLC5_IB_OFFSET 0x1d894 |
|---|
| 4984 | #define regSDMA4_RLC5_IB_OFFSET_BASE_IDX 0 |
|---|
| 4985 | #define regSDMA4_RLC5_IB_BASE_LO 0x1d895 |
|---|
| 4986 | #define regSDMA4_RLC5_IB_BASE_LO_BASE_IDX 0 |
|---|
| 4987 | #define regSDMA4_RLC5_IB_BASE_HI 0x1d896 |
|---|
| 4988 | #define regSDMA4_RLC5_IB_BASE_HI_BASE_IDX 0 |
|---|
| 4989 | #define regSDMA4_RLC5_IB_SIZE 0x1d897 |
|---|
| 4990 | #define regSDMA4_RLC5_IB_SIZE_BASE_IDX 0 |
|---|
| 4991 | #define regSDMA4_RLC5_SKIP_CNTL 0x1d898 |
|---|
| 4992 | #define regSDMA4_RLC5_SKIP_CNTL_BASE_IDX 0 |
|---|
| 4993 | #define regSDMA4_RLC5_CONTEXT_STATUS 0x1d899 |
|---|
| 4994 | #define regSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 4995 | #define regSDMA4_RLC5_DOORBELL 0x1d89a |
|---|
| 4996 | #define regSDMA4_RLC5_DOORBELL_BASE_IDX 0 |
|---|
| 4997 | #define regSDMA4_RLC5_STATUS 0x1d8b0 |
|---|
| 4998 | #define regSDMA4_RLC5_STATUS_BASE_IDX 0 |
|---|
| 4999 | #define regSDMA4_RLC5_DOORBELL_LOG 0x1d8b1 |
|---|
| 5000 | #define regSDMA4_RLC5_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 5001 | #define regSDMA4_RLC5_WATERMARK 0x1d8b2 |
|---|
| 5002 | #define regSDMA4_RLC5_WATERMARK_BASE_IDX 0 |
|---|
| 5003 | #define regSDMA4_RLC5_DOORBELL_OFFSET 0x1d8b3 |
|---|
| 5004 | #define regSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 5005 | #define regSDMA4_RLC5_CSA_ADDR_LO 0x1d8b4 |
|---|
| 5006 | #define regSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 5007 | #define regSDMA4_RLC5_CSA_ADDR_HI 0x1d8b5 |
|---|
| 5008 | #define regSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 5009 | #define regSDMA4_RLC5_IB_SUB_REMAIN 0x1d8b7 |
|---|
| 5010 | #define regSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 5011 | #define regSDMA4_RLC5_PREEMPT 0x1d8b8 |
|---|
| 5012 | #define regSDMA4_RLC5_PREEMPT_BASE_IDX 0 |
|---|
| 5013 | #define regSDMA4_RLC5_DUMMY_REG 0x1d8b9 |
|---|
| 5014 | #define regSDMA4_RLC5_DUMMY_REG_BASE_IDX 0 |
|---|
| 5015 | #define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d8ba |
|---|
| 5016 | #define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 5017 | #define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d8bb |
|---|
| 5018 | #define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 5019 | #define regSDMA4_RLC5_RB_AQL_CNTL 0x1d8bc |
|---|
| 5020 | #define regSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 5021 | #define regSDMA4_RLC5_MINOR_PTR_UPDATE 0x1d8bd |
|---|
| 5022 | #define regSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 5023 | #define regSDMA4_RLC5_MIDCMD_DATA0 0x1d8c8 |
|---|
| 5024 | #define regSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 5025 | #define regSDMA4_RLC5_MIDCMD_DATA1 0x1d8c9 |
|---|
| 5026 | #define regSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 5027 | #define regSDMA4_RLC5_MIDCMD_DATA2 0x1d8ca |
|---|
| 5028 | #define regSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 5029 | #define regSDMA4_RLC5_MIDCMD_DATA3 0x1d8cb |
|---|
| 5030 | #define regSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 5031 | #define regSDMA4_RLC5_MIDCMD_DATA4 0x1d8cc |
|---|
| 5032 | #define regSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 5033 | #define regSDMA4_RLC5_MIDCMD_DATA5 0x1d8cd |
|---|
| 5034 | #define regSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 5035 | #define regSDMA4_RLC5_MIDCMD_DATA6 0x1d8ce |
|---|
| 5036 | #define regSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 5037 | #define regSDMA4_RLC5_MIDCMD_DATA7 0x1d8cf |
|---|
| 5038 | #define regSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 5039 | #define regSDMA4_RLC5_MIDCMD_DATA8 0x1d8d0 |
|---|
| 5040 | #define regSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 5041 | #define regSDMA4_RLC5_MIDCMD_DATA9 0x1d8d1 |
|---|
| 5042 | #define regSDMA4_RLC5_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 5043 | #define regSDMA4_RLC5_MIDCMD_DATA10 0x1d8d2 |
|---|
| 5044 | #define regSDMA4_RLC5_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 5045 | #define regSDMA4_RLC5_MIDCMD_CNTL 0x1d8d3 |
|---|
| 5046 | #define regSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 5047 | #define regSDMA4_RLC6_RB_CNTL 0x1d8e0 |
|---|
| 5048 | #define regSDMA4_RLC6_RB_CNTL_BASE_IDX 0 |
|---|
| 5049 | #define regSDMA4_RLC6_RB_BASE 0x1d8e1 |
|---|
| 5050 | #define regSDMA4_RLC6_RB_BASE_BASE_IDX 0 |
|---|
| 5051 | #define regSDMA4_RLC6_RB_BASE_HI 0x1d8e2 |
|---|
| 5052 | #define regSDMA4_RLC6_RB_BASE_HI_BASE_IDX 0 |
|---|
| 5053 | #define regSDMA4_RLC6_RB_RPTR 0x1d8e3 |
|---|
| 5054 | #define regSDMA4_RLC6_RB_RPTR_BASE_IDX 0 |
|---|
| 5055 | #define regSDMA4_RLC6_RB_RPTR_HI 0x1d8e4 |
|---|
| 5056 | #define regSDMA4_RLC6_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 5057 | #define regSDMA4_RLC6_RB_WPTR 0x1d8e5 |
|---|
| 5058 | #define regSDMA4_RLC6_RB_WPTR_BASE_IDX 0 |
|---|
| 5059 | #define regSDMA4_RLC6_RB_WPTR_HI 0x1d8e6 |
|---|
| 5060 | #define regSDMA4_RLC6_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 5061 | #define regSDMA4_RLC6_RB_WPTR_POLL_CNTL 0x1d8e7 |
|---|
| 5062 | #define regSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 5063 | #define regSDMA4_RLC6_RB_RPTR_ADDR_HI 0x1d8e8 |
|---|
| 5064 | #define regSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 5065 | #define regSDMA4_RLC6_RB_RPTR_ADDR_LO 0x1d8e9 |
|---|
| 5066 | #define regSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 5067 | #define regSDMA4_RLC6_IB_CNTL 0x1d8ea |
|---|
| 5068 | #define regSDMA4_RLC6_IB_CNTL_BASE_IDX 0 |
|---|
| 5069 | #define regSDMA4_RLC6_IB_RPTR 0x1d8eb |
|---|
| 5070 | #define regSDMA4_RLC6_IB_RPTR_BASE_IDX 0 |
|---|
| 5071 | #define regSDMA4_RLC6_IB_OFFSET 0x1d8ec |
|---|
| 5072 | #define regSDMA4_RLC6_IB_OFFSET_BASE_IDX 0 |
|---|
| 5073 | #define regSDMA4_RLC6_IB_BASE_LO 0x1d8ed |
|---|
| 5074 | #define regSDMA4_RLC6_IB_BASE_LO_BASE_IDX 0 |
|---|
| 5075 | #define regSDMA4_RLC6_IB_BASE_HI 0x1d8ee |
|---|
| 5076 | #define regSDMA4_RLC6_IB_BASE_HI_BASE_IDX 0 |
|---|
| 5077 | #define regSDMA4_RLC6_IB_SIZE 0x1d8ef |
|---|
| 5078 | #define regSDMA4_RLC6_IB_SIZE_BASE_IDX 0 |
|---|
| 5079 | #define regSDMA4_RLC6_SKIP_CNTL 0x1d8f0 |
|---|
| 5080 | #define regSDMA4_RLC6_SKIP_CNTL_BASE_IDX 0 |
|---|
| 5081 | #define regSDMA4_RLC6_CONTEXT_STATUS 0x1d8f1 |
|---|
| 5082 | #define regSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 5083 | #define regSDMA4_RLC6_DOORBELL 0x1d8f2 |
|---|
| 5084 | #define regSDMA4_RLC6_DOORBELL_BASE_IDX 0 |
|---|
| 5085 | #define regSDMA4_RLC6_STATUS 0x1d908 |
|---|
| 5086 | #define regSDMA4_RLC6_STATUS_BASE_IDX 0 |
|---|
| 5087 | #define regSDMA4_RLC6_DOORBELL_LOG 0x1d909 |
|---|
| 5088 | #define regSDMA4_RLC6_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 5089 | #define regSDMA4_RLC6_WATERMARK 0x1d90a |
|---|
| 5090 | #define regSDMA4_RLC6_WATERMARK_BASE_IDX 0 |
|---|
| 5091 | #define regSDMA4_RLC6_DOORBELL_OFFSET 0x1d90b |
|---|
| 5092 | #define regSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 5093 | #define regSDMA4_RLC6_CSA_ADDR_LO 0x1d90c |
|---|
| 5094 | #define regSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 5095 | #define regSDMA4_RLC6_CSA_ADDR_HI 0x1d90d |
|---|
| 5096 | #define regSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 5097 | #define regSDMA4_RLC6_IB_SUB_REMAIN 0x1d90f |
|---|
| 5098 | #define regSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 5099 | #define regSDMA4_RLC6_PREEMPT 0x1d910 |
|---|
| 5100 | #define regSDMA4_RLC6_PREEMPT_BASE_IDX 0 |
|---|
| 5101 | #define regSDMA4_RLC6_DUMMY_REG 0x1d911 |
|---|
| 5102 | #define regSDMA4_RLC6_DUMMY_REG_BASE_IDX 0 |
|---|
| 5103 | #define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d912 |
|---|
| 5104 | #define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 5105 | #define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d913 |
|---|
| 5106 | #define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 5107 | #define regSDMA4_RLC6_RB_AQL_CNTL 0x1d914 |
|---|
| 5108 | #define regSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 5109 | #define regSDMA4_RLC6_MINOR_PTR_UPDATE 0x1d915 |
|---|
| 5110 | #define regSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 5111 | #define regSDMA4_RLC6_MIDCMD_DATA0 0x1d920 |
|---|
| 5112 | #define regSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 5113 | #define regSDMA4_RLC6_MIDCMD_DATA1 0x1d921 |
|---|
| 5114 | #define regSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 5115 | #define regSDMA4_RLC6_MIDCMD_DATA2 0x1d922 |
|---|
| 5116 | #define regSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 5117 | #define regSDMA4_RLC6_MIDCMD_DATA3 0x1d923 |
|---|
| 5118 | #define regSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 5119 | #define regSDMA4_RLC6_MIDCMD_DATA4 0x1d924 |
|---|
| 5120 | #define regSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 5121 | #define regSDMA4_RLC6_MIDCMD_DATA5 0x1d925 |
|---|
| 5122 | #define regSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 5123 | #define regSDMA4_RLC6_MIDCMD_DATA6 0x1d926 |
|---|
| 5124 | #define regSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 5125 | #define regSDMA4_RLC6_MIDCMD_DATA7 0x1d927 |
|---|
| 5126 | #define regSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 5127 | #define regSDMA4_RLC6_MIDCMD_DATA8 0x1d928 |
|---|
| 5128 | #define regSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 5129 | #define regSDMA4_RLC6_MIDCMD_DATA9 0x1d929 |
|---|
| 5130 | #define regSDMA4_RLC6_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 5131 | #define regSDMA4_RLC6_MIDCMD_DATA10 0x1d92a |
|---|
| 5132 | #define regSDMA4_RLC6_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 5133 | #define regSDMA4_RLC6_MIDCMD_CNTL 0x1d92b |
|---|
| 5134 | #define regSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 5135 | #define regSDMA4_RLC7_RB_CNTL 0x1d938 |
|---|
| 5136 | #define regSDMA4_RLC7_RB_CNTL_BASE_IDX 0 |
|---|
| 5137 | #define regSDMA4_RLC7_RB_BASE 0x1d939 |
|---|
| 5138 | #define regSDMA4_RLC7_RB_BASE_BASE_IDX 0 |
|---|
| 5139 | #define regSDMA4_RLC7_RB_BASE_HI 0x1d93a |
|---|
| 5140 | #define regSDMA4_RLC7_RB_BASE_HI_BASE_IDX 0 |
|---|
| 5141 | #define regSDMA4_RLC7_RB_RPTR 0x1d93b |
|---|
| 5142 | #define regSDMA4_RLC7_RB_RPTR_BASE_IDX 0 |
|---|
| 5143 | #define regSDMA4_RLC7_RB_RPTR_HI 0x1d93c |
|---|
| 5144 | #define regSDMA4_RLC7_RB_RPTR_HI_BASE_IDX 0 |
|---|
| 5145 | #define regSDMA4_RLC7_RB_WPTR 0x1d93d |
|---|
| 5146 | #define regSDMA4_RLC7_RB_WPTR_BASE_IDX 0 |
|---|
| 5147 | #define regSDMA4_RLC7_RB_WPTR_HI 0x1d93e |
|---|
| 5148 | #define regSDMA4_RLC7_RB_WPTR_HI_BASE_IDX 0 |
|---|
| 5149 | #define regSDMA4_RLC7_RB_WPTR_POLL_CNTL 0x1d93f |
|---|
| 5150 | #define regSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
|---|
| 5151 | #define regSDMA4_RLC7_RB_RPTR_ADDR_HI 0x1d940 |
|---|
| 5152 | #define regSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 |
|---|
| 5153 | #define regSDMA4_RLC7_RB_RPTR_ADDR_LO 0x1d941 |
|---|
| 5154 | #define regSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 |
|---|
| 5155 | #define regSDMA4_RLC7_IB_CNTL 0x1d942 |
|---|
| 5156 | #define regSDMA4_RLC7_IB_CNTL_BASE_IDX 0 |
|---|
| 5157 | #define regSDMA4_RLC7_IB_RPTR 0x1d943 |
|---|
| 5158 | #define regSDMA4_RLC7_IB_RPTR_BASE_IDX 0 |
|---|
| 5159 | #define regSDMA4_RLC7_IB_OFFSET 0x1d944 |
|---|
| 5160 | #define regSDMA4_RLC7_IB_OFFSET_BASE_IDX 0 |
|---|
| 5161 | #define regSDMA4_RLC7_IB_BASE_LO 0x1d945 |
|---|
| 5162 | #define regSDMA4_RLC7_IB_BASE_LO_BASE_IDX 0 |
|---|
| 5163 | #define regSDMA4_RLC7_IB_BASE_HI 0x1d946 |
|---|
| 5164 | #define regSDMA4_RLC7_IB_BASE_HI_BASE_IDX 0 |
|---|
| 5165 | #define regSDMA4_RLC7_IB_SIZE 0x1d947 |
|---|
| 5166 | #define regSDMA4_RLC7_IB_SIZE_BASE_IDX 0 |
|---|
| 5167 | #define regSDMA4_RLC7_SKIP_CNTL 0x1d948 |
|---|
| 5168 | #define regSDMA4_RLC7_SKIP_CNTL_BASE_IDX 0 |
|---|
| 5169 | #define regSDMA4_RLC7_CONTEXT_STATUS 0x1d949 |
|---|
| 5170 | #define regSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX 0 |
|---|
| 5171 | #define regSDMA4_RLC7_DOORBELL 0x1d94a |
|---|
| 5172 | #define regSDMA4_RLC7_DOORBELL_BASE_IDX 0 |
|---|
| 5173 | #define regSDMA4_RLC7_STATUS 0x1d960 |
|---|
| 5174 | #define regSDMA4_RLC7_STATUS_BASE_IDX 0 |
|---|
| 5175 | #define regSDMA4_RLC7_DOORBELL_LOG 0x1d961 |
|---|
| 5176 | #define regSDMA4_RLC7_DOORBELL_LOG_BASE_IDX 0 |
|---|
| 5177 | #define regSDMA4_RLC7_WATERMARK 0x1d962 |
|---|
| 5178 | #define regSDMA4_RLC7_WATERMARK_BASE_IDX 0 |
|---|
| 5179 | #define regSDMA4_RLC7_DOORBELL_OFFSET 0x1d963 |
|---|
| 5180 | #define regSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX 0 |
|---|
| 5181 | #define regSDMA4_RLC7_CSA_ADDR_LO 0x1d964 |
|---|
| 5182 | #define regSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX 0 |
|---|
| 5183 | #define regSDMA4_RLC7_CSA_ADDR_HI 0x1d965 |
|---|
| 5184 | #define regSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX 0 |
|---|
| 5185 | #define regSDMA4_RLC7_IB_SUB_REMAIN 0x1d967 |
|---|
| 5186 | #define regSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX 0 |
|---|
| 5187 | #define regSDMA4_RLC7_PREEMPT 0x1d968 |
|---|
| 5188 | #define regSDMA4_RLC7_PREEMPT_BASE_IDX 0 |
|---|
| 5189 | #define regSDMA4_RLC7_DUMMY_REG 0x1d969 |
|---|
| 5190 | #define regSDMA4_RLC7_DUMMY_REG_BASE_IDX 0 |
|---|
| 5191 | #define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d96a |
|---|
| 5192 | #define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
|---|
| 5193 | #define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d96b |
|---|
| 5194 | #define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
|---|
| 5195 | #define regSDMA4_RLC7_RB_AQL_CNTL 0x1d96c |
|---|
| 5196 | #define regSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX 0 |
|---|
| 5197 | #define regSDMA4_RLC7_MINOR_PTR_UPDATE 0x1d96d |
|---|
| 5198 | #define regSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 |
|---|
| 5199 | #define regSDMA4_RLC7_MIDCMD_DATA0 0x1d978 |
|---|
| 5200 | #define regSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX 0 |
|---|
| 5201 | #define regSDMA4_RLC7_MIDCMD_DATA1 0x1d979 |
|---|
| 5202 | #define regSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX 0 |
|---|
| 5203 | #define regSDMA4_RLC7_MIDCMD_DATA2 0x1d97a |
|---|
| 5204 | #define regSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX 0 |
|---|
| 5205 | #define regSDMA4_RLC7_MIDCMD_DATA3 0x1d97b |
|---|
| 5206 | #define regSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX 0 |
|---|
| 5207 | #define regSDMA4_RLC7_MIDCMD_DATA4 0x1d97c |
|---|
| 5208 | #define regSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX 0 |
|---|
| 5209 | #define regSDMA4_RLC7_MIDCMD_DATA5 0x1d97d |
|---|
| 5210 | #define regSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX 0 |
|---|
| 5211 | #define regSDMA4_RLC7_MIDCMD_DATA6 0x1d97e |
|---|
| 5212 | #define regSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX 0 |
|---|
| 5213 | #define regSDMA4_RLC7_MIDCMD_DATA7 0x1d97f |
|---|
| 5214 | #define regSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX 0 |
|---|
| 5215 | #define regSDMA4_RLC7_MIDCMD_DATA8 0x1d980 |
|---|
| 5216 | #define regSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX 0 |
|---|
| 5217 | #define regSDMA4_RLC7_MIDCMD_DATA9 0x1d981 |
|---|
| 5218 | #define regSDMA4_RLC7_MIDCMD_DATA9_BASE_IDX 0 |
|---|
| 5219 | #define regSDMA4_RLC7_MIDCMD_DATA10 0x1d982 |
|---|
| 5220 | #define regSDMA4_RLC7_MIDCMD_DATA10_BASE_IDX 0 |
|---|
| 5221 | #define regSDMA4_RLC7_MIDCMD_CNTL 0x1d983 |
|---|
| 5222 | #define regSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX 0 |
|---|
| 5223 | |
|---|
| 5224 | #endif |
|---|
| 5225 | |
|---|
