| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _thm_10_0_SH_MASK_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | // addressBlock: thm_thm_SmuThmDec |
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| 26 | //THM_TCON_CUR_TMP |
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| 27 | #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 |
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| 28 | #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 |
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| 29 | #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 |
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| 30 | #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 |
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| 31 | #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 |
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| 32 | #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 |
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| 33 | #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 |
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| 34 | #define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 |
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| 35 | #define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 |
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| 36 | #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL |
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| 37 | #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L |
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| 38 | #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L |
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| 39 | #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L |
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| 40 | #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L |
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| 41 | #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L |
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| 42 | #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L |
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| 43 | #define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L |
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| 44 | #define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L |
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| 45 | //THM_TCON_HTC |
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| 46 | #define THM_TCON_HTC__HTC_EN__SHIFT 0x0 |
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| 47 | #define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 |
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| 48 | #define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 |
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| 49 | #define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 |
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| 50 | #define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 |
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| 51 | #define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 |
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| 52 | #define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 |
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| 53 | #define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa |
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| 54 | #define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb |
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| 55 | #define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc |
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| 56 | #define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 |
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| 57 | #define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 |
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| 58 | #define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b |
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| 59 | #define THM_TCON_HTC__HTC_EN_MASK 0x00000001L |
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| 60 | #define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L |
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| 61 | #define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L |
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| 62 | #define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L |
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| 63 | #define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L |
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| 64 | #define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L |
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| 65 | #define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x00000200L |
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| 66 | #define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L |
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| 67 | #define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L |
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| 68 | #define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L |
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| 69 | #define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L |
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| 70 | #define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L |
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| 71 | #define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L |
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| 72 | //THM_TCON_THERM_TRIP |
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| 73 | #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 |
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| 74 | #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 |
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| 75 | #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 |
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| 76 | #define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 |
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| 77 | #define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 |
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| 78 | #define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 |
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| 79 | #define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 |
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| 80 | #define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe |
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| 81 | #define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f |
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| 82 | #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L |
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| 83 | #define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L |
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| 84 | #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L |
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| 85 | #define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L |
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| 86 | #define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L |
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| 87 | #define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L |
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| 88 | #define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L |
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| 89 | #define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L |
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| 90 | #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L |
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| 91 | //THM_CTF_DELAY |
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| 92 | #define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 |
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| 93 | #define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL |
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| 94 | //THM_GPIO_PROCHOT_CTRL |
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| 95 | #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 |
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| 96 | #define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 |
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| 97 | #define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 |
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| 98 | #define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 |
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| 99 | #define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 |
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| 100 | #define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 |
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| 101 | #define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 |
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| 102 | #define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 |
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| 103 | #define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 |
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| 104 | #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 |
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| 105 | #define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 |
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| 106 | #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 |
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| 107 | #define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 |
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| 108 | #define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f |
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| 109 | #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L |
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| 110 | #define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L |
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| 111 | #define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L |
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| 112 | #define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L |
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| 113 | #define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L |
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| 114 | #define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L |
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| 115 | #define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L |
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| 116 | #define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L |
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| 117 | #define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L |
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| 118 | #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L |
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| 119 | #define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L |
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| 120 | #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L |
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| 121 | #define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L |
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| 122 | #define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L |
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| 123 | //THM_THERMAL_INT_ENA |
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| 124 | #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 |
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| 125 | #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 |
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| 126 | #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 |
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| 127 | #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 |
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| 128 | #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 |
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| 129 | #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 |
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| 130 | #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L |
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| 131 | #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L |
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| 132 | #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L |
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| 133 | #define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L |
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| 134 | #define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L |
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| 135 | #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L |
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| 136 | //THM_THERMAL_INT_CTRL |
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| 137 | #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 |
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| 138 | #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 |
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| 139 | #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 |
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| 140 | #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 |
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| 141 | #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 |
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| 142 | #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a |
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| 143 | #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b |
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| 144 | #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c |
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| 145 | #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d |
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| 146 | #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL |
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| 147 | #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L |
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| 148 | #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L |
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| 149 | #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L |
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| 150 | #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L |
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| 151 | #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L |
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| 152 | #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L |
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| 153 | #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L |
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| 154 | #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L |
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| 155 | //THM_THERMAL_INT_STATUS |
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| 156 | #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 |
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| 157 | #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 |
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| 158 | #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 |
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| 159 | #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 |
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| 160 | #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L |
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| 161 | #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L |
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| 162 | #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L |
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| 163 | #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L |
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| 164 | //THM_TMON0_RDIL0_DATA |
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| 165 | #define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 |
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| 166 | #define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb |
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| 167 | #define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc |
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| 168 | #define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL |
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| 169 | #define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L |
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| 170 | #define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L |
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| 171 | //THM_TMON0_RDIL1_DATA |
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| 172 | #define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 |
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| 173 | #define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb |
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| 174 | #define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc |
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| 175 | #define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL |
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| 176 | #define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L |
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| 177 | #define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L |
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| 178 | //THM_TMON0_RDIL2_DATA |
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| 179 | #define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 |
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| 180 | #define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb |
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| 181 | #define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc |
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| 182 | #define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL |
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| 183 | #define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L |
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| 184 | #define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L |
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| 185 | //THM_TMON0_RDIL3_DATA |
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| 186 | #define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 |
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| 187 | #define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb |
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| 188 | #define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc |
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| 189 | #define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL |
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| 190 | #define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L |
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| 191 | #define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L |
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| 192 | //THM_TMON0_RDIL4_DATA |
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| 193 | #define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 |
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| 194 | #define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb |
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| 195 | #define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc |
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| 196 | #define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL |
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| 197 | #define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L |
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| 198 | #define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L |
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| 199 | //THM_TMON0_RDIL5_DATA |
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| 200 | #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 |
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| 201 | #define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb |
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| 202 | #define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc |
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| 203 | #define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL |
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| 204 | #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L |
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| 205 | #define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L |
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| 206 | //THM_TMON0_RDIL6_DATA |
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| 207 | #define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 |
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| 208 | #define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb |
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| 209 | #define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc |
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| 210 | #define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL |
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| 211 | #define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L |
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| 212 | #define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L |
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| 213 | //THM_TMON0_RDIL7_DATA |
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| 214 | #define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 |
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| 215 | #define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb |
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| 216 | #define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc |
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| 217 | #define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL |
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| 218 | #define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L |
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| 219 | #define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L |
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| 220 | //THM_TMON0_RDIL8_DATA |
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| 221 | #define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 |
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| 222 | #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb |
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| 223 | #define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc |
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| 224 | #define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL |
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| 225 | #define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L |
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| 226 | #define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L |
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| 227 | //THM_TMON0_RDIL9_DATA |
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| 228 | #define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 |
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| 229 | #define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb |
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| 230 | #define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc |
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| 231 | #define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL |
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| 232 | #define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L |
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| 233 | #define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L |
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| 234 | //THM_TMON0_RDIL10_DATA |
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| 235 | #define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 |
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| 236 | #define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb |
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| 237 | #define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc |
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| 238 | #define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL |
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| 239 | #define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L |
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| 240 | #define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L |
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| 241 | //THM_TMON0_RDIL11_DATA |
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| 242 | #define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 |
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| 243 | #define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb |
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| 244 | #define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc |
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| 245 | #define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL |
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| 246 | #define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L |
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| 247 | #define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L |
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| 248 | //THM_TMON0_RDIL12_DATA |
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| 249 | #define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 |
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| 250 | #define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb |
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| 251 | #define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc |
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| 252 | #define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL |
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| 253 | #define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L |
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| 254 | #define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L |
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| 255 | //THM_TMON0_RDIL13_DATA |
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| 256 | #define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 |
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| 257 | #define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb |
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| 258 | #define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc |
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| 259 | #define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL |
|---|
| 260 | #define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L |
|---|
| 261 | #define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 262 | //THM_TMON0_RDIL14_DATA |
|---|
| 263 | #define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 |
|---|
| 264 | #define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb |
|---|
| 265 | #define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc |
|---|
| 266 | #define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL |
|---|
| 267 | #define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L |
|---|
| 268 | #define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 269 | //THM_TMON0_RDIL15_DATA |
|---|
| 270 | #define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 |
|---|
| 271 | #define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb |
|---|
| 272 | #define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc |
|---|
| 273 | #define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL |
|---|
| 274 | #define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L |
|---|
| 275 | #define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 276 | //THM_TMON0_RDIR0_DATA |
|---|
| 277 | #define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 |
|---|
| 278 | #define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb |
|---|
| 279 | #define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc |
|---|
| 280 | #define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL |
|---|
| 281 | #define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L |
|---|
| 282 | #define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 283 | //THM_TMON0_RDIR1_DATA |
|---|
| 284 | #define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 |
|---|
| 285 | #define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb |
|---|
| 286 | #define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc |
|---|
| 287 | #define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL |
|---|
| 288 | #define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L |
|---|
| 289 | #define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 290 | //THM_TMON0_RDIR2_DATA |
|---|
| 291 | #define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 |
|---|
| 292 | #define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb |
|---|
| 293 | #define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc |
|---|
| 294 | #define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL |
|---|
| 295 | #define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L |
|---|
| 296 | #define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 297 | //THM_TMON0_RDIR3_DATA |
|---|
| 298 | #define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 |
|---|
| 299 | #define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb |
|---|
| 300 | #define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc |
|---|
| 301 | #define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL |
|---|
| 302 | #define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L |
|---|
| 303 | #define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 304 | //THM_TMON0_RDIR4_DATA |
|---|
| 305 | #define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 |
|---|
| 306 | #define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb |
|---|
| 307 | #define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc |
|---|
| 308 | #define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL |
|---|
| 309 | #define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L |
|---|
| 310 | #define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 311 | //THM_TMON0_RDIR5_DATA |
|---|
| 312 | #define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 |
|---|
| 313 | #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb |
|---|
| 314 | #define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc |
|---|
| 315 | #define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL |
|---|
| 316 | #define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L |
|---|
| 317 | #define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 318 | //THM_TMON0_RDIR6_DATA |
|---|
| 319 | #define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 |
|---|
| 320 | #define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb |
|---|
| 321 | #define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc |
|---|
| 322 | #define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL |
|---|
| 323 | #define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L |
|---|
| 324 | #define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 325 | //THM_TMON0_RDIR7_DATA |
|---|
| 326 | #define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 |
|---|
| 327 | #define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb |
|---|
| 328 | #define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc |
|---|
| 329 | #define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL |
|---|
| 330 | #define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L |
|---|
| 331 | #define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 332 | //THM_TMON0_RDIR8_DATA |
|---|
| 333 | #define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 |
|---|
| 334 | #define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb |
|---|
| 335 | #define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc |
|---|
| 336 | #define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL |
|---|
| 337 | #define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L |
|---|
| 338 | #define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 339 | //THM_TMON0_RDIR9_DATA |
|---|
| 340 | #define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 |
|---|
| 341 | #define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb |
|---|
| 342 | #define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc |
|---|
| 343 | #define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL |
|---|
| 344 | #define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L |
|---|
| 345 | #define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 346 | //THM_TMON0_RDIR10_DATA |
|---|
| 347 | #define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 |
|---|
| 348 | #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb |
|---|
| 349 | #define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc |
|---|
| 350 | #define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL |
|---|
| 351 | #define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L |
|---|
| 352 | #define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 353 | //THM_TMON0_RDIR11_DATA |
|---|
| 354 | #define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 |
|---|
| 355 | #define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb |
|---|
| 356 | #define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc |
|---|
| 357 | #define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL |
|---|
| 358 | #define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L |
|---|
| 359 | #define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 360 | //THM_TMON0_RDIR12_DATA |
|---|
| 361 | #define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 |
|---|
| 362 | #define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb |
|---|
| 363 | #define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc |
|---|
| 364 | #define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL |
|---|
| 365 | #define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L |
|---|
| 366 | #define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 367 | //THM_TMON0_RDIR13_DATA |
|---|
| 368 | #define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 |
|---|
| 369 | #define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb |
|---|
| 370 | #define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc |
|---|
| 371 | #define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL |
|---|
| 372 | #define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L |
|---|
| 373 | #define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 374 | //THM_TMON0_RDIR14_DATA |
|---|
| 375 | #define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 |
|---|
| 376 | #define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb |
|---|
| 377 | #define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc |
|---|
| 378 | #define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL |
|---|
| 379 | #define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L |
|---|
| 380 | #define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 381 | //THM_TMON0_RDIR15_DATA |
|---|
| 382 | #define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 |
|---|
| 383 | #define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb |
|---|
| 384 | #define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc |
|---|
| 385 | #define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL |
|---|
| 386 | #define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L |
|---|
| 387 | #define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 388 | //THM_TMON0_INT_DATA |
|---|
| 389 | #define THM_TMON0_INT_DATA__Z__SHIFT 0x0 |
|---|
| 390 | #define THM_TMON0_INT_DATA__VALID__SHIFT 0xb |
|---|
| 391 | #define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc |
|---|
| 392 | #define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL |
|---|
| 393 | #define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L |
|---|
| 394 | #define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L |
|---|
| 395 | //THM_TMON0_CTRL |
|---|
| 396 | #define THM_TMON0_CTRL__POWER_DOWN__SHIFT 0x0 |
|---|
| 397 | #define THM_TMON0_CTRL__BGADJ__SHIFT 0x1 |
|---|
| 398 | #define THM_TMON0_CTRL__BGADJ_MODE__SHIFT 0x9 |
|---|
| 399 | #define THM_TMON0_CTRL__TMON_PAUSE__SHIFT 0xa |
|---|
| 400 | #define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT 0xb |
|---|
| 401 | #define THM_TMON0_CTRL__DEBUG_MODE__SHIFT 0xc |
|---|
| 402 | #define THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT 0xd |
|---|
| 403 | #define THM_TMON0_CTRL__POWER_DOWN_MASK 0x00000001L |
|---|
| 404 | #define THM_TMON0_CTRL__BGADJ_MASK 0x000001FEL |
|---|
| 405 | #define THM_TMON0_CTRL__BGADJ_MODE_MASK 0x00000200L |
|---|
| 406 | #define THM_TMON0_CTRL__TMON_PAUSE_MASK 0x00000400L |
|---|
| 407 | #define THM_TMON0_CTRL__INT_MEAS_EN_MASK 0x00000800L |
|---|
| 408 | #define THM_TMON0_CTRL__DEBUG_MODE_MASK 0x00001000L |
|---|
| 409 | #define THM_TMON0_CTRL__EN_CFG_SERDES_MASK 0x00002000L |
|---|
| 410 | //THM_TMON0_CTRL2 |
|---|
| 411 | #define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT 0x0 |
|---|
| 412 | #define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT 0x10 |
|---|
| 413 | #define THM_TMON0_CTRL2__RDIL_PRESENT_MASK 0x0000FFFFL |
|---|
| 414 | #define THM_TMON0_CTRL2__RDIR_PRESENT_MASK 0xFFFF0000L |
|---|
| 415 | //THM_TMON0_DEBUG |
|---|
| 416 | #define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 |
|---|
| 417 | #define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 |
|---|
| 418 | #define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001FL |
|---|
| 419 | #define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000FFE0L |
|---|
| 420 | //THM_DIE1_TEMP |
|---|
| 421 | #define THM_DIE1_TEMP__TEMP__SHIFT 0x0 |
|---|
| 422 | #define THM_DIE1_TEMP__VALID__SHIFT 0xb |
|---|
| 423 | #define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL |
|---|
| 424 | #define THM_DIE1_TEMP__VALID_MASK 0x00000800L |
|---|
| 425 | //THM_DIE2_TEMP |
|---|
| 426 | #define THM_DIE2_TEMP__TEMP__SHIFT 0x0 |
|---|
| 427 | #define THM_DIE2_TEMP__VALID__SHIFT 0xb |
|---|
| 428 | #define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL |
|---|
| 429 | #define THM_DIE2_TEMP__VALID_MASK 0x00000800L |
|---|
| 430 | //THM_DIE3_TEMP |
|---|
| 431 | #define THM_DIE3_TEMP__TEMP__SHIFT 0x0 |
|---|
| 432 | #define THM_DIE3_TEMP__VALID__SHIFT 0xb |
|---|
| 433 | #define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL |
|---|
| 434 | #define THM_DIE3_TEMP__VALID_MASK 0x00000800L |
|---|
| 435 | //THM_SW_TEMP |
|---|
| 436 | #define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 |
|---|
| 437 | #define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL |
|---|
| 438 | //CG_MULT_THERMAL_CTRL |
|---|
| 439 | #define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 |
|---|
| 440 | #define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 |
|---|
| 441 | #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 |
|---|
| 442 | #define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 |
|---|
| 443 | #define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL |
|---|
| 444 | #define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L |
|---|
| 445 | #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L |
|---|
| 446 | #define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L |
|---|
| 447 | //CG_MULT_THERMAL_STATUS |
|---|
| 448 | #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 |
|---|
| 449 | #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 |
|---|
| 450 | #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL |
|---|
| 451 | #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L |
|---|
| 452 | //CG_THERMAL_RANGE |
|---|
| 453 | #define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 |
|---|
| 454 | #define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 |
|---|
| 455 | #define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL |
|---|
| 456 | #define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L |
|---|
| 457 | //THM_TMON_CONFIG |
|---|
| 458 | #define THM_TMON_CONFIG__NUM_ACQ__SHIFT 0x0 |
|---|
| 459 | #define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 |
|---|
| 460 | #define THM_TMON_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 |
|---|
| 461 | #define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT 0x5 |
|---|
| 462 | #define THM_TMON_CONFIG__RE_CALIB_EN__SHIFT 0x6 |
|---|
| 463 | #define THM_TMON_CONFIG__Z__SHIFT 0x15 |
|---|
| 464 | #define THM_TMON_CONFIG__NUM_ACQ_MASK 0x00000007L |
|---|
| 465 | #define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK 0x00000008L |
|---|
| 466 | #define THM_TMON_CONFIG__RDI_INTERLEAVE_MASK 0x00000010L |
|---|
| 467 | #define THM_TMON_CONFIG__CONFIG_SOURCE_MASK 0x00000020L |
|---|
| 468 | #define THM_TMON_CONFIG__RE_CALIB_EN_MASK 0x00000040L |
|---|
| 469 | #define THM_TMON_CONFIG__Z_MASK 0xFFE00000L |
|---|
| 470 | //THM_TMON_CONFIG2 |
|---|
| 471 | #define THM_TMON_CONFIG2__A__SHIFT 0x0 |
|---|
| 472 | #define THM_TMON_CONFIG2__B__SHIFT 0xc |
|---|
| 473 | #define THM_TMON_CONFIG2__C__SHIFT 0x12 |
|---|
| 474 | #define THM_TMON_CONFIG2__K__SHIFT 0x1d |
|---|
| 475 | #define THM_TMON_CONFIG2__A_MASK 0x00000FFFL |
|---|
| 476 | #define THM_TMON_CONFIG2__B_MASK 0x0003F000L |
|---|
| 477 | #define THM_TMON_CONFIG2__C_MASK 0x1FFC0000L |
|---|
| 478 | #define THM_TMON_CONFIG2__K_MASK 0x20000000L |
|---|
| 479 | //THM_TMON0_COEFF |
|---|
| 480 | #define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 |
|---|
| 481 | #define THM_TMON0_COEFF__D__SHIFT 0xb |
|---|
| 482 | #define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL |
|---|
| 483 | #define THM_TMON0_COEFF__D_MASK 0x0003F800L |
|---|
| 484 | //THM_TCON_LOCAL0 |
|---|
| 485 | #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 |
|---|
| 486 | #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 |
|---|
| 487 | #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L |
|---|
| 488 | #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L |
|---|
| 489 | //THM_TCON_LOCAL1 |
|---|
| 490 | #define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 |
|---|
| 491 | #define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 |
|---|
| 492 | #define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 |
|---|
| 493 | #define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 |
|---|
| 494 | #define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L |
|---|
| 495 | #define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L |
|---|
| 496 | #define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L |
|---|
| 497 | #define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L |
|---|
| 498 | //THM_TCON_LOCAL2 |
|---|
| 499 | #define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 |
|---|
| 500 | #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 |
|---|
| 501 | #define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 |
|---|
| 502 | #define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 |
|---|
| 503 | #define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa |
|---|
| 504 | #define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb |
|---|
| 505 | #define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L |
|---|
| 506 | #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL |
|---|
| 507 | #define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L |
|---|
| 508 | #define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L |
|---|
| 509 | #define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L |
|---|
| 510 | #define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L |
|---|
| 511 | //THM_TCON_LOCAL3 |
|---|
| 512 | #define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 |
|---|
| 513 | #define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL |
|---|
| 514 | //THM_TCON_LOCAL4 |
|---|
| 515 | #define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 |
|---|
| 516 | #define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL |
|---|
| 517 | //THM_TCON_LOCAL5 |
|---|
| 518 | #define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 |
|---|
| 519 | #define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL |
|---|
| 520 | //THM_TCON_LOCAL6 |
|---|
| 521 | #define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 |
|---|
| 522 | #define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL |
|---|
| 523 | //THM_TCON_LOCAL7 |
|---|
| 524 | #define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 |
|---|
| 525 | #define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL |
|---|
| 526 | //THM_TCON_LOCAL8 |
|---|
| 527 | #define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 |
|---|
| 528 | #define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL |
|---|
| 529 | //THM_TCON_LOCAL9 |
|---|
| 530 | #define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 |
|---|
| 531 | #define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL |
|---|
| 532 | //THM_TCON_LOCAL10 |
|---|
| 533 | #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 |
|---|
| 534 | #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL |
|---|
| 535 | //THM_TCON_LOCAL11 |
|---|
| 536 | #define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 |
|---|
| 537 | #define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL |
|---|
| 538 | //THM_TCON_LOCAL12 |
|---|
| 539 | #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 |
|---|
| 540 | #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL |
|---|
| 541 | //THM_TCON_LOCAL13 |
|---|
| 542 | #define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 |
|---|
| 543 | #define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L |
|---|
| 544 | //THM_PWRMGT |
|---|
| 545 | #define THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN__SHIFT 0x0 |
|---|
| 546 | #define THM_PWRMGT__SBAXI_CLK_GATE_EN__SHIFT 0x1 |
|---|
| 547 | #define THM_PWRMGT__SB_CLK_GATE_MAX_CNT__SHIFT 0x8 |
|---|
| 548 | #define THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN_MASK 0x00000001L |
|---|
| 549 | #define THM_PWRMGT__SBAXI_CLK_GATE_EN_MASK 0x00000002L |
|---|
| 550 | #define THM_PWRMGT__SB_CLK_GATE_MAX_CNT_MASK 0x00FFFF00L |
|---|
| 551 | //SMUSBI_SBIREGADDR |
|---|
| 552 | #define SMUSBI_SBIREGADDR__SBI_REGADDR__SHIFT 0x0 |
|---|
| 553 | #define SMUSBI_SBIREGADDR__SBI_REGADDR_MASK 0x000007FFL |
|---|
| 554 | //SMUSBI_SBIREGDATA |
|---|
| 555 | #define SMUSBI_SBIREGDATA__SBI_REGDATA__SHIFT 0x0 |
|---|
| 556 | #define SMUSBI_SBIREGDATA__SBI_REGDATA_MASK 0xFFFFFFFFL |
|---|
| 557 | //SMUSBI_ERRATA_STAT_REG |
|---|
| 558 | #define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG__SHIFT 0x0 |
|---|
| 559 | #define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG_MASK 0xFFFFFFFFL |
|---|
| 560 | //SMUSBI_SBICTRL |
|---|
| 561 | #define SMUSBI_SBICTRL__CK_SPRSBIWRDONE__SHIFT 0x0 |
|---|
| 562 | #define SMUSBI_SBICTRL__NB_SBISELECT__SHIFT 0x1 |
|---|
| 563 | #define SMUSBI_SBICTRL__NB_SBIADDR__SHIFT 0x2 |
|---|
| 564 | #define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE__SHIFT 0x5 |
|---|
| 565 | #define SMUSBI_SBICTRL__CK_SPRSBIWRDONE_MASK 0x00000001L |
|---|
| 566 | #define SMUSBI_SBICTRL__NB_SBISELECT_MASK 0x00000002L |
|---|
| 567 | #define SMUSBI_SBICTRL__NB_SBIADDR_MASK 0x0000001CL |
|---|
| 568 | #define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE_MASK 0x00000020L |
|---|
| 569 | //SMUSBI_CKNBIRESET |
|---|
| 570 | #define SMUSBI_CKNBIRESET__CKNBIRESET__SHIFT 0x0 |
|---|
| 571 | #define SMUSBI_CKNBIRESET__CKNBIRESET_MASK 0x00000001L |
|---|
| 572 | //SMUSBI_TIMING |
|---|
| 573 | #define SMUSBI_TIMING__SETUP_TIME__SHIFT 0x0 |
|---|
| 574 | #define SMUSBI_TIMING__SETUP_TIME_OVERRIDE__SHIFT 0x8 |
|---|
| 575 | #define SMUSBI_TIMING__HOLD_TIME__SHIFT 0x10 |
|---|
| 576 | #define SMUSBI_TIMING__HOLD_TIME_OVERRIDE__SHIFT 0x18 |
|---|
| 577 | #define SMUSBI_TIMING__SETUP_TIME_MASK 0x0000003FL |
|---|
| 578 | #define SMUSBI_TIMING__SETUP_TIME_OVERRIDE_MASK 0x00000100L |
|---|
| 579 | #define SMUSBI_TIMING__HOLD_TIME_MASK 0x00FF0000L |
|---|
| 580 | #define SMUSBI_TIMING__HOLD_TIME_OVERRIDE_MASK 0x01000000L |
|---|
| 581 | //SMUSBI_HS_TIMING |
|---|
| 582 | #define SMUSBI_HS_TIMING__HS_SETUP_TIME__SHIFT 0x0 |
|---|
| 583 | #define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE__SHIFT 0x8 |
|---|
| 584 | #define SMUSBI_HS_TIMING__HS_HOLD_TIME__SHIFT 0x10 |
|---|
| 585 | #define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE__SHIFT 0x18 |
|---|
| 586 | #define SMUSBI_HS_TIMING__HS_SETUP_TIME_MASK 0x0000003FL |
|---|
| 587 | #define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE_MASK 0x00000100L |
|---|
| 588 | #define SMUSBI_HS_TIMING__HS_HOLD_TIME_MASK 0x00FF0000L |
|---|
| 589 | #define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE_MASK 0x01000000L |
|---|
| 590 | //SBTSI_REMOTE_TEMP |
|---|
| 591 | #define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 |
|---|
| 592 | #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb |
|---|
| 593 | #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 |
|---|
| 594 | #define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL |
|---|
| 595 | #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L |
|---|
| 596 | #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L |
|---|
| 597 | //SBRMI_CONTROL |
|---|
| 598 | #define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 |
|---|
| 599 | #define SBRMI_CONTROL__DPD__SHIFT 0x1 |
|---|
| 600 | #define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 |
|---|
| 601 | #define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L |
|---|
| 602 | #define SBRMI_CONTROL__DPD_MASK 0x00000002L |
|---|
| 603 | #define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L |
|---|
| 604 | //SBRMI_COMMAND |
|---|
| 605 | #define SBRMI_COMMAND__Command__SHIFT 0x0 |
|---|
| 606 | #define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 |
|---|
| 607 | #define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 |
|---|
| 608 | #define SBRMI_COMMAND__CommandSent__SHIFT 0x18 |
|---|
| 609 | #define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 |
|---|
| 610 | #define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a |
|---|
| 611 | #define SBRMI_COMMAND__Status__SHIFT 0x1c |
|---|
| 612 | #define SBRMI_COMMAND__Command_MASK 0x000000FFL |
|---|
| 613 | #define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L |
|---|
| 614 | #define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L |
|---|
| 615 | #define SBRMI_COMMAND__CommandSent_MASK 0x01000000L |
|---|
| 616 | #define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L |
|---|
| 617 | #define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L |
|---|
| 618 | #define SBRMI_COMMAND__Status_MASK 0xF0000000L |
|---|
| 619 | //SBRMI_WRITE_DATA0 |
|---|
| 620 | #define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 |
|---|
| 621 | #define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 |
|---|
| 622 | #define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 |
|---|
| 623 | #define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 |
|---|
| 624 | #define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL |
|---|
| 625 | #define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L |
|---|
| 626 | #define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L |
|---|
| 627 | #define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L |
|---|
| 628 | //SBRMI_WRITE_DATA1 |
|---|
| 629 | #define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 |
|---|
| 630 | #define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 |
|---|
| 631 | #define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 |
|---|
| 632 | #define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 |
|---|
| 633 | #define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL |
|---|
| 634 | #define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L |
|---|
| 635 | #define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L |
|---|
| 636 | #define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L |
|---|
| 637 | //SBRMI_WRITE_DATA2 |
|---|
| 638 | #define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 |
|---|
| 639 | #define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 |
|---|
| 640 | #define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 |
|---|
| 641 | #define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 |
|---|
| 642 | #define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL |
|---|
| 643 | #define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L |
|---|
| 644 | #define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L |
|---|
| 645 | #define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L |
|---|
| 646 | //SBRMI_READ_DATA0 |
|---|
| 647 | #define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 |
|---|
| 648 | #define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 |
|---|
| 649 | #define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 |
|---|
| 650 | #define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 |
|---|
| 651 | #define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL |
|---|
| 652 | #define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L |
|---|
| 653 | #define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L |
|---|
| 654 | #define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L |
|---|
| 655 | //SBRMI_READ_DATA1 |
|---|
| 656 | #define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 |
|---|
| 657 | #define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 |
|---|
| 658 | #define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 |
|---|
| 659 | #define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 |
|---|
| 660 | #define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL |
|---|
| 661 | #define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L |
|---|
| 662 | #define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L |
|---|
| 663 | #define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L |
|---|
| 664 | //SBRMI_CORE_EN_NUMBER |
|---|
| 665 | #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 |
|---|
| 666 | #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL |
|---|
| 667 | //SBRMI_CORE_EN_STATUS0 |
|---|
| 668 | #define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 |
|---|
| 669 | #define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL |
|---|
| 670 | //SBRMI_CORE_EN_STATUS1 |
|---|
| 671 | #define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 |
|---|
| 672 | #define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL |
|---|
| 673 | //SBRMI_APIC_STATUS0 |
|---|
| 674 | #define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 |
|---|
| 675 | #define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL |
|---|
| 676 | //SBRMI_APIC_STATUS1 |
|---|
| 677 | #define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 |
|---|
| 678 | #define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL |
|---|
| 679 | //SBRMI_MCE_STATUS0 |
|---|
| 680 | #define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 |
|---|
| 681 | #define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL |
|---|
| 682 | //SBRMI_MCE_STATUS1 |
|---|
| 683 | #define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 |
|---|
| 684 | #define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL |
|---|
| 685 | //SMBUS_CNTL0 |
|---|
| 686 | #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 |
|---|
| 687 | #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 |
|---|
| 688 | #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 |
|---|
| 689 | #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 |
|---|
| 690 | #define SMBUS_CNTL0__THM_READY__SHIFT 0x14 |
|---|
| 691 | #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L |
|---|
| 692 | #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL |
|---|
| 693 | #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L |
|---|
| 694 | #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L |
|---|
| 695 | #define SMBUS_CNTL0__THM_READY_MASK 0x00100000L |
|---|
| 696 | //SMBUS_CNTL1 |
|---|
| 697 | #define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 |
|---|
| 698 | #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 |
|---|
| 699 | #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 |
|---|
| 700 | #define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L |
|---|
| 701 | #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL |
|---|
| 702 | #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L |
|---|
| 703 | //SMBUS_BLKWR_CMD_CTRL0 |
|---|
| 704 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 |
|---|
| 705 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 |
|---|
| 706 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 |
|---|
| 707 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 |
|---|
| 708 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL |
|---|
| 709 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L |
|---|
| 710 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L |
|---|
| 711 | #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L |
|---|
| 712 | //SMBUS_BLKWR_CMD_CTRL1 |
|---|
| 713 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 |
|---|
| 714 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 |
|---|
| 715 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 |
|---|
| 716 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 |
|---|
| 717 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL |
|---|
| 718 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L |
|---|
| 719 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L |
|---|
| 720 | #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L |
|---|
| 721 | //SMBUS_BLKRD_CMD_CTRL0 |
|---|
| 722 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 |
|---|
| 723 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 |
|---|
| 724 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 |
|---|
| 725 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 |
|---|
| 726 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL |
|---|
| 727 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L |
|---|
| 728 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L |
|---|
| 729 | #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L |
|---|
| 730 | //SMBUS_BLKRD_CMD_CTRL1 |
|---|
| 731 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 |
|---|
| 732 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 |
|---|
| 733 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 |
|---|
| 734 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 |
|---|
| 735 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL |
|---|
| 736 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L |
|---|
| 737 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L |
|---|
| 738 | #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L |
|---|
| 739 | //SMBUS_TIMING_CNTL0 |
|---|
| 740 | #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 |
|---|
| 741 | #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 |
|---|
| 742 | #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL |
|---|
| 743 | #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L |
|---|
| 744 | //SMBUS_TIMING_CNTL1 |
|---|
| 745 | #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 |
|---|
| 746 | #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 |
|---|
| 747 | #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb |
|---|
| 748 | #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 |
|---|
| 749 | #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL |
|---|
| 750 | #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L |
|---|
| 751 | #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L |
|---|
| 752 | #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L |
|---|
| 753 | //SMBUS_TIMING_CNTL2 |
|---|
| 754 | #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 |
|---|
| 755 | #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd |
|---|
| 756 | #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL |
|---|
| 757 | #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L |
|---|
| 758 | //SMBUS_TRIGGER_CNTL |
|---|
| 759 | #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 |
|---|
| 760 | #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 |
|---|
| 761 | #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L |
|---|
| 762 | #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L |
|---|
| 763 | //SMBUS_UDID_CNTL0 |
|---|
| 764 | #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 |
|---|
| 765 | #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f |
|---|
| 766 | #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL |
|---|
| 767 | #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L |
|---|
| 768 | //SMBUS_UDID_CNTL1 |
|---|
| 769 | #define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 |
|---|
| 770 | #define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL |
|---|
| 771 | //SMBUS_UDID_CNTL2 |
|---|
| 772 | #define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 |
|---|
| 773 | #define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 |
|---|
| 774 | #define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 |
|---|
| 775 | #define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 |
|---|
| 776 | #define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 |
|---|
| 777 | #define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa |
|---|
| 778 | #define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L |
|---|
| 779 | #define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL |
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| 780 | #define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L |
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| 781 | #define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L |
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| 782 | #define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L |
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| 783 | #define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L |
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| 784 | //SMUSBI_SMBUS |
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| 785 | #define SMUSBI_SMBUS__Spare0__SHIFT 0x0 |
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| 786 | #define SMUSBI_SMBUS__Spare1__SHIFT 0x1 |
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| 787 | #define SMUSBI_SMBUS__ResBiasEn__SHIFT 0x2 |
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| 788 | #define SMUSBI_SMBUS__CompSel__SHIFT 0x3 |
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| 789 | #define SMUSBI_SMBUS__NG__SHIFT 0x4 |
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| 790 | #define SMUSBI_SMBUS__I2cRxSel__SHIFT 0x8 |
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| 791 | #define SMUSBI_SMBUS__PdEn0__SHIFT 0xa |
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| 792 | #define SMUSBI_SMBUS__PdEn1__SHIFT 0xb |
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| 793 | #define SMUSBI_SMBUS__FallSlewSel__SHIFT 0xc |
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| 794 | #define SMUSBI_SMBUS__Slewn__SHIFT 0xe |
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| 795 | #define SMUSBI_SMBUS__SpikeRcEn__SHIFT 0xf |
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| 796 | #define SMUSBI_SMBUS__SpikeRcSel__SHIFT 0x10 |
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| 797 | #define SMUSBI_SMBUS__CSel0p9__SHIFT 0x11 |
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| 798 | #define SMUSBI_SMBUS__CSel1p1__SHIFT 0x12 |
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| 799 | #define SMUSBI_SMBUS__RSel0p9__SHIFT 0x13 |
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| 800 | #define SMUSBI_SMBUS__RSel1p1__SHIFT 0x14 |
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| 801 | #define SMUSBI_SMBUS__BiasCrtEn__SHIFT 0x15 |
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| 802 | #define SMUSBI_SMBUS__DI2C0__SHIFT 0x16 |
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| 803 | #define SMUSBI_SMBUS__DI2C1__SHIFT 0x17 |
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| 804 | #define SMUSBI_SMBUS__DI2C0_OVERRIDE__SHIFT 0x18 |
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| 805 | #define SMUSBI_SMBUS__DI2C1_OVERRIDE__SHIFT 0x19 |
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| 806 | #define SMUSBI_SMBUS__Y0__SHIFT 0x1e |
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| 807 | #define SMUSBI_SMBUS__Y1__SHIFT 0x1f |
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| 808 | #define SMUSBI_SMBUS__Spare0_MASK 0x00000001L |
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| 809 | #define SMUSBI_SMBUS__Spare1_MASK 0x00000002L |
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| 810 | #define SMUSBI_SMBUS__ResBiasEn_MASK 0x00000004L |
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| 811 | #define SMUSBI_SMBUS__CompSel_MASK 0x00000008L |
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| 812 | #define SMUSBI_SMBUS__NG_MASK 0x000000F0L |
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| 813 | #define SMUSBI_SMBUS__I2cRxSel_MASK 0x00000300L |
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| 814 | #define SMUSBI_SMBUS__PdEn0_MASK 0x00000400L |
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| 815 | #define SMUSBI_SMBUS__PdEn1_MASK 0x00000800L |
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| 816 | #define SMUSBI_SMBUS__FallSlewSel_MASK 0x00003000L |
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| 817 | #define SMUSBI_SMBUS__Slewn_MASK 0x00004000L |
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| 818 | #define SMUSBI_SMBUS__SpikeRcEn_MASK 0x00008000L |
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| 819 | #define SMUSBI_SMBUS__SpikeRcSel_MASK 0x00010000L |
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| 820 | #define SMUSBI_SMBUS__CSel0p9_MASK 0x00020000L |
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| 821 | #define SMUSBI_SMBUS__CSel1p1_MASK 0x00040000L |
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| 822 | #define SMUSBI_SMBUS__RSel0p9_MASK 0x00080000L |
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| 823 | #define SMUSBI_SMBUS__RSel1p1_MASK 0x00100000L |
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| 824 | #define SMUSBI_SMBUS__BiasCrtEn_MASK 0x00200000L |
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| 825 | #define SMUSBI_SMBUS__DI2C0_MASK 0x00400000L |
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| 826 | #define SMUSBI_SMBUS__DI2C1_MASK 0x00800000L |
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| 827 | #define SMUSBI_SMBUS__DI2C0_OVERRIDE_MASK 0x01000000L |
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| 828 | #define SMUSBI_SMBUS__DI2C1_OVERRIDE_MASK 0x02000000L |
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| 829 | #define SMUSBI_SMBUS__Y0_MASK 0x40000000L |
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| 830 | #define SMUSBI_SMBUS__Y1_MASK 0x80000000L |
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| 831 | //SMUSBI_ALERT |
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| 832 | #define SMUSBI_ALERT__TXIMPSEL__SHIFT 0x0 |
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| 833 | #define SMUSBI_ALERT__PD__SHIFT 0x1 |
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| 834 | #define SMUSBI_ALERT__PU__SHIFT 0x2 |
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| 835 | #define SMUSBI_ALERT__SCHMEN__SHIFT 0x3 |
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| 836 | #define SMUSBI_ALERT__S0__SHIFT 0x4 |
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| 837 | #define SMUSBI_ALERT__S1__SHIFT 0x5 |
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| 838 | #define SMUSBI_ALERT__RXEN__SHIFT 0x6 |
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| 839 | #define SMUSBI_ALERT__RXSEL0__SHIFT 0x7 |
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| 840 | #define SMUSBI_ALERT__RXSEL1__SHIFT 0x8 |
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| 841 | #define SMUSBI_ALERT__OE_OVERRIDE__SHIFT 0x10 |
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| 842 | #define SMUSBI_ALERT__OE__SHIFT 0x11 |
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| 843 | #define SMUSBI_ALERT__A_OVERRIDE__SHIFT 0x12 |
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| 844 | #define SMUSBI_ALERT__A__SHIFT 0x13 |
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| 845 | #define SMUSBI_ALERT__Y__SHIFT 0x1f |
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| 846 | #define SMUSBI_ALERT__TXIMPSEL_MASK 0x00000001L |
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| 847 | #define SMUSBI_ALERT__PD_MASK 0x00000002L |
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| 848 | #define SMUSBI_ALERT__PU_MASK 0x00000004L |
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| 849 | #define SMUSBI_ALERT__SCHMEN_MASK 0x00000008L |
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| 850 | #define SMUSBI_ALERT__S0_MASK 0x00000010L |
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| 851 | #define SMUSBI_ALERT__S1_MASK 0x00000020L |
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| 852 | #define SMUSBI_ALERT__RXEN_MASK 0x00000040L |
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| 853 | #define SMUSBI_ALERT__RXSEL0_MASK 0x00000080L |
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| 854 | #define SMUSBI_ALERT__RXSEL1_MASK 0x00000100L |
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| 855 | #define SMUSBI_ALERT__OE_OVERRIDE_MASK 0x00010000L |
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| 856 | #define SMUSBI_ALERT__OE_MASK 0x00020000L |
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| 857 | #define SMUSBI_ALERT__A_OVERRIDE_MASK 0x00040000L |
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| 858 | #define SMUSBI_ALERT__A_MASK 0x00080000L |
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| 859 | #define SMUSBI_ALERT__Y_MASK 0x80000000L |
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| 860 | //THM_TMON0_REMOTE_START |
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| 861 | #define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 |
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| 862 | #define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL |
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| 863 | //THM_TMON0_REMOTE_END |
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| 864 | #define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 |
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| 865 | #define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL |
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| 866 | //THM_TMON1_REMOTE_START |
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| 867 | #define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 |
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| 868 | #define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL |
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| 869 | //THM_TMON1_REMOTE_END |
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| 870 | #define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 |
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| 871 | #define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL |
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| 872 | //THM_TMON2_REMOTE_START |
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| 873 | #define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 |
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| 874 | #define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL |
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| 875 | //THM_TMON2_REMOTE_END |
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| 876 | #define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 |
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| 877 | #define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL |
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| 878 | //THM_TMON3_REMOTE_START |
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| 879 | #define THM_TMON3_REMOTE_START__DATA__SHIFT 0x0 |
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| 880 | #define THM_TMON3_REMOTE_START__DATA_MASK 0xFFFFFFFFL |
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| 881 | //THM_TMON3_REMOTE_END |
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| 882 | #define THM_TMON3_REMOTE_END__DATA__SHIFT 0x0 |
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| 883 | #define THM_TMON3_REMOTE_END__DATA_MASK 0xFFFFFFFFL |
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| 884 | |
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| 885 | #endif |
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| 886 | |
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