1 | /* |
2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _vcn_2_0_0_OFFSET_HEADER |
22 | #define |
23 | |
24 | |
25 | |
26 | // addressBlock: uvd0_jpegnpdec |
27 | // base address: 0x1e200 |
28 | #define mmUVD_JPEG_CNTL 0x0080 |
29 | #define mmUVD_JPEG_CNTL_BASE_IDX 0 |
30 | #define mmUVD_JPEG_RB_BASE 0x0081 |
31 | #define mmUVD_JPEG_RB_BASE_BASE_IDX 0 |
32 | #define mmUVD_JPEG_RB_WPTR 0x0082 |
33 | #define mmUVD_JPEG_RB_WPTR_BASE_IDX 0 |
34 | #define mmUVD_JPEG_RB_RPTR 0x0083 |
35 | #define mmUVD_JPEG_RB_RPTR_BASE_IDX 0 |
36 | #define mmUVD_JPEG_RB_SIZE 0x0084 |
37 | #define mmUVD_JPEG_RB_SIZE_BASE_IDX 0 |
38 | #define mmUVD_JPEG_DEC_SCRATCH0 0x0089 |
39 | #define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 |
40 | #define mmUVD_JPEG_INT_EN 0x008a |
41 | #define mmUVD_JPEG_INT_EN_BASE_IDX 0 |
42 | #define mmUVD_JPEG_INT_STAT 0x008b |
43 | #define mmUVD_JPEG_INT_STAT_BASE_IDX 0 |
44 | #define mmUVD_JPEG_PITCH 0x009f |
45 | #define mmUVD_JPEG_PITCH_BASE_IDX 0 |
46 | #define mmUVD_JPEG_UV_PITCH 0x00a0 |
47 | #define mmUVD_JPEG_UV_PITCH_BASE_IDX 0 |
48 | #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 |
49 | #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 |
50 | #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 |
51 | #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 |
52 | #define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 |
53 | #define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 |
54 | #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 |
55 | #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 |
56 | #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 |
57 | #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 |
58 | #define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 |
59 | #define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 |
60 | #define mmJPEG_DEC_ADDR_MODE 0x00a7 |
61 | #define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0 |
62 | #define mmUVD_JPEG_GPCOM_CMD 0x00a9 |
63 | #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0 |
64 | #define mmUVD_JPEG_GPCOM_DATA0 0x00aa |
65 | #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 |
66 | #define mmUVD_JPEG_GPCOM_DATA1 0x00ab |
67 | #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 |
68 | #define mmUVD_JPEG_SCRATCH1 0x00ae |
69 | #define mmUVD_JPEG_SCRATCH1_BASE_IDX 0 |
70 | #define mmUVD_JPEG_DEC_SOFT_RST 0x00af |
71 | #define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 |
72 | |
73 | |
74 | // addressBlock: uvd0_uvd_jpeg_enc_dec |
75 | // base address: 0x1e300 |
76 | #define mmUVD_JPEG_ENC_INT_EN 0x00c1 |
77 | #define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0 |
78 | #define mmUVD_JPEG_ENC_INT_STATUS 0x00c2 |
79 | #define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 |
80 | #define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 |
81 | #define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 |
82 | #define mmUVD_JPEG_ENC_SCRATCH1 0x00ce |
83 | #define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 |
84 | |
85 | |
86 | // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec |
87 | // base address: 0x1e380 |
88 | #define mmUVD_JPEG_ENC_STATUS 0x00e5 |
89 | #define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0 |
90 | #define mmUVD_JPEG_ENC_PITCH 0x00e6 |
91 | #define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0 |
92 | #define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7 |
93 | #define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 |
94 | #define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 |
95 | #define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 |
96 | #define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 |
97 | #define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 |
98 | #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea |
99 | #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 |
100 | #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb |
101 | #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 |
102 | #define mmJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec |
103 | #define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 |
104 | #define mmJPEG_ENC_ADDR_MODE 0x00ed |
105 | #define mmJPEG_ENC_ADDR_MODE_BASE_IDX 0 |
106 | #define mmUVD_JPEG_ENC_GPCOM_CMD 0x00ee |
107 | #define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 |
108 | #define mmUVD_JPEG_ENC_GPCOM_DATA0 0x00ef |
109 | #define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 |
110 | #define mmUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 |
111 | #define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 |
112 | #define mmUVD_JPEG_ENC_CGC_CNTL 0x00f5 |
113 | #define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 |
114 | #define mmUVD_JPEG_ENC_SCRATCH0 0x00f6 |
115 | #define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 |
116 | #define mmUVD_JPEG_ENC_SOFT_RST 0x00f7 |
117 | #define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 |
118 | |
119 | |
120 | // addressBlock: uvd0_uvd_jrbc_dec |
121 | // base address: 0x1e400 |
122 | #define mmUVD_JRBC_RB_WPTR 0x0100 |
123 | #define mmUVD_JRBC_RB_WPTR_BASE_IDX 0 |
124 | #define mmUVD_JRBC_RB_CNTL 0x0101 |
125 | #define mmUVD_JRBC_RB_CNTL_BASE_IDX 0 |
126 | #define mmUVD_JRBC_IB_SIZE 0x0102 |
127 | #define mmUVD_JRBC_IB_SIZE_BASE_IDX 0 |
128 | #define mmUVD_JRBC_URGENT_CNTL 0x0103 |
129 | #define mmUVD_JRBC_URGENT_CNTL_BASE_IDX 0 |
130 | #define mmUVD_JRBC_RB_REF_DATA 0x0104 |
131 | #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 0 |
132 | #define mmUVD_JRBC_RB_COND_RD_TIMER 0x0105 |
133 | #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 |
134 | #define mmUVD_JRBC_SOFT_RESET 0x0108 |
135 | #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 0 |
136 | #define mmUVD_JRBC_STATUS 0x0109 |
137 | #define mmUVD_JRBC_STATUS_BASE_IDX 0 |
138 | #define mmUVD_JRBC_RB_RPTR 0x010a |
139 | #define mmUVD_JRBC_RB_RPTR_BASE_IDX 0 |
140 | #define mmUVD_JRBC_RB_BUF_STATUS 0x010b |
141 | #define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 |
142 | #define mmUVD_JRBC_IB_BUF_STATUS 0x010c |
143 | #define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 |
144 | #define mmUVD_JRBC_IB_SIZE_UPDATE 0x010d |
145 | #define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 |
146 | #define mmUVD_JRBC_IB_COND_RD_TIMER 0x010e |
147 | #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 |
148 | #define mmUVD_JRBC_IB_REF_DATA 0x010f |
149 | #define mmUVD_JRBC_IB_REF_DATA_BASE_IDX 0 |
150 | #define mmUVD_JPEG_PREEMPT_CMD 0x0110 |
151 | #define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 |
152 | #define mmUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 |
153 | #define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 |
154 | #define mmUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 |
155 | #define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 |
156 | #define mmUVD_JRBC_RB_SIZE 0x0113 |
157 | #define mmUVD_JRBC_RB_SIZE_BASE_IDX 0 |
158 | #define mmUVD_JRBC_SCRATCH0 0x0114 |
159 | #define mmUVD_JRBC_SCRATCH0_BASE_IDX 0 |
160 | |
161 | |
162 | // addressBlock: uvd0_uvd_jrbc_enc_dec |
163 | // base address: 0x1e480 |
164 | #define mmUVD_JRBC_ENC_RB_WPTR 0x0120 |
165 | #define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 |
166 | #define mmUVD_JRBC_ENC_RB_CNTL 0x0121 |
167 | #define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 |
168 | #define mmUVD_JRBC_ENC_IB_SIZE 0x0122 |
169 | #define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 |
170 | #define mmUVD_JRBC_ENC_URGENT_CNTL 0x0123 |
171 | #define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 |
172 | #define mmUVD_JRBC_ENC_RB_REF_DATA 0x0124 |
173 | #define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 |
174 | #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 |
175 | #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 |
176 | #define mmUVD_JRBC_ENC_SOFT_RESET 0x0128 |
177 | #define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 |
178 | #define mmUVD_JRBC_ENC_STATUS 0x0129 |
179 | #define mmUVD_JRBC_ENC_STATUS_BASE_IDX 0 |
180 | #define mmUVD_JRBC_ENC_RB_RPTR 0x012a |
181 | #define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 |
182 | #define mmUVD_JRBC_ENC_RB_BUF_STATUS 0x012b |
183 | #define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 |
184 | #define mmUVD_JRBC_ENC_IB_BUF_STATUS 0x012c |
185 | #define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 |
186 | #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d |
187 | #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 |
188 | #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e |
189 | #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 |
190 | #define mmUVD_JRBC_ENC_IB_REF_DATA 0x012f |
191 | #define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 |
192 | #define mmUVD_JPEG_ENC_PREEMPT_CMD 0x0130 |
193 | #define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 |
194 | #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 |
195 | #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 |
196 | #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 |
197 | #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 |
198 | #define mmUVD_JRBC_ENC_RB_SIZE 0x0133 |
199 | #define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 |
200 | #define mmUVD_JRBC_ENC_SCRATCH0 0x0134 |
201 | #define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 |
202 | |
203 | |
204 | // addressBlock: uvd0_uvd_jmi_dec |
205 | // base address: 0x1e500 |
206 | #define mmUVD_JMI_CTRL 0x0145 |
207 | #define mmUVD_JMI_CTRL_BASE_IDX 0 |
208 | #define mmUVD_LMI_JRBC_CTRL 0x0146 |
209 | #define mmUVD_LMI_JRBC_CTRL_BASE_IDX 0 |
210 | #define mmUVD_LMI_JPEG_CTRL 0x0147 |
211 | #define mmUVD_LMI_JPEG_CTRL_BASE_IDX 0 |
212 | #define mmUVD_JMI_EJRBC_CTRL 0x0148 |
213 | #define mmUVD_JMI_EJRBC_CTRL_BASE_IDX 0 |
214 | #define mmUVD_LMI_EJPEG_CTRL 0x0149 |
215 | #define mmUVD_LMI_EJPEG_CTRL_BASE_IDX 0 |
216 | #define mmUVD_LMI_JRBC_IB_VMID 0x014f |
217 | #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 |
218 | #define mmUVD_LMI_JRBC_RB_VMID 0x0150 |
219 | #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 |
220 | #define mmUVD_LMI_JPEG_VMID 0x0151 |
221 | #define mmUVD_LMI_JPEG_VMID_BASE_IDX 0 |
222 | #define mmUVD_JMI_ENC_JRBC_IB_VMID 0x0152 |
223 | #define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 |
224 | #define mmUVD_JMI_ENC_JRBC_RB_VMID 0x0153 |
225 | #define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 |
226 | #define mmUVD_JMI_ENC_JPEG_VMID 0x0154 |
227 | #define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 |
228 | #define mmUVD_JMI_PERFMON_CTRL 0x015c |
229 | #define mmUVD_JMI_PERFMON_CTRL_BASE_IDX 0 |
230 | #define mmUVD_JMI_PERFMON_COUNT_LO 0x015d |
231 | #define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 |
232 | #define mmUVD_JMI_PERFMON_COUNT_HI 0x015e |
233 | #define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 |
234 | #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 |
235 | #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 |
236 | #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 |
237 | #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 |
238 | #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 |
239 | #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 |
240 | #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 |
241 | #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 |
242 | #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 |
243 | #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 |
244 | #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 |
245 | #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 |
246 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 |
247 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 |
248 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 |
249 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 |
250 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 |
251 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 |
252 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 |
253 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 |
254 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a |
255 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 |
256 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b |
257 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 |
258 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c |
259 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 |
260 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d |
261 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 |
262 | #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e |
263 | #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 |
264 | #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f |
265 | #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 |
266 | #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 |
267 | #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 |
268 | #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 |
269 | #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 |
270 | #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a |
271 | #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 |
272 | #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b |
273 | #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 |
274 | #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c |
275 | #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 |
276 | #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d |
277 | #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 |
278 | #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e |
279 | #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 |
280 | #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f |
281 | #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 |
282 | #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 |
283 | #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 |
284 | #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 |
285 | #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 |
286 | #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 |
287 | #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 |
288 | #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 |
289 | #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 |
290 | #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 |
291 | #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 |
292 | #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 |
293 | #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 |
294 | #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 |
295 | #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 |
296 | #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 |
297 | #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 |
298 | #define mmUVD_LMI_JPEG_PREEMPT_VMID 0x0188 |
299 | #define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 |
300 | #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 |
301 | #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 |
302 | #define mmUVD_LMI_JPEG2_VMID 0x018a |
303 | #define mmUVD_LMI_JPEG2_VMID_BASE_IDX 0 |
304 | #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b |
305 | #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 |
306 | #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c |
307 | #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 |
308 | #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d |
309 | #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 |
310 | #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e |
311 | #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 |
312 | #define mmUVD_LMI_JPEG_CTRL2 0x018f |
313 | #define mmUVD_LMI_JPEG_CTRL2_BASE_IDX 0 |
314 | #define mmUVD_JMI_DEC_SWAP_CNTL 0x0190 |
315 | #define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 |
316 | #define mmUVD_JMI_ENC_SWAP_CNTL 0x0191 |
317 | #define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 |
318 | #define mmUVD_JMI_CNTL 0x0192 |
319 | #define mmUVD_JMI_CNTL_BASE_IDX 0 |
320 | #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a |
321 | #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 |
322 | #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b |
323 | #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 |
324 | #define mmUVD_JMI_DEC_SWAP_CNTL2 0x019c |
325 | #define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 |
326 | |
327 | |
328 | // addressBlock: uvd0_uvd_jpeg_common_dec |
329 | // base address: 0x1e700 |
330 | #define mmJPEG_SOFT_RESET_STATUS 0x01c0 |
331 | #define mmJPEG_SOFT_RESET_STATUS_BASE_IDX 0 |
332 | #define mmJPEG_SYS_INT_EN 0x01c1 |
333 | #define mmJPEG_SYS_INT_EN_BASE_IDX 0 |
334 | #define mmJPEG_SYS_INT_STATUS 0x01c2 |
335 | #define mmJPEG_SYS_INT_STATUS_BASE_IDX 0 |
336 | #define mmJPEG_SYS_INT_ACK 0x01c3 |
337 | #define mmJPEG_SYS_INT_ACK_BASE_IDX 0 |
338 | #define mmJPEG_MASTINT_EN 0x01c8 |
339 | #define mmJPEG_MASTINT_EN_BASE_IDX 0 |
340 | #define mmJPEG_IH_CTRL 0x01c9 |
341 | #define mmJPEG_IH_CTRL_BASE_IDX 0 |
342 | #define mmJRBBM_ARB_CTRL 0x01cb |
343 | #define mmJRBBM_ARB_CTRL_BASE_IDX 0 |
344 | |
345 | |
346 | // addressBlock: uvd0_uvd_jpeg_common_sclk_dec |
347 | // base address: 0x1e780 |
348 | #define mmJPEG_CGC_GATE 0x01e0 |
349 | #define mmJPEG_CGC_GATE_BASE_IDX 0 |
350 | #define mmJPEG_CGC_CTRL 0x01e1 |
351 | #define mmJPEG_CGC_CTRL_BASE_IDX 0 |
352 | #define mmJPEG_CGC_STATUS 0x01e2 |
353 | #define mmJPEG_CGC_STATUS_BASE_IDX 0 |
354 | #define mmJPEG_COMN_CGC_MEM_CTRL 0x01e3 |
355 | #define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 |
356 | #define mmJPEG_DEC_CGC_MEM_CTRL 0x01e4 |
357 | #define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 |
358 | #define mmJPEG2_DEC_CGC_MEM_CTRL 0x01e5 |
359 | #define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 |
360 | #define mmJPEG_ENC_CGC_MEM_CTRL 0x01e6 |
361 | #define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 |
362 | #define mmJPEG_SOFT_RESET2 0x01e7 |
363 | #define mmJPEG_SOFT_RESET2_BASE_IDX 0 |
364 | #define mmJPEG_PERF_BANK_CONF 0x01e8 |
365 | #define mmJPEG_PERF_BANK_CONF_BASE_IDX 0 |
366 | #define mmJPEG_PERF_BANK_EVENT_SEL 0x01e9 |
367 | #define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 |
368 | #define mmJPEG_PERF_BANK_COUNT0 0x01ea |
369 | #define mmJPEG_PERF_BANK_COUNT0_BASE_IDX 0 |
370 | #define mmJPEG_PERF_BANK_COUNT1 0x01eb |
371 | #define mmJPEG_PERF_BANK_COUNT1_BASE_IDX 0 |
372 | #define mmJPEG_PERF_BANK_COUNT2 0x01ec |
373 | #define mmJPEG_PERF_BANK_COUNT2_BASE_IDX 0 |
374 | #define mmJPEG_PERF_BANK_COUNT3 0x01ed |
375 | #define mmJPEG_PERF_BANK_COUNT3_BASE_IDX 0 |
376 | |
377 | |
378 | // addressBlock: uvd0_uvd_pg_dec |
379 | // base address: 0x1f800 |
380 | #define mmUVD_PGFSM_CONFIG 0x0000 |
381 | #define mmUVD_PGFSM_CONFIG_BASE_IDX 1 |
382 | #define mmUVD_PGFSM_STATUS 0x0001 |
383 | #define mmUVD_PGFSM_STATUS_BASE_IDX 1 |
384 | #define mmUVD_POWER_STATUS 0x0004 |
385 | #define mmUVD_POWER_STATUS_BASE_IDX 1 |
386 | #define mmUVD_PG_IND_INDEX 0x0005 |
387 | #define mmUVD_PG_IND_INDEX_BASE_IDX 1 |
388 | #define mmUVD_PG_IND_DATA 0x0006 |
389 | #define mmUVD_PG_IND_DATA_BASE_IDX 1 |
390 | #define mmCC_UVD_HARVESTING 0x0007 |
391 | #define mmCC_UVD_HARVESTING_BASE_IDX 1 |
392 | #define mmUVD_JPEG_POWER_STATUS 0x000a |
393 | #define mmUVD_JPEG_POWER_STATUS_BASE_IDX 1 |
394 | #define mmUVD_DPG_LMA_CTL 0x0011 |
395 | #define mmUVD_DPG_LMA_CTL_BASE_IDX 1 |
396 | #define mmUVD_DPG_LMA_DATA 0x0012 |
397 | #define mmUVD_DPG_LMA_DATA_BASE_IDX 1 |
398 | #define mmUVD_DPG_LMA_MASK 0x0013 |
399 | #define mmUVD_DPG_LMA_MASK_BASE_IDX 1 |
400 | #define mmUVD_DPG_PAUSE 0x0014 |
401 | #define mmUVD_DPG_PAUSE_BASE_IDX 1 |
402 | #define mmUVD_SCRATCH1 0x0015 |
403 | #define mmUVD_SCRATCH1_BASE_IDX 1 |
404 | #define mmUVD_SCRATCH2 0x0016 |
405 | #define mmUVD_SCRATCH2_BASE_IDX 1 |
406 | #define mmUVD_SCRATCH3 0x0017 |
407 | #define mmUVD_SCRATCH3_BASE_IDX 1 |
408 | #define mmUVD_SCRATCH4 0x0018 |
409 | #define mmUVD_SCRATCH4_BASE_IDX 1 |
410 | #define mmUVD_SCRATCH5 0x0019 |
411 | #define mmUVD_SCRATCH5_BASE_IDX 1 |
412 | #define mmUVD_SCRATCH6 0x001a |
413 | #define mmUVD_SCRATCH6_BASE_IDX 1 |
414 | #define mmUVD_SCRATCH7 0x001b |
415 | #define mmUVD_SCRATCH7_BASE_IDX 1 |
416 | #define mmUVD_SCRATCH8 0x001c |
417 | #define mmUVD_SCRATCH8_BASE_IDX 1 |
418 | #define mmUVD_SCRATCH9 0x001d |
419 | #define mmUVD_SCRATCH9_BASE_IDX 1 |
420 | #define mmUVD_SCRATCH10 0x001e |
421 | #define mmUVD_SCRATCH10_BASE_IDX 1 |
422 | #define mmUVD_SCRATCH11 0x001f |
423 | #define mmUVD_SCRATCH11_BASE_IDX 1 |
424 | #define mmUVD_SCRATCH12 0x0020 |
425 | #define mmUVD_SCRATCH12_BASE_IDX 1 |
426 | #define mmUVD_SCRATCH13 0x0021 |
427 | #define mmUVD_SCRATCH13_BASE_IDX 1 |
428 | #define mmUVD_SCRATCH14 0x0022 |
429 | #define mmUVD_SCRATCH14_BASE_IDX 1 |
430 | #define mmUVD_FREE_COUNTER_REG 0x0024 |
431 | #define mmUVD_FREE_COUNTER_REG_BASE_IDX 1 |
432 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 |
433 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
434 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 |
435 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
436 | #define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 |
437 | #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
438 | #define mmUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 |
439 | #define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 |
440 | #define mmUVD_PF_STATUS 0x0039 |
441 | #define mmUVD_PF_STATUS_BASE_IDX 1 |
442 | #define mmUVD_DPG_CLK_EN_VCPU_REPORT 0x003c |
443 | #define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 |
444 | #define mmUVD_GFX8_ADDR_CONFIG 0x0049 |
445 | #define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 |
446 | #define mmUVD_GFX10_ADDR_CONFIG 0x004a |
447 | #define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 |
448 | #define mmUVD_GPCNT2_CNTL 0x004b |
449 | #define mmUVD_GPCNT2_CNTL_BASE_IDX 1 |
450 | #define mmUVD_GPCNT2_TARGET_LOWER 0x004c |
451 | #define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 |
452 | #define mmUVD_GPCNT2_STATUS_LOWER 0x004d |
453 | #define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 |
454 | #define mmUVD_GPCNT2_TARGET_UPPER 0x004e |
455 | #define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 |
456 | #define mmUVD_GPCNT2_STATUS_UPPER 0x004f |
457 | #define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 |
458 | #define mmUVD_GPCNT3_CNTL 0x0050 |
459 | #define mmUVD_GPCNT3_CNTL_BASE_IDX 1 |
460 | #define mmUVD_GPCNT3_TARGET_LOWER 0x0051 |
461 | #define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 |
462 | #define mmUVD_GPCNT3_STATUS_LOWER 0x0052 |
463 | #define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 |
464 | #define mmUVD_GPCNT3_TARGET_UPPER 0x0053 |
465 | #define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 |
466 | #define mmUVD_GPCNT3_STATUS_UPPER 0x0054 |
467 | #define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 |
468 | #define mmUVD_TSC_LOWER 0x0057 |
469 | #define mmUVD_TSC_LOWER_BASE_IDX 1 |
470 | #define mmUVD_TSC_UPPER 0x0058 |
471 | #define mmUVD_TSC_UPPER_BASE_IDX 1 |
472 | |
473 | |
474 | // addressBlock: uvd0_uvddec |
475 | // base address: 0x1ff00 |
476 | #define mmUVD_SEMA_CNTL 0x01c0 |
477 | #define mmUVD_SEMA_CNTL_BASE_IDX 1 |
478 | #define mmUVD_RB_RPTR3 0x01db |
479 | #define mmUVD_RB_RPTR3_BASE_IDX 1 |
480 | #define mmUVD_RB_WPTR3 0x01dc |
481 | #define mmUVD_RB_WPTR3_BASE_IDX 1 |
482 | #define mmUVD_RB_BASE_LO3 0x01dd |
483 | #define mmUVD_RB_BASE_LO3_BASE_IDX 1 |
484 | #define mmUVD_RB_BASE_HI3 0x01de |
485 | #define mmUVD_RB_BASE_HI3_BASE_IDX 1 |
486 | #define mmUVD_RB_SIZE3 0x01df |
487 | #define mmUVD_RB_SIZE3_BASE_IDX 1 |
488 | #define mmUVD_RB_ARB_CTRL 0x01e0 |
489 | #define mmUVD_RB_ARB_CTRL_BASE_IDX 1 |
490 | #define mmUVD_LMI_LAT_CTRL 0x01e2 |
491 | #define mmUVD_LMI_LAT_CTRL_BASE_IDX 1 |
492 | #define mmUVD_LMI_LAT_CNTR 0x01e3 |
493 | #define mmUVD_LMI_LAT_CNTR_BASE_IDX 1 |
494 | #define mmUVD_LMI_AVG_LAT_CNTR 0x01e4 |
495 | #define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 |
496 | #define mmUVD_SOFT_RESET2 0x01e6 |
497 | #define mmUVD_SOFT_RESET2_BASE_IDX 1 |
498 | #define mmUVD_LMI_SPH 0x01e7 |
499 | #define mmUVD_LMI_SPH_BASE_IDX 1 |
500 | #define mmUVD_CTX_INDEX 0x01e8 |
501 | #define mmUVD_CTX_INDEX_BASE_IDX 1 |
502 | #define mmUVD_CTX_DATA 0x01e9 |
503 | #define mmUVD_CTX_DATA_BASE_IDX 1 |
504 | #define mmUVD_CGC_GATE 0x01ea |
505 | #define mmUVD_CGC_GATE_BASE_IDX 1 |
506 | #define mmUVD_CGC_STATUS 0x01eb |
507 | #define mmUVD_CGC_STATUS_BASE_IDX 1 |
508 | #define mmUVD_CGC_CTRL 0x01ec |
509 | #define mmUVD_CGC_CTRL_BASE_IDX 1 |
510 | #define mmUVD_CGC_UDEC_STATUS 0x01ed |
511 | #define mmUVD_CGC_UDEC_STATUS_BASE_IDX 1 |
512 | #define mmUVD_CXW_WR_INT_ID 0x01ee |
513 | #define mmUVD_CXW_WR_INT_ID_BASE_IDX 1 |
514 | #define mmUVD_CXW_WR_INT_CTX_ID 0x01ef |
515 | #define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 |
516 | #define mmUVD_VCPU_INT_ROUTE 0x01f3 |
517 | #define mmUVD_VCPU_INT_ROUTE_BASE_IDX 1 |
518 | #define mmUVD_GP_SCRATCH0 0x01f4 |
519 | #define mmUVD_GP_SCRATCH0_BASE_IDX 1 |
520 | #define mmUVD_GP_SCRATCH1 0x01f5 |
521 | #define mmUVD_GP_SCRATCH1_BASE_IDX 1 |
522 | #define mmUVD_GP_SCRATCH2 0x01f6 |
523 | #define mmUVD_GP_SCRATCH2_BASE_IDX 1 |
524 | #define mmUVD_GP_SCRATCH3 0x01f7 |
525 | #define mmUVD_GP_SCRATCH3_BASE_IDX 1 |
526 | #define mmUVD_GP_SCRATCH4 0x01f8 |
527 | #define mmUVD_GP_SCRATCH4_BASE_IDX 1 |
528 | #define mmUVD_GP_SCRATCH5 0x01f9 |
529 | #define mmUVD_GP_SCRATCH5_BASE_IDX 1 |
530 | #define mmUVD_GP_SCRATCH6 0x01fa |
531 | #define mmUVD_GP_SCRATCH6_BASE_IDX 1 |
532 | #define mmUVD_GP_SCRATCH7 0x01fb |
533 | #define mmUVD_GP_SCRATCH7_BASE_IDX 1 |
534 | #define mmUVD_LMI_VCPU_CACHE_VMID 0x01fc |
535 | #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 |
536 | #define mmUVD_LMI_CTRL2 0x01fd |
537 | #define mmUVD_LMI_CTRL2_BASE_IDX 1 |
538 | #define mmUVD_MASTINT_EN 0x0200 |
539 | #define mmUVD_MASTINT_EN_BASE_IDX 1 |
540 | #define mmUVD_SYS_INT_EN 0x0201 |
541 | #define mmUVD_SYS_INT_EN_BASE_IDX 1 |
542 | #define mmUVD_SYS_INT_STATUS 0x0202 |
543 | #define mmUVD_SYS_INT_STATUS_BASE_IDX 1 |
544 | #define mmUVD_SYS_INT_ACK 0x0203 |
545 | #define mmUVD_SYS_INT_ACK_BASE_IDX 1 |
546 | #define mmUVD_VCPU_INT_EN 0x0204 |
547 | #define mmUVD_VCPU_INT_EN_BASE_IDX 1 |
548 | #define mmUVD_VCPU_INT_ACK 0x0206 |
549 | #define mmUVD_VCPU_INT_ACK_BASE_IDX 1 |
550 | #define mmUVD_TOP_CTRL 0x0207 |
551 | #define mmUVD_TOP_CTRL_BASE_IDX 1 |
552 | #define mmUVD_ENC_VCPU_INT_EN 0x021f |
553 | #define mmUVD_ENC_VCPU_INT_EN_BASE_IDX 1 |
554 | #define mmUVD_ENC_VCPU_INT_ACK 0x0221 |
555 | #define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 |
556 | #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x0222 |
557 | #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 |
558 | #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0x0223 |
559 | #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 |
560 | #define mmUVD_LMI_URGENT_CTRL 0x0224 |
561 | #define mmUVD_LMI_URGENT_CTRL_BASE_IDX 1 |
562 | #define mmUVD_LMI_CTRL 0x0226 |
563 | #define mmUVD_LMI_CTRL_BASE_IDX 1 |
564 | #define mmUVD_LMI_STATUS 0x0227 |
565 | #define mmUVD_LMI_STATUS_BASE_IDX 1 |
566 | #define mmUVD_LMI_VM_CTRL 0x0228 |
567 | #define mmUVD_LMI_VM_CTRL_BASE_IDX 1 |
568 | #define mmUVD_LMI_PERFMON_CTRL 0x022a |
569 | #define mmUVD_LMI_PERFMON_CTRL_BASE_IDX 1 |
570 | #define mmUVD_LMI_PERFMON_COUNT_LO 0x022b |
571 | #define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 |
572 | #define mmUVD_LMI_PERFMON_COUNT_HI 0x022c |
573 | #define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 |
574 | #define mmUVD_LMI_SWAP_CNTL 0x022d |
575 | #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 |
576 | #define mmUVD_UDEC_ADR 0x022e |
577 | #define mmUVD_UDEC_ADR_BASE_IDX 1 |
578 | #define mmUVD_MP_SWAP_CNTL 0x022f |
579 | #define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 |
580 | #define mmUVD_MPC_LUMA_SRCH 0x0231 |
581 | #define mmUVD_MPC_LUMA_SRCH_BASE_IDX 1 |
582 | #define mmUVD_MPC_LUMA_HIT 0x0232 |
583 | #define mmUVD_MPC_LUMA_HIT_BASE_IDX 1 |
584 | #define mmUVD_MPC_LUMA_HITPEND 0x0233 |
585 | #define mmUVD_MPC_LUMA_HITPEND_BASE_IDX 1 |
586 | #define mmUVD_MPC_CHROMA_SRCH 0x0234 |
587 | #define mmUVD_MPC_CHROMA_SRCH_BASE_IDX 1 |
588 | #define mmUVD_MPC_CHROMA_HIT 0x0235 |
589 | #define mmUVD_MPC_CHROMA_HIT_BASE_IDX 1 |
590 | #define mmUVD_MPC_CHROMA_HITPEND 0x0236 |
591 | #define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 |
592 | #define mmUVD_MPC_CNTL 0x0237 |
593 | #define mmUVD_MPC_CNTL_BASE_IDX 1 |
594 | #define mmUVD_MPC_PITCH 0x0238 |
595 | #define mmUVD_MPC_PITCH_BASE_IDX 1 |
596 | #define mmUVD_MPC_SET_MUXA0 0x0239 |
597 | #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 |
598 | #define mmUVD_MPC_SET_MUXA1 0x023a |
599 | #define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 |
600 | #define mmUVD_MPC_SET_MUXB0 0x023b |
601 | #define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 |
602 | #define mmUVD_MPC_SET_MUXB1 0x023c |
603 | #define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 |
604 | #define mmUVD_MPC_SET_MUX 0x023d |
605 | #define mmUVD_MPC_SET_MUX_BASE_IDX 1 |
606 | #define mmUVD_MPC_SET_ALU 0x023e |
607 | #define mmUVD_MPC_SET_ALU_BASE_IDX 1 |
608 | #define mmUVD_GPCOM_SYS_CMD 0x023f |
609 | #define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 |
610 | #define mmUVD_GPCOM_SYS_DATA0 0x0240 |
611 | #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 |
612 | #define mmUVD_GPCOM_SYS_DATA1 0x0241 |
613 | #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 |
614 | #define mmUVD_VCPU_CACHE_OFFSET0 0x0242 |
615 | #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
616 | #define mmUVD_VCPU_CACHE_SIZE0 0x0243 |
617 | #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 |
618 | #define mmUVD_VCPU_CACHE_OFFSET1 0x0244 |
619 | #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 |
620 | #define mmUVD_VCPU_CACHE_SIZE1 0x0245 |
621 | #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 |
622 | #define mmUVD_VCPU_CACHE_OFFSET2 0x0246 |
623 | #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 |
624 | #define mmUVD_VCPU_CACHE_SIZE2 0x0247 |
625 | #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 |
626 | #define mmUVD_VCPU_CACHE_OFFSET3 0x0248 |
627 | #define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 |
628 | #define mmUVD_VCPU_CACHE_SIZE3 0x0249 |
629 | #define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 |
630 | #define mmUVD_VCPU_CACHE_OFFSET4 0x024a |
631 | #define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 |
632 | #define mmUVD_VCPU_CACHE_SIZE4 0x024b |
633 | #define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 |
634 | #define mmUVD_VCPU_CACHE_OFFSET5 0x024c |
635 | #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 |
636 | #define mmUVD_VCPU_CACHE_SIZE5 0x024d |
637 | #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 |
638 | #define mmUVD_VCPU_CACHE_OFFSET6 0x024e |
639 | #define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 |
640 | #define mmUVD_VCPU_CACHE_SIZE6 0x024f |
641 | #define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 |
642 | #define mmUVD_VCPU_CACHE_OFFSET7 0x0250 |
643 | #define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 |
644 | #define mmUVD_VCPU_CACHE_SIZE7 0x0251 |
645 | #define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 |
646 | #define mmUVD_VCPU_CACHE_OFFSET8 0x0252 |
647 | #define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 |
648 | #define mmUVD_VCPU_CACHE_SIZE8 0x0253 |
649 | #define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 |
650 | #define mmUVD_VCPU_NONCACHE_OFFSET0 0x0254 |
651 | #define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 |
652 | #define mmUVD_VCPU_NONCACHE_SIZE0 0x0255 |
653 | #define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 |
654 | #define mmUVD_VCPU_NONCACHE_OFFSET1 0x0256 |
655 | #define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 |
656 | #define mmUVD_VCPU_NONCACHE_SIZE1 0x0257 |
657 | #define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 |
658 | #define mmUVD_VCPU_CNTL 0x0258 |
659 | #define mmUVD_VCPU_CNTL_BASE_IDX 1 |
660 | #define mmUVD_VCPU_PRID 0x0259 |
661 | #define mmUVD_VCPU_PRID_BASE_IDX 1 |
662 | #define mmUVD_VCPU_TRCE 0x025a |
663 | #define mmUVD_VCPU_TRCE_BASE_IDX 1 |
664 | #define mmUVD_VCPU_TRCE_RD 0x025b |
665 | #define mmUVD_VCPU_TRCE_RD_BASE_IDX 1 |
666 | #define mmUVD_MPC_PERF0 0x025c |
667 | #define mmUVD_MPC_PERF0_BASE_IDX 1 |
668 | #define mmUVD_MPC_PERF1 0x025d |
669 | #define mmUVD_MPC_PERF1_BASE_IDX 1 |
670 | #define mmUVD_CXW_WR 0x025f |
671 | #define mmUVD_CXW_WR_BASE_IDX 1 |
672 | #define mmUVD_SOFT_RESET 0x0260 |
673 | #define mmUVD_SOFT_RESET_BASE_IDX 1 |
674 | #define mmUVD_LMI_RBC_IB_VMID 0x0261 |
675 | #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 |
676 | #define mmUVD_RBC_IB_SIZE 0x0262 |
677 | #define mmUVD_RBC_IB_SIZE_BASE_IDX 1 |
678 | #define mmUVD_LMI_RBC_RB_VMID 0x0263 |
679 | #define mmUVD_LMI_RBC_RB_VMID_BASE_IDX 1 |
680 | #define mmUVD_RBC_RB_RPTR 0x0264 |
681 | #define mmUVD_RBC_RB_RPTR_BASE_IDX 1 |
682 | #define mmUVD_RBC_RB_WPTR 0x0265 |
683 | #define mmUVD_RBC_RB_WPTR_BASE_IDX 1 |
684 | #define mmUVD_RBC_RB_WPTR_CNTL 0x0266 |
685 | #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 |
686 | #define mmUVD_RBC_READ_REQ_URGENT_CNTL 0x0267 |
687 | #define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 |
688 | #define mmUVD_RBC_WPTR_STATUS 0x0268 |
689 | #define mmUVD_RBC_WPTR_STATUS_BASE_IDX 1 |
690 | #define mmUVD_RBC_RB_CNTL 0x0269 |
691 | #define mmUVD_RBC_RB_CNTL_BASE_IDX 1 |
692 | #define mmUVD_RBC_RB_RPTR_ADDR 0x026a |
693 | #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 |
694 | #define mmUVD_JOB_START 0x026d |
695 | #define mmUVD_JOB_START_BASE_IDX 1 |
696 | #define mmUVD_JOB_DONE 0x026e |
697 | #define mmUVD_JOB_DONE_BASE_IDX 1 |
698 | #define mmUVD_STATUS 0x026f |
699 | #define mmUVD_STATUS_BASE_IDX 1 |
700 | #define mmUVD_SEMA_TIMEOUT_STATUS 0x0270 |
701 | #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 |
702 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x0271 |
703 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 |
704 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x0272 |
705 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 |
706 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x0273 |
707 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 |
708 | #define mmUVD_CXW_EN 0x0274 |
709 | #define mmUVD_CXW_EN_BASE_IDX 1 |
710 | #define mmUVD_CXW_SE 0x0275 |
711 | #define mmUVD_CXW_SE_BASE_IDX 1 |
712 | #define mmUVD_CXW_FINISHED 0x0276 |
713 | #define mmUVD_CXW_FINISHED_BASE_IDX 1 |
714 | #define mmUVD_CXW_SHIFT_FINISHED 0x0277 |
715 | #define mmUVD_CXW_SHIFT_FINISHED_BASE_IDX 1 |
716 | #define mmUVD_CXW_START 0x0278 |
717 | #define mmUVD_CXW_START_BASE_IDX 1 |
718 | #define mmUVD_CXW_BLOCK_STATUS 0x0279 |
719 | #define mmUVD_CXW_BLOCK_STATUS_BASE_IDX 1 |
720 | #define mmUVD_STOP_CONTEXT 0x027a |
721 | #define mmUVD_STOP_CONTEXT_BASE_IDX 1 |
722 | #define mmUVD_CXW_SAVE_AREA_ADDR 0x027b |
723 | #define mmUVD_CXW_SAVE_AREA_ADDR_BASE_IDX 1 |
724 | #define mmUVD_CBUF_ID 0x027c |
725 | #define mmUVD_CBUF_ID_BASE_IDX 1 |
726 | #define mmUVD_CONTEXT_ID 0x027d |
727 | #define mmUVD_CONTEXT_ID_BASE_IDX 1 |
728 | #define mmUVD_CXW_SAVE_AREA_SIZE 0x027e |
729 | #define mmUVD_CXW_SAVE_AREA_SIZE_BASE_IDX 1 |
730 | #define mmUVD_CONTEXT_ID2 0x027f |
731 | #define mmUVD_CONTEXT_ID2_BASE_IDX 1 |
732 | #define mmUVD_CXW_CNTL 0x0280 |
733 | #define mmUVD_CXW_CNTL_BASE_IDX 1 |
734 | #define mmUVD_CXW_EVENT 0x0281 |
735 | #define mmUVD_CXW_EVENT_BASE_IDX 1 |
736 | #define mmUVD_CXW_SCAN_AREA_OFFSET 0x0282 |
737 | #define mmUVD_CXW_SCAN_AREA_OFFSET_BASE_IDX 1 |
738 | #define mmUVD_CXW_SHIFT_CNTL 0x0283 |
739 | #define mmUVD_CXW_SHIFT_CNTL_BASE_IDX 1 |
740 | #define mmUVD_RBC_CAM_EN 0x0286 |
741 | #define mmUVD_RBC_CAM_EN_BASE_IDX 1 |
742 | #define mmUVD_RBC_CAM_INDEX 0x0287 |
743 | #define mmUVD_RBC_CAM_INDEX_BASE_IDX 1 |
744 | #define mmUVD_RBC_CAM_DATA 0x0288 |
745 | #define mmUVD_RBC_CAM_DATA_BASE_IDX 1 |
746 | #define mmUVD_RBC_VCPU_ACCESS 0x0289 |
747 | #define mmUVD_RBC_VCPU_ACCESS_BASE_IDX 1 |
748 | #define mmUVD_CXW_INT_ID 0x0293 |
749 | #define mmUVD_CXW_INT_ID_BASE_IDX 1 |
750 | #define mmUVD_LMI_CRC0 0x0294 |
751 | #define mmUVD_LMI_CRC0_BASE_IDX 1 |
752 | #define mmUVD_LMI_CRC1 0x0295 |
753 | #define mmUVD_LMI_CRC1_BASE_IDX 1 |
754 | #define mmUVD_LMI_CRC2 0x0296 |
755 | #define mmUVD_LMI_CRC2_BASE_IDX 1 |
756 | #define mmUVD_LMI_CRC3 0x0297 |
757 | #define mmUVD_LMI_CRC3_BASE_IDX 1 |
758 | #define mmUVD_RBC_WPTR_POLL_CNTL 0x0298 |
759 | #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 |
760 | #define mmUVD_RBC_WPTR_POLL_ADDR 0x0299 |
761 | #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 |
762 | #define mmUVD_RB_BASE_LO4 0x029f |
763 | #define mmUVD_RB_BASE_LO4_BASE_IDX 1 |
764 | #define mmUVD_RB_BASE_HI4 0x02a0 |
765 | #define mmUVD_RB_BASE_HI4_BASE_IDX 1 |
766 | #define mmUVD_RB_SIZE4 0x02a1 |
767 | #define mmUVD_RB_SIZE4_BASE_IDX 1 |
768 | #define mmUVD_RB_RPTR4 0x02a2 |
769 | #define mmUVD_RB_RPTR4_BASE_IDX 1 |
770 | #define mmUVD_LMI_MC_CREDITS 0x02a3 |
771 | #define mmUVD_LMI_MC_CREDITS_BASE_IDX 1 |
772 | #define mmUVD_RBC_BUF_STATUS 0x02b0 |
773 | #define mmUVD_RBC_BUF_STATUS_BASE_IDX 1 |
774 | #define mmUVD_RBC_IB_SIZE_UPDATE 0x02b1 |
775 | #define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 |
776 | #define mmUVD_RBC_BDM_PRE 0x02b2 |
777 | #define mmUVD_RBC_BDM_PRE_BASE_IDX 1 |
778 | #define mmCG_TIMESTAMP_LOW 0x02b5 |
779 | #define mmCG_TIMESTAMP_LOW_BASE_IDX 1 |
780 | #define mmCG_TIMESTAMP_HIGH 0x02b6 |
781 | #define mmCG_TIMESTAMP_HIGH_BASE_IDX 1 |
782 | #define mmUVD_UMC_UVD_CTL_CMD 0x02b7 |
783 | #define mmUVD_UMC_UVD_CTL_CMD_BASE_IDX 1 |
784 | #define mmUVD_UMC_UVD_BLOCK_REQ 0x02b8 |
785 | #define mmUVD_UMC_UVD_BLOCK_REQ_BASE_IDX 1 |
786 | #define mmUVD_RBC_CXW_RELEASE 0x02b9 |
787 | #define mmUVD_RBC_CXW_RELEASE_BASE_IDX 1 |
788 | #define mmUVD_YBASE 0x02ba |
789 | #define mmUVD_YBASE_BASE_IDX 1 |
790 | #define mmUVD_UVBASE 0x02bb |
791 | #define mmUVD_UVBASE_BASE_IDX 1 |
792 | #define mmUVD_PITCH 0x02bc |
793 | #define mmUVD_PITCH_BASE_IDX 1 |
794 | #define mmUVD_WIDTH 0x02bd |
795 | #define mmUVD_WIDTH_BASE_IDX 1 |
796 | #define mmUVD_HEIGHT 0x02be |
797 | #define mmUVD_HEIGHT_BASE_IDX 1 |
798 | #define mmUVD_PICCOUNT 0x02bf |
799 | #define mmUVD_PICCOUNT_BASE_IDX 1 |
800 | |
801 | |
802 | // addressBlock: uvd0_uvdnpdec |
803 | // base address: 0x20700 |
804 | #define mmUVD_SEMA_ADDR_LOW 0x0580 |
805 | #define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 |
806 | #define mmUVD_SEMA_ADDR_HIGH 0x0581 |
807 | #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 |
808 | #define mmUVD_SEMA_CMD 0x0582 |
809 | #define mmUVD_SEMA_CMD_BASE_IDX 1 |
810 | #define mmUVD_GPCOM_VCPU_CMD 0x0583 |
811 | #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 |
812 | #define mmUVD_GPCOM_VCPU_DATA0 0x0584 |
813 | #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 |
814 | #define mmUVD_GPCOM_VCPU_DATA1 0x0585 |
815 | #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 |
816 | #define mmUVD_ENGINE_CNTL 0x0586 |
817 | #define mmUVD_ENGINE_CNTL_BASE_IDX 1 |
818 | #define mmUVD_SUVD_CGC_GATE 0x05a4 |
819 | #define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 |
820 | #define mmUVD_SUVD_CGC_STATUS 0x05a5 |
821 | #define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 |
822 | #define mmUVD_SUVD_CGC_CTRL 0x05a6 |
823 | #define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 |
824 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x05ac |
825 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 |
826 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x05ad |
827 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 |
828 | #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x05ae |
829 | #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 |
830 | #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x05af |
831 | #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 |
832 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x05b0 |
833 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 |
834 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x05b1 |
835 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 |
836 | #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x05b2 |
837 | #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 |
838 | #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x05b3 |
839 | #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 |
840 | #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x05b4 |
841 | #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 |
842 | #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x05b5 |
843 | #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 |
844 | #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x05b6 |
845 | #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 |
846 | #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x05b7 |
847 | #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 |
848 | #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x05b8 |
849 | #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 |
850 | #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x05b9 |
851 | #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 |
852 | #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x05ba |
853 | #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 |
854 | #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x05bb |
855 | #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 |
856 | #define mmUVD_SCRATCH_NP 0x05bc |
857 | #define mmUVD_SCRATCH_NP_BASE_IDX 1 |
858 | #define mmUVD_NO_OP 0x05bf |
859 | #define mmUVD_NO_OP_BASE_IDX 1 |
860 | #define mmMDM_DMA_CMD 0x05c0 |
861 | #define mmMDM_DMA_CMD_BASE_IDX 1 |
862 | #define mmMDM_DMA_STATUS 0x05c1 |
863 | #define mmMDM_DMA_STATUS_BASE_IDX 1 |
864 | #define mmMDM_DMA_CTL 0x05c2 |
865 | #define mmMDM_DMA_CTL_BASE_IDX 1 |
866 | #define mmMDM_ENC_PIPE_BUSY 0x05c3 |
867 | #define mmMDM_ENC_PIPE_BUSY_BASE_IDX 1 |
868 | #define mmMDM_WIG_PIPE_BUSY 0x05c5 |
869 | #define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1 |
870 | #define mmUVD_VERSION 0x05c9 |
871 | #define mmUVD_VERSION_BASE_IDX 1 |
872 | #define mmUVD_GP_SCRATCH8 0x05ca |
873 | #define mmUVD_GP_SCRATCH8_BASE_IDX 1 |
874 | #define mmUVD_GP_SCRATCH9 0x05cb |
875 | #define mmUVD_GP_SCRATCH9_BASE_IDX 1 |
876 | #define mmUVD_GP_SCRATCH10 0x05cc |
877 | #define mmUVD_GP_SCRATCH10_BASE_IDX 1 |
878 | #define mmUVD_GP_SCRATCH11 0x05cd |
879 | #define mmUVD_GP_SCRATCH11_BASE_IDX 1 |
880 | #define mmUVD_GP_SCRATCH12 0x05ce |
881 | #define mmUVD_GP_SCRATCH12_BASE_IDX 1 |
882 | #define mmUVD_GP_SCRATCH13 0x05cf |
883 | #define mmUVD_GP_SCRATCH13_BASE_IDX 1 |
884 | #define mmUVD_GP_SCRATCH14 0x05d0 |
885 | #define mmUVD_GP_SCRATCH14_BASE_IDX 1 |
886 | #define mmUVD_GP_SCRATCH15 0x05d1 |
887 | #define mmUVD_GP_SCRATCH15_BASE_IDX 1 |
888 | #define mmUVD_GP_SCRATCH16 0x05d2 |
889 | #define mmUVD_GP_SCRATCH16_BASE_IDX 1 |
890 | #define mmUVD_GP_SCRATCH17 0x05d3 |
891 | #define mmUVD_GP_SCRATCH17_BASE_IDX 1 |
892 | #define mmUVD_GP_SCRATCH18 0x05d4 |
893 | #define mmUVD_GP_SCRATCH18_BASE_IDX 1 |
894 | #define mmUVD_GP_SCRATCH19 0x05d5 |
895 | #define mmUVD_GP_SCRATCH19_BASE_IDX 1 |
896 | #define mmUVD_GP_SCRATCH20 0x05d6 |
897 | #define mmUVD_GP_SCRATCH20_BASE_IDX 1 |
898 | #define mmUVD_GP_SCRATCH21 0x05d7 |
899 | #define mmUVD_GP_SCRATCH21_BASE_IDX 1 |
900 | #define mmUVD_GP_SCRATCH22 0x05d8 |
901 | #define mmUVD_GP_SCRATCH22_BASE_IDX 1 |
902 | #define mmUVD_GP_SCRATCH23 0x05d9 |
903 | #define mmUVD_GP_SCRATCH23_BASE_IDX 1 |
904 | #define mmUVD_ENC_REG_INDEX 0x05da |
905 | #define mmUVD_ENC_REG_INDEX_BASE_IDX 1 |
906 | #define mmUVD_ENC_REG_DATA 0x05db |
907 | #define mmUVD_ENC_REG_DATA_BASE_IDX 1 |
908 | #define mmUVD_OUT_RB_BASE_LO 0x05dc |
909 | #define mmUVD_OUT_RB_BASE_LO_BASE_IDX 1 |
910 | #define mmUVD_OUT_RB_BASE_HI 0x05dd |
911 | #define mmUVD_OUT_RB_BASE_HI_BASE_IDX 1 |
912 | #define mmUVD_OUT_RB_SIZE 0x05de |
913 | #define mmUVD_OUT_RB_SIZE_BASE_IDX 1 |
914 | #define mmUVD_OUT_RB_RPTR 0x05df |
915 | #define mmUVD_OUT_RB_RPTR_BASE_IDX 1 |
916 | #define mmUVD_OUT_RB_WPTR 0x05e0 |
917 | #define mmUVD_OUT_RB_WPTR_BASE_IDX 1 |
918 | #define mmUVD_RB_BASE_LO2 0x05e1 |
919 | #define mmUVD_RB_BASE_LO2_BASE_IDX 1 |
920 | #define mmUVD_RB_BASE_HI2 0x05e2 |
921 | #define mmUVD_RB_BASE_HI2_BASE_IDX 1 |
922 | #define mmUVD_RB_SIZE2 0x05e3 |
923 | #define mmUVD_RB_SIZE2_BASE_IDX 1 |
924 | #define mmUVD_RB_RPTR2 0x05e4 |
925 | #define mmUVD_RB_RPTR2_BASE_IDX 1 |
926 | #define mmUVD_RB_WPTR2 0x05e5 |
927 | #define mmUVD_RB_WPTR2_BASE_IDX 1 |
928 | #define mmUVD_RB_BASE_LO 0x05e6 |
929 | #define mmUVD_RB_BASE_LO_BASE_IDX 1 |
930 | #define mmUVD_RB_BASE_HI 0x05e7 |
931 | #define mmUVD_RB_BASE_HI_BASE_IDX 1 |
932 | #define mmUVD_RB_SIZE 0x05e8 |
933 | #define mmUVD_RB_SIZE_BASE_IDX 1 |
934 | #define mmUVD_RB_RPTR 0x05e9 |
935 | #define mmUVD_RB_RPTR_BASE_IDX 1 |
936 | #define mmUVD_RB_WPTR 0x05ea |
937 | #define mmUVD_RB_WPTR_BASE_IDX 1 |
938 | #define mmUVD_ENC_PIPE_BUSY 0x05eb |
939 | #define mmUVD_ENC_PIPE_BUSY_BASE_IDX 1 |
940 | #define mmUVD_RB_WPTR4 0x0616 |
941 | #define mmUVD_RB_WPTR4_BASE_IDX 1 |
942 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x061e |
943 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
944 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x061f |
945 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
946 | #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x0620 |
947 | #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 |
948 | #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x0621 |
949 | #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 |
950 | #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0622 |
951 | #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 |
952 | #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0623 |
953 | #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 |
954 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0626 |
955 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
956 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0627 |
957 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 |
958 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0628 |
959 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 |
960 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0629 |
961 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
962 | |
963 | |
964 | // addressBlock: uvd0_uvdnp2dec |
965 | // base address: 0x21100 |
966 | #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0640 |
967 | #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 |
968 | #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0641 |
969 | #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 |
970 | #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0642 |
971 | #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 |
972 | #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0643 |
973 | #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 |
974 | #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0644 |
975 | #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 |
976 | #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0645 |
977 | #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 |
978 | #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0646 |
979 | #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 |
980 | #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0647 |
981 | #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 |
982 | #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0648 |
983 | #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 |
984 | #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0649 |
985 | #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 |
986 | #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x064a |
987 | #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 |
988 | #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x064b |
989 | #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 |
990 | #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x064c |
991 | #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 |
992 | #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x064d |
993 | #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 |
994 | #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x064e |
995 | #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 |
996 | #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x064f |
997 | #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 |
998 | #define mmUVD_LMI_MMSCH_NC_VMID 0x0651 |
999 | #define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 |
1000 | #define mmUVD_LMI_MMSCH_CTRL 0x0652 |
1001 | #define mmUVD_LMI_MMSCH_CTRL_BASE_IDX 1 |
1002 | #define mmUVD_MMSCH_SOFT_RESET 0x0654 |
1003 | #define mmUVD_MMSCH_SOFT_RESET_BASE_IDX 1 |
1004 | #define mmUVD_LMI_ARB_CTRL2 0x0662 |
1005 | #define mmUVD_LMI_ARB_CTRL2_BASE_IDX 1 |
1006 | |
1007 | |
1008 | #endif |
1009 | |