| 1 | /* |
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| 2 | * Copyright 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: AMD |
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| 23 | * |
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| 24 | */ |
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| 25 | |
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| 26 | #ifndef __IRQSRCS_DCN_1_0_H__ |
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| 27 | #define __IRQSRCS_DCN_1_0_H__ |
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| 28 | |
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| 29 | |
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| 30 | #define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 31 | #define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 |
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| 32 | |
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| 33 | #define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 34 | #define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 |
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| 35 | |
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| 36 | #define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 37 | #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 |
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| 38 | |
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| 39 | #define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 40 | #define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 |
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| 41 | |
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| 42 | #define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 43 | #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 |
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| 44 | |
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| 45 | #define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 46 | #define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 |
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| 47 | |
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| 48 | #define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 49 | #define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 |
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| 50 | |
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| 51 | #define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 52 | #define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 |
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| 53 | |
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| 54 | #define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 55 | #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 |
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| 56 | |
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| 57 | #define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 58 | #define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 |
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| 59 | |
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| 60 | #define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 61 | #define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 |
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| 62 | |
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| 63 | #define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 64 | #define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 |
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| 65 | |
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| 66 | #define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 67 | #define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 |
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| 68 | |
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| 69 | #define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 70 | #define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 |
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| 71 | |
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| 72 | #define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 73 | #define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 |
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| 74 | |
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| 75 | #define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 76 | #define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 |
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| 77 | |
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| 78 | #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse |
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| 79 | #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 |
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| 80 | |
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| 81 | #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level |
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| 82 | #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 |
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| 83 | |
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| 84 | #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse |
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| 85 | #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 |
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| 86 | |
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| 87 | #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level |
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| 88 | #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 |
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| 89 | |
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| 90 | #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse |
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| 91 | #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 |
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| 92 | |
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| 93 | #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level |
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| 94 | #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 |
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| 95 | |
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| 96 | #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 97 | #define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 |
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| 98 | |
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| 99 | #define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level |
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| 100 | #define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 |
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| 101 | |
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| 102 | #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level |
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| 103 | #define DCN_1_0__CTXID__DMCU_SCP_INT 14 |
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| 104 | |
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| 105 | #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 106 | #define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 |
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| 107 | |
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| 108 | #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 109 | #define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 |
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| 110 | |
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| 111 | #define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 112 | #define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 |
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| 113 | |
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| 114 | #define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level |
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| 115 | #define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 |
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| 116 | |
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| 117 | #define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level |
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| 118 | #define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 |
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| 119 | |
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| 120 | #define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level |
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| 121 | #define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 |
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| 122 | |
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| 123 | #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse |
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| 124 | #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 |
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| 125 | |
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| 126 | #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level |
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| 127 | #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 |
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| 128 | |
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| 129 | #define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse |
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| 130 | #define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 |
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| 131 | |
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| 132 | #define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 133 | #define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 |
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| 134 | |
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| 135 | #define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 136 | #define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 |
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| 137 | |
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| 138 | #define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 139 | #define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 |
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| 140 | |
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| 141 | #define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 142 | #define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 |
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| 143 | |
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| 144 | #define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 145 | #define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 |
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| 146 | |
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| 147 | #define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 148 | #define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 |
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| 149 | |
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| 150 | #define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 151 | #define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 |
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| 152 | |
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| 153 | #define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 154 | #define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 |
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| 155 | |
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| 156 | #define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 157 | #define DCN_1_0__CTXID__DC_HPD1_INT 0 |
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| 158 | |
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| 159 | #define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 160 | #define DCN_1_0__CTXID__DC_HPD2_INT 1 |
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| 161 | |
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| 162 | #define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 163 | #define DCN_1_0__CTXID__DC_HPD3_INT 2 |
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| 164 | |
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| 165 | #define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 166 | #define DCN_1_0__CTXID__DC_HPD4_INT 3 |
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| 167 | |
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| 168 | #define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 169 | #define DCN_1_0__CTXID__DC_HPD5_INT 4 |
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| 170 | |
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| 171 | #define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level |
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| 172 | #define DCN_1_0__CTXID__DC_HPD6_INT 5 |
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| 173 | |
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| 174 | #define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 175 | #define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 |
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| 176 | |
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| 177 | #define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 178 | #define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 |
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| 179 | |
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| 180 | #define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 181 | #define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 |
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| 182 | |
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| 183 | #define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 184 | #define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 |
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| 185 | |
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| 186 | #define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 187 | #define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 |
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| 188 | |
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| 189 | #define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level |
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| 190 | #define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 |
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| 191 | |
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| 192 | #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 193 | #define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 |
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| 194 | |
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| 195 | #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 196 | #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 |
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| 197 | |
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| 198 | #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 199 | #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 |
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| 200 | |
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| 201 | #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 202 | #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 |
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| 203 | |
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| 204 | #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 205 | #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 |
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| 206 | |
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| 207 | #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 208 | #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 |
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| 209 | |
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| 210 | #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 211 | #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 |
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| 212 | |
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| 213 | #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 214 | #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 |
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| 215 | |
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| 216 | #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 217 | #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 |
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| 218 | |
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| 219 | #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 220 | #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 |
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| 221 | |
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| 222 | #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 223 | #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 |
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| 224 | |
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| 225 | #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 226 | #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 |
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| 227 | |
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| 228 | #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 229 | #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 |
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| 230 | |
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| 231 | #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 232 | #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 |
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| 233 | |
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| 234 | #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 235 | #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 |
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| 236 | |
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| 237 | #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 238 | #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 |
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| 239 | |
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| 240 | #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 241 | #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 |
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| 242 | |
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| 243 | #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 244 | #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 |
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| 245 | |
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| 246 | #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 247 | #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 |
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| 248 | |
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| 249 | #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 250 | #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 |
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| 251 | |
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| 252 | #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 253 | #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 |
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| 254 | |
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| 255 | #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 256 | #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 |
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| 257 | |
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| 258 | #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 259 | #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 |
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| 260 | |
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| 261 | #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 262 | #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 |
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| 263 | |
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| 264 | #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse |
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| 265 | #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 |
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| 266 | |
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| 267 | #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 268 | #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 |
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| 269 | |
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| 270 | #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 271 | #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 |
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| 272 | |
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| 273 | #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 274 | #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 |
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| 275 | |
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| 276 | #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 277 | #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 |
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| 278 | |
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| 279 | #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 280 | #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 |
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| 281 | |
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| 282 | #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 283 | #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 |
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| 284 | |
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| 285 | #define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 286 | #define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 |
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| 287 | |
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| 288 | #define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 289 | #define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 |
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| 290 | |
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| 291 | #define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 292 | #define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 |
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| 293 | |
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| 294 | #define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 295 | #define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 |
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| 296 | |
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| 297 | #define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 298 | #define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 |
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| 299 | |
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| 300 | #define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level |
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| 301 | #define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 |
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| 302 | |
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| 303 | #define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level |
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| 304 | #define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 |
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| 305 | |
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| 306 | #define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 307 | #define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 |
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| 308 | |
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| 309 | #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 310 | #define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 |
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| 311 | |
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| 312 | #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 313 | #define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 |
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| 314 | |
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| 315 | #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 316 | #define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 |
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| 317 | |
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| 318 | #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 319 | #define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 |
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| 320 | |
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| 321 | #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 322 | #define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 |
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| 323 | |
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| 324 | #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level |
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| 325 | #define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 |
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| 326 | |
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| 327 | #define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level |
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| 328 | #define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 |
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| 329 | |
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| 330 | #define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level |
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| 331 | #define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 |
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| 332 | |
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| 333 | #define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 334 | #define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 |
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| 335 | |
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| 336 | #define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 337 | #define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 |
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| 338 | |
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| 339 | #define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 340 | #define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 |
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| 341 | |
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| 342 | #define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 343 | #define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 |
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| 344 | |
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| 345 | #define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 346 | #define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 |
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| 347 | |
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| 348 | #define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 349 | #define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 |
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| 350 | |
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| 351 | #define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 352 | #define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 |
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| 353 | |
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| 354 | #define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 355 | #define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 |
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| 356 | |
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| 357 | #define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 358 | #define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 |
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| 359 | |
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| 360 | #define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 361 | #define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 |
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| 362 | |
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| 363 | #define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level |
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| 364 | #define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 |
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| 365 | |
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| 366 | #define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level |
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| 367 | #define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 |
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| 368 | |
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| 369 | #define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 370 | #define DCN_1_0__CTXID__VGA_CRT_INT 12 |
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| 371 | |
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| 372 | #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 373 | #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 |
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| 374 | |
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| 375 | #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 376 | #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 |
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| 377 | |
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| 378 | #define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 379 | #define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 |
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| 380 | |
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| 381 | #define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 382 | #define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 |
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| 383 | |
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| 384 | #define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 385 | #define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 |
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| 386 | |
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| 387 | #define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 388 | #define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 |
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| 389 | |
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| 390 | #define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 391 | #define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 |
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| 392 | |
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| 393 | #define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 394 | #define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 |
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| 395 | |
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| 396 | #define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level |
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| 397 | #define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 |
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| 398 | |
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| 399 | #define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level |
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| 400 | #define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 |
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| 401 | |
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| 402 | #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 403 | #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 |
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| 404 | |
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| 405 | #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 406 | #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 |
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| 407 | |
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| 408 | #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 409 | #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 |
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| 410 | |
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| 411 | #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 412 | #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 |
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| 413 | |
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| 414 | #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 415 | #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 |
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| 416 | |
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| 417 | #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level |
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| 418 | #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 |
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| 419 | |
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| 420 | #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 421 | #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 |
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| 422 | |
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| 423 | #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 424 | #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 |
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| 425 | |
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| 426 | #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 427 | #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 |
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| 428 | |
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| 429 | #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 430 | #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 |
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| 431 | |
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| 432 | #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 433 | #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 |
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| 434 | |
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| 435 | #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 436 | #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 |
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| 437 | |
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| 438 | #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 439 | #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 |
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| 440 | |
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| 441 | #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
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| 442 | #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 |
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| 443 | |
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| 444 | #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 445 | #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 |
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| 446 | |
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| 447 | #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 448 | #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 |
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| 449 | |
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| 450 | #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 451 | #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 |
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| 452 | |
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| 453 | #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 454 | #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 |
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| 455 | |
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| 456 | #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 457 | #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 |
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| 458 | |
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| 459 | #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 460 | #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 |
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| 461 | |
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| 462 | #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 463 | #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 |
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| 464 | |
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| 465 | #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 466 | #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 |
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| 467 | |
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| 468 | #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 469 | #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 |
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| 470 | |
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| 471 | #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 472 | #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 |
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| 473 | |
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| 474 | #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 475 | #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 |
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| 476 | |
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| 477 | #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 478 | #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 |
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| 479 | |
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| 480 | #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 481 | #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 |
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| 482 | |
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| 483 | #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level |
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| 484 | #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 |
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| 485 | |
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| 486 | #define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level |
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| 487 | #define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 |
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| 488 | |
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| 489 | #define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level |
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| 490 | #define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 |
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| 491 | |
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| 492 | #define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level |
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| 493 | #define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 |
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| 494 | |
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| 495 | #define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level |
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| 496 | #define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 |
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| 497 | |
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| 498 | #define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 499 | #define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 |
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| 500 | |
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| 501 | #define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level |
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| 502 | #define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 |
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| 503 | |
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| 504 | #define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 505 | #define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 |
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| 506 | |
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| 507 | #define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 508 | #define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 |
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| 509 | |
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| 510 | #define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 511 | #define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 |
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| 512 | |
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| 513 | #define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 514 | #define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 |
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| 515 | |
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| 516 | #define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 517 | #define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 |
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| 518 | |
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| 519 | #define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 520 | #define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 |
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| 521 | |
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| 522 | #define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 523 | #define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 |
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| 524 | |
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| 525 | #define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
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| 526 | #define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 |
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| 527 | |
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| 528 | #define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 529 | #define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 |
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| 530 | |
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| 531 | #define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 532 | #define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 |
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| 533 | |
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| 534 | #define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 535 | #define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 |
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| 536 | |
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| 537 | #define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 538 | #define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 |
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| 539 | |
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| 540 | #define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 541 | #define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 |
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| 542 | |
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| 543 | #define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 544 | #define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 |
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| 545 | |
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| 546 | #define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 547 | #define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 |
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| 548 | |
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| 549 | #define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 550 | #define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 |
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| 551 | |
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| 552 | #define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 553 | #define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 |
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| 554 | |
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| 555 | #define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 556 | #define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 |
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| 557 | |
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| 558 | #define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 559 | #define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 |
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| 560 | |
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| 561 | #define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse |
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| 562 | #define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 |
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| 563 | |
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| 564 | #define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 565 | #define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 566 | #define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 567 | #define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 568 | #define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 569 | #define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 570 | |
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| 571 | #define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse |
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| 572 | #define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 |
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| 573 | |
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| 574 | #define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse |
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| 575 | #define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 |
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| 576 | |
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| 577 | #define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse |
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| 578 | #define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 |
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| 579 | |
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| 580 | #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse |
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| 581 | #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 |
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| 582 | |
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| 583 | #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse |
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| 584 | #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 |
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| 585 | |
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| 586 | #define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 587 | #define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 |
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| 588 | |
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| 589 | #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 590 | #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 |
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| 591 | |
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| 592 | #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 593 | #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 |
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| 594 | |
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| 595 | #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 596 | #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 |
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| 597 | |
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| 598 | #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 599 | #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 |
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| 600 | |
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| 601 | #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 602 | #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 |
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| 603 | |
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| 604 | #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 605 | #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 |
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| 606 | |
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| 607 | #define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse |
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| 608 | #define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 |
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| 609 | |
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| 610 | #define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 611 | #define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 |
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| 612 | |
|---|
| 613 | #define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 614 | #define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 |
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| 615 | |
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| 616 | #define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 617 | #define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 |
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| 618 | |
|---|
| 619 | #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
|---|
| 620 | #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 |
|---|
| 621 | |
|---|
| 622 | #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
|---|
| 623 | #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 |
|---|
| 624 | |
|---|
| 625 | #define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
|---|
| 626 | #define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 |
|---|
| 627 | |
|---|
| 628 | #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 629 | #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 |
|---|
| 630 | |
|---|
| 631 | #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 632 | #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 |
|---|
| 633 | |
|---|
| 634 | #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 635 | #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 |
|---|
| 636 | |
|---|
| 637 | #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 638 | #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 |
|---|
| 639 | |
|---|
| 640 | #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 641 | #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 |
|---|
| 642 | |
|---|
| 643 | #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 644 | #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 |
|---|
| 645 | |
|---|
| 646 | #define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
|---|
| 647 | #define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 |
|---|
| 648 | |
|---|
| 649 | #define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 650 | #define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 |
|---|
| 651 | |
|---|
| 652 | #define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 653 | #define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 |
|---|
| 654 | |
|---|
| 655 | #define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 656 | #define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 |
|---|
| 657 | |
|---|
| 658 | #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 659 | #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 |
|---|
| 660 | |
|---|
| 661 | #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 662 | #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 |
|---|
| 663 | |
|---|
| 664 | #define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
|---|
| 665 | #define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 |
|---|
| 666 | |
|---|
| 667 | #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 668 | #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 |
|---|
| 669 | |
|---|
| 670 | #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 671 | #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 |
|---|
| 672 | |
|---|
| 673 | #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 674 | #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 |
|---|
| 675 | |
|---|
| 676 | #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 677 | #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 |
|---|
| 678 | |
|---|
| 679 | #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 680 | #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 |
|---|
| 681 | |
|---|
| 682 | #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 683 | #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 |
|---|
| 684 | |
|---|
| 685 | #define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
|---|
| 686 | #define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 |
|---|
| 687 | |
|---|
| 688 | #define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 689 | #define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 |
|---|
| 690 | |
|---|
| 691 | #define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 692 | #define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 |
|---|
| 693 | |
|---|
| 694 | #define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 695 | #define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 |
|---|
| 696 | |
|---|
| 697 | #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 698 | #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 |
|---|
| 699 | |
|---|
| 700 | #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 701 | #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 |
|---|
| 702 | |
|---|
| 703 | #define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
|---|
| 704 | #define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 |
|---|
| 705 | |
|---|
| 706 | #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 707 | #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 |
|---|
| 708 | |
|---|
| 709 | #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 710 | #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 |
|---|
| 711 | |
|---|
| 712 | #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 713 | #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 |
|---|
| 714 | |
|---|
| 715 | #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 716 | #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 |
|---|
| 717 | |
|---|
| 718 | #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 719 | #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 |
|---|
| 720 | |
|---|
| 721 | #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 722 | #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 |
|---|
| 723 | |
|---|
| 724 | #define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
|---|
| 725 | #define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 |
|---|
| 726 | |
|---|
| 727 | #define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 728 | #define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 |
|---|
| 729 | |
|---|
| 730 | #define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 731 | #define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 |
|---|
| 732 | |
|---|
| 733 | #define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 734 | #define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 |
|---|
| 735 | |
|---|
| 736 | #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 737 | #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 |
|---|
| 738 | |
|---|
| 739 | #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 740 | #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 |
|---|
| 741 | |
|---|
| 742 | #define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
|---|
| 743 | #define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 |
|---|
| 744 | |
|---|
| 745 | #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 746 | #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 |
|---|
| 747 | |
|---|
| 748 | #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 749 | #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 |
|---|
| 750 | |
|---|
| 751 | #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 752 | #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 |
|---|
| 753 | |
|---|
| 754 | #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 755 | #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 |
|---|
| 756 | |
|---|
| 757 | #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 758 | #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 |
|---|
| 759 | |
|---|
| 760 | #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 761 | #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 |
|---|
| 762 | |
|---|
| 763 | #define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
|---|
| 764 | #define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 |
|---|
| 765 | |
|---|
| 766 | #define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse |
|---|
| 767 | #define DCN_1_0__CTXID__DC_D1_VBLANK 0 |
|---|
| 768 | |
|---|
| 769 | #define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse |
|---|
| 770 | #define DCN_1_0__CTXID__DC_D1_VLINE1 1 |
|---|
| 771 | |
|---|
| 772 | #define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse |
|---|
| 773 | #define DCN_1_0__CTXID__DC_D1_VLINE2 2 |
|---|
| 774 | |
|---|
| 775 | #define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse |
|---|
| 776 | #define DCN_1_0__CTXID__DC_D2_VBLANK 3 |
|---|
| 777 | |
|---|
| 778 | #define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse |
|---|
| 779 | #define DCN_1_0__CTXID__DC_D2_VLINE1 4 |
|---|
| 780 | |
|---|
| 781 | #define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse |
|---|
| 782 | #define DCN_1_0__CTXID__DC_D2_VLINE2 5 |
|---|
| 783 | |
|---|
| 784 | #define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
|---|
| 785 | #define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 |
|---|
| 786 | |
|---|
| 787 | #define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level |
|---|
| 788 | #define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 |
|---|
| 789 | |
|---|
| 790 | #define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level |
|---|
| 791 | #define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 |
|---|
| 792 | |
|---|
| 793 | #define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level |
|---|
| 794 | #define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 |
|---|
| 795 | |
|---|
| 796 | #define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level |
|---|
| 797 | #define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 |
|---|
| 798 | |
|---|
| 799 | #define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level |
|---|
| 800 | #define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 |
|---|
| 801 | |
|---|
| 802 | #define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level |
|---|
| 803 | #define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 |
|---|
| 804 | |
|---|
| 805 | #define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level |
|---|
| 806 | #define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 |
|---|
| 807 | |
|---|
| 808 | #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse |
|---|
| 809 | #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 810 | |
|---|
| 811 | #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level |
|---|
| 812 | #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 813 | |
|---|
| 814 | #define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse |
|---|
| 815 | #define DCN_1_0__CTXID__DC_D3_VBLANK 9 |
|---|
| 816 | |
|---|
| 817 | #define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse |
|---|
| 818 | #define DCN_1_0__CTXID__DC_D3_VLINE1 10 |
|---|
| 819 | |
|---|
| 820 | #define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse |
|---|
| 821 | #define DCN_1_0__CTXID__DC_D3_VLINE2 11 |
|---|
| 822 | |
|---|
| 823 | #define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 824 | #define DCN_1_0__CTXID__DC_D4_VBLANK 12 |
|---|
| 825 | |
|---|
| 826 | #define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 827 | #define DCN_1_0__CTXID__DC_D4_VLINE1 13 |
|---|
| 828 | |
|---|
| 829 | #define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 830 | #define DCN_1_0__CTXID__DC_D4_VLINE2 14 |
|---|
| 831 | |
|---|
| 832 | #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse |
|---|
| 833 | #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 834 | |
|---|
| 835 | #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level |
|---|
| 836 | #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 837 | |
|---|
| 838 | #define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 839 | #define DCN_1_0__CTXID__DC_D5_VBLANK 9 |
|---|
| 840 | |
|---|
| 841 | #define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 842 | #define DCN_1_0__CTXID__DC_D5_VLINE1 10 |
|---|
| 843 | |
|---|
| 844 | #define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 845 | #define DCN_1_0__CTXID__DC_D5_VLINE2 11 |
|---|
| 846 | |
|---|
| 847 | #define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 848 | #define DCN_1_0__CTXID__DC_D6_VBLANK 12 |
|---|
| 849 | |
|---|
| 850 | #define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 851 | #define DCN_1_0__CTXID__DC_D6_VLINE1 13 |
|---|
| 852 | |
|---|
| 853 | #define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 854 | #define DCN_1_0__CTXID__DC_D6_VLINE2 14 |
|---|
| 855 | |
|---|
| 856 | #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse |
|---|
| 857 | #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 858 | |
|---|
| 859 | #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level |
|---|
| 860 | #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 861 | |
|---|
| 862 | #define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 863 | #define DCN_1_0__CTXID__DC_D7_VBLANK 9 |
|---|
| 864 | |
|---|
| 865 | #define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 866 | #define DCN_1_0__CTXID__DC_D7_VLINE1 10 |
|---|
| 867 | |
|---|
| 868 | #define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 869 | #define DCN_1_0__CTXID__DC_D7_VLINE2 11 |
|---|
| 870 | |
|---|
| 871 | #define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 872 | #define DCN_1_0__CTXID__DC_D8_VBLANK 12 |
|---|
| 873 | |
|---|
| 874 | #define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 875 | #define DCN_1_0__CTXID__DC_D8_VLINE1 13 |
|---|
| 876 | |
|---|
| 877 | #define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 878 | #define DCN_1_0__CTXID__DC_D8_VLINE2 14 |
|---|
| 879 | |
|---|
| 880 | #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse |
|---|
| 881 | #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 882 | |
|---|
| 883 | #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level |
|---|
| 884 | #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 885 | |
|---|
| 886 | #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse |
|---|
| 887 | #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 888 | |
|---|
| 889 | #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level |
|---|
| 890 | #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 891 | |
|---|
| 892 | #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse |
|---|
| 893 | #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 894 | |
|---|
| 895 | #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level |
|---|
| 896 | #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 897 | |
|---|
| 898 | #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse |
|---|
| 899 | #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 900 | |
|---|
| 901 | #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level |
|---|
| 902 | #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 903 | |
|---|
| 904 | #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse |
|---|
| 905 | #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 906 | |
|---|
| 907 | #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level |
|---|
| 908 | #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 909 | |
|---|
| 910 | #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse |
|---|
| 911 | #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 912 | |
|---|
| 913 | #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
|---|
| 914 | #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 915 | |
|---|
| 916 | #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse |
|---|
| 917 | #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 918 | |
|---|
| 919 | #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level |
|---|
| 920 | #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 921 | |
|---|
| 922 | #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse |
|---|
| 923 | #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 924 | |
|---|
| 925 | #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level |
|---|
| 926 | #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 927 | |
|---|
| 928 | #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse |
|---|
| 929 | #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 930 | |
|---|
| 931 | #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level |
|---|
| 932 | #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 933 | |
|---|
| 934 | #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse |
|---|
| 935 | #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 936 | |
|---|
| 937 | #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level |
|---|
| 938 | #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 939 | |
|---|
| 940 | #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse |
|---|
| 941 | #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 942 | |
|---|
| 943 | #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level |
|---|
| 944 | #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 945 | |
|---|
| 946 | #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse |
|---|
| 947 | #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 948 | |
|---|
| 949 | #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level |
|---|
| 950 | #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 951 | |
|---|
| 952 | #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse |
|---|
| 953 | #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 954 | |
|---|
| 955 | #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level |
|---|
| 956 | #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 957 | |
|---|
| 958 | #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse |
|---|
| 959 | #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 960 | |
|---|
| 961 | #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level |
|---|
| 962 | #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 963 | |
|---|
| 964 | #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse |
|---|
| 965 | #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 966 | |
|---|
| 967 | #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level |
|---|
| 968 | #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 969 | |
|---|
| 970 | #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse |
|---|
| 971 | #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 972 | |
|---|
| 973 | #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level |
|---|
| 974 | #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 975 | |
|---|
| 976 | #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
|---|
| 977 | #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 |
|---|
| 978 | |
|---|
| 979 | #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level |
|---|
| 980 | #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 |
|---|
| 981 | |
|---|
| 982 | #define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 983 | #define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 |
|---|
| 984 | |
|---|
| 985 | #define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 986 | #define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 |
|---|
| 987 | |
|---|
| 988 | #define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 989 | #define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 |
|---|
| 990 | |
|---|
| 991 | #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 992 | #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 |
|---|
| 993 | |
|---|
| 994 | #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 995 | #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 |
|---|
| 996 | |
|---|
| 997 | #define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
|---|
| 998 | #define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 |
|---|
| 999 | |
|---|
| 1000 | #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 1001 | #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 |
|---|
| 1002 | |
|---|
| 1003 | #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
|---|
| 1004 | #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 |
|---|
| 1005 | |
|---|
| 1006 | #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
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| 1007 | #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 |
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| 1008 | |
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| 1009 | #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
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| 1010 | #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 |
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| 1011 | |
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| 1012 | #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
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| 1013 | #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 |
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| 1014 | |
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| 1015 | #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
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| 1016 | #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 |
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| 1017 | |
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| 1018 | #define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
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| 1019 | #define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 |
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| 1020 | |
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| 1021 | #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1022 | #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 |
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| 1023 | |
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| 1024 | #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level |
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| 1025 | #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 |
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| 1026 | |
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| 1027 | #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1028 | #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 |
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| 1029 | |
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| 1030 | #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level |
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| 1031 | #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 |
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| 1032 | |
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| 1033 | #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse |
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| 1034 | #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 |
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| 1035 | |
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| 1036 | #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level |
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| 1037 | #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 |
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| 1038 | |
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| 1039 | #define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1040 | #define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1041 | #define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1042 | #define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1043 | #define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1044 | #define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1045 | |
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| 1046 | #define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1047 | #define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1048 | #define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1049 | #define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1050 | #define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1051 | #define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse |
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| 1052 | |
|---|
| 1053 | #define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse |
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| 1054 | #define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse |
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| 1055 | #define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse |
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| 1056 | #define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse |
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| 1057 | #define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse |
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| 1058 | #define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse |
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| 1059 | |
|---|
| 1060 | #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1061 | #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 |
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| 1062 | |
|---|
| 1063 | #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1064 | #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 |
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| 1065 | |
|---|
| 1066 | #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1067 | #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 |
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| 1068 | |
|---|
| 1069 | #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1070 | #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 |
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| 1071 | |
|---|
| 1072 | #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1073 | #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 |
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| 1074 | |
|---|
| 1075 | #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1076 | #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 |
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| 1077 | |
|---|
| 1078 | #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1079 | #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 |
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| 1080 | |
|---|
| 1081 | #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1082 | #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 |
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| 1083 | |
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| 1084 | #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1085 | #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 |
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| 1086 | |
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| 1087 | #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1088 | #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 |
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| 1089 | |
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| 1090 | #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1091 | #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 |
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| 1092 | |
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| 1093 | #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1094 | #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 |
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| 1095 | |
|---|
| 1096 | #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1097 | #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 |
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| 1098 | |
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| 1099 | #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1100 | #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 |
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| 1101 | |
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| 1102 | #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1103 | #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 |
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| 1104 | |
|---|
| 1105 | #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level |
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| 1106 | #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 |
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| 1107 | |
|---|
| 1108 | #define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1109 | #define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1110 | #define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1111 | #define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1112 | #define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1113 | #define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1114 | #define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1115 | #define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1116 | |
|---|
| 1117 | #define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse |
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| 1118 | #define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse |
|---|
| 1119 | #define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse |
|---|
| 1120 | #define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse |
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| 1121 | #define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse |
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| 1122 | #define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse |
|---|
| 1123 | |
|---|
| 1124 | #define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1125 | #define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1126 | #define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1127 | #define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1128 | #define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1129 | #define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1130 | #define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1131 | #define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse |
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| 1132 | |
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| 1133 | #define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68 |
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| 1134 | #define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6 |
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| 1135 | #define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 0x68 // DMCUB_IHC_outbox1_ready_int IHC_DMCUB_outbox1_ready_int_ack DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE24 Level/Pulse |
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| 1136 | #define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 8 |
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| 1137 | |
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| 1138 | #endif // __IRQSRCS_DCN_1_0_H__ |
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| 1139 | |
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