1 | /* |
2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #if !defined (_navi10_ENUM_HEADER) |
22 | #define |
23 | |
24 | #ifndef _DRIVER_BUILD |
25 | #ifndef GL_ZERO |
26 | #define GL__ZERO BLEND_ZERO |
27 | #define GL__ONE BLEND_ONE |
28 | #define GL__SRC_COLOR BLEND_SRC_COLOR |
29 | #define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR |
30 | #define GL__DST_COLOR BLEND_DST_COLOR |
31 | #define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR |
32 | #define GL__SRC_ALPHA BLEND_SRC_ALPHA |
33 | #define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA |
34 | #define GL__DST_ALPHA BLEND_DST_ALPHA |
35 | #define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA |
36 | #define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE |
37 | #define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR |
38 | #define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR |
39 | #define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA |
40 | #define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA |
41 | #endif |
42 | #endif |
43 | |
44 | /******************************************************* |
45 | * GDS DATA_TYPE Enums |
46 | *******************************************************/ |
47 | |
48 | #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H |
49 | #define ENUMS_GDS_PERFCOUNT_SELECT_H |
50 | typedef enum GDS_PERFCOUNT_SELECT { |
51 | GDS_PERF_SEL_DS_ADDR_CONFL = 0, |
52 | GDS_PERF_SEL_DS_BANK_CONFL = 1, |
53 | GDS_PERF_SEL_WBUF_FLUSH = 2, |
54 | GDS_PERF_SEL_WR_COMP = 3, |
55 | GDS_PERF_SEL_WBUF_WR = 4, |
56 | GDS_PERF_SEL_RBUF_HIT = 5, |
57 | GDS_PERF_SEL_RBUF_MISS = 6, |
58 | GDS_PERF_SEL_SE0_SH0_NORET = 7, |
59 | GDS_PERF_SEL_SE0_SH0_RET = 8, |
60 | GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, |
61 | GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, |
62 | GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, |
63 | GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, |
64 | GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, |
65 | GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, |
66 | GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, |
67 | GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, |
68 | GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, |
69 | GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, |
70 | GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, |
71 | GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, |
72 | GDS_PERF_SEL_SE0_SH1_NORET = 21, |
73 | GDS_PERF_SEL_SE0_SH1_RET = 22, |
74 | GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, |
75 | GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, |
76 | GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, |
77 | GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, |
78 | GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, |
79 | GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, |
80 | GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, |
81 | GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, |
82 | GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, |
83 | GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, |
84 | GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, |
85 | GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, |
86 | GDS_PERF_SEL_SE1_SH0_NORET = 35, |
87 | GDS_PERF_SEL_SE1_SH0_RET = 36, |
88 | GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, |
89 | GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, |
90 | GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, |
91 | GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, |
92 | GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, |
93 | GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, |
94 | GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, |
95 | GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, |
96 | GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, |
97 | GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, |
98 | GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, |
99 | GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, |
100 | GDS_PERF_SEL_SE1_SH1_NORET = 49, |
101 | GDS_PERF_SEL_SE1_SH1_RET = 50, |
102 | GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, |
103 | GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, |
104 | GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, |
105 | GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, |
106 | GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, |
107 | GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, |
108 | GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, |
109 | GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, |
110 | GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, |
111 | GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, |
112 | GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, |
113 | GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, |
114 | GDS_PERF_SEL_SE2_SH0_NORET = 63, |
115 | GDS_PERF_SEL_SE2_SH0_RET = 64, |
116 | GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, |
117 | GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, |
118 | GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, |
119 | GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, |
120 | GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, |
121 | GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, |
122 | GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, |
123 | GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, |
124 | GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, |
125 | GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, |
126 | GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, |
127 | GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, |
128 | GDS_PERF_SEL_SE2_SH1_NORET = 77, |
129 | GDS_PERF_SEL_SE2_SH1_RET = 78, |
130 | GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, |
131 | GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, |
132 | GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, |
133 | GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, |
134 | GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, |
135 | GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, |
136 | GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, |
137 | GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, |
138 | GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, |
139 | GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, |
140 | GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, |
141 | GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, |
142 | GDS_PERF_SEL_SE3_SH0_NORET = 91, |
143 | GDS_PERF_SEL_SE3_SH0_RET = 92, |
144 | GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, |
145 | GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, |
146 | GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, |
147 | GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, |
148 | GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, |
149 | GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, |
150 | GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, |
151 | GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, |
152 | GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, |
153 | GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, |
154 | GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, |
155 | GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, |
156 | GDS_PERF_SEL_SE3_SH1_NORET = 105, |
157 | GDS_PERF_SEL_SE3_SH1_RET = 106, |
158 | GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, |
159 | GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, |
160 | GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, |
161 | GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, |
162 | GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, |
163 | GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, |
164 | GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, |
165 | GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, |
166 | GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, |
167 | GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, |
168 | GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, |
169 | GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, |
170 | GDS_PERF_SEL_GWS_RELEASED = 119, |
171 | GDS_PERF_SEL_GWS_BYPASS = 120, |
172 | } GDS_PERFCOUNT_SELECT; |
173 | #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ |
174 | |
175 | /******************************************************* |
176 | * Chip Enums |
177 | *******************************************************/ |
178 | |
179 | /* |
180 | * GATCL1RequestType enum |
181 | */ |
182 | |
183 | typedef enum GATCL1RequestType { |
184 | GATCL1_TYPE_NORMAL = 0x00000000, |
185 | GATCL1_TYPE_SHOOTDOWN = 0x00000001, |
186 | GATCL1_TYPE_BYPASS = 0x00000002, |
187 | } GATCL1RequestType; |
188 | |
189 | /* |
190 | * UTCL1RequestType enum |
191 | */ |
192 | |
193 | typedef enum UTCL1RequestType { |
194 | UTCL1_TYPE_NORMAL = 0x00000000, |
195 | UTCL1_TYPE_SHOOTDOWN = 0x00000001, |
196 | UTCL1_TYPE_BYPASS = 0x00000002, |
197 | } UTCL1RequestType; |
198 | |
199 | /* |
200 | * UTCL1FaultType enum |
201 | */ |
202 | |
203 | typedef enum UTCL1FaultType { |
204 | UTCL1_XNACK_SUCCESS = 0x00000000, |
205 | UTCL1_XNACK_RETRY = 0x00000001, |
206 | UTCL1_XNACK_PRT = 0x00000002, |
207 | UTCL1_XNACK_NO_RETRY = 0x00000003, |
208 | } UTCL1FaultType; |
209 | |
210 | /* |
211 | * UTCL0RequestType enum |
212 | */ |
213 | |
214 | typedef enum UTCL0RequestType { |
215 | UTCL0_TYPE_NORMAL = 0x00000000, |
216 | UTCL0_TYPE_SHOOTDOWN = 0x00000001, |
217 | UTCL0_TYPE_BYPASS = 0x00000002, |
218 | } UTCL0RequestType; |
219 | |
220 | /* |
221 | * UTCL0FaultType enum |
222 | */ |
223 | |
224 | typedef enum UTCL0FaultType { |
225 | UTCL0_XNACK_SUCCESS = 0x00000000, |
226 | UTCL0_XNACK_RETRY = 0x00000001, |
227 | UTCL0_XNACK_PRT = 0x00000002, |
228 | UTCL0_XNACK_NO_RETRY = 0x00000003, |
229 | } UTCL0FaultType; |
230 | |
231 | /* |
232 | * VMEMCMD_RETURN_ORDER enum |
233 | */ |
234 | |
235 | typedef enum VMEMCMD_RETURN_ORDER { |
236 | VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000, |
237 | VMEMCMD_RETURN_IN_ORDER = 0x00000001, |
238 | VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002, |
239 | } VMEMCMD_RETURN_ORDER; |
240 | |
241 | /* |
242 | * GL0V_CACHE_POLICIES enum |
243 | */ |
244 | |
245 | typedef enum GL0V_CACHE_POLICIES { |
246 | GL0V_CACHE_POLICY_MISS_LRU = 0x00000000, |
247 | GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001, |
248 | GL0V_CACHE_POLICY_HIT_LRU = 0x00000002, |
249 | GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003, |
250 | } GL0V_CACHE_POLICIES; |
251 | |
252 | /* |
253 | * GL1_CACHE_POLICIES enum |
254 | */ |
255 | |
256 | typedef enum GL1_CACHE_POLICIES { |
257 | GL1_CACHE_POLICY_MISS_LRU = 0x00000000, |
258 | GL1_CACHE_POLICY_MISS_EVICT = 0x00000001, |
259 | GL1_CACHE_POLICY_HIT_LRU = 0x00000002, |
260 | GL1_CACHE_POLICY_HIT_EVICT = 0x00000003, |
261 | } GL1_CACHE_POLICIES; |
262 | |
263 | /* |
264 | * GL1_CACHE_STORE_POLICIES enum |
265 | */ |
266 | |
267 | typedef enum GL1_CACHE_STORE_POLICIES { |
268 | GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000, |
269 | } GL1_CACHE_STORE_POLICIES; |
270 | |
271 | /* |
272 | * TCC_CACHE_POLICIES enum |
273 | */ |
274 | |
275 | typedef enum TCC_CACHE_POLICIES { |
276 | TCC_CACHE_POLICY_LRU = 0x00000000, |
277 | TCC_CACHE_POLICY_STREAM = 0x00000001, |
278 | } TCC_CACHE_POLICIES; |
279 | |
280 | /* |
281 | * TCC_MTYPE enum |
282 | */ |
283 | |
284 | typedef enum TCC_MTYPE { |
285 | MTYPE_NC = 0x00000000, |
286 | MTYPE_WC = 0x00000001, |
287 | MTYPE_CC = 0x00000002, |
288 | } TCC_MTYPE; |
289 | |
290 | /* |
291 | * GL2_CACHE_POLICIES enum |
292 | */ |
293 | |
294 | typedef enum GL2_CACHE_POLICIES { |
295 | GL2_CACHE_POLICY_LRU = 0x00000000, |
296 | GL2_CACHE_POLICY_STREAM = 0x00000001, |
297 | GL2_CACHE_POLICY_NOA = 0x00000002, |
298 | GL2_CACHE_POLICY_BYPASS = 0x00000003, |
299 | } GL2_CACHE_POLICIES; |
300 | |
301 | /* |
302 | * MTYPE enum |
303 | */ |
304 | |
305 | typedef enum MTYPE { |
306 | MTYPE_C_RW_US = 0x00000000, |
307 | MTYPE_RESERVED_1 = 0x00000001, |
308 | MTYPE_C_RO_S = 0x00000002, |
309 | MTYPE_UC = 0x00000003, |
310 | MTYPE_C_RW_S = 0x00000004, |
311 | MTYPE_RESERVED_5 = 0x00000005, |
312 | MTYPE_C_RO_US = 0x00000006, |
313 | MTYPE_RESERVED_7 = 0x00000007, |
314 | } MTYPE; |
315 | |
316 | /* |
317 | * RMI_CID enum |
318 | */ |
319 | |
320 | typedef enum RMI_CID { |
321 | RMI_CID_CC = 0x00000000, |
322 | RMI_CID_FC = 0x00000001, |
323 | RMI_CID_CM = 0x00000002, |
324 | RMI_CID_DC = 0x00000003, |
325 | RMI_CID_Z = 0x00000004, |
326 | RMI_CID_S = 0x00000005, |
327 | RMI_CID_TILE = 0x00000006, |
328 | RMI_CID_ZPCPSD = 0x00000007, |
329 | } RMI_CID; |
330 | |
331 | /* |
332 | * WritePolicy enum |
333 | */ |
334 | |
335 | typedef enum WritePolicy { |
336 | CACHE_LRU_WR = 0x00000000, |
337 | CACHE_STREAM = 0x00000001, |
338 | CACHE_BYPASS = 0x00000002, |
339 | UNCACHED_WR = 0x00000003, |
340 | } WritePolicy; |
341 | |
342 | /* |
343 | * ReadPolicy enum |
344 | */ |
345 | |
346 | typedef enum ReadPolicy { |
347 | CACHE_LRU_RD = 0x00000000, |
348 | CACHE_NOA = 0x00000001, |
349 | UNCACHED_RD = 0x00000002, |
350 | RESERVED_RDPOLICY = 0x00000003, |
351 | } ReadPolicy; |
352 | |
353 | /* |
354 | * PERFMON_COUNTER_MODE enum |
355 | */ |
356 | |
357 | typedef enum PERFMON_COUNTER_MODE { |
358 | PERFMON_COUNTER_MODE_ACCUM = 0x00000000, |
359 | PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, |
360 | PERFMON_COUNTER_MODE_MAX = 0x00000002, |
361 | PERFMON_COUNTER_MODE_DIRTY = 0x00000003, |
362 | PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, |
363 | PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, |
364 | PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, |
365 | PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, |
366 | PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, |
367 | PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, |
368 | PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, |
369 | } PERFMON_COUNTER_MODE; |
370 | |
371 | /* |
372 | * PERFMON_SPM_MODE enum |
373 | */ |
374 | |
375 | typedef enum PERFMON_SPM_MODE { |
376 | PERFMON_SPM_MODE_OFF = 0x00000000, |
377 | PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, |
378 | PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, |
379 | PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, |
380 | PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, |
381 | PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, |
382 | PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, |
383 | PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, |
384 | PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, |
385 | PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, |
386 | PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, |
387 | } PERFMON_SPM_MODE; |
388 | |
389 | /* |
390 | * SurfaceTiling enum |
391 | */ |
392 | |
393 | typedef enum SurfaceTiling { |
394 | ARRAY_LINEAR = 0x00000000, |
395 | ARRAY_TILED = 0x00000001, |
396 | } SurfaceTiling; |
397 | |
398 | /* |
399 | * SurfaceArray enum |
400 | */ |
401 | |
402 | typedef enum SurfaceArray { |
403 | ARRAY_1D = 0x00000000, |
404 | ARRAY_2D = 0x00000001, |
405 | ARRAY_3D = 0x00000002, |
406 | ARRAY_3D_SLICE = 0x00000003, |
407 | } SurfaceArray; |
408 | |
409 | /* |
410 | * ColorArray enum |
411 | */ |
412 | |
413 | typedef enum ColorArray { |
414 | ARRAY_2D_ALT_COLOR = 0x00000000, |
415 | ARRAY_2D_COLOR = 0x00000001, |
416 | ARRAY_3D_SLICE_COLOR = 0x00000003, |
417 | } ColorArray; |
418 | |
419 | /* |
420 | * DepthArray enum |
421 | */ |
422 | |
423 | typedef enum DepthArray { |
424 | ARRAY_2D_ALT_DEPTH = 0x00000000, |
425 | ARRAY_2D_DEPTH = 0x00000001, |
426 | } DepthArray; |
427 | |
428 | /* |
429 | * ENUM_NUM_SIMD_PER_CU enum |
430 | */ |
431 | |
432 | typedef enum ENUM_NUM_SIMD_PER_CU { |
433 | NUM_SIMD_PER_CU = 0x00000002, |
434 | } ENUM_NUM_SIMD_PER_CU; |
435 | |
436 | /* |
437 | * DSM_ENABLE_ERROR_INJECT enum |
438 | */ |
439 | |
440 | typedef enum DSM_ENABLE_ERROR_INJECT { |
441 | DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, |
442 | DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, |
443 | DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, |
444 | DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, |
445 | } DSM_ENABLE_ERROR_INJECT; |
446 | |
447 | /* |
448 | * DSM_SELECT_INJECT_DELAY enum |
449 | */ |
450 | |
451 | typedef enum DSM_SELECT_INJECT_DELAY { |
452 | DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, |
453 | DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, |
454 | } DSM_SELECT_INJECT_DELAY; |
455 | |
456 | /* |
457 | * DSM_DATA_SEL enum |
458 | */ |
459 | |
460 | typedef enum DSM_DATA_SEL { |
461 | DSM_DATA_SEL_DISABLE = 0x00000000, |
462 | DSM_DATA_SEL_0 = 0x00000001, |
463 | DSM_DATA_SEL_1 = 0x00000002, |
464 | DSM_DATA_SEL_BOTH = 0x00000003, |
465 | } DSM_DATA_SEL; |
466 | |
467 | /* |
468 | * DSM_SINGLE_WRITE enum |
469 | */ |
470 | |
471 | typedef enum DSM_SINGLE_WRITE { |
472 | DSM_SINGLE_WRITE_DIS = 0x00000000, |
473 | DSM_SINGLE_WRITE_EN = 0x00000001, |
474 | } DSM_SINGLE_WRITE; |
475 | |
476 | /* |
477 | * Hdp_SurfaceEndian enum |
478 | */ |
479 | |
480 | typedef enum Hdp_SurfaceEndian { |
481 | HDP_ENDIAN_NONE = 0x00000000, |
482 | HDP_ENDIAN_8IN16 = 0x00000001, |
483 | HDP_ENDIAN_8IN32 = 0x00000002, |
484 | HDP_ENDIAN_8IN64 = 0x00000003, |
485 | } Hdp_SurfaceEndian; |
486 | |
487 | /******************************************************* |
488 | * CNVC_CFG Enums |
489 | *******************************************************/ |
490 | |
491 | /* |
492 | * CNVC_ENABLE enum |
493 | */ |
494 | |
495 | typedef enum CNVC_ENABLE { |
496 | CNVC_DIS = 0x00000000, |
497 | CNVC_EN = 0x00000001, |
498 | } CNVC_ENABLE; |
499 | |
500 | /* |
501 | * CNVC_BYPASS enum |
502 | */ |
503 | |
504 | typedef enum CNVC_BYPASS { |
505 | CNVC_BYPASS_DISABLE = 0x00000000, |
506 | CNVC_BYPASS_EN = 0x00000001, |
507 | } CNVC_BYPASS; |
508 | |
509 | /* |
510 | * CNVC_PENDING enum |
511 | */ |
512 | |
513 | typedef enum CNVC_PENDING { |
514 | CNVC_NOT_PENDING = 0x00000000, |
515 | CNVC_YES_PENDING = 0x00000001, |
516 | } CNVC_PENDING; |
517 | |
518 | /* |
519 | * DENORM_TRUNCATE enum |
520 | */ |
521 | |
522 | typedef enum DENORM_TRUNCATE { |
523 | CNVC_ROUND = 0x00000000, |
524 | CNVC_TRUNCATE = 0x00000001, |
525 | } DENORM_TRUNCATE; |
526 | |
527 | /* |
528 | * PIX_EXPAND_MODE enum |
529 | */ |
530 | |
531 | typedef enum PIX_EXPAND_MODE { |
532 | PIX_DYNAMIC_EXPANSION = 0x00000000, |
533 | PIX_ZERO_EXPANSION = 0x00000001, |
534 | } PIX_EXPAND_MODE; |
535 | |
536 | /* |
537 | * SURFACE_PIXEL_FORMAT enum |
538 | */ |
539 | |
540 | typedef enum SURFACE_PIXEL_FORMAT { |
541 | ARGB1555 = 0x00000001, |
542 | RGBA5551 = 0x00000002, |
543 | RGB565 = 0x00000003, |
544 | BGR565 = 0x00000004, |
545 | ARGB4444 = 0x00000005, |
546 | RGBA4444 = 0x00000006, |
547 | ARGB8888 = 0x00000008, |
548 | RGBA8888 = 0x00000009, |
549 | ARGB2101010 = 0x0000000a, |
550 | RGBA1010102 = 0x0000000b, |
551 | AYCrCb8888 = 0x0000000c, |
552 | YCrCbA8888 = 0x0000000d, |
553 | ACrYCb8888 = 0x0000000e, |
554 | CrYCbA8888 = 0x0000000f, |
555 | ARGB16161616_10MSB = 0x00000010, |
556 | RGBA16161616_10MSB = 0x00000011, |
557 | ARGB16161616_10LSB = 0x00000012, |
558 | RGBA16161616_10LSB = 0x00000013, |
559 | ARGB16161616_12MSB = 0x00000014, |
560 | RGBA16161616_12MSB = 0x00000015, |
561 | ARGB16161616_12LSB = 0x00000016, |
562 | RGBA16161616_12LSB = 0x00000017, |
563 | ARGB16161616_FLOAT = 0x00000018, |
564 | RGBA16161616_FLOAT = 0x00000019, |
565 | ARGB16161616_UNORM = 0x0000001a, |
566 | RGBA16161616_UNORM = 0x0000001b, |
567 | ARGB16161616_SNORM = 0x0000001c, |
568 | RGBA16161616_SNORM = 0x0000001d, |
569 | AYCrCb16161616_10MSB = 0x00000020, |
570 | AYCrCb16161616_10LSB = 0x00000021, |
571 | YCrCbA16161616_10MSB = 0x00000022, |
572 | YCrCbA16161616_10LSB = 0x00000023, |
573 | ACrYCb16161616_10MSB = 0x00000024, |
574 | ACrYCb16161616_10LSB = 0x00000025, |
575 | CrYCbA16161616_10MSB = 0x00000026, |
576 | CrYCbA16161616_10LSB = 0x00000027, |
577 | AYCrCb16161616_12MSB = 0x00000028, |
578 | AYCrCb16161616_12LSB = 0x00000029, |
579 | YCrCbA16161616_12MSB = 0x0000002a, |
580 | YCrCbA16161616_12LSB = 0x0000002b, |
581 | ACrYCb16161616_12MSB = 0x0000002c, |
582 | ACrYCb16161616_12LSB = 0x0000002d, |
583 | CrYCbA16161616_12MSB = 0x0000002e, |
584 | CrYCbA16161616_12LSB = 0x0000002f, |
585 | Y8_CrCb88_420_PLANAR = 0x00000040, |
586 | Y8_CbCr88_420_PLANAR = 0x00000041, |
587 | Y10_CrCb1010_420_PLANAR = 0x00000042, |
588 | Y10_CbCr1010_420_PLANAR = 0x00000043, |
589 | Y12_CrCb1212_420_PLANAR = 0x00000044, |
590 | Y12_CbCr1212_420_PLANAR = 0x00000045, |
591 | YCrYCb8888_422_PACKED = 0x00000048, |
592 | YCbYCr8888_422_PACKED = 0x00000049, |
593 | CrYCbY8888_422_PACKED = 0x0000004a, |
594 | CbYCrY8888_422_PACKED = 0x0000004b, |
595 | YCrYCb10101010_422_PACKED = 0x0000004c, |
596 | YCbYCr10101010_422_PACKED = 0x0000004d, |
597 | CrYCbY10101010_422_PACKED = 0x0000004e, |
598 | CbYCrY10101010_422_PACKED = 0x0000004f, |
599 | YCrYCb12121212_422_PACKED = 0x00000050, |
600 | YCbYCr12121212_422_PACKED = 0x00000051, |
601 | CrYCbY12121212_422_PACKED = 0x00000052, |
602 | CbYCrY12121212_422_PACKED = 0x00000053, |
603 | RGB111110_FIX = 0x00000070, |
604 | BGR101111_FIX = 0x00000071, |
605 | ACrYCb2101010 = 0x00000072, |
606 | CrYCbA1010102 = 0x00000073, |
607 | RGB111110_FLOAT = 0x00000076, |
608 | BGR101111_FLOAT = 0x00000077, |
609 | MONO_8 = 0x00000078, |
610 | MONO_10MSB = 0x00000079, |
611 | MONO_10LSB = 0x0000007a, |
612 | MONO_12MSB = 0x0000007b, |
613 | MONO_12LSB = 0x0000007c, |
614 | MONO_16 = 0x0000007d, |
615 | } SURFACE_PIXEL_FORMAT; |
616 | |
617 | /* |
618 | * XNORM enum |
619 | */ |
620 | |
621 | typedef enum XNORM { |
622 | XNORM_A = 0x00000000, |
623 | XNORM_B = 0x00000001, |
624 | } XNORM; |
625 | |
626 | /* |
627 | * COLOR_KEYER_MODE enum |
628 | */ |
629 | |
630 | typedef enum COLOR_KEYER_MODE { |
631 | FORCE_00 = 0x00000000, |
632 | FORCE_FF = 0x00000001, |
633 | RANGE_00 = 0x00000002, |
634 | RANGE_FF = 0x00000003, |
635 | } COLOR_KEYER_MODE; |
636 | |
637 | /******************************************************* |
638 | * CNVC_CUR Enums |
639 | *******************************************************/ |
640 | |
641 | /* |
642 | * CUR_ENABLE enum |
643 | */ |
644 | |
645 | typedef enum CUR_ENABLE { |
646 | CUR_DIS = 0x00000000, |
647 | CUR_EN = 0x00000001, |
648 | } CUR_ENABLE; |
649 | |
650 | /* |
651 | * CUR_PENDING enum |
652 | */ |
653 | |
654 | typedef enum CUR_PENDING { |
655 | CUR_NOT_PENDING = 0x00000000, |
656 | CUR_YES_PENDING = 0x00000001, |
657 | } CUR_PENDING; |
658 | |
659 | /* |
660 | * CUR_EXPAND_MODE enum |
661 | */ |
662 | |
663 | typedef enum CUR_EXPAND_MODE { |
664 | CUR_DYNAMIC_EXPANSION = 0x00000000, |
665 | CUR_ZERO_EXPANSION = 0x00000001, |
666 | } CUR_EXPAND_MODE; |
667 | |
668 | /* |
669 | * CUR_ROM_EN enum |
670 | */ |
671 | |
672 | typedef enum CUR_ROM_EN { |
673 | CUR_FP_NO_ROM = 0x00000000, |
674 | CUR_FP_USE_ROM = 0x00000001, |
675 | } CUR_ROM_EN; |
676 | |
677 | /* |
678 | * CUR_MODE enum |
679 | */ |
680 | |
681 | typedef enum CUR_MODE { |
682 | MONO_2BIT = 0x00000000, |
683 | COLOR_24BIT_1BIT_AND = 0x00000001, |
684 | COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, |
685 | COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, |
686 | COLOR_64BIT_FP_PREMULT = 0x00000004, |
687 | COLOR_64BIT_FP_UNPREMULT = 0x00000005, |
688 | } CUR_MODE; |
689 | |
690 | /* |
691 | * CUR_INV_CLAMP enum |
692 | */ |
693 | |
694 | typedef enum CUR_INV_CLAMP { |
695 | CUR_CLAMP_DIS = 0x00000000, |
696 | CUR_CLAMP_EN = 0x00000001, |
697 | } CUR_INV_CLAMP; |
698 | |
699 | /******************************************************* |
700 | * DSCL Enums |
701 | *******************************************************/ |
702 | |
703 | /* |
704 | * SCL_COEF_FILTER_TYPE_SEL enum |
705 | */ |
706 | |
707 | typedef enum SCL_COEF_FILTER_TYPE_SEL { |
708 | SCL_COEF_LUMA_VERT_FILTER = 0x00000000, |
709 | SCL_COEF_LUMA_HORZ_FILTER = 0x00000001, |
710 | SCL_COEF_CHROMA_VERT_FILTER = 0x00000002, |
711 | SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003, |
712 | SCL_COEF_ALPHA_VERT_FILTER = 0x00000004, |
713 | SCL_COEF_ALPHA_HORZ_FILTER = 0x00000005, |
714 | } SCL_COEF_FILTER_TYPE_SEL; |
715 | |
716 | /* |
717 | * DSCL_MODE_SEL enum |
718 | */ |
719 | |
720 | typedef enum DSCL_MODE_SEL { |
721 | DSCL_MODE_SCALING_444_BYPASS = 0x00000000, |
722 | DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001, |
723 | DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002, |
724 | DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003, |
725 | DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004, |
726 | DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005, |
727 | DSCL_MODE_DSCL_BYPASS = 0x00000006, |
728 | } DSCL_MODE_SEL; |
729 | |
730 | /* |
731 | * SCL_AUTOCAL_MODE enum |
732 | */ |
733 | |
734 | typedef enum SCL_AUTOCAL_MODE { |
735 | AUTOCAL_MODE_OFF = 0x00000000, |
736 | AUTOCAL_MODE_AUTOSCALE = 0x00000001, |
737 | AUTOCAL_MODE_AUTOCENTER = 0x00000002, |
738 | AUTOCAL_MODE_AUTOREPLICATE = 0x00000003, |
739 | } SCL_AUTOCAL_MODE; |
740 | |
741 | /* |
742 | * SCL_COEF_RAM_SEL enum |
743 | */ |
744 | |
745 | typedef enum SCL_COEF_RAM_SEL { |
746 | SCL_COEF_RAM_SEL_0 = 0x00000000, |
747 | SCL_COEF_RAM_SEL_1 = 0x00000001, |
748 | } SCL_COEF_RAM_SEL; |
749 | |
750 | /* |
751 | * SCL_CHROMA_COEF enum |
752 | */ |
753 | |
754 | typedef enum SCL_CHROMA_COEF { |
755 | SCL_CHROMA_COEF_LUMA = 0x00000000, |
756 | SCL_CHROMA_COEF_CHROMA = 0x00000001, |
757 | } SCL_CHROMA_COEF; |
758 | |
759 | /* |
760 | * SCL_ALPHA_COEF enum |
761 | */ |
762 | |
763 | typedef enum SCL_ALPHA_COEF { |
764 | SCL_ALPHA_COEF_LUMA = 0x00000000, |
765 | SCL_ALPHA_COEF_ALPHA = 0x00000001, |
766 | } SCL_ALPHA_COEF; |
767 | |
768 | /* |
769 | * COEF_RAM_SELECT_RD enum |
770 | */ |
771 | |
772 | typedef enum COEF_RAM_SELECT_RD { |
773 | COEF_RAM_SELECT_BACK = 0x00000000, |
774 | COEF_RAM_SELECT_CURRENT = 0x00000001, |
775 | } COEF_RAM_SELECT_RD; |
776 | |
777 | /* |
778 | * SCL_2TAP_HARDCODE enum |
779 | */ |
780 | |
781 | typedef enum SCL_2TAP_HARDCODE { |
782 | SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000, |
783 | SCL_COEF_2TAP_HARDCODE_ON = 0x00000001, |
784 | } SCL_2TAP_HARDCODE; |
785 | |
786 | /* |
787 | * SCL_SHARP_EN enum |
788 | */ |
789 | |
790 | typedef enum SCL_SHARP_EN { |
791 | SCL_SHARP_DISABLE = 0x00000000, |
792 | SCL_SHARP_ENABLE = 0x00000001, |
793 | } SCL_SHARP_EN; |
794 | |
795 | /* |
796 | * SCL_BOUNDARY enum |
797 | */ |
798 | |
799 | typedef enum SCL_BOUNDARY { |
800 | SCL_BOUNDARY_EDGE = 0x00000000, |
801 | SCL_BOUNDARY_BLACK = 0x00000001, |
802 | } SCL_BOUNDARY; |
803 | |
804 | /* |
805 | * LB_INTERLEAVE_EN enum |
806 | */ |
807 | |
808 | typedef enum LB_INTERLEAVE_EN { |
809 | LB_INTERLEAVE_DISABLE = 0x00000000, |
810 | LB_INTERLEAVE_ENABLE = 0x00000001, |
811 | } LB_INTERLEAVE_EN; |
812 | |
813 | /* |
814 | * LB_ALPHA_EN enum |
815 | */ |
816 | |
817 | typedef enum LB_ALPHA_EN { |
818 | LB_ALPHA_DISABLE = 0x00000000, |
819 | LB_ALPHA_ENABLE = 0x00000001, |
820 | } LB_ALPHA_EN; |
821 | |
822 | /* |
823 | * OBUF_BYPASS_SEL enum |
824 | */ |
825 | |
826 | typedef enum OBUF_BYPASS_SEL { |
827 | OBUF_BYPASS_DIS = 0x00000000, |
828 | OBUF_BYPASS_EN = 0x00000001, |
829 | } OBUF_BYPASS_SEL; |
830 | |
831 | /* |
832 | * OBUF_USE_FULL_BUFFER_SEL enum |
833 | */ |
834 | |
835 | typedef enum OBUF_USE_FULL_BUFFER_SEL { |
836 | OBUF_RECOUT = 0x00000000, |
837 | OBUF_FULL = 0x00000001, |
838 | } OBUF_USE_FULL_BUFFER_SEL; |
839 | |
840 | /* |
841 | * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum |
842 | */ |
843 | |
844 | typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL { |
845 | OBUF_FULL_RECOUT = 0x00000000, |
846 | OBUF_HALF_RECOUT = 0x00000001, |
847 | } OBUF_IS_HALF_RECOUT_WIDTH_SEL; |
848 | |
849 | /******************************************************* |
850 | * CM Enums |
851 | *******************************************************/ |
852 | |
853 | /* |
854 | * CM_BYPASS enum |
855 | */ |
856 | |
857 | typedef enum CM_BYPASS { |
858 | NON_BYPASS = 0x00000000, |
859 | BYPASS_EN = 0x00000001, |
860 | } CM_BYPASS; |
861 | |
862 | /* |
863 | * CM_EN enum |
864 | */ |
865 | |
866 | typedef enum CM_EN { |
867 | CM_DISABLE = 0x00000000, |
868 | CM_ENABLE = 0x00000001, |
869 | } CM_EN; |
870 | |
871 | /* |
872 | * CM_PENDING enum |
873 | */ |
874 | |
875 | typedef enum CM_PENDING { |
876 | CM_NOT_PENDING = 0x00000000, |
877 | CM_YES_PENDING = 0x00000001, |
878 | } CM_PENDING; |
879 | |
880 | /* |
881 | * CM_DATA_SIGNED enum |
882 | */ |
883 | |
884 | typedef enum CM_DATA_SIGNED { |
885 | UNSIGNED = 0x00000000, |
886 | SIGNED = 0x00000001, |
887 | } CM_DATA_SIGNED; |
888 | |
889 | /* |
890 | * CM_WRITE_BASE_ONLY enum |
891 | */ |
892 | |
893 | typedef enum CM_WRITE_BASE_ONLY { |
894 | WRITE_BOTH = 0x00000000, |
895 | WRITE_BASE_ONLY = 0x00000001, |
896 | } CM_WRITE_BASE_ONLY; |
897 | |
898 | /* |
899 | * CM_LUT_4_CONFIG_ENUM enum |
900 | */ |
901 | |
902 | typedef enum CM_LUT_4_CONFIG_ENUM { |
903 | LUT_4CFG_NO_MEMORY = 0x00000000, |
904 | LUT_4CFG_ROM_A = 0x00000001, |
905 | LUT_4CFG_ROM_B = 0x00000002, |
906 | LUT_4CFG_MEMORY_A = 0x00000003, |
907 | LUT_4CFG_MEMORY_B = 0x00000004, |
908 | } CM_LUT_4_CONFIG_ENUM; |
909 | |
910 | /* |
911 | * CM_LUT_2_CONFIG_ENUM enum |
912 | */ |
913 | |
914 | typedef enum CM_LUT_2_CONFIG_ENUM { |
915 | LUT_2CFG_NO_MEMORY = 0x00000000, |
916 | LUT_2CFG_MEMORY_A = 0x00000001, |
917 | LUT_2CFG_MEMORY_B = 0x00000002, |
918 | } CM_LUT_2_CONFIG_ENUM; |
919 | |
920 | /* |
921 | * CM_LUT_4_MODE_ENUM enum |
922 | */ |
923 | |
924 | typedef enum CM_LUT_4_MODE_ENUM { |
925 | LUT_4_MODE_BYPASS = 0x00000000, |
926 | LUT_4_MODE_ROMA_LUT = 0x00000001, |
927 | LUT_4_MODE_ROMB_LUT = 0x00000002, |
928 | LUT_4_MODE_RAMA_LUT = 0x00000003, |
929 | LUT_4_MODE_RAMB_LUT = 0x00000004, |
930 | } CM_LUT_4_MODE_ENUM; |
931 | |
932 | /* |
933 | * CM_LUT_2_MODE_ENUM enum |
934 | */ |
935 | |
936 | typedef enum CM_LUT_2_MODE_ENUM { |
937 | LUT_2_MODE_BYPASS = 0x00000000, |
938 | LUT_2_MODE_RAMA_LUT = 0x00000001, |
939 | LUT_2_MODE_RAMB_LUT = 0x00000002, |
940 | } CM_LUT_2_MODE_ENUM; |
941 | |
942 | /* |
943 | * CM_LUT_RAM_SEL enum |
944 | */ |
945 | |
946 | typedef enum CM_LUT_RAM_SEL { |
947 | RAMA_ACCESS = 0x00000000, |
948 | RAMB_ACCESS = 0x00000001, |
949 | } CM_LUT_RAM_SEL; |
950 | |
951 | /* |
952 | * CM_LUT_NUM_SEG enum |
953 | */ |
954 | |
955 | typedef enum CM_LUT_NUM_SEG { |
956 | SEGMENTS_1 = 0x00000000, |
957 | SEGMENTS_2 = 0x00000001, |
958 | SEGMENTS_4 = 0x00000002, |
959 | SEGMENTS_8 = 0x00000003, |
960 | SEGMENTS_16 = 0x00000004, |
961 | SEGMENTS_32 = 0x00000005, |
962 | SEGMENTS_64 = 0x00000006, |
963 | SEGMENTS_128 = 0x00000007, |
964 | } CM_LUT_NUM_SEG; |
965 | |
966 | /* |
967 | * CM_ICSC_MODE_ENUM enum |
968 | */ |
969 | |
970 | typedef enum CM_ICSC_MODE_ENUM { |
971 | BYPASS_ICSC = 0x00000000, |
972 | COEF_ICSC = 0x00000001, |
973 | COEF_ICSC_B = 0x00000002, |
974 | } CM_ICSC_MODE_ENUM; |
975 | |
976 | /* |
977 | * CM_GAMUT_REMAP_MODE_ENUM enum |
978 | */ |
979 | |
980 | typedef enum CM_GAMUT_REMAP_MODE_ENUM { |
981 | BYPASS_GAMUT = 0x00000000, |
982 | GAMUT_COEF = 0x00000001, |
983 | GAMUT_COEF_B = 0x00000002, |
984 | } CM_GAMUT_REMAP_MODE_ENUM; |
985 | |
986 | /* |
987 | * CM_COEF_FORMAT_ENUM enum |
988 | */ |
989 | |
990 | typedef enum CM_COEF_FORMAT_ENUM { |
991 | FIX_S2_13 = 0x00000000, |
992 | FIX_S3_12 = 0x00000001, |
993 | } CM_COEF_FORMAT_ENUM; |
994 | |
995 | /* |
996 | * CMC_LUT_2_CONFIG_ENUM enum |
997 | */ |
998 | |
999 | typedef enum CMC_LUT_2_CONFIG_ENUM { |
1000 | CMC_LUT_2CFG_NO_MEMORY = 0x00000000, |
1001 | CMC_LUT_2CFG_MEMORY_A = 0x00000001, |
1002 | CMC_LUT_2CFG_MEMORY_B = 0x00000002, |
1003 | } CMC_LUT_2_CONFIG_ENUM; |
1004 | |
1005 | /* |
1006 | * CMC_LUT_2_MODE_ENUM enum |
1007 | */ |
1008 | |
1009 | typedef enum CMC_LUT_2_MODE_ENUM { |
1010 | CMC_LUT_2_MODE_BYPASS = 0x00000000, |
1011 | CMC_LUT_2_MODE_RAMA_LUT = 0x00000001, |
1012 | CMC_LUT_2_MODE_RAMB_LUT = 0x00000002, |
1013 | } CMC_LUT_2_MODE_ENUM; |
1014 | |
1015 | /* |
1016 | * CMC_LUT_RAM_SEL enum |
1017 | */ |
1018 | |
1019 | typedef enum CMC_LUT_RAM_SEL { |
1020 | CMC_RAMA_ACCESS = 0x00000000, |
1021 | CMC_RAMB_ACCESS = 0x00000001, |
1022 | } CMC_LUT_RAM_SEL; |
1023 | |
1024 | /* |
1025 | * CMC_3DLUT_RAM_SEL enum |
1026 | */ |
1027 | |
1028 | typedef enum CMC_3DLUT_RAM_SEL { |
1029 | CMC_RAM0_ACCESS = 0x00000000, |
1030 | CMC_RAM1_ACCESS = 0x00000001, |
1031 | CMC_RAM2_ACCESS = 0x00000002, |
1032 | CMC_RAM3_ACCESS = 0x00000003, |
1033 | } CMC_3DLUT_RAM_SEL; |
1034 | |
1035 | /* |
1036 | * CMC_LUT_NUM_SEG enum |
1037 | */ |
1038 | |
1039 | typedef enum CMC_LUT_NUM_SEG { |
1040 | CMC_SEGMENTS_1 = 0x00000000, |
1041 | CMC_SEGMENTS_2 = 0x00000001, |
1042 | CMC_SEGMENTS_4 = 0x00000002, |
1043 | CMC_SEGMENTS_8 = 0x00000003, |
1044 | CMC_SEGMENTS_16 = 0x00000004, |
1045 | CMC_SEGMENTS_32 = 0x00000005, |
1046 | CMC_SEGMENTS_64 = 0x00000006, |
1047 | CMC_SEGMENTS_128 = 0x00000007, |
1048 | } CMC_LUT_NUM_SEG; |
1049 | |
1050 | /* |
1051 | * CMC_3DLUT_30BIT_ENUM enum |
1052 | */ |
1053 | |
1054 | typedef enum CMC_3DLUT_30BIT_ENUM { |
1055 | CMC_3DLUT_36BIT = 0x00000000, |
1056 | CMC_3DLUT_30BIT = 0x00000001, |
1057 | } CMC_3DLUT_30BIT_ENUM; |
1058 | |
1059 | /* |
1060 | * CMC_3DLUT_SIZE_ENUM enum |
1061 | */ |
1062 | |
1063 | typedef enum CMC_3DLUT_SIZE_ENUM { |
1064 | CMC_3DLUT_17CUBE = 0x00000000, |
1065 | CMC_3DLUT_9CUBE = 0x00000001, |
1066 | } CMC_3DLUT_SIZE_ENUM; |
1067 | |
1068 | /******************************************************* |
1069 | * DPP_TOP Enums |
1070 | *******************************************************/ |
1071 | |
1072 | /* |
1073 | * TEST_CLK_SEL enum |
1074 | */ |
1075 | |
1076 | typedef enum TEST_CLK_SEL { |
1077 | TEST_CLK_SEL_0 = 0x00000000, |
1078 | TEST_CLK_SEL_1 = 0x00000001, |
1079 | TEST_CLK_SEL_2 = 0x00000002, |
1080 | TEST_CLK_SEL_3 = 0x00000003, |
1081 | TEST_CLK_SEL_4 = 0x00000004, |
1082 | TEST_CLK_SEL_5 = 0x00000005, |
1083 | TEST_CLK_SEL_6 = 0x00000006, |
1084 | TEST_CLK_SEL_7 = 0x00000007, |
1085 | TEST_CLK_SEL_8 = 0x00000008, |
1086 | } TEST_CLK_SEL; |
1087 | |
1088 | /* |
1089 | * CRC_SRC_SEL enum |
1090 | */ |
1091 | |
1092 | typedef enum CRC_SRC_SEL { |
1093 | CRC_SRC_0 = 0x00000000, |
1094 | CRC_SRC_1 = 0x00000001, |
1095 | CRC_SRC_2 = 0x00000002, |
1096 | CRC_SRC_3 = 0x00000003, |
1097 | } CRC_SRC_SEL; |
1098 | |
1099 | /* |
1100 | * CRC_IN_PIX_SEL enum |
1101 | */ |
1102 | |
1103 | typedef enum CRC_IN_PIX_SEL { |
1104 | CRC_IN_PIX_0 = 0x00000000, |
1105 | CRC_IN_PIX_1 = 0x00000001, |
1106 | CRC_IN_PIX_2 = 0x00000002, |
1107 | CRC_IN_PIX_3 = 0x00000003, |
1108 | CRC_IN_PIX_4 = 0x00000004, |
1109 | CRC_IN_PIX_5 = 0x00000005, |
1110 | CRC_IN_PIX_6 = 0x00000006, |
1111 | CRC_IN_PIX_7 = 0x00000007, |
1112 | } CRC_IN_PIX_SEL; |
1113 | |
1114 | /* |
1115 | * CRC_CUR_BITS_SEL enum |
1116 | */ |
1117 | |
1118 | typedef enum CRC_CUR_BITS_SEL { |
1119 | CRC_CUR_BITS_0 = 0x00000000, |
1120 | CRC_CUR_BITS_1 = 0x00000001, |
1121 | } CRC_CUR_BITS_SEL; |
1122 | |
1123 | /* |
1124 | * CRC_IN_CUR_SEL enum |
1125 | */ |
1126 | |
1127 | typedef enum CRC_IN_CUR_SEL { |
1128 | CRC_IN_CUR_0 = 0x00000000, |
1129 | CRC_IN_CUR_1 = 0x00000001, |
1130 | } CRC_IN_CUR_SEL; |
1131 | |
1132 | /* |
1133 | * CRC_CUR_SEL enum |
1134 | */ |
1135 | |
1136 | typedef enum CRC_CUR_SEL { |
1137 | CRC_CUR_0 = 0x00000000, |
1138 | CRC_CUR_1 = 0x00000001, |
1139 | } CRC_CUR_SEL; |
1140 | |
1141 | /* |
1142 | * CRC_STEREO_SEL enum |
1143 | */ |
1144 | |
1145 | typedef enum CRC_STEREO_SEL { |
1146 | CRC_STEREO_0 = 0x00000000, |
1147 | CRC_STEREO_1 = 0x00000001, |
1148 | CRC_STEREO_2 = 0x00000002, |
1149 | CRC_STEREO_3 = 0x00000003, |
1150 | } CRC_STEREO_SEL; |
1151 | |
1152 | /* |
1153 | * CRC_INTERLACE_SEL enum |
1154 | */ |
1155 | |
1156 | typedef enum CRC_INTERLACE_SEL { |
1157 | CRC_INTERLACE_0 = 0x00000000, |
1158 | CRC_INTERLACE_1 = 0x00000001, |
1159 | CRC_INTERLACE_2 = 0x00000002, |
1160 | CRC_INTERLACE_3 = 0x00000003, |
1161 | } CRC_INTERLACE_SEL; |
1162 | |
1163 | /******************************************************* |
1164 | * DC_PERFMON Enums |
1165 | *******************************************************/ |
1166 | |
1167 | /* |
1168 | * PERFCOUNTER_CVALUE_SEL enum |
1169 | */ |
1170 | |
1171 | typedef enum PERFCOUNTER_CVALUE_SEL { |
1172 | PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000, |
1173 | PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001, |
1174 | PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002, |
1175 | PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003, |
1176 | PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004, |
1177 | PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005, |
1178 | PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006, |
1179 | PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007, |
1180 | } PERFCOUNTER_CVALUE_SEL; |
1181 | |
1182 | /* |
1183 | * PERFCOUNTER_INC_MODE enum |
1184 | */ |
1185 | |
1186 | typedef enum PERFCOUNTER_INC_MODE { |
1187 | PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000, |
1188 | PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001, |
1189 | PERFCOUNTER_INC_MODE_LSB = 0x00000002, |
1190 | PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003, |
1191 | PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004, |
1192 | } PERFCOUNTER_INC_MODE; |
1193 | |
1194 | /* |
1195 | * PERFCOUNTER_HW_CNTL_SEL enum |
1196 | */ |
1197 | |
1198 | typedef enum PERFCOUNTER_HW_CNTL_SEL { |
1199 | PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000, |
1200 | PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001, |
1201 | } PERFCOUNTER_HW_CNTL_SEL; |
1202 | |
1203 | /* |
1204 | * PERFCOUNTER_RUNEN_MODE enum |
1205 | */ |
1206 | |
1207 | typedef enum PERFCOUNTER_RUNEN_MODE { |
1208 | PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000, |
1209 | PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001, |
1210 | } PERFCOUNTER_RUNEN_MODE; |
1211 | |
1212 | /* |
1213 | * PERFCOUNTER_CNTOFF_START_DIS enum |
1214 | */ |
1215 | |
1216 | typedef enum PERFCOUNTER_CNTOFF_START_DIS { |
1217 | PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000, |
1218 | PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001, |
1219 | } PERFCOUNTER_CNTOFF_START_DIS; |
1220 | |
1221 | /* |
1222 | * PERFCOUNTER_RESTART_EN enum |
1223 | */ |
1224 | |
1225 | typedef enum PERFCOUNTER_RESTART_EN { |
1226 | PERFCOUNTER_RESTART_DISABLE = 0x00000000, |
1227 | PERFCOUNTER_RESTART_ENABLE = 0x00000001, |
1228 | } PERFCOUNTER_RESTART_EN; |
1229 | |
1230 | /* |
1231 | * PERFCOUNTER_INT_EN enum |
1232 | */ |
1233 | |
1234 | typedef enum PERFCOUNTER_INT_EN { |
1235 | PERFCOUNTER_INT_DISABLE = 0x00000000, |
1236 | PERFCOUNTER_INT_ENABLE = 0x00000001, |
1237 | } PERFCOUNTER_INT_EN; |
1238 | |
1239 | /* |
1240 | * PERFCOUNTER_OFF_MASK enum |
1241 | */ |
1242 | |
1243 | typedef enum PERFCOUNTER_OFF_MASK { |
1244 | PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000, |
1245 | PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001, |
1246 | } PERFCOUNTER_OFF_MASK; |
1247 | |
1248 | /* |
1249 | * PERFCOUNTER_ACTIVE enum |
1250 | */ |
1251 | |
1252 | typedef enum PERFCOUNTER_ACTIVE { |
1253 | PERFCOUNTER_IS_IDLE = 0x00000000, |
1254 | PERFCOUNTER_IS_ACTIVE = 0x00000001, |
1255 | } PERFCOUNTER_ACTIVE; |
1256 | |
1257 | /* |
1258 | * PERFCOUNTER_INT_TYPE enum |
1259 | */ |
1260 | |
1261 | typedef enum PERFCOUNTER_INT_TYPE { |
1262 | PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000, |
1263 | PERFCOUNTER_INT_TYPE_PULSE = 0x00000001, |
1264 | } PERFCOUNTER_INT_TYPE; |
1265 | |
1266 | /* |
1267 | * PERFCOUNTER_COUNTED_VALUE_TYPE enum |
1268 | */ |
1269 | |
1270 | typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { |
1271 | PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000, |
1272 | PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001, |
1273 | PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002, |
1274 | } PERFCOUNTER_COUNTED_VALUE_TYPE; |
1275 | |
1276 | /* |
1277 | * PERFCOUNTER_HW_STOP1_SEL enum |
1278 | */ |
1279 | |
1280 | typedef enum PERFCOUNTER_HW_STOP1_SEL { |
1281 | PERFCOUNTER_HW_STOP1_0 = 0x00000000, |
1282 | PERFCOUNTER_HW_STOP1_1 = 0x00000001, |
1283 | } PERFCOUNTER_HW_STOP1_SEL; |
1284 | |
1285 | /* |
1286 | * PERFCOUNTER_HW_STOP2_SEL enum |
1287 | */ |
1288 | |
1289 | typedef enum PERFCOUNTER_HW_STOP2_SEL { |
1290 | PERFCOUNTER_HW_STOP2_0 = 0x00000000, |
1291 | PERFCOUNTER_HW_STOP2_1 = 0x00000001, |
1292 | } PERFCOUNTER_HW_STOP2_SEL; |
1293 | |
1294 | /* |
1295 | * PERFCOUNTER_CNTL_SEL enum |
1296 | */ |
1297 | |
1298 | typedef enum PERFCOUNTER_CNTL_SEL { |
1299 | PERFCOUNTER_CNTL_SEL_0 = 0x00000000, |
1300 | PERFCOUNTER_CNTL_SEL_1 = 0x00000001, |
1301 | PERFCOUNTER_CNTL_SEL_2 = 0x00000002, |
1302 | PERFCOUNTER_CNTL_SEL_3 = 0x00000003, |
1303 | PERFCOUNTER_CNTL_SEL_4 = 0x00000004, |
1304 | PERFCOUNTER_CNTL_SEL_5 = 0x00000005, |
1305 | PERFCOUNTER_CNTL_SEL_6 = 0x00000006, |
1306 | PERFCOUNTER_CNTL_SEL_7 = 0x00000007, |
1307 | } PERFCOUNTER_CNTL_SEL; |
1308 | |
1309 | /* |
1310 | * PERFCOUNTER_CNT0_STATE enum |
1311 | */ |
1312 | |
1313 | typedef enum PERFCOUNTER_CNT0_STATE { |
1314 | PERFCOUNTER_CNT0_STATE_RESET = 0x00000000, |
1315 | PERFCOUNTER_CNT0_STATE_START = 0x00000001, |
1316 | PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002, |
1317 | PERFCOUNTER_CNT0_STATE_HW = 0x00000003, |
1318 | } PERFCOUNTER_CNT0_STATE; |
1319 | |
1320 | /* |
1321 | * PERFCOUNTER_STATE_SEL0 enum |
1322 | */ |
1323 | |
1324 | typedef enum PERFCOUNTER_STATE_SEL0 { |
1325 | PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000, |
1326 | PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001, |
1327 | } PERFCOUNTER_STATE_SEL0; |
1328 | |
1329 | /* |
1330 | * PERFCOUNTER_CNT1_STATE enum |
1331 | */ |
1332 | |
1333 | typedef enum PERFCOUNTER_CNT1_STATE { |
1334 | PERFCOUNTER_CNT1_STATE_RESET = 0x00000000, |
1335 | PERFCOUNTER_CNT1_STATE_START = 0x00000001, |
1336 | PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002, |
1337 | PERFCOUNTER_CNT1_STATE_HW = 0x00000003, |
1338 | } PERFCOUNTER_CNT1_STATE; |
1339 | |
1340 | /* |
1341 | * PERFCOUNTER_STATE_SEL1 enum |
1342 | */ |
1343 | |
1344 | typedef enum PERFCOUNTER_STATE_SEL1 { |
1345 | PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000, |
1346 | PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001, |
1347 | } PERFCOUNTER_STATE_SEL1; |
1348 | |
1349 | /* |
1350 | * PERFCOUNTER_CNT2_STATE enum |
1351 | */ |
1352 | |
1353 | typedef enum PERFCOUNTER_CNT2_STATE { |
1354 | PERFCOUNTER_CNT2_STATE_RESET = 0x00000000, |
1355 | PERFCOUNTER_CNT2_STATE_START = 0x00000001, |
1356 | PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002, |
1357 | PERFCOUNTER_CNT2_STATE_HW = 0x00000003, |
1358 | } PERFCOUNTER_CNT2_STATE; |
1359 | |
1360 | /* |
1361 | * PERFCOUNTER_STATE_SEL2 enum |
1362 | */ |
1363 | |
1364 | typedef enum PERFCOUNTER_STATE_SEL2 { |
1365 | PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000, |
1366 | PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001, |
1367 | } PERFCOUNTER_STATE_SEL2; |
1368 | |
1369 | /* |
1370 | * PERFCOUNTER_CNT3_STATE enum |
1371 | */ |
1372 | |
1373 | typedef enum PERFCOUNTER_CNT3_STATE { |
1374 | PERFCOUNTER_CNT3_STATE_RESET = 0x00000000, |
1375 | PERFCOUNTER_CNT3_STATE_START = 0x00000001, |
1376 | PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002, |
1377 | PERFCOUNTER_CNT3_STATE_HW = 0x00000003, |
1378 | } PERFCOUNTER_CNT3_STATE; |
1379 | |
1380 | /* |
1381 | * PERFCOUNTER_STATE_SEL3 enum |
1382 | */ |
1383 | |
1384 | typedef enum PERFCOUNTER_STATE_SEL3 { |
1385 | PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000, |
1386 | PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001, |
1387 | } PERFCOUNTER_STATE_SEL3; |
1388 | |
1389 | /* |
1390 | * PERFCOUNTER_CNT4_STATE enum |
1391 | */ |
1392 | |
1393 | typedef enum PERFCOUNTER_CNT4_STATE { |
1394 | PERFCOUNTER_CNT4_STATE_RESET = 0x00000000, |
1395 | PERFCOUNTER_CNT4_STATE_START = 0x00000001, |
1396 | PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002, |
1397 | PERFCOUNTER_CNT4_STATE_HW = 0x00000003, |
1398 | } PERFCOUNTER_CNT4_STATE; |
1399 | |
1400 | /* |
1401 | * PERFCOUNTER_STATE_SEL4 enum |
1402 | */ |
1403 | |
1404 | typedef enum PERFCOUNTER_STATE_SEL4 { |
1405 | PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000, |
1406 | PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001, |
1407 | } PERFCOUNTER_STATE_SEL4; |
1408 | |
1409 | /* |
1410 | * PERFCOUNTER_CNT5_STATE enum |
1411 | */ |
1412 | |
1413 | typedef enum PERFCOUNTER_CNT5_STATE { |
1414 | PERFCOUNTER_CNT5_STATE_RESET = 0x00000000, |
1415 | PERFCOUNTER_CNT5_STATE_START = 0x00000001, |
1416 | PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002, |
1417 | PERFCOUNTER_CNT5_STATE_HW = 0x00000003, |
1418 | } PERFCOUNTER_CNT5_STATE; |
1419 | |
1420 | /* |
1421 | * PERFCOUNTER_STATE_SEL5 enum |
1422 | */ |
1423 | |
1424 | typedef enum PERFCOUNTER_STATE_SEL5 { |
1425 | PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000, |
1426 | PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001, |
1427 | } PERFCOUNTER_STATE_SEL5; |
1428 | |
1429 | /* |
1430 | * PERFCOUNTER_CNT6_STATE enum |
1431 | */ |
1432 | |
1433 | typedef enum PERFCOUNTER_CNT6_STATE { |
1434 | PERFCOUNTER_CNT6_STATE_RESET = 0x00000000, |
1435 | PERFCOUNTER_CNT6_STATE_START = 0x00000001, |
1436 | PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002, |
1437 | PERFCOUNTER_CNT6_STATE_HW = 0x00000003, |
1438 | } PERFCOUNTER_CNT6_STATE; |
1439 | |
1440 | /* |
1441 | * PERFCOUNTER_STATE_SEL6 enum |
1442 | */ |
1443 | |
1444 | typedef enum PERFCOUNTER_STATE_SEL6 { |
1445 | PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000, |
1446 | PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001, |
1447 | } PERFCOUNTER_STATE_SEL6; |
1448 | |
1449 | /* |
1450 | * PERFCOUNTER_CNT7_STATE enum |
1451 | */ |
1452 | |
1453 | typedef enum PERFCOUNTER_CNT7_STATE { |
1454 | PERFCOUNTER_CNT7_STATE_RESET = 0x00000000, |
1455 | PERFCOUNTER_CNT7_STATE_START = 0x00000001, |
1456 | PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002, |
1457 | PERFCOUNTER_CNT7_STATE_HW = 0x00000003, |
1458 | } PERFCOUNTER_CNT7_STATE; |
1459 | |
1460 | /* |
1461 | * PERFCOUNTER_STATE_SEL7 enum |
1462 | */ |
1463 | |
1464 | typedef enum PERFCOUNTER_STATE_SEL7 { |
1465 | PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000, |
1466 | PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001, |
1467 | } PERFCOUNTER_STATE_SEL7; |
1468 | |
1469 | /* |
1470 | * PERFMON_STATE enum |
1471 | */ |
1472 | |
1473 | typedef enum PERFMON_STATE { |
1474 | PERFMON_STATE_RESET = 0x00000000, |
1475 | PERFMON_STATE_START = 0x00000001, |
1476 | PERFMON_STATE_FREEZE = 0x00000002, |
1477 | PERFMON_STATE_HW = 0x00000003, |
1478 | } PERFMON_STATE; |
1479 | |
1480 | /* |
1481 | * PERFMON_CNTOFF_AND_OR enum |
1482 | */ |
1483 | |
1484 | typedef enum PERFMON_CNTOFF_AND_OR { |
1485 | PERFMON_CNTOFF_OR = 0x00000000, |
1486 | PERFMON_CNTOFF_AND = 0x00000001, |
1487 | } PERFMON_CNTOFF_AND_OR; |
1488 | |
1489 | /* |
1490 | * PERFMON_CNTOFF_INT_EN enum |
1491 | */ |
1492 | |
1493 | typedef enum PERFMON_CNTOFF_INT_EN { |
1494 | PERFMON_CNTOFF_INT_DISABLE = 0x00000000, |
1495 | PERFMON_CNTOFF_INT_ENABLE = 0x00000001, |
1496 | } PERFMON_CNTOFF_INT_EN; |
1497 | |
1498 | /* |
1499 | * PERFMON_CNTOFF_INT_TYPE enum |
1500 | */ |
1501 | |
1502 | typedef enum PERFMON_CNTOFF_INT_TYPE { |
1503 | PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000, |
1504 | PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001, |
1505 | } PERFMON_CNTOFF_INT_TYPE; |
1506 | |
1507 | /******************************************************* |
1508 | * HUBP Enums |
1509 | *******************************************************/ |
1510 | |
1511 | /* |
1512 | * ROTATION_ANGLE enum |
1513 | */ |
1514 | |
1515 | typedef enum ROTATION_ANGLE { |
1516 | ROTATE_0_DEGREES = 0x00000000, |
1517 | ROTATE_90_DEGREES = 0x00000001, |
1518 | ROTATE_180_DEGREES = 0x00000002, |
1519 | ROTATE_270_DEGREES = 0x00000003, |
1520 | } ROTATION_ANGLE; |
1521 | |
1522 | /* |
1523 | * H_MIRROR_EN enum |
1524 | */ |
1525 | |
1526 | typedef enum H_MIRROR_EN { |
1527 | HW_MIRRORING_DISABLE = 0x00000000, |
1528 | HW_MIRRORING_ENABLE = 0x00000001, |
1529 | } H_MIRROR_EN; |
1530 | |
1531 | /* |
1532 | * NUM_PIPES enum |
1533 | */ |
1534 | |
1535 | typedef enum NUM_PIPES { |
1536 | ONE_PIPE = 0x00000000, |
1537 | TWO_PIPES = 0x00000001, |
1538 | FOUR_PIPES = 0x00000002, |
1539 | EIGHT_PIPES = 0x00000003, |
1540 | SIXTEEN_PIPES = 0x00000004, |
1541 | THIRTY_TWO_PIPES = 0x00000005, |
1542 | SIXTY_FOUR_PIPES = 0x00000006, |
1543 | } NUM_PIPES; |
1544 | |
1545 | /* |
1546 | * NUM_BANKS enum |
1547 | */ |
1548 | |
1549 | typedef enum NUM_BANKS { |
1550 | ONE_BANK = 0x00000000, |
1551 | TWO_BANKS = 0x00000001, |
1552 | FOUR_BANKS = 0x00000002, |
1553 | EIGHT_BANKS = 0x00000003, |
1554 | SIXTEEN_BANKS = 0x00000004, |
1555 | } NUM_BANKS; |
1556 | |
1557 | /* |
1558 | * SW_MODE enum |
1559 | */ |
1560 | |
1561 | typedef enum SW_MODE { |
1562 | SWIZZLE_LINEAR = 0x00000000, |
1563 | SWIZZLE_4KB_S = 0x00000005, |
1564 | SWIZZLE_4KB_D = 0x00000006, |
1565 | SWIZZLE_64KB_S = 0x00000009, |
1566 | SWIZZLE_64KB_D = 0x0000000a, |
1567 | SWIZZLE_VAR_S = 0x0000000d, |
1568 | SWIZZLE_VAR_D = 0x0000000e, |
1569 | SWIZZLE_64KB_S_T = 0x00000011, |
1570 | SWIZZLE_64KB_D_T = 0x00000012, |
1571 | SWIZZLE_4KB_S_X = 0x00000015, |
1572 | SWIZZLE_4KB_D_X = 0x00000016, |
1573 | SWIZZLE_64KB_S_X = 0x00000019, |
1574 | SWIZZLE_64KB_D_X = 0x0000001a, |
1575 | SWIZZLE_64KB_R_X = 0x0000001b, |
1576 | SWIZZLE_VAR_S_X = 0x0000001d, |
1577 | SWIZZLE_VAR_D_X = 0x0000001e, |
1578 | } SW_MODE; |
1579 | |
1580 | /* |
1581 | * PIPE_INTERLEAVE enum |
1582 | */ |
1583 | |
1584 | typedef enum PIPE_INTERLEAVE { |
1585 | PIPE_INTERLEAVE_256B = 0x00000000, |
1586 | PIPE_INTERLEAVE_512B = 0x00000001, |
1587 | PIPE_INTERLEAVE_1KB = 0x00000002, |
1588 | } PIPE_INTERLEAVE; |
1589 | |
1590 | /* |
1591 | * LEGACY_PIPE_INTERLEAVE enum |
1592 | */ |
1593 | |
1594 | typedef enum LEGACY_PIPE_INTERLEAVE { |
1595 | LEGACY_PIPE_INTERLEAVE_256B = 0x00000000, |
1596 | LEGACY_PIPE_INTERLEAVE_512B = 0x00000001, |
1597 | } LEGACY_PIPE_INTERLEAVE; |
1598 | |
1599 | /* |
1600 | * NUM_SE enum |
1601 | */ |
1602 | |
1603 | typedef enum NUM_SE { |
1604 | ONE_SHADER_ENGIN = 0x00000000, |
1605 | TWO_SHADER_ENGINS = 0x00000001, |
1606 | FOUR_SHADER_ENGINS = 0x00000002, |
1607 | EIGHT_SHADER_ENGINS = 0x00000003, |
1608 | } NUM_SE; |
1609 | |
1610 | /* |
1611 | * NUM_RB_PER_SE enum |
1612 | */ |
1613 | |
1614 | typedef enum NUM_RB_PER_SE { |
1615 | ONE_RB_PER_SE = 0x00000000, |
1616 | TWO_RB_PER_SE = 0x00000001, |
1617 | FOUR_RB_PER_SE = 0x00000002, |
1618 | } NUM_RB_PER_SE; |
1619 | |
1620 | /* |
1621 | * MAX_COMPRESSED_FRAGS enum |
1622 | */ |
1623 | |
1624 | typedef enum MAX_COMPRESSED_FRAGS { |
1625 | ONE_FRAGMENT = 0x00000000, |
1626 | TWO_FRAGMENTS = 0x00000001, |
1627 | FOUR_FRAGMENTS = 0x00000002, |
1628 | EIGHT_FRAGMENTS = 0x00000003, |
1629 | } MAX_COMPRESSED_FRAGS; |
1630 | |
1631 | /* |
1632 | * DIM_TYPE enum |
1633 | */ |
1634 | |
1635 | typedef enum DIM_TYPE { |
1636 | DIM_TYPE_1D = 0x00000000, |
1637 | DIM_TYPE_2D = 0x00000001, |
1638 | DIM_TYPE_3D = 0x00000002, |
1639 | DIM_TYPE_RESERVED = 0x00000003, |
1640 | } DIM_TYPE; |
1641 | |
1642 | /* |
1643 | * META_LINEAR enum |
1644 | */ |
1645 | |
1646 | typedef enum META_LINEAR { |
1647 | META_SURF_TILED = 0x00000000, |
1648 | META_SURF_LINEAR = 0x00000001, |
1649 | } META_LINEAR; |
1650 | |
1651 | /* |
1652 | * RB_ALIGNED enum |
1653 | */ |
1654 | |
1655 | typedef enum RB_ALIGNED { |
1656 | RB_UNALIGNED_META_SURF = 0x00000000, |
1657 | RB_ALIGNED_META_SURF = 0x00000001, |
1658 | } RB_ALIGNED; |
1659 | |
1660 | /* |
1661 | * PIPE_ALIGNED enum |
1662 | */ |
1663 | |
1664 | typedef enum PIPE_ALIGNED { |
1665 | PIPE_UNALIGNED_SURF = 0x00000000, |
1666 | PIPE_ALIGNED_SURF = 0x00000001, |
1667 | } PIPE_ALIGNED; |
1668 | |
1669 | /* |
1670 | * ARRAY_MODE enum |
1671 | */ |
1672 | |
1673 | typedef enum ARRAY_MODE { |
1674 | AM_LINEAR_GENERAL = 0x00000000, |
1675 | AM_LINEAR_ALIGNED = 0x00000001, |
1676 | AM_1D_TILED_THIN1 = 0x00000002, |
1677 | AM_1D_TILED_THICK = 0x00000003, |
1678 | AM_2D_TILED_THIN1 = 0x00000004, |
1679 | AM_PRT_TILED_THIN1 = 0x00000005, |
1680 | AM_PRT_2D_TILED_THIN1 = 0x00000006, |
1681 | AM_2D_TILED_THICK = 0x00000007, |
1682 | AM_2D_TILED_XTHICK = 0x00000008, |
1683 | AM_PRT_TILED_THICK = 0x00000009, |
1684 | AM_PRT_2D_TILED_THICK = 0x0000000a, |
1685 | AM_PRT_3D_TILED_THIN1 = 0x0000000b, |
1686 | AM_3D_TILED_THIN1 = 0x0000000c, |
1687 | AM_3D_TILED_THICK = 0x0000000d, |
1688 | AM_3D_TILED_XTHICK = 0x0000000e, |
1689 | AM_PRT_3D_TILED_THICK = 0x0000000f, |
1690 | } ARRAY_MODE; |
1691 | |
1692 | /* |
1693 | * PIPE_CONFIG enum |
1694 | */ |
1695 | |
1696 | typedef enum PIPE_CONFIG { |
1697 | P2 = 0x00000000, |
1698 | P4_8x16 = 0x00000004, |
1699 | P4_16x16 = 0x00000005, |
1700 | P4_16x32 = 0x00000006, |
1701 | P4_32x32 = 0x00000007, |
1702 | P8_16x16_8x16 = 0x00000008, |
1703 | P8_16x32_8x16 = 0x00000009, |
1704 | P8_32x32_8x16 = 0x0000000a, |
1705 | P8_16x32_16x16 = 0x0000000b, |
1706 | P8_32x32_16x16 = 0x0000000c, |
1707 | P8_32x32_16x32 = 0x0000000d, |
1708 | P8_32x64_32x32 = 0x0000000e, |
1709 | P16_32x32_8x16 = 0x00000010, |
1710 | P16_32x32_16x16 = 0x00000011, |
1711 | P16_ADDR_SURF = 0x00000012, |
1712 | } PIPE_CONFIG; |
1713 | |
1714 | /* |
1715 | * MICRO_TILE_MODE_NEW enum |
1716 | */ |
1717 | |
1718 | typedef enum MICRO_TILE_MODE_NEW { |
1719 | DISPLAY_MICRO_TILING = 0x00000000, |
1720 | THIN_MICRO_TILING = 0x00000001, |
1721 | DEPTH_MICRO_TILING = 0x00000002, |
1722 | ROTATED_MICRO_TILING = 0x00000003, |
1723 | THICK_MICRO_TILING = 0x00000004, |
1724 | } MICRO_TILE_MODE_NEW; |
1725 | |
1726 | /* |
1727 | * TILE_SPLIT enum |
1728 | */ |
1729 | |
1730 | typedef enum TILE_SPLIT { |
1731 | SURF_TILE_SPLIT_64B = 0x00000000, |
1732 | SURF_TILE_SPLIT_128B = 0x00000001, |
1733 | SURF_TILE_SPLIT_256B = 0x00000002, |
1734 | SURF_TILE_SPLIT_512B = 0x00000003, |
1735 | SURF_TILE_SPLIT_1KB = 0x00000004, |
1736 | SURF_TILE_SPLIT_2KB = 0x00000005, |
1737 | SURF_TILE_SPLIT_4KB = 0x00000006, |
1738 | } TILE_SPLIT; |
1739 | |
1740 | /* |
1741 | * BANK_WIDTH enum |
1742 | */ |
1743 | |
1744 | typedef enum BANK_WIDTH { |
1745 | SURF_BANK_WIDTH_1 = 0x00000000, |
1746 | SURF_BANK_WIDTH_2 = 0x00000001, |
1747 | SURF_BANK_WIDTH_4 = 0x00000002, |
1748 | SURF_BANK_WIDTH_8 = 0x00000003, |
1749 | } BANK_WIDTH; |
1750 | |
1751 | /* |
1752 | * BANK_HEIGHT enum |
1753 | */ |
1754 | |
1755 | typedef enum BANK_HEIGHT { |
1756 | SURF_BANK_HEIGHT_1 = 0x00000000, |
1757 | SURF_BANK_HEIGHT_2 = 0x00000001, |
1758 | SURF_BANK_HEIGHT_4 = 0x00000002, |
1759 | SURF_BANK_HEIGHT_8 = 0x00000003, |
1760 | } BANK_HEIGHT; |
1761 | |
1762 | /* |
1763 | * MACRO_TILE_ASPECT enum |
1764 | */ |
1765 | |
1766 | typedef enum MACRO_TILE_ASPECT { |
1767 | SURF_MACRO_ASPECT_1 = 0x00000000, |
1768 | SURF_MACRO_ASPECT_2 = 0x00000001, |
1769 | SURF_MACRO_ASPECT_4 = 0x00000002, |
1770 | SURF_MACRO_ASPECT_8 = 0x00000003, |
1771 | } MACRO_TILE_ASPECT; |
1772 | |
1773 | /* |
1774 | * LEGACY_NUM_BANKS enum |
1775 | */ |
1776 | |
1777 | typedef enum LEGACY_NUM_BANKS { |
1778 | SURF_2_BANK = 0x00000000, |
1779 | SURF_4_BANK = 0x00000001, |
1780 | SURF_8_BANK = 0x00000002, |
1781 | SURF_16_BANK = 0x00000003, |
1782 | } LEGACY_NUM_BANKS; |
1783 | |
1784 | /* |
1785 | * SWATH_HEIGHT enum |
1786 | */ |
1787 | |
1788 | typedef enum SWATH_HEIGHT { |
1789 | SWATH_HEIGHT_1L = 0x00000000, |
1790 | SWATH_HEIGHT_2L = 0x00000001, |
1791 | SWATH_HEIGHT_4L = 0x00000002, |
1792 | SWATH_HEIGHT_8L = 0x00000003, |
1793 | SWATH_HEIGHT_16L = 0x00000004, |
1794 | } SWATH_HEIGHT; |
1795 | |
1796 | /* |
1797 | * PTE_ROW_HEIGHT_LINEAR enum |
1798 | */ |
1799 | |
1800 | typedef enum PTE_ROW_HEIGHT_LINEAR { |
1801 | PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000, |
1802 | PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001, |
1803 | PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002, |
1804 | PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003, |
1805 | PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004, |
1806 | PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005, |
1807 | PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006, |
1808 | PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007, |
1809 | } PTE_ROW_HEIGHT_LINEAR; |
1810 | |
1811 | /* |
1812 | * CHUNK_SIZE enum |
1813 | */ |
1814 | |
1815 | typedef enum CHUNK_SIZE { |
1816 | CHUNK_SIZE_1KB = 0x00000000, |
1817 | CHUNK_SIZE_2KB = 0x00000001, |
1818 | CHUNK_SIZE_4KB = 0x00000002, |
1819 | CHUNK_SIZE_8KB = 0x00000003, |
1820 | CHUNK_SIZE_16KB = 0x00000004, |
1821 | CHUNK_SIZE_32KB = 0x00000005, |
1822 | CHUNK_SIZE_64KB = 0x00000006, |
1823 | } CHUNK_SIZE; |
1824 | |
1825 | /* |
1826 | * MIN_CHUNK_SIZE enum |
1827 | */ |
1828 | |
1829 | typedef enum MIN_CHUNK_SIZE { |
1830 | NO_MIN_CHUNK_SIZE = 0x00000000, |
1831 | MIN_CHUNK_SIZE_256B = 0x00000001, |
1832 | MIN_CHUNK_SIZE_512B = 0x00000002, |
1833 | MIN_CHUNK_SIZE_1024B = 0x00000003, |
1834 | } MIN_CHUNK_SIZE; |
1835 | |
1836 | /* |
1837 | * META_CHUNK_SIZE enum |
1838 | */ |
1839 | |
1840 | typedef enum META_CHUNK_SIZE { |
1841 | META_CHUNK_SIZE_1KB = 0x00000000, |
1842 | META_CHUNK_SIZE_2KB = 0x00000001, |
1843 | META_CHUNK_SIZE_4KB = 0x00000002, |
1844 | META_CHUNK_SIZE_8KB = 0x00000003, |
1845 | } META_CHUNK_SIZE; |
1846 | |
1847 | /* |
1848 | * MIN_META_CHUNK_SIZE enum |
1849 | */ |
1850 | |
1851 | typedef enum MIN_META_CHUNK_SIZE { |
1852 | NO_MIN_META_CHUNK_SIZE = 0x00000000, |
1853 | MIN_META_CHUNK_SIZE_64B = 0x00000001, |
1854 | MIN_META_CHUNK_SIZE_128B = 0x00000002, |
1855 | MIN_META_CHUNK_SIZE_256B = 0x00000003, |
1856 | } MIN_META_CHUNK_SIZE; |
1857 | |
1858 | /* |
1859 | * DPTE_GROUP_SIZE enum |
1860 | */ |
1861 | |
1862 | typedef enum DPTE_GROUP_SIZE { |
1863 | DPTE_GROUP_SIZE_64B = 0x00000000, |
1864 | DPTE_GROUP_SIZE_128B = 0x00000001, |
1865 | DPTE_GROUP_SIZE_256B = 0x00000002, |
1866 | DPTE_GROUP_SIZE_512B = 0x00000003, |
1867 | DPTE_GROUP_SIZE_1024B = 0x00000004, |
1868 | DPTE_GROUP_SIZE_2048B = 0x00000005, |
1869 | DPTE_GROUP_SIZE_4096B = 0x00000006, |
1870 | DPTE_GROUP_SIZE_8192B = 0x00000007, |
1871 | } DPTE_GROUP_SIZE; |
1872 | |
1873 | /* |
1874 | * MPTE_GROUP_SIZE enum |
1875 | */ |
1876 | |
1877 | typedef enum MPTE_GROUP_SIZE { |
1878 | MPTE_GROUP_SIZE_64B = 0x00000000, |
1879 | MPTE_GROUP_SIZE_128B = 0x00000001, |
1880 | MPTE_GROUP_SIZE_256B = 0x00000002, |
1881 | MPTE_GROUP_SIZE_512B = 0x00000003, |
1882 | MPTE_GROUP_SIZE_1024B = 0x00000004, |
1883 | MPTE_GROUP_SIZE_2048B = 0x00000005, |
1884 | MPTE_GROUP_SIZE_4096B = 0x00000006, |
1885 | MPTE_GROUP_SIZE_8192B = 0x00000007, |
1886 | } MPTE_GROUP_SIZE; |
1887 | |
1888 | /* |
1889 | * HUBP_BLANK_EN enum |
1890 | */ |
1891 | |
1892 | typedef enum HUBP_BLANK_EN { |
1893 | HUBP_BLANK_SW_DEASSERT = 0x00000000, |
1894 | HUBP_BLANK_SW_ASSERT = 0x00000001, |
1895 | } HUBP_BLANK_EN; |
1896 | |
1897 | /* |
1898 | * HUBP_DISABLE enum |
1899 | */ |
1900 | |
1901 | typedef enum HUBP_DISABLE { |
1902 | HUBP_ENABLED = 0x00000000, |
1903 | HUBP_DISABLED = 0x00000001, |
1904 | } HUBP_DISABLE; |
1905 | |
1906 | /* |
1907 | * HUBP_TTU_DISABLE enum |
1908 | */ |
1909 | |
1910 | typedef enum HUBP_TTU_DISABLE { |
1911 | HUBP_TTU_ENABLED = 0x00000000, |
1912 | HUBP_TTU_DISABLED = 0x00000001, |
1913 | } HUBP_TTU_DISABLE; |
1914 | |
1915 | /* |
1916 | * HUBP_NO_OUTSTANDING_REQ enum |
1917 | */ |
1918 | |
1919 | typedef enum HUBP_NO_OUTSTANDING_REQ { |
1920 | OUTSTANDING_REQ = 0x00000000, |
1921 | NO_OUTSTANDING_REQ = 0x00000001, |
1922 | } HUBP_NO_OUTSTANDING_REQ; |
1923 | |
1924 | /* |
1925 | * HUBP_IN_BLANK enum |
1926 | */ |
1927 | |
1928 | typedef enum HUBP_IN_BLANK { |
1929 | HUBP_IN_ACTIVE = 0x00000000, |
1930 | HUBP_IN_VBLANK = 0x00000001, |
1931 | } HUBP_IN_BLANK; |
1932 | |
1933 | /* |
1934 | * HUBP_VTG_SEL enum |
1935 | */ |
1936 | |
1937 | typedef enum HUBP_VTG_SEL { |
1938 | VTG_SEL_0 = 0x00000000, |
1939 | VTG_SEL_1 = 0x00000001, |
1940 | VTG_SEL_2 = 0x00000002, |
1941 | VTG_SEL_3 = 0x00000003, |
1942 | VTG_SEL_4 = 0x00000004, |
1943 | VTG_SEL_5 = 0x00000005, |
1944 | } HUBP_VTG_SEL; |
1945 | |
1946 | /* |
1947 | * HUBP_VREADY_AT_OR_AFTER_VSYNC enum |
1948 | */ |
1949 | |
1950 | typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC { |
1951 | VREADY_BEFORE_VSYNC = 0x00000000, |
1952 | VREADY_AT_OR_AFTER_VSYNC = 0x00000001, |
1953 | } HUBP_VREADY_AT_OR_AFTER_VSYNC; |
1954 | |
1955 | /* |
1956 | * VMPG_SIZE enum |
1957 | */ |
1958 | |
1959 | typedef enum VMPG_SIZE { |
1960 | VMPG_SIZE_4KB = 0x00000000, |
1961 | VMPG_SIZE_64KB = 0x00000001, |
1962 | } VMPG_SIZE; |
1963 | |
1964 | /* |
1965 | * HUBP_MEASURE_WIN_MODE_DCFCLK enum |
1966 | */ |
1967 | |
1968 | typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK { |
1969 | HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000, |
1970 | HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001, |
1971 | HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002, |
1972 | HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003, |
1973 | } HUBP_MEASURE_WIN_MODE_DCFCLK; |
1974 | |
1975 | /******************************************************* |
1976 | * HUBPREQ Enums |
1977 | *******************************************************/ |
1978 | |
1979 | /* |
1980 | * SURFACE_TMZ enum |
1981 | */ |
1982 | |
1983 | typedef enum SURFACE_TMZ { |
1984 | SURFACE_IS_NOT_TMZ = 0x00000000, |
1985 | SURFACE_IS_TMZ = 0x00000001, |
1986 | } SURFACE_TMZ; |
1987 | |
1988 | /* |
1989 | * SURFACE_DCC enum |
1990 | */ |
1991 | |
1992 | typedef enum SURFACE_DCC { |
1993 | SURFACE_IS_NOT_DCC = 0x00000000, |
1994 | SURFACE_IS_DCC = 0x00000001, |
1995 | } SURFACE_DCC; |
1996 | |
1997 | /* |
1998 | * SURFACE_DCC_IND_64B enum |
1999 | */ |
2000 | |
2001 | typedef enum SURFACE_DCC_IND_64B { |
2002 | SURFACE_DCC_IS_NOT_IND_64B = 0x00000000, |
2003 | SURFACE_DCC_IS_IND_64B = 0x00000001, |
2004 | } SURFACE_DCC_IND_64B; |
2005 | |
2006 | /* |
2007 | * SURFACE_FLIP_TYPE enum |
2008 | */ |
2009 | |
2010 | typedef enum SURFACE_FLIP_TYPE { |
2011 | SURFACE_V_FLIP = 0x00000000, |
2012 | SURFACE_I_FLIP = 0x00000001, |
2013 | } SURFACE_FLIP_TYPE; |
2014 | |
2015 | /* |
2016 | * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum |
2017 | */ |
2018 | |
2019 | typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC { |
2020 | FLIP_ANY_FRAME = 0x00000000, |
2021 | FLIP_LEFT_EYE = 0x00000001, |
2022 | FLIP_RIGHT_EYE = 0x00000002, |
2023 | SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003, |
2024 | } SURFACE_FLIP_MODE_FOR_STEREOSYNC; |
2025 | |
2026 | /* |
2027 | * SURFACE_UPDATE_LOCK enum |
2028 | */ |
2029 | |
2030 | typedef enum SURFACE_UPDATE_LOCK { |
2031 | SURFACE_UPDATE_IS_UNLOCKED = 0x00000000, |
2032 | SURFACE_UPDATE_IS_LOCKED = 0x00000001, |
2033 | } SURFACE_UPDATE_LOCK; |
2034 | |
2035 | /* |
2036 | * SURFACE_FLIP_IN_STEREOSYNC enum |
2037 | */ |
2038 | |
2039 | typedef enum SURFACE_FLIP_IN_STEREOSYNC { |
2040 | SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000, |
2041 | SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001, |
2042 | } SURFACE_FLIP_IN_STEREOSYNC; |
2043 | |
2044 | /* |
2045 | * SURFACE_FLIP_STEREO_SELECT_DISABLE enum |
2046 | */ |
2047 | |
2048 | typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE { |
2049 | SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000, |
2050 | SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001, |
2051 | } SURFACE_FLIP_STEREO_SELECT_DISABLE; |
2052 | |
2053 | /* |
2054 | * SURFACE_FLIP_STEREO_SELECT_POLARITY enum |
2055 | */ |
2056 | |
2057 | typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY { |
2058 | SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000, |
2059 | SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001, |
2060 | } SURFACE_FLIP_STEREO_SELECT_POLARITY; |
2061 | |
2062 | /* |
2063 | * SURFACE_INUSE_RAED_NO_LATCH enum |
2064 | */ |
2065 | |
2066 | typedef enum SURFACE_INUSE_RAED_NO_LATCH { |
2067 | SURFACE_INUSE_IS_LATCHED = 0x00000000, |
2068 | SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001, |
2069 | } SURFACE_INUSE_RAED_NO_LATCH; |
2070 | |
2071 | /* |
2072 | * INT_MASK enum |
2073 | */ |
2074 | |
2075 | typedef enum INT_MASK { |
2076 | INT_DISABLED = 0x00000000, |
2077 | INT_ENABLED = 0x00000001, |
2078 | } INT_MASK; |
2079 | |
2080 | /* |
2081 | * SURFACE_FLIP_INT_TYPE enum |
2082 | */ |
2083 | |
2084 | typedef enum SURFACE_FLIP_INT_TYPE { |
2085 | SURFACE_FLIP_INT_LEVEL = 0x00000000, |
2086 | SURFACE_FLIP_INT_PULSE = 0x00000001, |
2087 | } SURFACE_FLIP_INT_TYPE; |
2088 | |
2089 | /* |
2090 | * SURFACE_FLIP_AWAY_INT_TYPE enum |
2091 | */ |
2092 | |
2093 | typedef enum SURFACE_FLIP_AWAY_INT_TYPE { |
2094 | SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000, |
2095 | SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001, |
2096 | } SURFACE_FLIP_AWAY_INT_TYPE; |
2097 | |
2098 | /* |
2099 | * SURFACE_FLIP_VUPDATE_SKIP_NUM enum |
2100 | */ |
2101 | |
2102 | typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM { |
2103 | SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000, |
2104 | SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001, |
2105 | SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002, |
2106 | SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003, |
2107 | SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004, |
2108 | SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005, |
2109 | SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006, |
2110 | SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007, |
2111 | SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008, |
2112 | SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009, |
2113 | SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a, |
2114 | SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b, |
2115 | SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c, |
2116 | SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d, |
2117 | SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e, |
2118 | SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f, |
2119 | } SURFACE_FLIP_VUPDATE_SKIP_NUM; |
2120 | |
2121 | /* |
2122 | * DFQ_SIZE enum |
2123 | */ |
2124 | |
2125 | typedef enum DFQ_SIZE { |
2126 | DFQ_SIZE_0 = 0x00000000, |
2127 | DFQ_SIZE_1 = 0x00000001, |
2128 | DFQ_SIZE_2 = 0x00000002, |
2129 | DFQ_SIZE_3 = 0x00000003, |
2130 | DFQ_SIZE_4 = 0x00000004, |
2131 | DFQ_SIZE_5 = 0x00000005, |
2132 | DFQ_SIZE_6 = 0x00000006, |
2133 | DFQ_SIZE_7 = 0x00000007, |
2134 | } DFQ_SIZE; |
2135 | |
2136 | /* |
2137 | * DFQ_MIN_FREE_ENTRIES enum |
2138 | */ |
2139 | |
2140 | typedef enum DFQ_MIN_FREE_ENTRIES { |
2141 | DFQ_MIN_FREE_ENTRIES_0 = 0x00000000, |
2142 | DFQ_MIN_FREE_ENTRIES_1 = 0x00000001, |
2143 | DFQ_MIN_FREE_ENTRIES_2 = 0x00000002, |
2144 | DFQ_MIN_FREE_ENTRIES_3 = 0x00000003, |
2145 | DFQ_MIN_FREE_ENTRIES_4 = 0x00000004, |
2146 | DFQ_MIN_FREE_ENTRIES_5 = 0x00000005, |
2147 | DFQ_MIN_FREE_ENTRIES_6 = 0x00000006, |
2148 | DFQ_MIN_FREE_ENTRIES_7 = 0x00000007, |
2149 | } DFQ_MIN_FREE_ENTRIES; |
2150 | |
2151 | /* |
2152 | * DFQ_NUM_ENTRIES enum |
2153 | */ |
2154 | |
2155 | typedef enum DFQ_NUM_ENTRIES { |
2156 | DFQ_NUM_ENTRIES_0 = 0x00000000, |
2157 | DFQ_NUM_ENTRIES_1 = 0x00000001, |
2158 | DFQ_NUM_ENTRIES_2 = 0x00000002, |
2159 | DFQ_NUM_ENTRIES_3 = 0x00000003, |
2160 | DFQ_NUM_ENTRIES_4 = 0x00000004, |
2161 | DFQ_NUM_ENTRIES_5 = 0x00000005, |
2162 | DFQ_NUM_ENTRIES_6 = 0x00000006, |
2163 | DFQ_NUM_ENTRIES_7 = 0x00000007, |
2164 | DFQ_NUM_ENTRIES_8 = 0x00000008, |
2165 | } DFQ_NUM_ENTRIES; |
2166 | |
2167 | /* |
2168 | * FLIP_RATE enum |
2169 | */ |
2170 | |
2171 | typedef enum FLIP_RATE { |
2172 | FLIP_RATE_0 = 0x00000000, |
2173 | FLIP_RATE_1 = 0x00000001, |
2174 | FLIP_RATE_2 = 0x00000002, |
2175 | FLIP_RATE_3 = 0x00000003, |
2176 | FLIP_RATE_4 = 0x00000004, |
2177 | FLIP_RATE_5 = 0x00000005, |
2178 | FLIP_RATE_6 = 0x00000006, |
2179 | FLIP_RATE_7 = 0x00000007, |
2180 | } FLIP_RATE; |
2181 | |
2182 | /******************************************************* |
2183 | * HUBPRET Enums |
2184 | *******************************************************/ |
2185 | |
2186 | /* |
2187 | * DETILE_BUFFER_PACKER_ENABLE enum |
2188 | */ |
2189 | |
2190 | typedef enum DETILE_BUFFER_PACKER_ENABLE { |
2191 | DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000, |
2192 | DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001, |
2193 | } DETILE_BUFFER_PACKER_ENABLE; |
2194 | |
2195 | /* |
2196 | * CROSSBAR_FOR_ALPHA enum |
2197 | */ |
2198 | |
2199 | typedef enum CROSSBAR_FOR_ALPHA { |
2200 | ALPHA_DATA_ON_ALPHA_PORT = 0x00000000, |
2201 | ALPHA_DATA_ON_Y_G_PORT = 0x00000001, |
2202 | ALPHA_DATA_ON_CB_B_PORT = 0x00000002, |
2203 | ALPHA_DATA_ON_CR_R_PORT = 0x00000003, |
2204 | } CROSSBAR_FOR_ALPHA; |
2205 | |
2206 | /* |
2207 | * CROSSBAR_FOR_Y_G enum |
2208 | */ |
2209 | |
2210 | typedef enum CROSSBAR_FOR_Y_G { |
2211 | Y_G_DATA_ON_ALPHA_PORT = 0x00000000, |
2212 | Y_G_DATA_ON_Y_G_PORT = 0x00000001, |
2213 | Y_G_DATA_ON_CB_B_PORT = 0x00000002, |
2214 | Y_G_DATA_ON_CR_R_PORT = 0x00000003, |
2215 | } CROSSBAR_FOR_Y_G; |
2216 | |
2217 | /* |
2218 | * CROSSBAR_FOR_CB_B enum |
2219 | */ |
2220 | |
2221 | typedef enum CROSSBAR_FOR_CB_B { |
2222 | CB_B_DATA_ON_ALPHA_PORT = 0x00000000, |
2223 | CB_B_DATA_ON_Y_G_PORT = 0x00000001, |
2224 | CB_B_DATA_ON_CB_B_PORT = 0x00000002, |
2225 | CB_B_DATA_ON_CR_R_PORT = 0x00000003, |
2226 | } CROSSBAR_FOR_CB_B; |
2227 | |
2228 | /* |
2229 | * CROSSBAR_FOR_CR_R enum |
2230 | */ |
2231 | |
2232 | typedef enum CROSSBAR_FOR_CR_R { |
2233 | CR_R_DATA_ON_ALPHA_PORT = 0x00000000, |
2234 | CR_R_DATA_ON_Y_G_PORT = 0x00000001, |
2235 | CR_R_DATA_ON_CB_B_PORT = 0x00000002, |
2236 | CR_R_DATA_ON_CR_R_PORT = 0x00000003, |
2237 | } CROSSBAR_FOR_CR_R; |
2238 | |
2239 | /* |
2240 | * DET_MEM_PWR_LIGHT_SLEEP_MODE enum |
2241 | */ |
2242 | |
2243 | typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE { |
2244 | DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, |
2245 | DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, |
2246 | DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, |
2247 | } DET_MEM_PWR_LIGHT_SLEEP_MODE; |
2248 | |
2249 | /* |
2250 | * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum |
2251 | */ |
2252 | |
2253 | typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE { |
2254 | PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, |
2255 | PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, |
2256 | } PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE; |
2257 | |
2258 | /******************************************************* |
2259 | * CURSOR Enums |
2260 | *******************************************************/ |
2261 | |
2262 | /* |
2263 | * CURSOR_ENABLE enum |
2264 | */ |
2265 | |
2266 | typedef enum CURSOR_ENABLE { |
2267 | CURSOR_IS_DISABLE = 0x00000000, |
2268 | CURSOR_IS_ENABLE = 0x00000001, |
2269 | } CURSOR_ENABLE; |
2270 | |
2271 | /* |
2272 | * CURSOR_2X_MAGNIFY enum |
2273 | */ |
2274 | |
2275 | typedef enum CURSOR_2X_MAGNIFY { |
2276 | CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000, |
2277 | CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001, |
2278 | } CURSOR_2X_MAGNIFY; |
2279 | |
2280 | /* |
2281 | * CURSOR_MODE enum |
2282 | */ |
2283 | |
2284 | typedef enum CURSOR_MODE { |
2285 | CURSOR_MONO_2BIT = 0x00000000, |
2286 | CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001, |
2287 | CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, |
2288 | CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, |
2289 | CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004, |
2290 | CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005, |
2291 | } CURSOR_MODE; |
2292 | |
2293 | /* |
2294 | * CURSOR_SURFACE_TMZ enum |
2295 | */ |
2296 | |
2297 | typedef enum CURSOR_SURFACE_TMZ { |
2298 | CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000, |
2299 | CURSOR_SURFACE_IS_TMZ = 0x00000001, |
2300 | } CURSOR_SURFACE_TMZ; |
2301 | |
2302 | /* |
2303 | * CURSOR_SNOOP enum |
2304 | */ |
2305 | |
2306 | typedef enum CURSOR_SNOOP { |
2307 | CURSOR_IS_NOT_SNOOP = 0x00000000, |
2308 | CURSOR_IS_SNOOP = 0x00000001, |
2309 | } CURSOR_SNOOP; |
2310 | |
2311 | /* |
2312 | * CURSOR_SYSTEM enum |
2313 | */ |
2314 | |
2315 | typedef enum CURSOR_SYSTEM { |
2316 | CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000, |
2317 | CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001, |
2318 | } CURSOR_SYSTEM; |
2319 | |
2320 | /* |
2321 | * CURSOR_PITCH enum |
2322 | */ |
2323 | |
2324 | typedef enum CURSOR_PITCH { |
2325 | CURSOR_PITCH_64_PIXELS = 0x00000000, |
2326 | CURSOR_PITCH_128_PIXELS = 0x00000001, |
2327 | CURSOR_PITCH_256_PIXELS = 0x00000002, |
2328 | } CURSOR_PITCH; |
2329 | |
2330 | /* |
2331 | * CURSOR_LINES_PER_CHUNK enum |
2332 | */ |
2333 | |
2334 | typedef enum CURSOR_LINES_PER_CHUNK { |
2335 | CURSOR_LINE_PER_CHUNK_1 = 0x00000000, |
2336 | CURSOR_LINE_PER_CHUNK_2 = 0x00000001, |
2337 | CURSOR_LINE_PER_CHUNK_4 = 0x00000002, |
2338 | CURSOR_LINE_PER_CHUNK_8 = 0x00000003, |
2339 | CURSOR_LINE_PER_CHUNK_16 = 0x00000004, |
2340 | } CURSOR_LINES_PER_CHUNK; |
2341 | |
2342 | /* |
2343 | * CURSOR_PERFMON_LATENCY_MEASURE_EN enum |
2344 | */ |
2345 | |
2346 | typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN { |
2347 | CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000, |
2348 | CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001, |
2349 | } CURSOR_PERFMON_LATENCY_MEASURE_EN; |
2350 | |
2351 | /* |
2352 | * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum |
2353 | */ |
2354 | |
2355 | typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL { |
2356 | CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000, |
2357 | CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001, |
2358 | } CURSOR_PERFMON_LATENCY_MEASURE_SEL; |
2359 | |
2360 | /* |
2361 | * CURSOR_STEREO_EN enum |
2362 | */ |
2363 | |
2364 | typedef enum CURSOR_STEREO_EN { |
2365 | CURSOR_STEREO_IS_DISABLED = 0x00000000, |
2366 | CURSOR_STEREO_IS_ENABLED = 0x00000001, |
2367 | } CURSOR_STEREO_EN; |
2368 | |
2369 | /* |
2370 | * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum |
2371 | */ |
2372 | |
2373 | typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS { |
2374 | CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000, |
2375 | CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001, |
2376 | } CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS; |
2377 | |
2378 | /* |
2379 | * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum |
2380 | */ |
2381 | |
2382 | typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE { |
2383 | CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, |
2384 | CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, |
2385 | CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, |
2386 | } CROB_MEM_PWR_LIGHT_SLEEP_MODE; |
2387 | |
2388 | /* |
2389 | * DMDATA_UPDATED enum |
2390 | */ |
2391 | |
2392 | typedef enum DMDATA_UPDATED { |
2393 | DMDATA_NOT_UPDATED = 0x00000000, |
2394 | DMDATA_WAS_UPDATED = 0x00000001, |
2395 | } DMDATA_UPDATED; |
2396 | |
2397 | /* |
2398 | * DMDATA_REPEAT enum |
2399 | */ |
2400 | |
2401 | typedef enum DMDATA_REPEAT { |
2402 | DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000, |
2403 | DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001, |
2404 | } DMDATA_REPEAT; |
2405 | |
2406 | /* |
2407 | * DMDATA_MODE enum |
2408 | */ |
2409 | |
2410 | typedef enum DMDATA_MODE { |
2411 | DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000, |
2412 | DMDATA_HARDWARE_UPDATE_MODE = 0x00000001, |
2413 | } DMDATA_MODE; |
2414 | |
2415 | /* |
2416 | * DMDATA_QOS_MODE enum |
2417 | */ |
2418 | |
2419 | typedef enum DMDATA_QOS_MODE { |
2420 | DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000, |
2421 | DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001, |
2422 | } DMDATA_QOS_MODE; |
2423 | |
2424 | /* |
2425 | * DMDATA_DONE enum |
2426 | */ |
2427 | |
2428 | typedef enum DMDATA_DONE { |
2429 | DMDATA_NOT_SENT_TO_DIG = 0x00000000, |
2430 | DMDATA_SENT_TO_DIG = 0x00000001, |
2431 | } DMDATA_DONE; |
2432 | |
2433 | /* |
2434 | * DMDATA_UNDERFLOW enum |
2435 | */ |
2436 | |
2437 | typedef enum DMDATA_UNDERFLOW { |
2438 | DMDATA_NOT_UNDERFLOW = 0x00000000, |
2439 | DMDATA_UNDERFLOWED = 0x00000001, |
2440 | } DMDATA_UNDERFLOW; |
2441 | |
2442 | /* |
2443 | * DMDATA_UNDERFLOW_CLEAR enum |
2444 | */ |
2445 | |
2446 | typedef enum DMDATA_UNDERFLOW_CLEAR { |
2447 | DMDATA_DONT_CLEAR = 0x00000000, |
2448 | DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001, |
2449 | } DMDATA_UNDERFLOW_CLEAR; |
2450 | |
2451 | /******************************************************* |
2452 | * HUBPXFC Enums |
2453 | *******************************************************/ |
2454 | |
2455 | /* |
2456 | * HUBP_XFC_PIXEL_FORMAT_ENUM enum |
2457 | */ |
2458 | |
2459 | typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM { |
2460 | HUBP_XFC_PIXEL_IS_32BPP = 0x00000000, |
2461 | HUBP_XFC_PIXEL_IS_64BPP = 0x00000001, |
2462 | } HUBP_XFC_PIXEL_FORMAT_ENUM; |
2463 | |
2464 | /* |
2465 | * HUBP_XFC_FRAME_MODE_ENUM enum |
2466 | */ |
2467 | |
2468 | typedef enum HUBP_XFC_FRAME_MODE_ENUM { |
2469 | HUBP_XFC_PARTIAL_FRAME_MODE = 0x00000000, |
2470 | HUBP_XFC_FULL_FRAME_MODE = 0x00000001, |
2471 | } HUBP_XFC_FRAME_MODE_ENUM; |
2472 | |
2473 | /* |
2474 | * HUBP_XFC_CHUNK_SIZE_ENUM enum |
2475 | */ |
2476 | |
2477 | typedef enum HUBP_XFC_CHUNK_SIZE_ENUM { |
2478 | HUBP_XFC_CHUNK_SIZE_256B = 0x00000000, |
2479 | HUBP_XFC_CHUNK_SIZE_512B = 0x00000001, |
2480 | HUBP_XFC_CHUNK_SIZE_1KB = 0x00000002, |
2481 | HUBP_XFC_CHUNK_SIZE_2KB = 0x00000003, |
2482 | HUBP_XFC_CHUNK_SIZE_4KB = 0x00000004, |
2483 | HUBP_XFC_CHUNK_SIZE_8KB = 0x00000005, |
2484 | HUBP_XFC_CHUNK_SIZE_16KB = 0x00000006, |
2485 | HUBP_XFC_CHUNK_SIZE_32KB = 0x00000007, |
2486 | } HUBP_XFC_CHUNK_SIZE_ENUM; |
2487 | |
2488 | /******************************************************* |
2489 | * XFC Enums |
2490 | *******************************************************/ |
2491 | |
2492 | /* |
2493 | * MMHUBBUB_XFC_XFCMON_MODE_ENUM enum |
2494 | */ |
2495 | |
2496 | typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM { |
2497 | MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0x00000000, |
2498 | MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 0x00000001, |
2499 | MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 0x00000002, |
2500 | } MMHUBBUB_XFC_XFCMON_MODE_ENUM; |
2501 | |
2502 | /* |
2503 | * MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum |
2504 | */ |
2505 | |
2506 | typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM { |
2507 | MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0x00000000, |
2508 | MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 0x00000001, |
2509 | } MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM; |
2510 | |
2511 | /******************************************************* |
2512 | * XFCP Enums |
2513 | *******************************************************/ |
2514 | |
2515 | /* |
2516 | * MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum |
2517 | */ |
2518 | |
2519 | typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM { |
2520 | MMHUBBUB_XFC_PIXEL_IS_32BPP = 0x00000000, |
2521 | MMHUBBUB_XFC_PIXEL_IS_64BPP = 0x00000001, |
2522 | } MMHUBBUB_XFC_PIXEL_FORMAT_ENUM; |
2523 | |
2524 | /* |
2525 | * MMHUBBUB_XFC_FRAME_MODE_ENUM enum |
2526 | */ |
2527 | |
2528 | typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM { |
2529 | MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0x00000000, |
2530 | MMHUBBUB_XFC_FULL_FRAME_MODE = 0x00000001, |
2531 | } MMHUBBUB_XFC_FRAME_MODE_ENUM; |
2532 | |
2533 | /******************************************************* |
2534 | * MPC_CFG Enums |
2535 | *******************************************************/ |
2536 | |
2537 | /* |
2538 | * MPC_CFG_MPC_TEST_CLK_SEL enum |
2539 | */ |
2540 | |
2541 | typedef enum MPC_CFG_MPC_TEST_CLK_SEL { |
2542 | MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000, |
2543 | MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001, |
2544 | MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002, |
2545 | MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003, |
2546 | } MPC_CFG_MPC_TEST_CLK_SEL; |
2547 | |
2548 | /* |
2549 | * MPC_CRC_CALC_MODE enum |
2550 | */ |
2551 | |
2552 | typedef enum MPC_CRC_CALC_MODE { |
2553 | MPC_CRC_ONE_SHOT_MODE = 0x00000000, |
2554 | MPC_CRC_CONTINUOUS_MODE = 0x00000001, |
2555 | } MPC_CRC_CALC_MODE; |
2556 | |
2557 | /* |
2558 | * MPC_CRC_CALC_STEREO_MODE enum |
2559 | */ |
2560 | |
2561 | typedef enum MPC_CRC_CALC_STEREO_MODE { |
2562 | MPC_CRC_STEREO_MODE_LEFT = 0x00000000, |
2563 | MPC_CRC_STEREO_MODE_RIGHT = 0x00000001, |
2564 | MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002, |
2565 | MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003, |
2566 | } MPC_CRC_CALC_STEREO_MODE; |
2567 | |
2568 | /* |
2569 | * MPC_CRC_CALC_INTERLACE_MODE enum |
2570 | */ |
2571 | |
2572 | typedef enum MPC_CRC_CALC_INTERLACE_MODE { |
2573 | MPC_CRC_INTERLACE_MODE_TOP = 0x00000000, |
2574 | MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, |
2575 | MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002, |
2576 | MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003, |
2577 | } MPC_CRC_CALC_INTERLACE_MODE; |
2578 | |
2579 | /* |
2580 | * MPC_CRC_SOURCE_SELECT enum |
2581 | */ |
2582 | |
2583 | typedef enum MPC_CRC_SOURCE_SELECT { |
2584 | MPC_CRC_SOURCE_SEL_DPP = 0x00000000, |
2585 | MPC_CRC_SOURCE_SEL_OPP = 0x00000001, |
2586 | MPC_CRC_SOURCE_SEL_DWB = 0x00000002, |
2587 | MPC_CRC_SOURCE_SEL_OTHER = 0x00000003, |
2588 | } MPC_CRC_SOURCE_SELECT; |
2589 | |
2590 | /* |
2591 | * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum |
2592 | */ |
2593 | |
2594 | typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET { |
2595 | MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, |
2596 | MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, |
2597 | } MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET; |
2598 | |
2599 | /* |
2600 | * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum |
2601 | */ |
2602 | |
2603 | typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET { |
2604 | MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, |
2605 | MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, |
2606 | } MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET; |
2607 | |
2608 | /* |
2609 | * MPC_CFG_CFG_VUPDATE_LOCK_SET enum |
2610 | */ |
2611 | |
2612 | typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET { |
2613 | MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, |
2614 | MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, |
2615 | } MPC_CFG_CFG_VUPDATE_LOCK_SET; |
2616 | |
2617 | /* |
2618 | * MPC_CFG_ADR_VUPDATE_LOCK_SET enum |
2619 | */ |
2620 | |
2621 | typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET { |
2622 | MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000, |
2623 | MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001, |
2624 | } MPC_CFG_ADR_VUPDATE_LOCK_SET; |
2625 | |
2626 | /* |
2627 | * MPC_CFG_CUR_VUPDATE_LOCK_SET enum |
2628 | */ |
2629 | |
2630 | typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET { |
2631 | MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, |
2632 | MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, |
2633 | } MPC_CFG_CUR_VUPDATE_LOCK_SET; |
2634 | |
2635 | /* |
2636 | * MPC_OUT_RATE_CONTROL_DISABLE_SET enum |
2637 | */ |
2638 | |
2639 | typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET { |
2640 | MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000, |
2641 | MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001, |
2642 | } MPC_OUT_RATE_CONTROL_DISABLE_SET; |
2643 | |
2644 | /* |
2645 | * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum |
2646 | */ |
2647 | |
2648 | typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE { |
2649 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000, |
2650 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001, |
2651 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002, |
2652 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003, |
2653 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004, |
2654 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005, |
2655 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006, |
2656 | MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007, |
2657 | } MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE; |
2658 | |
2659 | /******************************************************* |
2660 | * MPC_OCSC Enums |
2661 | *******************************************************/ |
2662 | |
2663 | /* |
2664 | * MPC_OCSC_COEF_FORMAT enum |
2665 | */ |
2666 | |
2667 | typedef enum MPC_OCSC_COEF_FORMAT { |
2668 | MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000, |
2669 | MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001, |
2670 | } MPC_OCSC_COEF_FORMAT; |
2671 | |
2672 | /* |
2673 | * MPC_OUT_CSC_MODE enum |
2674 | */ |
2675 | |
2676 | typedef enum MPC_OUT_CSC_MODE { |
2677 | MPC_OUT_CSC_MODE_0 = 0x00000000, |
2678 | MPC_OUT_CSC_MODE_1 = 0x00000001, |
2679 | MPC_OUT_CSC_MODE_2 = 0x00000002, |
2680 | MPC_OUT_CSC_MODE_RSV = 0x00000003, |
2681 | } MPC_OUT_CSC_MODE; |
2682 | |
2683 | /******************************************************* |
2684 | * MPCC Enums |
2685 | *******************************************************/ |
2686 | |
2687 | /* |
2688 | * MPCC_CONTROL_MPCC_MODE enum |
2689 | */ |
2690 | |
2691 | typedef enum MPCC_CONTROL_MPCC_MODE { |
2692 | MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000, |
2693 | MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001, |
2694 | MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002, |
2695 | MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003, |
2696 | } MPCC_CONTROL_MPCC_MODE; |
2697 | |
2698 | /* |
2699 | * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum |
2700 | */ |
2701 | |
2702 | typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE { |
2703 | MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000, |
2704 | MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, |
2705 | MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002, |
2706 | MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003, |
2707 | } MPCC_CONTROL_MPCC_ALPHA_BLND_MODE; |
2708 | |
2709 | /* |
2710 | * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum |
2711 | */ |
2712 | |
2713 | typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE { |
2714 | MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000, |
2715 | MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001, |
2716 | } MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE; |
2717 | |
2718 | /* |
2719 | * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum |
2720 | */ |
2721 | |
2722 | typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY { |
2723 | MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000, |
2724 | MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001, |
2725 | } MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY; |
2726 | |
2727 | /* |
2728 | * MPCC_SM_CONTROL_MPCC_SM_EN enum |
2729 | */ |
2730 | |
2731 | typedef enum MPCC_SM_CONTROL_MPCC_SM_EN { |
2732 | MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000, |
2733 | MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001, |
2734 | } MPCC_SM_CONTROL_MPCC_SM_EN; |
2735 | |
2736 | /* |
2737 | * MPCC_SM_CONTROL_MPCC_SM_MODE enum |
2738 | */ |
2739 | |
2740 | typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE { |
2741 | MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000, |
2742 | MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002, |
2743 | MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, |
2744 | MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, |
2745 | } MPCC_SM_CONTROL_MPCC_SM_MODE; |
2746 | |
2747 | /* |
2748 | * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum |
2749 | */ |
2750 | |
2751 | typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT { |
2752 | MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000, |
2753 | MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001, |
2754 | } MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT; |
2755 | |
2756 | /* |
2757 | * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum |
2758 | */ |
2759 | |
2760 | typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT { |
2761 | MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000, |
2762 | MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001, |
2763 | } MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT; |
2764 | |
2765 | /* |
2766 | * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum |
2767 | */ |
2768 | |
2769 | typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL { |
2770 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, |
2771 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, |
2772 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, |
2773 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, |
2774 | } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL; |
2775 | |
2776 | /* |
2777 | * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum |
2778 | */ |
2779 | |
2780 | typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL { |
2781 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, |
2782 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, |
2783 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, |
2784 | MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, |
2785 | } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL; |
2786 | |
2787 | /* |
2788 | * MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum |
2789 | */ |
2790 | |
2791 | typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK { |
2792 | MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0x00000000, |
2793 | MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 0x00000001, |
2794 | } MPCC_STALL_STATUS_MPCC_STALL_INT_ACK; |
2795 | |
2796 | /* |
2797 | * MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum |
2798 | */ |
2799 | |
2800 | typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK { |
2801 | MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0x00000000, |
2802 | MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 0x00000001, |
2803 | } MPCC_STALL_STATUS_MPCC_STALL_INT_MASK; |
2804 | |
2805 | /* |
2806 | * MPCC_BG_COLOR_BPC enum |
2807 | */ |
2808 | |
2809 | typedef enum MPCC_BG_COLOR_BPC { |
2810 | MPCC_BG_COLOR_BPC_8bit = 0x00000000, |
2811 | MPCC_BG_COLOR_BPC_9bit = 0x00000001, |
2812 | MPCC_BG_COLOR_BPC_10bit = 0x00000002, |
2813 | MPCC_BG_COLOR_BPC_11bit = 0x00000003, |
2814 | MPCC_BG_COLOR_BPC_12bit = 0x00000004, |
2815 | } MPCC_BG_COLOR_BPC; |
2816 | |
2817 | /* |
2818 | * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum |
2819 | */ |
2820 | |
2821 | typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE { |
2822 | MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000, |
2823 | MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001, |
2824 | } MPCC_CONTROL_MPCC_BOT_GAIN_MODE; |
2825 | |
2826 | /******************************************************* |
2827 | * MPCC_OGAM Enums |
2828 | *******************************************************/ |
2829 | |
2830 | /* |
2831 | * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum |
2832 | */ |
2833 | |
2834 | typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL { |
2835 | MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000, |
2836 | MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001, |
2837 | } MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL; |
2838 | |
2839 | /* |
2840 | * MPCC_OGAM_MODE_MPCC_OGAM_MODE enum |
2841 | */ |
2842 | |
2843 | typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE { |
2844 | MPCC_OGAM_MODE_0 = 0x00000000, |
2845 | MPCC_OGAM_MODE_1 = 0x00000001, |
2846 | MPCC_OGAM_MODE_2 = 0x00000002, |
2847 | MPCC_OGAM_MODE_RSV = 0x00000003, |
2848 | } MPCC_OGAM_MODE_MPCC_OGAM_MODE; |
2849 | |
2850 | /******************************************************* |
2851 | * DPG Enums |
2852 | *******************************************************/ |
2853 | |
2854 | /* |
2855 | * ENUM_DPG_EN enum |
2856 | */ |
2857 | |
2858 | typedef enum ENUM_DPG_EN { |
2859 | ENUM_DPG_DISABLE = 0x00000000, |
2860 | ENUM_DPG_ENABLE = 0x00000001, |
2861 | } ENUM_DPG_EN; |
2862 | |
2863 | /* |
2864 | * ENUM_DPG_MODE enum |
2865 | */ |
2866 | |
2867 | typedef enum ENUM_DPG_MODE { |
2868 | ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000, |
2869 | ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001, |
2870 | ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002, |
2871 | ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003, |
2872 | ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004, |
2873 | ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005, |
2874 | ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006, |
2875 | ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007, |
2876 | } ENUM_DPG_MODE; |
2877 | |
2878 | /* |
2879 | * ENUM_DPG_DYNAMIC_RANGE enum |
2880 | */ |
2881 | |
2882 | typedef enum ENUM_DPG_DYNAMIC_RANGE { |
2883 | ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000, |
2884 | ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001, |
2885 | } ENUM_DPG_DYNAMIC_RANGE; |
2886 | |
2887 | /* |
2888 | * ENUM_DPG_BIT_DEPTH enum |
2889 | */ |
2890 | |
2891 | typedef enum ENUM_DPG_BIT_DEPTH { |
2892 | ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000, |
2893 | ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001, |
2894 | ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002, |
2895 | ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003, |
2896 | } ENUM_DPG_BIT_DEPTH; |
2897 | |
2898 | /* |
2899 | * ENUM_DPG_FIELD_POLARITY enum |
2900 | */ |
2901 | |
2902 | typedef enum ENUM_DPG_FIELD_POLARITY { |
2903 | ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, |
2904 | ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, |
2905 | } ENUM_DPG_FIELD_POLARITY; |
2906 | |
2907 | /******************************************************* |
2908 | * FMT Enums |
2909 | *******************************************************/ |
2910 | |
2911 | /* |
2912 | * FMT_CONTROL_PIXEL_ENCODING enum |
2913 | */ |
2914 | |
2915 | typedef enum FMT_CONTROL_PIXEL_ENCODING { |
2916 | FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000, |
2917 | FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001, |
2918 | FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002, |
2919 | FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003, |
2920 | } FMT_CONTROL_PIXEL_ENCODING; |
2921 | |
2922 | /* |
2923 | * FMT_CONTROL_SUBSAMPLING_MODE enum |
2924 | */ |
2925 | |
2926 | typedef enum FMT_CONTROL_SUBSAMPLING_MODE { |
2927 | FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000, |
2928 | FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001, |
2929 | FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002, |
2930 | FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003, |
2931 | } FMT_CONTROL_SUBSAMPLING_MODE; |
2932 | |
2933 | /* |
2934 | * FMT_CONTROL_SUBSAMPLING_ORDER enum |
2935 | */ |
2936 | |
2937 | typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { |
2938 | FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000, |
2939 | FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001, |
2940 | } FMT_CONTROL_SUBSAMPLING_ORDER; |
2941 | |
2942 | /* |
2943 | * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum |
2944 | */ |
2945 | |
2946 | typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { |
2947 | FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000, |
2948 | FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001, |
2949 | } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; |
2950 | |
2951 | /* |
2952 | * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum |
2953 | */ |
2954 | |
2955 | typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { |
2956 | FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000, |
2957 | FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001, |
2958 | } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; |
2959 | |
2960 | /* |
2961 | * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum |
2962 | */ |
2963 | |
2964 | typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { |
2965 | FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000, |
2966 | FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001, |
2967 | FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002, |
2968 | } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; |
2969 | |
2970 | /* |
2971 | * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum |
2972 | */ |
2973 | |
2974 | typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { |
2975 | FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000, |
2976 | FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, |
2977 | FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002, |
2978 | } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; |
2979 | |
2980 | /* |
2981 | * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum |
2982 | */ |
2983 | |
2984 | typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { |
2985 | FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000, |
2986 | FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001, |
2987 | FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002, |
2988 | } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; |
2989 | |
2990 | /* |
2991 | * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum |
2992 | */ |
2993 | |
2994 | typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { |
2995 | FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000, |
2996 | FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001, |
2997 | } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; |
2998 | |
2999 | /* |
3000 | * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum |
3001 | */ |
3002 | |
3003 | typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { |
3004 | FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000, |
3005 | FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001, |
3006 | FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002, |
3007 | FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003, |
3008 | } FMT_BIT_DEPTH_CONTROL_25FRC_SEL; |
3009 | |
3010 | /* |
3011 | * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum |
3012 | */ |
3013 | |
3014 | typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { |
3015 | FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000, |
3016 | FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001, |
3017 | FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002, |
3018 | FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003, |
3019 | } FMT_BIT_DEPTH_CONTROL_50FRC_SEL; |
3020 | |
3021 | /* |
3022 | * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum |
3023 | */ |
3024 | |
3025 | typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { |
3026 | FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000, |
3027 | FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001, |
3028 | FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002, |
3029 | FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003, |
3030 | } FMT_BIT_DEPTH_CONTROL_75FRC_SEL; |
3031 | |
3032 | /* |
3033 | * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum |
3034 | */ |
3035 | |
3036 | typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { |
3037 | FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000, |
3038 | FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001, |
3039 | } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; |
3040 | |
3041 | /* |
3042 | * FMT_CLAMP_CNTL_COLOR_FORMAT enum |
3043 | */ |
3044 | |
3045 | typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { |
3046 | FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000, |
3047 | FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001, |
3048 | FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002, |
3049 | FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003, |
3050 | FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004, |
3051 | FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005, |
3052 | FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006, |
3053 | FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007, |
3054 | } FMT_CLAMP_CNTL_COLOR_FORMAT; |
3055 | |
3056 | /* |
3057 | * FMT_SPATIAL_DITHER_MODE enum |
3058 | */ |
3059 | |
3060 | typedef enum FMT_SPATIAL_DITHER_MODE { |
3061 | FMT_SPATIAL_DITHER_MODE_0 = 0x00000000, |
3062 | FMT_SPATIAL_DITHER_MODE_1 = 0x00000001, |
3063 | FMT_SPATIAL_DITHER_MODE_2 = 0x00000002, |
3064 | FMT_SPATIAL_DITHER_MODE_3 = 0x00000003, |
3065 | } FMT_SPATIAL_DITHER_MODE; |
3066 | |
3067 | /* |
3068 | * FMT_DYNAMIC_EXP_MODE enum |
3069 | */ |
3070 | |
3071 | typedef enum FMT_DYNAMIC_EXP_MODE { |
3072 | FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000, |
3073 | FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001, |
3074 | } FMT_DYNAMIC_EXP_MODE; |
3075 | |
3076 | /* |
3077 | * FMTMEM_PWR_FORCE_CTRL enum |
3078 | */ |
3079 | |
3080 | typedef enum FMTMEM_PWR_FORCE_CTRL { |
3081 | FMTMEM_NO_FORCE_REQUEST = 0x00000000, |
3082 | FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, |
3083 | FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, |
3084 | FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, |
3085 | } FMTMEM_PWR_FORCE_CTRL; |
3086 | |
3087 | /* |
3088 | * FMTMEM_PWR_DIS_CTRL enum |
3089 | */ |
3090 | |
3091 | typedef enum FMTMEM_PWR_DIS_CTRL { |
3092 | FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, |
3093 | FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, |
3094 | } FMTMEM_PWR_DIS_CTRL; |
3095 | |
3096 | /* |
3097 | * FMT_POWER_STATE_ENUM enum |
3098 | */ |
3099 | |
3100 | typedef enum FMT_POWER_STATE_ENUM { |
3101 | FMT_POWER_STATE_ENUM_ON = 0x00000000, |
3102 | FMT_POWER_STATE_ENUM_LS = 0x00000001, |
3103 | FMT_POWER_STATE_ENUM_DS = 0x00000002, |
3104 | FMT_POWER_STATE_ENUM_SD = 0x00000003, |
3105 | } FMT_POWER_STATE_ENUM; |
3106 | |
3107 | /* |
3108 | * FMT_STEREOSYNC_OVERRIDE_CONTROL enum |
3109 | */ |
3110 | |
3111 | typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL { |
3112 | FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000, |
3113 | FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001, |
3114 | } FMT_STEREOSYNC_OVERRIDE_CONTROL; |
3115 | |
3116 | /* |
3117 | * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum |
3118 | */ |
3119 | |
3120 | typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL { |
3121 | FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000, |
3122 | FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001, |
3123 | FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002, |
3124 | FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003, |
3125 | } FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL; |
3126 | |
3127 | /* |
3128 | * FMT_FRAME_RANDOM_ENABLE_CONTROL enum |
3129 | */ |
3130 | |
3131 | typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL { |
3132 | FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000, |
3133 | FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001, |
3134 | } FMT_FRAME_RANDOM_ENABLE_CONTROL; |
3135 | |
3136 | /* |
3137 | * FMT_RGB_RANDOM_ENABLE_CONTROL enum |
3138 | */ |
3139 | |
3140 | typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL { |
3141 | FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000, |
3142 | FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001, |
3143 | } FMT_RGB_RANDOM_ENABLE_CONTROL; |
3144 | |
3145 | /* |
3146 | * ENUM_FMT_PTI_FIELD_POLARITY enum |
3147 | */ |
3148 | |
3149 | typedef enum ENUM_FMT_PTI_FIELD_POLARITY { |
3150 | ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, |
3151 | ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, |
3152 | } ENUM_FMT_PTI_FIELD_POLARITY; |
3153 | |
3154 | /******************************************************* |
3155 | * OPP_PIPE Enums |
3156 | *******************************************************/ |
3157 | |
3158 | /* |
3159 | * OPP_PIPE_CLOCK_ENABLE_CONTROL enum |
3160 | */ |
3161 | |
3162 | typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL { |
3163 | OPP_PIPE_CLOCK_DISABLE = 0x00000000, |
3164 | OPP_PIPE_CLOCK_ENABLE = 0x00000001, |
3165 | } OPP_PIPE_CLOCK_ENABLE_CONTROL; |
3166 | |
3167 | /* |
3168 | * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum |
3169 | */ |
3170 | |
3171 | typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL { |
3172 | OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000, |
3173 | OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001, |
3174 | } OPP_PIPE_DIGTIAL_BYPASS_CONTROL; |
3175 | |
3176 | /******************************************************* |
3177 | * OPP_PIPE_CRC Enums |
3178 | *******************************************************/ |
3179 | |
3180 | /* |
3181 | * OPP_PIPE_CRC_EN enum |
3182 | */ |
3183 | |
3184 | typedef enum OPP_PIPE_CRC_EN { |
3185 | OPP_PIPE_CRC_DISABLE = 0x00000000, |
3186 | OPP_PIPE_CRC_ENABLE = 0x00000001, |
3187 | } OPP_PIPE_CRC_EN; |
3188 | |
3189 | /* |
3190 | * OPP_PIPE_CRC_CONT_EN enum |
3191 | */ |
3192 | |
3193 | typedef enum OPP_PIPE_CRC_CONT_EN { |
3194 | OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000, |
3195 | OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001, |
3196 | } OPP_PIPE_CRC_CONT_EN; |
3197 | |
3198 | /* |
3199 | * OPP_PIPE_CRC_STEREO_MODE enum |
3200 | */ |
3201 | |
3202 | typedef enum OPP_PIPE_CRC_STEREO_MODE { |
3203 | OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000, |
3204 | OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001, |
3205 | OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002, |
3206 | OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003, |
3207 | } OPP_PIPE_CRC_STEREO_MODE; |
3208 | |
3209 | /* |
3210 | * OPP_PIPE_CRC_STEREO_EN enum |
3211 | */ |
3212 | |
3213 | typedef enum OPP_PIPE_CRC_STEREO_EN { |
3214 | OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000, |
3215 | OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001, |
3216 | } OPP_PIPE_CRC_STEREO_EN; |
3217 | |
3218 | /* |
3219 | * OPP_PIPE_CRC_INTERLACE_MODE enum |
3220 | */ |
3221 | |
3222 | typedef enum OPP_PIPE_CRC_INTERLACE_MODE { |
3223 | OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000, |
3224 | OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, |
3225 | OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002, |
3226 | OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003, |
3227 | } OPP_PIPE_CRC_INTERLACE_MODE; |
3228 | |
3229 | /* |
3230 | * OPP_PIPE_CRC_INTERLACE_EN enum |
3231 | */ |
3232 | |
3233 | typedef enum OPP_PIPE_CRC_INTERLACE_EN { |
3234 | OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000, |
3235 | OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001, |
3236 | } OPP_PIPE_CRC_INTERLACE_EN; |
3237 | |
3238 | /* |
3239 | * OPP_PIPE_CRC_PIXEL_SELECT enum |
3240 | */ |
3241 | |
3242 | typedef enum OPP_PIPE_CRC_PIXEL_SELECT { |
3243 | OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000, |
3244 | OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001, |
3245 | OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002, |
3246 | OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003, |
3247 | } OPP_PIPE_CRC_PIXEL_SELECT; |
3248 | |
3249 | /* |
3250 | * OPP_PIPE_CRC_SOURCE_SELECT enum |
3251 | */ |
3252 | |
3253 | typedef enum OPP_PIPE_CRC_SOURCE_SELECT { |
3254 | OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000, |
3255 | OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001, |
3256 | } OPP_PIPE_CRC_SOURCE_SELECT; |
3257 | |
3258 | /* |
3259 | * OPP_PIPE_CRC_ONE_SHOT_PENDING enum |
3260 | */ |
3261 | |
3262 | typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING { |
3263 | OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000, |
3264 | OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001, |
3265 | } OPP_PIPE_CRC_ONE_SHOT_PENDING; |
3266 | |
3267 | /******************************************************* |
3268 | * OPP_TOP Enums |
3269 | *******************************************************/ |
3270 | |
3271 | /* |
3272 | * OPP_TOP_CLOCK_GATING_CONTROL enum |
3273 | */ |
3274 | |
3275 | typedef enum OPP_TOP_CLOCK_GATING_CONTROL { |
3276 | OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000, |
3277 | OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001, |
3278 | } OPP_TOP_CLOCK_GATING_CONTROL; |
3279 | |
3280 | /* |
3281 | * OPP_TOP_CLOCK_ENABLE_STATUS enum |
3282 | */ |
3283 | |
3284 | typedef enum OPP_TOP_CLOCK_ENABLE_STATUS { |
3285 | OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000, |
3286 | OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001, |
3287 | } OPP_TOP_CLOCK_ENABLE_STATUS; |
3288 | |
3289 | /* |
3290 | * OPP_TEST_CLK_SEL_CONTROL enum |
3291 | */ |
3292 | |
3293 | typedef enum OPP_TEST_CLK_SEL_CONTROL { |
3294 | OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000, |
3295 | OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001, |
3296 | OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002, |
3297 | OPP_TEST_CLK_SEL_RESERVED0 = 0x00000003, |
3298 | OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000004, |
3299 | OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000005, |
3300 | OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x00000006, |
3301 | OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x00000007, |
3302 | OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 0x00000008, |
3303 | OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 0x00000009, |
3304 | } OPP_TEST_CLK_SEL_CONTROL; |
3305 | |
3306 | /******************************************************* |
3307 | * OTG Enums |
3308 | *******************************************************/ |
3309 | |
3310 | /* |
3311 | * OTG_CONTROL_OTG_START_POINT_CNTL enum |
3312 | */ |
3313 | |
3314 | typedef enum OTG_CONTROL_OTG_START_POINT_CNTL { |
3315 | OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000, |
3316 | OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001, |
3317 | } OTG_CONTROL_OTG_START_POINT_CNTL; |
3318 | |
3319 | /* |
3320 | * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum |
3321 | */ |
3322 | |
3323 | typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL { |
3324 | OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000, |
3325 | OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001, |
3326 | } OTG_CONTROL_OTG_FIELD_NUMBER_CNTL; |
3327 | |
3328 | /* |
3329 | * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum |
3330 | */ |
3331 | |
3332 | typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL { |
3333 | OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000, |
3334 | OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001, |
3335 | OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 0x00000002, |
3336 | OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003, |
3337 | } OTG_CONTROL_OTG_DISABLE_POINT_CNTL; |
3338 | |
3339 | /* |
3340 | * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum |
3341 | */ |
3342 | |
3343 | typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY { |
3344 | OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000, |
3345 | OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001, |
3346 | } OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY; |
3347 | |
3348 | /* |
3349 | * OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum |
3350 | */ |
3351 | |
3352 | typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE { |
3353 | OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000, |
3354 | OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001, |
3355 | } OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE; |
3356 | |
3357 | /* |
3358 | * OTG_CONTROL_OTG_SOF_PULL_EN enum |
3359 | */ |
3360 | |
3361 | typedef enum OTG_CONTROL_OTG_SOF_PULL_EN { |
3362 | OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0x00000000, |
3363 | OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 0x00000001, |
3364 | } OTG_CONTROL_OTG_SOF_PULL_EN; |
3365 | |
3366 | /* |
3367 | * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum |
3368 | */ |
3369 | |
3370 | typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL { |
3371 | OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000, |
3372 | OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001, |
3373 | } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL; |
3374 | |
3375 | /* |
3376 | * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum |
3377 | */ |
3378 | |
3379 | typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL { |
3380 | OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000, |
3381 | OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001, |
3382 | } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL; |
3383 | |
3384 | /* |
3385 | * OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum |
3386 | */ |
3387 | |
3388 | typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN { |
3389 | OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000, |
3390 | OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001, |
3391 | } OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN; |
3392 | |
3393 | /* |
3394 | * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum |
3395 | */ |
3396 | |
3397 | typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC { |
3398 | OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000, |
3399 | OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001, |
3400 | } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC; |
3401 | |
3402 | /* |
3403 | * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum |
3404 | */ |
3405 | |
3406 | typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT { |
3407 | OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000, |
3408 | OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001, |
3409 | } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT; |
3410 | |
3411 | /* |
3412 | * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum |
3413 | */ |
3414 | |
3415 | typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD { |
3416 | OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000, |
3417 | OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001, |
3418 | } OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD; |
3419 | |
3420 | /* |
3421 | * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum |
3422 | */ |
3423 | |
3424 | typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { |
3425 | OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000, |
3426 | OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001, |
3427 | } OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; |
3428 | |
3429 | /* |
3430 | * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum |
3431 | */ |
3432 | |
3433 | typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR { |
3434 | OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000, |
3435 | OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001, |
3436 | } OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR; |
3437 | |
3438 | /* |
3439 | * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum |
3440 | */ |
3441 | |
3442 | typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN { |
3443 | OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000, |
3444 | OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001, |
3445 | } OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN; |
3446 | |
3447 | /* |
3448 | * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum |
3449 | */ |
3450 | |
3451 | typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT { |
3452 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000, |
3453 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001, |
3454 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002, |
3455 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003, |
3456 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004, |
3457 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005, |
3458 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006, |
3459 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, |
3460 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, |
3461 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, |
3462 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, |
3463 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b, |
3464 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c, |
3465 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, |
3466 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e, |
3467 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, |
3468 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, |
3469 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, |
3470 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012, |
3471 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013, |
3472 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014, |
3473 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, |
3474 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, |
3475 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017, |
3476 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018, |
3477 | } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT; |
3478 | |
3479 | /* |
3480 | * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum |
3481 | */ |
3482 | |
3483 | typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT { |
3484 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000, |
3485 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001, |
3486 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002, |
3487 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003, |
3488 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004, |
3489 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005, |
3490 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006, |
3491 | OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007, |
3492 | } OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT; |
3493 | |
3494 | /* |
3495 | * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum |
3496 | */ |
3497 | |
3498 | typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT { |
3499 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000, |
3500 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001, |
3501 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002, |
3502 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003, |
3503 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004, |
3504 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005, |
3505 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006, |
3506 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, |
3507 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, |
3508 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, |
3509 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, |
3510 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b, |
3511 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c, |
3512 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, |
3513 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e, |
3514 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, |
3515 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, |
3516 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, |
3517 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012, |
3518 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013, |
3519 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014, |
3520 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, |
3521 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, |
3522 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017, |
3523 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018, |
3524 | } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT; |
3525 | |
3526 | /* |
3527 | * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum |
3528 | */ |
3529 | |
3530 | typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT { |
3531 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, |
3532 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, |
3533 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, |
3534 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, |
3535 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 0x00000004, |
3536 | OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 0x00000005, |
3537 | } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT; |
3538 | |
3539 | /* |
3540 | * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum |
3541 | */ |
3542 | |
3543 | typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT { |
3544 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000, |
3545 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001, |
3546 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002, |
3547 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003, |
3548 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004, |
3549 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005, |
3550 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006, |
3551 | OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007, |
3552 | } OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT; |
3553 | |
3554 | /* |
3555 | * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum |
3556 | */ |
3557 | |
3558 | typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT { |
3559 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, |
3560 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, |
3561 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, |
3562 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, |
3563 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 0x00000004, |
3564 | OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 0x00000005, |
3565 | } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT; |
3566 | |
3567 | /* |
3568 | * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum |
3569 | */ |
3570 | |
3571 | typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN { |
3572 | OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000, |
3573 | OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001, |
3574 | } OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN; |
3575 | |
3576 | /* |
3577 | * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum |
3578 | */ |
3579 | |
3580 | typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR { |
3581 | OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000, |
3582 | OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001, |
3583 | } OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR; |
3584 | |
3585 | /* |
3586 | * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum |
3587 | */ |
3588 | |
3589 | typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN { |
3590 | OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000, |
3591 | OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001, |
3592 | } OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN; |
3593 | |
3594 | /* |
3595 | * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum |
3596 | */ |
3597 | |
3598 | typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR { |
3599 | OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000, |
3600 | OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001, |
3601 | } OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR; |
3602 | |
3603 | /* |
3604 | * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum |
3605 | */ |
3606 | |
3607 | typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE { |
3608 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000, |
3609 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001, |
3610 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002, |
3611 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003, |
3612 | } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE; |
3613 | |
3614 | /* |
3615 | * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum |
3616 | */ |
3617 | |
3618 | typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK { |
3619 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000, |
3620 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001, |
3621 | } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK; |
3622 | |
3623 | /* |
3624 | * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum |
3625 | */ |
3626 | |
3627 | typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL { |
3628 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000, |
3629 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001, |
3630 | } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL; |
3631 | |
3632 | /* |
3633 | * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum |
3634 | */ |
3635 | |
3636 | typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR { |
3637 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000, |
3638 | OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001, |
3639 | } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR; |
3640 | |
3641 | /* |
3642 | * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum |
3643 | */ |
3644 | |
3645 | typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT { |
3646 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000, |
3647 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001, |
3648 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002, |
3649 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003, |
3650 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004, |
3651 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005, |
3652 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006, |
3653 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007, |
3654 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008, |
3655 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009, |
3656 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a, |
3657 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b, |
3658 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c, |
3659 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d, |
3660 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e, |
3661 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE = 0x0000000f, |
3662 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010, |
3663 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011, |
3664 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012, |
3665 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013, |
3666 | } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT; |
3667 | |
3668 | /* |
3669 | * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum |
3670 | */ |
3671 | |
3672 | typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY { |
3673 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000, |
3674 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001, |
3675 | } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY; |
3676 | |
3677 | /* |
3678 | * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum |
3679 | */ |
3680 | |
3681 | typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY { |
3682 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000, |
3683 | OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001, |
3684 | } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY; |
3685 | |
3686 | /* |
3687 | * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum |
3688 | */ |
3689 | |
3690 | typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE { |
3691 | OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000, |
3692 | OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001, |
3693 | OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002, |
3694 | OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003, |
3695 | } OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE; |
3696 | |
3697 | /* |
3698 | * OTG_CONTROL_OTG_MASTER_EN enum |
3699 | */ |
3700 | |
3701 | typedef enum OTG_CONTROL_OTG_MASTER_EN { |
3702 | OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000, |
3703 | OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001, |
3704 | } OTG_CONTROL_OTG_MASTER_EN; |
3705 | |
3706 | /* |
3707 | * OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN enum |
3708 | */ |
3709 | |
3710 | typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN { |
3711 | OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE = 0x00000000, |
3712 | OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE = 0x00000001, |
3713 | } OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN; |
3714 | |
3715 | /* |
3716 | * OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE enum |
3717 | */ |
3718 | |
3719 | typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE { |
3720 | OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE = 0x00000000, |
3721 | OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE = 0x00000001, |
3722 | } OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE; |
3723 | |
3724 | /* |
3725 | * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum |
3726 | */ |
3727 | |
3728 | typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE { |
3729 | OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000, |
3730 | OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001, |
3731 | } OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE; |
3732 | |
3733 | /* |
3734 | * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum |
3735 | */ |
3736 | |
3737 | typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD { |
3738 | OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000, |
3739 | OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001, |
3740 | OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002, |
3741 | OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003, |
3742 | } OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD; |
3743 | |
3744 | /* |
3745 | * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY enum |
3746 | */ |
3747 | |
3748 | typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY { |
3749 | OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000, |
3750 | OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001, |
3751 | } OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY; |
3752 | |
3753 | /* |
3754 | * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT enum |
3755 | */ |
3756 | |
3757 | typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT { |
3758 | OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE = 0x00000000, |
3759 | OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE = 0x00000001, |
3760 | } OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT; |
3761 | |
3762 | /* |
3763 | * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum |
3764 | */ |
3765 | |
3766 | typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN { |
3767 | OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000, |
3768 | OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001, |
3769 | } OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN; |
3770 | |
3771 | /* |
3772 | * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum |
3773 | */ |
3774 | |
3775 | typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE { |
3776 | OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000, |
3777 | OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001, |
3778 | } OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; |
3779 | |
3780 | /* |
3781 | * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum |
3782 | */ |
3783 | |
3784 | typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR { |
3785 | OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000, |
3786 | OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001, |
3787 | } OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR; |
3788 | |
3789 | /* |
3790 | * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum |
3791 | */ |
3792 | |
3793 | typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE { |
3794 | OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000, |
3795 | OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001, |
3796 | OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002, |
3797 | OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003, |
3798 | } OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE; |
3799 | |
3800 | /* |
3801 | * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum |
3802 | */ |
3803 | |
3804 | typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY { |
3805 | OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000, |
3806 | OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001, |
3807 | } OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY; |
3808 | |
3809 | /* |
3810 | * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum |
3811 | */ |
3812 | |
3813 | typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY { |
3814 | OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000, |
3815 | OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001, |
3816 | } OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY; |
3817 | |
3818 | /* |
3819 | * OTG_STEREO_CONTROL_OTG_STEREO_EN enum |
3820 | */ |
3821 | |
3822 | typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN { |
3823 | OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000, |
3824 | OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001, |
3825 | } OTG_STEREO_CONTROL_OTG_STEREO_EN; |
3826 | |
3827 | /* |
3828 | * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum |
3829 | */ |
3830 | |
3831 | typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR { |
3832 | OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000, |
3833 | OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001, |
3834 | } OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR; |
3835 | |
3836 | /* |
3837 | * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum |
3838 | */ |
3839 | |
3840 | typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL { |
3841 | OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000, |
3842 | OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001, |
3843 | OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002, |
3844 | OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003, |
3845 | } OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL; |
3846 | |
3847 | /* |
3848 | * OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY enum |
3849 | */ |
3850 | |
3851 | typedef enum OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY { |
3852 | OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000, |
3853 | OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001, |
3854 | } OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY; |
3855 | |
3856 | /* |
3857 | * OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY enum |
3858 | */ |
3859 | |
3860 | typedef enum OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY { |
3861 | OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000, |
3862 | OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001, |
3863 | } OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY; |
3864 | |
3865 | /* |
3866 | * OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN enum |
3867 | */ |
3868 | |
3869 | typedef enum OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN { |
3870 | OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE = 0x00000000, |
3871 | OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE = 0x00000001, |
3872 | } OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN; |
3873 | |
3874 | /* |
3875 | * OTG_START_LINE_CONTROL_OTG_PREFETCH_EN enum |
3876 | */ |
3877 | |
3878 | typedef enum OTG_START_LINE_CONTROL_OTG_PREFETCH_EN { |
3879 | OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE = 0x00000000, |
3880 | OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE = 0x00000001, |
3881 | } OTG_START_LINE_CONTROL_OTG_PREFETCH_EN; |
3882 | |
3883 | /* |
3884 | * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum |
3885 | */ |
3886 | |
3887 | typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK { |
3888 | OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000, |
3889 | OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001, |
3890 | } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK; |
3891 | |
3892 | /* |
3893 | * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum |
3894 | */ |
3895 | |
3896 | typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE { |
3897 | OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000, |
3898 | OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001, |
3899 | } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE; |
3900 | |
3901 | /* |
3902 | * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK enum |
3903 | */ |
3904 | |
3905 | typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK { |
3906 | OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE = 0x00000000, |
3907 | OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE = 0x00000001, |
3908 | } OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK; |
3909 | |
3910 | /* |
3911 | * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE enum |
3912 | */ |
3913 | |
3914 | typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE { |
3915 | OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE = 0x00000000, |
3916 | OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE = 0x00000001, |
3917 | } OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE; |
3918 | |
3919 | /* |
3920 | * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum |
3921 | */ |
3922 | |
3923 | typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK { |
3924 | OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000, |
3925 | OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001, |
3926 | } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK; |
3927 | |
3928 | /* |
3929 | * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum |
3930 | */ |
3931 | |
3932 | typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE { |
3933 | OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000, |
3934 | OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001, |
3935 | } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE; |
3936 | |
3937 | /* |
3938 | * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum |
3939 | */ |
3940 | |
3941 | typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK { |
3942 | OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000, |
3943 | OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001, |
3944 | } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK; |
3945 | |
3946 | /* |
3947 | * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum |
3948 | */ |
3949 | |
3950 | typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE { |
3951 | OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000, |
3952 | OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001, |
3953 | } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE; |
3954 | |
3955 | /* |
3956 | * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum |
3957 | */ |
3958 | |
3959 | typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK { |
3960 | OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000, |
3961 | OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001, |
3962 | } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK; |
3963 | |
3964 | /* |
3965 | * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum |
3966 | */ |
3967 | |
3968 | typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE { |
3969 | OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000, |
3970 | OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001, |
3971 | } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE; |
3972 | |
3973 | /* |
3974 | * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum |
3975 | */ |
3976 | |
3977 | typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK { |
3978 | OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000, |
3979 | OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001, |
3980 | } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK; |
3981 | |
3982 | /* |
3983 | * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum |
3984 | */ |
3985 | |
3986 | typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE { |
3987 | OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000, |
3988 | OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001, |
3989 | } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE; |
3990 | |
3991 | /* |
3992 | * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum |
3993 | */ |
3994 | |
3995 | typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK { |
3996 | OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000, |
3997 | OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001, |
3998 | } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK; |
3999 | |
4000 | /* |
4001 | * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum |
4002 | */ |
4003 | |
4004 | typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE { |
4005 | OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000, |
4006 | OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001, |
4007 | } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE; |
4008 | |
4009 | /* |
4010 | * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum |
4011 | */ |
4012 | |
4013 | typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK { |
4014 | OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000, |
4015 | OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001, |
4016 | } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK; |
4017 | |
4018 | /* |
4019 | * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum |
4020 | */ |
4021 | |
4022 | typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE { |
4023 | OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000, |
4024 | OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001, |
4025 | } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE; |
4026 | |
4027 | /* |
4028 | * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum |
4029 | */ |
4030 | |
4031 | typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK { |
4032 | OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000, |
4033 | OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001, |
4034 | } OTG_UPDATE_LOCK_OTG_UPDATE_LOCK; |
4035 | |
4036 | /* |
4037 | * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum |
4038 | */ |
4039 | |
4040 | typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY { |
4041 | OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000, |
4042 | OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001, |
4043 | } OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY; |
4044 | |
4045 | /* |
4046 | * OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN enum |
4047 | */ |
4048 | |
4049 | typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN { |
4050 | OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000, |
4051 | OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001, |
4052 | } OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN; |
4053 | |
4054 | /* |
4055 | * OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE enum |
4056 | */ |
4057 | |
4058 | typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE { |
4059 | OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000, |
4060 | OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001, |
4061 | OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002, |
4062 | OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003, |
4063 | } OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE; |
4064 | |
4065 | /* |
4066 | * OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE enum |
4067 | */ |
4068 | |
4069 | typedef enum OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE { |
4070 | OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000, |
4071 | OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001, |
4072 | } OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE; |
4073 | |
4074 | /* |
4075 | * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum |
4076 | */ |
4077 | |
4078 | typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { |
4079 | MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000, |
4080 | MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001, |
4081 | } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; |
4082 | |
4083 | /* |
4084 | * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum |
4085 | */ |
4086 | |
4087 | typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME { |
4088 | OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000, |
4089 | OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001, |
4090 | OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002, |
4091 | OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003, |
4092 | } OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME; |
4093 | |
4094 | /* |
4095 | * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum |
4096 | */ |
4097 | |
4098 | typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { |
4099 | MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000, |
4100 | MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001, |
4101 | } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; |
4102 | |
4103 | /* |
4104 | * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum |
4105 | */ |
4106 | |
4107 | typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { |
4108 | MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000, |
4109 | MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001, |
4110 | MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002, |
4111 | MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003, |
4112 | } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; |
4113 | |
4114 | /* |
4115 | * OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE enum |
4116 | */ |
4117 | |
4118 | typedef enum OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE { |
4119 | OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000, |
4120 | OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001, |
4121 | OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002, |
4122 | } OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE; |
4123 | |
4124 | /* |
4125 | * OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR enum |
4126 | */ |
4127 | |
4128 | typedef enum OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR { |
4129 | OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE = 0x00000000, |
4130 | OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE = 0x00000001, |
4131 | } OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR; |
4132 | |
4133 | /* |
4134 | * OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR enum |
4135 | */ |
4136 | |
4137 | typedef enum OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR { |
4138 | OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000, |
4139 | OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001, |
4140 | } OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR; |
4141 | |
4142 | /* |
4143 | * OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR enum |
4144 | */ |
4145 | |
4146 | typedef enum OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR { |
4147 | OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0x00000000, |
4148 | OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE = 0x00000001, |
4149 | } OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR; |
4150 | |
4151 | /* |
4152 | * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum |
4153 | */ |
4154 | |
4155 | typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { |
4156 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000, |
4157 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001, |
4158 | } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; |
4159 | |
4160 | /* |
4161 | * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum |
4162 | */ |
4163 | |
4164 | typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE { |
4165 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000, |
4166 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001, |
4167 | } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE; |
4168 | |
4169 | /* |
4170 | * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum |
4171 | */ |
4172 | |
4173 | typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR { |
4174 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000, |
4175 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001, |
4176 | } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR; |
4177 | |
4178 | /* |
4179 | * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum |
4180 | */ |
4181 | |
4182 | typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE { |
4183 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000, |
4184 | OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001, |
4185 | } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE; |
4186 | |
4187 | /* |
4188 | * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum |
4189 | */ |
4190 | |
4191 | typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR { |
4192 | OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000, |
4193 | OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001, |
4194 | } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR; |
4195 | |
4196 | /* |
4197 | * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum |
4198 | */ |
4199 | |
4200 | typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE { |
4201 | OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000, |
4202 | OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001, |
4203 | } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE; |
4204 | |
4205 | /* |
4206 | * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum |
4207 | */ |
4208 | |
4209 | typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE { |
4210 | OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000, |
4211 | OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001, |
4212 | } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE; |
4213 | |
4214 | /* |
4215 | * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum |
4216 | */ |
4217 | |
4218 | typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR { |
4219 | OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000, |
4220 | OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001, |
4221 | } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR; |
4222 | |
4223 | /* |
4224 | * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum |
4225 | */ |
4226 | |
4227 | typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE { |
4228 | OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000, |
4229 | OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001, |
4230 | } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE; |
4231 | |
4232 | /* |
4233 | * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum |
4234 | */ |
4235 | |
4236 | typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE { |
4237 | OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000, |
4238 | OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001, |
4239 | } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE; |
4240 | |
4241 | /* |
4242 | * OTG_CRC_CNTL_OTG_CRC_EN enum |
4243 | */ |
4244 | |
4245 | typedef enum OTG_CRC_CNTL_OTG_CRC_EN { |
4246 | OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000, |
4247 | OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001, |
4248 | } OTG_CRC_CNTL_OTG_CRC_EN; |
4249 | |
4250 | /* |
4251 | * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum |
4252 | */ |
4253 | |
4254 | typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN { |
4255 | OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000, |
4256 | OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001, |
4257 | } OTG_CRC_CNTL_OTG_CRC_CONT_EN; |
4258 | |
4259 | /* |
4260 | * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum |
4261 | */ |
4262 | |
4263 | typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE { |
4264 | OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000, |
4265 | OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001, |
4266 | OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002, |
4267 | OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003, |
4268 | } OTG_CRC_CNTL_OTG_CRC_STEREO_MODE; |
4269 | |
4270 | /* |
4271 | * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum |
4272 | */ |
4273 | |
4274 | typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE { |
4275 | OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000, |
4276 | OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, |
4277 | OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, |
4278 | OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003, |
4279 | } OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE; |
4280 | |
4281 | /* |
4282 | * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum |
4283 | */ |
4284 | |
4285 | typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS { |
4286 | OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000, |
4287 | OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001, |
4288 | } OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS; |
4289 | |
4290 | /* |
4291 | * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum |
4292 | */ |
4293 | |
4294 | typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT { |
4295 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000, |
4296 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001, |
4297 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002, |
4298 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003, |
4299 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004, |
4300 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005, |
4301 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006, |
4302 | OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007, |
4303 | } OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT; |
4304 | |
4305 | /* |
4306 | * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum |
4307 | */ |
4308 | |
4309 | typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT { |
4310 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000, |
4311 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001, |
4312 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002, |
4313 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003, |
4314 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004, |
4315 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005, |
4316 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006, |
4317 | OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007, |
4318 | } OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT; |
4319 | |
4320 | /* |
4321 | * OTG_CRC_CNTL2_OTG_CRC_DSC_MODE enum |
4322 | */ |
4323 | |
4324 | typedef enum OTG_CRC_CNTL2_OTG_CRC_DSC_MODE { |
4325 | OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE = 0x00000000, |
4326 | OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE = 0x00000001, |
4327 | } OTG_CRC_CNTL2_OTG_CRC_DSC_MODE; |
4328 | |
4329 | /* |
4330 | * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE enum |
4331 | */ |
4332 | |
4333 | typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE { |
4334 | OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE = 0x00000000, |
4335 | OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE = 0x00000001, |
4336 | } OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE; |
4337 | |
4338 | /* |
4339 | * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE enum |
4340 | */ |
4341 | |
4342 | typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE { |
4343 | OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE = 0x00000000, |
4344 | OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1 = 0x00000001, |
4345 | OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2 = 0x00000002, |
4346 | OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3 = 0x00000003, |
4347 | } OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE; |
4348 | |
4349 | /* |
4350 | * OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT enum |
4351 | */ |
4352 | |
4353 | typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT { |
4354 | OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0 = 0x00000000, |
4355 | OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1 = 0x00000001, |
4356 | OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2 = 0x00000002, |
4357 | OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3 = 0x00000003, |
4358 | } OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT; |
4359 | |
4360 | /* |
4361 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE enum |
4362 | */ |
4363 | |
4364 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE { |
4365 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000, |
4366 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001, |
4367 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002, |
4368 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003, |
4369 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE; |
4370 | |
4371 | /* |
4372 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum |
4373 | */ |
4374 | |
4375 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE { |
4376 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000, |
4377 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001, |
4378 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE; |
4379 | |
4380 | /* |
4381 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum |
4382 | */ |
4383 | |
4384 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE { |
4385 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000, |
4386 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001, |
4387 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE; |
4388 | |
4389 | /* |
4390 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum |
4391 | */ |
4392 | |
4393 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW { |
4394 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000, |
4395 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001, |
4396 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002, |
4397 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003, |
4398 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW; |
4399 | |
4400 | /* |
4401 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE enum |
4402 | */ |
4403 | |
4404 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE { |
4405 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000, |
4406 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001, |
4407 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE; |
4408 | |
4409 | /* |
4410 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE enum |
4411 | */ |
4412 | |
4413 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE { |
4414 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000, |
4415 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001, |
4416 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE; |
4417 | |
4418 | /* |
4419 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY enum |
4420 | */ |
4421 | |
4422 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY { |
4423 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000, |
4424 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001, |
4425 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY; |
4426 | |
4427 | /* |
4428 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY enum |
4429 | */ |
4430 | |
4431 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY { |
4432 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000, |
4433 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001, |
4434 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY; |
4435 | |
4436 | /* |
4437 | * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE enum |
4438 | */ |
4439 | |
4440 | typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE { |
4441 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000, |
4442 | OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001, |
4443 | } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE; |
4444 | |
4445 | /* |
4446 | * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum |
4447 | */ |
4448 | |
4449 | typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE { |
4450 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000, |
4451 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001, |
4452 | } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE; |
4453 | |
4454 | /* |
4455 | * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR enum |
4456 | */ |
4457 | |
4458 | typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR { |
4459 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000, |
4460 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001, |
4461 | } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR; |
4462 | |
4463 | /* |
4464 | * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE enum |
4465 | */ |
4466 | |
4467 | typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE { |
4468 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000, |
4469 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001, |
4470 | } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE; |
4471 | |
4472 | /* |
4473 | * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum |
4474 | */ |
4475 | |
4476 | typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT { |
4477 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000, |
4478 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001, |
4479 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002, |
4480 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003, |
4481 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004, |
4482 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005, |
4483 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006, |
4484 | OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007, |
4485 | } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT; |
4486 | |
4487 | /* |
4488 | * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE enum |
4489 | */ |
4490 | |
4491 | typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE { |
4492 | OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000, |
4493 | OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001, |
4494 | } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE; |
4495 | |
4496 | /* |
4497 | * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR enum |
4498 | */ |
4499 | |
4500 | typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR { |
4501 | OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000, |
4502 | OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001, |
4503 | } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR; |
4504 | |
4505 | /* |
4506 | * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE enum |
4507 | */ |
4508 | |
4509 | typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE { |
4510 | OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000, |
4511 | OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001, |
4512 | } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE; |
4513 | |
4514 | /* |
4515 | * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum |
4516 | */ |
4517 | |
4518 | typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE { |
4519 | OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000, |
4520 | OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001, |
4521 | } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE; |
4522 | |
4523 | /* |
4524 | * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR enum |
4525 | */ |
4526 | |
4527 | typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR { |
4528 | OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000, |
4529 | OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001, |
4530 | } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR; |
4531 | |
4532 | /* |
4533 | * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum |
4534 | */ |
4535 | |
4536 | typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE { |
4537 | OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000, |
4538 | OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001, |
4539 | } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE; |
4540 | |
4541 | /* |
4542 | * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum |
4543 | */ |
4544 | |
4545 | typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE { |
4546 | OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000, |
4547 | OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001, |
4548 | } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE; |
4549 | |
4550 | /* |
4551 | * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum |
4552 | */ |
4553 | |
4554 | typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR { |
4555 | OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000, |
4556 | OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001, |
4557 | } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR; |
4558 | |
4559 | /* |
4560 | * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum |
4561 | */ |
4562 | |
4563 | typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE { |
4564 | OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000, |
4565 | OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001, |
4566 | } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE; |
4567 | |
4568 | /* |
4569 | * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum |
4570 | */ |
4571 | |
4572 | typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE { |
4573 | OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000, |
4574 | OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001, |
4575 | } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE; |
4576 | |
4577 | /* |
4578 | * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum |
4579 | */ |
4580 | |
4581 | typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE { |
4582 | OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000, |
4583 | OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001, |
4584 | } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE; |
4585 | |
4586 | /* |
4587 | * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum |
4588 | */ |
4589 | |
4590 | typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN { |
4591 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000, |
4592 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001, |
4593 | } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN; |
4594 | |
4595 | /* |
4596 | * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum |
4597 | */ |
4598 | |
4599 | typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB { |
4600 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000, |
4601 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001, |
4602 | } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB; |
4603 | |
4604 | /* |
4605 | * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum |
4606 | */ |
4607 | |
4608 | typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE { |
4609 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000, |
4610 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001, |
4611 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002, |
4612 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003, |
4613 | } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE; |
4614 | |
4615 | /* |
4616 | * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum |
4617 | */ |
4618 | |
4619 | typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR { |
4620 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000, |
4621 | OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001, |
4622 | } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR; |
4623 | |
4624 | /* |
4625 | * OTG_V_SYNC_A_POL enum |
4626 | */ |
4627 | |
4628 | typedef enum OTG_V_SYNC_A_POL { |
4629 | OTG_V_SYNC_A_POL_HIGH = 0x00000000, |
4630 | OTG_V_SYNC_A_POL_LOW = 0x00000001, |
4631 | } OTG_V_SYNC_A_POL; |
4632 | |
4633 | /* |
4634 | * OTG_H_SYNC_A_POL enum |
4635 | */ |
4636 | |
4637 | typedef enum OTG_H_SYNC_A_POL { |
4638 | OTG_H_SYNC_A_POL_HIGH = 0x00000000, |
4639 | OTG_H_SYNC_A_POL_LOW = 0x00000001, |
4640 | } OTG_H_SYNC_A_POL; |
4641 | |
4642 | /* |
4643 | * OTG_HORZ_REPETITION_COUNT enum |
4644 | */ |
4645 | |
4646 | typedef enum OTG_HORZ_REPETITION_COUNT { |
4647 | OTG_HORZ_REPETITION_COUNT_0 = 0x00000000, |
4648 | OTG_HORZ_REPETITION_COUNT_1 = 0x00000001, |
4649 | OTG_HORZ_REPETITION_COUNT_2 = 0x00000002, |
4650 | OTG_HORZ_REPETITION_COUNT_3 = 0x00000003, |
4651 | OTG_HORZ_REPETITION_COUNT_4 = 0x00000004, |
4652 | OTG_HORZ_REPETITION_COUNT_5 = 0x00000005, |
4653 | OTG_HORZ_REPETITION_COUNT_6 = 0x00000006, |
4654 | OTG_HORZ_REPETITION_COUNT_7 = 0x00000007, |
4655 | OTG_HORZ_REPETITION_COUNT_8 = 0x00000008, |
4656 | OTG_HORZ_REPETITION_COUNT_9 = 0x00000009, |
4657 | OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a, |
4658 | OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b, |
4659 | OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c, |
4660 | OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d, |
4661 | OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e, |
4662 | OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f, |
4663 | } OTG_HORZ_REPETITION_COUNT; |
4664 | |
4665 | /* |
4666 | * MASTER_UPDATE_LOCK_SEL enum |
4667 | */ |
4668 | |
4669 | typedef enum MASTER_UPDATE_LOCK_SEL { |
4670 | MASTER_UPDATE_LOCK_SEL_0 = 0x00000000, |
4671 | MASTER_UPDATE_LOCK_SEL_1 = 0x00000001, |
4672 | MASTER_UPDATE_LOCK_SEL_2 = 0x00000002, |
4673 | MASTER_UPDATE_LOCK_SEL_3 = 0x00000003, |
4674 | MASTER_UPDATE_LOCK_SEL_4 = 0x00000004, |
4675 | MASTER_UPDATE_LOCK_SEL_5 = 0x00000005, |
4676 | } MASTER_UPDATE_LOCK_SEL; |
4677 | |
4678 | /* |
4679 | * DRR_UPDATE_LOCK_SEL enum |
4680 | */ |
4681 | |
4682 | typedef enum DRR_UPDATE_LOCK_SEL { |
4683 | DRR_UPDATE_LOCK_SEL_0 = 0x00000000, |
4684 | DRR_UPDATE_LOCK_SEL_1 = 0x00000001, |
4685 | DRR_UPDATE_LOCK_SEL_2 = 0x00000002, |
4686 | DRR_UPDATE_LOCK_SEL_3 = 0x00000003, |
4687 | DRR_UPDATE_LOCK_SEL_4 = 0x00000004, |
4688 | DRR_UPDATE_LOCK_SEL_5 = 0x00000005, |
4689 | } DRR_UPDATE_LOCK_SEL; |
4690 | |
4691 | /* |
4692 | * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum |
4693 | */ |
4694 | |
4695 | typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL { |
4696 | OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000, |
4697 | OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001, |
4698 | OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002, |
4699 | OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003, |
4700 | OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4 = 0x00000004, |
4701 | OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5 = 0x00000005, |
4702 | } OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL; |
4703 | |
4704 | /* |
4705 | * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum |
4706 | */ |
4707 | |
4708 | typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD { |
4709 | MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000, |
4710 | MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001, |
4711 | MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000002, |
4712 | } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD; |
4713 | |
4714 | /* |
4715 | * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum |
4716 | */ |
4717 | |
4718 | typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL { |
4719 | MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000, |
4720 | MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001, |
4721 | MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002, |
4722 | MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003, |
4723 | } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL; |
4724 | |
4725 | /* |
4726 | * OTG_H_TIMING_DIV_BY2 enum |
4727 | */ |
4728 | |
4729 | typedef enum OTG_H_TIMING_DIV_BY2 { |
4730 | OTG_H_TIMING_DIV_BY2_FALSE = 0x00000000, |
4731 | OTG_H_TIMING_DIV_BY2_TRUE = 0x00000001, |
4732 | } OTG_H_TIMING_DIV_BY2; |
4733 | |
4734 | /* |
4735 | * OTG_H_TIMING_DIV_BY2_UPDATE_MODE enum |
4736 | */ |
4737 | |
4738 | typedef enum OTG_H_TIMING_DIV_BY2_UPDATE_MODE { |
4739 | OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0 = 0x00000000, |
4740 | OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1 = 0x00000001, |
4741 | } OTG_H_TIMING_DIV_BY2_UPDATE_MODE; |
4742 | |
4743 | /* |
4744 | * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum |
4745 | */ |
4746 | |
4747 | typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL { |
4748 | OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, |
4749 | OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, |
4750 | OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, |
4751 | OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, |
4752 | } OTG_TRIGA_RISING_EDGE_DETECT_CNTL; |
4753 | |
4754 | /* |
4755 | * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum |
4756 | */ |
4757 | |
4758 | typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL { |
4759 | OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, |
4760 | OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, |
4761 | OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, |
4762 | OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, |
4763 | } OTG_TRIGA_FALLING_EDGE_DETECT_CNTL; |
4764 | |
4765 | /* |
4766 | * OTG_TRIGA_FREQUENCY_SELECT enum |
4767 | */ |
4768 | |
4769 | typedef enum OTG_TRIGA_FREQUENCY_SELECT { |
4770 | OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000, |
4771 | OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001, |
4772 | OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002, |
4773 | OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003, |
4774 | } OTG_TRIGA_FREQUENCY_SELECT; |
4775 | |
4776 | /* |
4777 | * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum |
4778 | */ |
4779 | |
4780 | typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL { |
4781 | OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, |
4782 | OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, |
4783 | OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, |
4784 | OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, |
4785 | } OTG_TRIGB_RISING_EDGE_DETECT_CNTL; |
4786 | |
4787 | /* |
4788 | * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum |
4789 | */ |
4790 | |
4791 | typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL { |
4792 | OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, |
4793 | OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, |
4794 | OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, |
4795 | OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, |
4796 | } OTG_TRIGB_FALLING_EDGE_DETECT_CNTL; |
4797 | |
4798 | /* |
4799 | * OTG_TRIGB_FREQUENCY_SELECT enum |
4800 | */ |
4801 | |
4802 | typedef enum OTG_TRIGB_FREQUENCY_SELECT { |
4803 | OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000, |
4804 | OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001, |
4805 | OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002, |
4806 | OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003, |
4807 | } OTG_TRIGB_FREQUENCY_SELECT; |
4808 | |
4809 | /* |
4810 | * OTG_PIPE_ABORT enum |
4811 | */ |
4812 | |
4813 | typedef enum OTG_PIPE_ABORT { |
4814 | OTG_PIPE_ABORT_0 = 0x00000000, |
4815 | OTG_PIPE_ABORT_1 = 0x00000001, |
4816 | } OTG_PIPE_ABORT; |
4817 | |
4818 | /* |
4819 | * OTG_MASTER_UPDATE_LOCK_GSL_EN enum |
4820 | */ |
4821 | |
4822 | typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN { |
4823 | OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000, |
4824 | OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001, |
4825 | } OTG_MASTER_UPDATE_LOCK_GSL_EN; |
4826 | |
4827 | /* |
4828 | * OTG_PTI_CONTROL_OTG_PIT_EN enum |
4829 | */ |
4830 | |
4831 | typedef enum OTG_PTI_CONTROL_OTG_PIT_EN { |
4832 | OTG_PTI_CONTROL_OTG_PIT_EN_FALSE = 0x00000000, |
4833 | OTG_PTI_CONTROL_OTG_PIT_EN_TRUE = 0x00000001, |
4834 | } OTG_PTI_CONTROL_OTG_PIT_EN; |
4835 | |
4836 | /* |
4837 | * OTG_GSL_MASTER_MODE enum |
4838 | */ |
4839 | |
4840 | typedef enum OTG_GSL_MASTER_MODE { |
4841 | OTG_GSL_MASTER_MODE_0 = 0x00000000, |
4842 | OTG_GSL_MASTER_MODE_1 = 0x00000001, |
4843 | OTG_GSL_MASTER_MODE_2 = 0x00000002, |
4844 | OTG_GSL_MASTER_MODE_3 = 0x00000003, |
4845 | } OTG_GSL_MASTER_MODE; |
4846 | |
4847 | /******************************************************* |
4848 | * DMCUB Enums |
4849 | *******************************************************/ |
4850 | |
4851 | /* |
4852 | * DC_DMCUB_TIMER_WINDOW enum |
4853 | */ |
4854 | |
4855 | typedef enum DC_DMCUB_TIMER_WINDOW { |
4856 | BITS_31_0 = 0x00000000, |
4857 | BITS_32_1 = 0x00000001, |
4858 | BITS_33_2 = 0x00000002, |
4859 | BITS_34_3 = 0x00000003, |
4860 | BITS_35_4 = 0x00000004, |
4861 | BITS_36_5 = 0x00000005, |
4862 | BITS_37_6 = 0x00000006, |
4863 | BITS_38_7 = 0x00000007, |
4864 | } DC_DMCUB_TIMER_WINDOW; |
4865 | |
4866 | /* |
4867 | * DC_DMCUB_INT_TYPE enum |
4868 | */ |
4869 | |
4870 | typedef enum DC_DMCUB_INT_TYPE { |
4871 | INT_LEVEL = 0x00000000, |
4872 | INT_PULSE = 0x00000001, |
4873 | } DC_DMCUB_INT_TYPE; |
4874 | |
4875 | /******************************************************* |
4876 | * RBBMIF Enums |
4877 | *******************************************************/ |
4878 | |
4879 | /* |
4880 | * INVALID_REG_ACCESS_TYPE enum |
4881 | */ |
4882 | |
4883 | typedef enum INVALID_REG_ACCESS_TYPE { |
4884 | REG_UNALLOCATED_ADDR_WRITE = 0x00000000, |
4885 | REG_UNALLOCATED_ADDR_READ = 0x00000001, |
4886 | REG_VIRTUAL_WRITE = 0x00000002, |
4887 | REG_VIRTUAL_READ = 0x00000003, |
4888 | } INVALID_REG_ACCESS_TYPE; |
4889 | |
4890 | /******************************************************* |
4891 | * IHC Enums |
4892 | *******************************************************/ |
4893 | |
4894 | /* |
4895 | * DMU_DC_GPU_TIMER_START_POSITION enum |
4896 | */ |
4897 | |
4898 | typedef enum DMU_DC_GPU_TIMER_START_POSITION { |
4899 | DMU_GPU_TIMER_START_0_END_27 = 0x00000000, |
4900 | DMU_GPU_TIMER_START_1_END_28 = 0x00000001, |
4901 | DMU_GPU_TIMER_START_2_END_29 = 0x00000002, |
4902 | DMU_GPU_TIMER_START_3_END_30 = 0x00000003, |
4903 | DMU_GPU_TIMER_START_4_END_31 = 0x00000004, |
4904 | DMU_GPU_TIMER_START_6_END_33 = 0x00000005, |
4905 | DMU_GPU_TIMER_START_8_END_35 = 0x00000006, |
4906 | DMU_GPU_TIMER_START_10_END_37 = 0x00000007, |
4907 | } DMU_DC_GPU_TIMER_START_POSITION; |
4908 | |
4909 | /* |
4910 | * DMU_DC_GPU_TIMER_READ_SELECT enum |
4911 | */ |
4912 | |
4913 | typedef enum DMU_DC_GPU_TIMER_READ_SELECT { |
4914 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000, |
4915 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001, |
4916 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002, |
4917 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003, |
4918 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004, |
4919 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005, |
4920 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006, |
4921 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007, |
4922 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8 = 0x00000008, |
4923 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9 = 0x00000009, |
4924 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10 = 0x0000000a, |
4925 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11 = 0x0000000b, |
4926 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c, |
4927 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d, |
4928 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e, |
4929 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f, |
4930 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010, |
4931 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011, |
4932 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012, |
4933 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013, |
4934 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20 = 0x00000014, |
4935 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21 = 0x00000015, |
4936 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22 = 0x00000016, |
4937 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23 = 0x00000017, |
4938 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018, |
4939 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019, |
4940 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a, |
4941 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b, |
4942 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c, |
4943 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d, |
4944 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e, |
4945 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f, |
4946 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32 = 0x00000020, |
4947 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33 = 0x00000021, |
4948 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34 = 0x00000022, |
4949 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35 = 0x00000023, |
4950 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024, |
4951 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025, |
4952 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026, |
4953 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027, |
4954 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028, |
4955 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029, |
4956 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a, |
4957 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b, |
4958 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44 = 0x0000002c, |
4959 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45 = 0x0000002d, |
4960 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46 = 0x0000002e, |
4961 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47 = 0x0000002f, |
4962 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030, |
4963 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031, |
4964 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032, |
4965 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033, |
4966 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034, |
4967 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035, |
4968 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036, |
4969 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037, |
4970 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56 = 0x00000038, |
4971 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57 = 0x00000039, |
4972 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58 = 0x0000003a, |
4973 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59 = 0x0000003b, |
4974 | RESERVED_60 = 0x0000003c, |
4975 | RESERVED_61 = 0x0000003d, |
4976 | RESERVED_62 = 0x0000003e, |
4977 | RESERVED_63 = 0x0000003f, |
4978 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040, |
4979 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041, |
4980 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042, |
4981 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043, |
4982 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044, |
4983 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045, |
4984 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046, |
4985 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047, |
4986 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72 = 0x00000048, |
4987 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73 = 0x00000049, |
4988 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74 = 0x0000004a, |
4989 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75 = 0x0000004b, |
4990 | DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c, |
4991 | DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d, |
4992 | DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e, |
4993 | DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f, |
4994 | DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050, |
4995 | DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051, |
4996 | DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052, |
4997 | DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053, |
4998 | DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84 = 0x00000054, |
4999 | DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85 = 0x00000055, |
5000 | DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86 = 0x00000056, |
5001 | DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87 = 0x00000057, |
5002 | RESERVED_88 = 0x00000058, |
5003 | RESERVED_89 = 0x00000059, |
5004 | RESERVED_90 = 0x0000005a, |
5005 | RESERVED_91 = 0x0000005b, |
5006 | } DMU_DC_GPU_TIMER_READ_SELECT; |
5007 | |
5008 | /* |
5009 | * IHC_INTERRUPT_LINE_STATUS enum |
5010 | */ |
5011 | |
5012 | typedef enum IHC_INTERRUPT_LINE_STATUS { |
5013 | INTERRUPT_LINE_NOT_ASSERTED = 0x00000000, |
5014 | INTERRUPT_LINE_ASSERTED = 0x00000001, |
5015 | } IHC_INTERRUPT_LINE_STATUS; |
5016 | |
5017 | /******************************************************* |
5018 | * DMU_MISC Enums |
5019 | *******************************************************/ |
5020 | |
5021 | /* |
5022 | * DMU_CLOCK_GATING_DISABLE enum |
5023 | */ |
5024 | |
5025 | typedef enum DMU_CLOCK_GATING_DISABLE { |
5026 | DMU_ENABLE_CLOCK_GATING = 0x00000000, |
5027 | DMU_DISABLE_CLOCK_GATING = 0x00000001, |
5028 | } DMU_CLOCK_GATING_DISABLE; |
5029 | |
5030 | /* |
5031 | * DMU_CLOCK_ON enum |
5032 | */ |
5033 | |
5034 | typedef enum DMU_CLOCK_ON { |
5035 | DMU_CLOCK_STATUS_ON = 0x00000000, |
5036 | DMU_CLOCK_STATUS_OFF = 0x00000001, |
5037 | } DMU_CLOCK_ON; |
5038 | |
5039 | /* |
5040 | * DC_SMU_INTERRUPT_ENABLE enum |
5041 | */ |
5042 | |
5043 | typedef enum DC_SMU_INTERRUPT_ENABLE { |
5044 | DISABLE_THE_INTERRUPT = 0x00000000, |
5045 | ENABLE_THE_INTERRUPT = 0x00000001, |
5046 | } DC_SMU_INTERRUPT_ENABLE; |
5047 | |
5048 | /* |
5049 | * STATIC_SCREEN_SMU_INTR enum |
5050 | */ |
5051 | |
5052 | typedef enum STATIC_SCREEN_SMU_INTR { |
5053 | STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000, |
5054 | SET_STATIC_SCREEN_SMU_INTR = 0x00000001, |
5055 | } STATIC_SCREEN_SMU_INTR; |
5056 | |
5057 | /******************************************************* |
5058 | * DCCG Enums |
5059 | *******************************************************/ |
5060 | |
5061 | /* |
5062 | * ENABLE enum |
5063 | */ |
5064 | |
5065 | typedef enum ENABLE { |
5066 | DISABLE_THE_FEATURE = 0x00000000, |
5067 | ENABLE_THE_FEATURE = 0x00000001, |
5068 | } ENABLE; |
5069 | |
5070 | /* |
5071 | * DS_HW_CAL_ENABLE enum |
5072 | */ |
5073 | |
5074 | typedef enum DS_HW_CAL_ENABLE { |
5075 | DS_HW_CAL_DIS = 0x00000000, |
5076 | DS_HW_CAL_EN = 0x00000001, |
5077 | } DS_HW_CAL_ENABLE; |
5078 | |
5079 | /* |
5080 | * ENABLE_CLOCK enum |
5081 | */ |
5082 | |
5083 | typedef enum ENABLE_CLOCK { |
5084 | DISABLE_THE_CLOCK = 0x00000000, |
5085 | ENABLE_THE_CLOCK = 0x00000001, |
5086 | } ENABLE_CLOCK; |
5087 | |
5088 | /* |
5089 | * CLEAR_SMU_INTR enum |
5090 | */ |
5091 | |
5092 | typedef enum CLEAR_SMU_INTR { |
5093 | SMU_INTR_STATUS_NOOP = 0x00000000, |
5094 | SMU_INTR_STATUS_CLEAR = 0x00000001, |
5095 | } CLEAR_SMU_INTR; |
5096 | |
5097 | /* |
5098 | * JITTER_REMOVE_DISABLE enum |
5099 | */ |
5100 | |
5101 | typedef enum JITTER_REMOVE_DISABLE { |
5102 | ENABLE_JITTER_REMOVAL = 0x00000000, |
5103 | DISABLE_JITTER_REMOVAL = 0x00000001, |
5104 | } JITTER_REMOVE_DISABLE; |
5105 | |
5106 | /* |
5107 | * DS_REF_SRC enum |
5108 | */ |
5109 | |
5110 | typedef enum DS_REF_SRC { |
5111 | DS_REF_IS_XTALIN = 0x00000000, |
5112 | DS_REF_IS_EXT_GENLOCK = 0x00000001, |
5113 | DS_REF_IS_PCIE = 0x00000002, |
5114 | } DS_REF_SRC; |
5115 | |
5116 | /* |
5117 | * DISABLE_CLOCK_GATING enum |
5118 | */ |
5119 | |
5120 | typedef enum DISABLE_CLOCK_GATING { |
5121 | CLOCK_GATING_ENABLED = 0x00000000, |
5122 | CLOCK_GATING_DISABLED = 0x00000001, |
5123 | } DISABLE_CLOCK_GATING; |
5124 | |
5125 | /* |
5126 | * DISABLE_CLOCK_GATING_IN_DCO enum |
5127 | */ |
5128 | |
5129 | typedef enum DISABLE_CLOCK_GATING_IN_DCO { |
5130 | CLOCK_GATING_ENABLED_IN_DCO = 0x00000000, |
5131 | CLOCK_GATING_DISABLED_IN_DCO = 0x00000001, |
5132 | } DISABLE_CLOCK_GATING_IN_DCO; |
5133 | |
5134 | /* |
5135 | * DCCG_DEEP_COLOR_CNTL enum |
5136 | */ |
5137 | |
5138 | typedef enum DCCG_DEEP_COLOR_CNTL { |
5139 | DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000, |
5140 | DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001, |
5141 | DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002, |
5142 | DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003, |
5143 | } DCCG_DEEP_COLOR_CNTL; |
5144 | |
5145 | /* |
5146 | * REFCLK_CLOCK_EN enum |
5147 | */ |
5148 | |
5149 | typedef enum REFCLK_CLOCK_EN { |
5150 | REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000, |
5151 | REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001, |
5152 | } REFCLK_CLOCK_EN; |
5153 | |
5154 | /* |
5155 | * REFCLK_SRC_SEL enum |
5156 | */ |
5157 | |
5158 | typedef enum REFCLK_SRC_SEL { |
5159 | REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000, |
5160 | REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001, |
5161 | } REFCLK_SRC_SEL; |
5162 | |
5163 | /* |
5164 | * DPREFCLK_SRC_SEL enum |
5165 | */ |
5166 | |
5167 | typedef enum DPREFCLK_SRC_SEL { |
5168 | DPREFCLK_SRC_SEL_CK = 0x00000000, |
5169 | DPREFCLK_SRC_SEL_P0PLL = 0x00000001, |
5170 | DPREFCLK_SRC_SEL_P1PLL = 0x00000002, |
5171 | DPREFCLK_SRC_SEL_P2PLL = 0x00000003, |
5172 | } DPREFCLK_SRC_SEL; |
5173 | |
5174 | /* |
5175 | * XTAL_REF_SEL enum |
5176 | */ |
5177 | |
5178 | typedef enum XTAL_REF_SEL { |
5179 | XTAL_REF_SEL_1X = 0x00000000, |
5180 | XTAL_REF_SEL_2X = 0x00000001, |
5181 | } XTAL_REF_SEL; |
5182 | |
5183 | /* |
5184 | * XTAL_REF_CLOCK_SOURCE_SEL enum |
5185 | */ |
5186 | |
5187 | typedef enum XTAL_REF_CLOCK_SOURCE_SEL { |
5188 | XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000, |
5189 | XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001, |
5190 | } XTAL_REF_CLOCK_SOURCE_SEL; |
5191 | |
5192 | /* |
5193 | * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum |
5194 | */ |
5195 | |
5196 | typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { |
5197 | MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, |
5198 | MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, |
5199 | } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; |
5200 | |
5201 | /* |
5202 | * ALLOW_SR_ON_TRANS_REQ enum |
5203 | */ |
5204 | |
5205 | typedef enum ALLOW_SR_ON_TRANS_REQ { |
5206 | ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000, |
5207 | ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001, |
5208 | } ALLOW_SR_ON_TRANS_REQ; |
5209 | |
5210 | /* |
5211 | * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum |
5212 | */ |
5213 | |
5214 | typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { |
5215 | MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, |
5216 | MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, |
5217 | } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; |
5218 | |
5219 | /* |
5220 | * PIPE_PIXEL_RATE_SOURCE enum |
5221 | */ |
5222 | |
5223 | typedef enum PIPE_PIXEL_RATE_SOURCE { |
5224 | PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000, |
5225 | PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001, |
5226 | PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002, |
5227 | } PIPE_PIXEL_RATE_SOURCE; |
5228 | |
5229 | /* |
5230 | * TEST_CLK_DIV_SEL enum |
5231 | */ |
5232 | |
5233 | typedef enum TEST_CLK_DIV_SEL { |
5234 | NO_DIV = 0x00000000, |
5235 | DIV_2 = 0x00000001, |
5236 | DIV_4 = 0x00000002, |
5237 | DIV_8 = 0x00000003, |
5238 | } TEST_CLK_DIV_SEL; |
5239 | |
5240 | /* |
5241 | * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum |
5242 | */ |
5243 | |
5244 | typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { |
5245 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000, |
5246 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001, |
5247 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002, |
5248 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003, |
5249 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004, |
5250 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005, |
5251 | PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000006, |
5252 | } PIPE_PHYPLL_PIXEL_RATE_SOURCE; |
5253 | |
5254 | /* |
5255 | * PIPE_PIXEL_RATE_PLL_SOURCE enum |
5256 | */ |
5257 | |
5258 | typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { |
5259 | PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000, |
5260 | PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001, |
5261 | } PIPE_PIXEL_RATE_PLL_SOURCE; |
5262 | |
5263 | /* |
5264 | * DP_DTO_DS_DISABLE enum |
5265 | */ |
5266 | |
5267 | typedef enum DP_DTO_DS_DISABLE { |
5268 | DP_DTO_DESPREAD_DISABLE = 0x00000000, |
5269 | DP_DTO_DESPREAD_ENABLE = 0x00000001, |
5270 | } DP_DTO_DS_DISABLE; |
5271 | |
5272 | /* |
5273 | * OTG_ADD_PIXEL enum |
5274 | */ |
5275 | |
5276 | typedef enum OTG_ADD_PIXEL { |
5277 | OTG_ADD_PIXEL_NOOP = 0x00000000, |
5278 | OTG_ADD_PIXEL_FORCE = 0x00000001, |
5279 | } OTG_ADD_PIXEL; |
5280 | |
5281 | /* |
5282 | * OTG_DROP_PIXEL enum |
5283 | */ |
5284 | |
5285 | typedef enum OTG_DROP_PIXEL { |
5286 | OTG_DROP_PIXEL_NOOP = 0x00000000, |
5287 | OTG_DROP_PIXEL_FORCE = 0x00000001, |
5288 | } OTG_DROP_PIXEL; |
5289 | |
5290 | /* |
5291 | * SYMCLK_FE_FORCE_EN enum |
5292 | */ |
5293 | |
5294 | typedef enum SYMCLK_FE_FORCE_EN { |
5295 | SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000, |
5296 | SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001, |
5297 | } SYMCLK_FE_FORCE_EN; |
5298 | |
5299 | /* |
5300 | * SYMCLK_FE_FORCE_SRC enum |
5301 | */ |
5302 | |
5303 | typedef enum SYMCLK_FE_FORCE_SRC { |
5304 | SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000, |
5305 | SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001, |
5306 | SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002, |
5307 | SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003, |
5308 | SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004, |
5309 | SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005, |
5310 | SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000006, |
5311 | } SYMCLK_FE_FORCE_SRC; |
5312 | |
5313 | /* |
5314 | * DVOACLK_COARSE_SKEW_CNTL enum |
5315 | */ |
5316 | |
5317 | typedef enum DVOACLK_COARSE_SKEW_CNTL { |
5318 | DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, |
5319 | DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, |
5320 | DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, |
5321 | DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, |
5322 | DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004, |
5323 | DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005, |
5324 | DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006, |
5325 | DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007, |
5326 | DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008, |
5327 | DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009, |
5328 | DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a, |
5329 | DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b, |
5330 | DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c, |
5331 | DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d, |
5332 | DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e, |
5333 | DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f, |
5334 | DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010, |
5335 | DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011, |
5336 | DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012, |
5337 | DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013, |
5338 | DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014, |
5339 | DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015, |
5340 | DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016, |
5341 | DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017, |
5342 | DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018, |
5343 | DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019, |
5344 | DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a, |
5345 | DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b, |
5346 | DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c, |
5347 | DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d, |
5348 | DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e, |
5349 | } DVOACLK_COARSE_SKEW_CNTL; |
5350 | |
5351 | /* |
5352 | * DVOACLK_FINE_SKEW_CNTL enum |
5353 | */ |
5354 | |
5355 | typedef enum DVOACLK_FINE_SKEW_CNTL { |
5356 | DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, |
5357 | DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, |
5358 | DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, |
5359 | DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, |
5360 | DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004, |
5361 | DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005, |
5362 | DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006, |
5363 | DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007, |
5364 | } DVOACLK_FINE_SKEW_CNTL; |
5365 | |
5366 | /* |
5367 | * DVOACLKD_IN_PHASE enum |
5368 | */ |
5369 | |
5370 | typedef enum DVOACLKD_IN_PHASE { |
5371 | DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, |
5372 | DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001, |
5373 | } DVOACLKD_IN_PHASE; |
5374 | |
5375 | /* |
5376 | * DVOACLKC_IN_PHASE enum |
5377 | */ |
5378 | |
5379 | typedef enum DVOACLKC_IN_PHASE { |
5380 | DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, |
5381 | DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001, |
5382 | } DVOACLKC_IN_PHASE; |
5383 | |
5384 | /* |
5385 | * DVOACLKC_MVP_IN_PHASE enum |
5386 | */ |
5387 | |
5388 | typedef enum DVOACLKC_MVP_IN_PHASE { |
5389 | DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, |
5390 | DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001, |
5391 | } DVOACLKC_MVP_IN_PHASE; |
5392 | |
5393 | /* |
5394 | * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum |
5395 | */ |
5396 | |
5397 | typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { |
5398 | DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000, |
5399 | DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001, |
5400 | } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; |
5401 | |
5402 | /* |
5403 | * DCCG_AUDIO_DTO0_SOURCE_SEL enum |
5404 | */ |
5405 | |
5406 | typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { |
5407 | DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000, |
5408 | DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001, |
5409 | DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002, |
5410 | DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003, |
5411 | DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4 = 0x00000004, |
5412 | DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5 = 0x00000005, |
5413 | DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006, |
5414 | } DCCG_AUDIO_DTO0_SOURCE_SEL; |
5415 | |
5416 | /* |
5417 | * DCCG_AUDIO_DTO_SEL enum |
5418 | */ |
5419 | |
5420 | typedef enum DCCG_AUDIO_DTO_SEL { |
5421 | DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000, |
5422 | DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001, |
5423 | DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002, |
5424 | } DCCG_AUDIO_DTO_SEL; |
5425 | |
5426 | /* |
5427 | * DCCG_AUDIO_DTO2_SOURCE_SEL enum |
5428 | */ |
5429 | |
5430 | typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { |
5431 | DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000, |
5432 | DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001, |
5433 | } DCCG_AUDIO_DTO2_SOURCE_SEL; |
5434 | |
5435 | /* |
5436 | * DCCG_AUDIO_DTO_USE_512FBR_DTO enum |
5437 | */ |
5438 | |
5439 | typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { |
5440 | DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000, |
5441 | DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001, |
5442 | } DCCG_AUDIO_DTO_USE_512FBR_DTO; |
5443 | |
5444 | /* |
5445 | * DISPCLK_FREQ_RAMP_DONE enum |
5446 | */ |
5447 | |
5448 | typedef enum DISPCLK_FREQ_RAMP_DONE { |
5449 | DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000, |
5450 | DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001, |
5451 | } DISPCLK_FREQ_RAMP_DONE; |
5452 | |
5453 | /* |
5454 | * DCCG_FIFO_ERRDET_RESET enum |
5455 | */ |
5456 | |
5457 | typedef enum DCCG_FIFO_ERRDET_RESET { |
5458 | DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000, |
5459 | DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001, |
5460 | } DCCG_FIFO_ERRDET_RESET; |
5461 | |
5462 | /* |
5463 | * DCCG_FIFO_ERRDET_STATE enum |
5464 | */ |
5465 | |
5466 | typedef enum DCCG_FIFO_ERRDET_STATE { |
5467 | DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000, |
5468 | DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001, |
5469 | } DCCG_FIFO_ERRDET_STATE; |
5470 | |
5471 | /* |
5472 | * DCCG_FIFO_ERRDET_OVR_EN enum |
5473 | */ |
5474 | |
5475 | typedef enum DCCG_FIFO_ERRDET_OVR_EN { |
5476 | DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000, |
5477 | DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001, |
5478 | } DCCG_FIFO_ERRDET_OVR_EN; |
5479 | |
5480 | /* |
5481 | * DISPCLK_CHG_FWD_CORR_DISABLE enum |
5482 | */ |
5483 | |
5484 | typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { |
5485 | DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000, |
5486 | DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001, |
5487 | } DISPCLK_CHG_FWD_CORR_DISABLE; |
5488 | |
5489 | /* |
5490 | * DC_MEM_GLOBAL_PWR_REQ_DIS enum |
5491 | */ |
5492 | |
5493 | typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { |
5494 | DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000, |
5495 | DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001, |
5496 | } DC_MEM_GLOBAL_PWR_REQ_DIS; |
5497 | |
5498 | /* |
5499 | * DCCG_PERF_RUN enum |
5500 | */ |
5501 | |
5502 | typedef enum DCCG_PERF_RUN { |
5503 | DCCG_PERF_RUN_NOOP = 0x00000000, |
5504 | DCCG_PERF_RUN_START = 0x00000001, |
5505 | } DCCG_PERF_RUN; |
5506 | |
5507 | /* |
5508 | * DCCG_PERF_MODE_VSYNC enum |
5509 | */ |
5510 | |
5511 | typedef enum DCCG_PERF_MODE_VSYNC { |
5512 | DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000, |
5513 | DCCG_PERF_MODE_VSYNC_START = 0x00000001, |
5514 | } DCCG_PERF_MODE_VSYNC; |
5515 | |
5516 | /* |
5517 | * DCCG_PERF_MODE_HSYNC enum |
5518 | */ |
5519 | |
5520 | typedef enum DCCG_PERF_MODE_HSYNC { |
5521 | DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000, |
5522 | DCCG_PERF_MODE_HSYNC_START = 0x00000001, |
5523 | } DCCG_PERF_MODE_HSYNC; |
5524 | |
5525 | /* |
5526 | * DCCG_PERF_OTG_SELECT enum |
5527 | */ |
5528 | |
5529 | typedef enum DCCG_PERF_OTG_SELECT { |
5530 | DCCG_PERF_SEL_OTG0 = 0x00000000, |
5531 | DCCG_PERF_SEL_OTG1 = 0x00000001, |
5532 | DCCG_PERF_SEL_OTG2 = 0x00000002, |
5533 | DCCG_PERF_SEL_OTG3 = 0x00000003, |
5534 | DCCG_PERF_SEL_OTG4 = 0x00000004, |
5535 | DCCG_PERF_SEL_OTG5 = 0x00000005, |
5536 | DCCG_PERF_SEL_RESERVED = 0x00000006, |
5537 | } DCCG_PERF_OTG_SELECT; |
5538 | |
5539 | /* |
5540 | * CLOCK_BRANCH_SOFT_RESET enum |
5541 | */ |
5542 | |
5543 | typedef enum CLOCK_BRANCH_SOFT_RESET { |
5544 | CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000, |
5545 | CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001, |
5546 | } CLOCK_BRANCH_SOFT_RESET; |
5547 | |
5548 | /* |
5549 | * PLL_CFG_IF_SOFT_RESET enum |
5550 | */ |
5551 | |
5552 | typedef enum PLL_CFG_IF_SOFT_RESET { |
5553 | PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000, |
5554 | PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001, |
5555 | } PLL_CFG_IF_SOFT_RESET; |
5556 | |
5557 | /* |
5558 | * DVO_ENABLE_RST enum |
5559 | */ |
5560 | |
5561 | typedef enum DVO_ENABLE_RST { |
5562 | DVO_ENABLE_RST_DISABLE = 0x00000000, |
5563 | DVO_ENABLE_RST_ENABLE = 0x00000001, |
5564 | } DVO_ENABLE_RST; |
5565 | |
5566 | /* |
5567 | * DS_JITTER_COUNT_SRC_SEL enum |
5568 | */ |
5569 | |
5570 | typedef enum DS_JITTER_COUNT_SRC_SEL { |
5571 | DS_JITTER_COUNT_SRC_SEL0 = 0x00000000, |
5572 | DS_JITTER_COUNT_SRC_SEL1 = 0x00000001, |
5573 | } DS_JITTER_COUNT_SRC_SEL; |
5574 | |
5575 | /* |
5576 | * DIO_FIFO_ERROR enum |
5577 | */ |
5578 | |
5579 | typedef enum DIO_FIFO_ERROR { |
5580 | DIO_FIFO_ERROR_00 = 0x00000000, |
5581 | DIO_FIFO_ERROR_01 = 0x00000001, |
5582 | DIO_FIFO_ERROR_10 = 0x00000002, |
5583 | DIO_FIFO_ERROR_11 = 0x00000003, |
5584 | } DIO_FIFO_ERROR; |
5585 | |
5586 | /* |
5587 | * VSYNC_CNT_REFCLK_SEL enum |
5588 | */ |
5589 | |
5590 | typedef enum VSYNC_CNT_REFCLK_SEL { |
5591 | VSYNC_CNT_REFCLK_SEL_0 = 0x00000000, |
5592 | VSYNC_CNT_REFCLK_SEL_1 = 0x00000001, |
5593 | } VSYNC_CNT_REFCLK_SEL; |
5594 | |
5595 | /* |
5596 | * VSYNC_CNT_RESET_SEL enum |
5597 | */ |
5598 | |
5599 | typedef enum VSYNC_CNT_RESET_SEL { |
5600 | VSYNC_CNT_RESET_SEL_0 = 0x00000000, |
5601 | VSYNC_CNT_RESET_SEL_1 = 0x00000001, |
5602 | } VSYNC_CNT_RESET_SEL; |
5603 | |
5604 | /* |
5605 | * VSYNC_CNT_LATCH_MASK enum |
5606 | */ |
5607 | |
5608 | typedef enum VSYNC_CNT_LATCH_MASK { |
5609 | VSYNC_CNT_LATCH_MASK_0 = 0x00000000, |
5610 | VSYNC_CNT_LATCH_MASK_1 = 0x00000001, |
5611 | } VSYNC_CNT_LATCH_MASK; |
5612 | |
5613 | /******************************************************* |
5614 | * HPD Enums |
5615 | *******************************************************/ |
5616 | |
5617 | /* |
5618 | * HPD_INT_CONTROL_ACK enum |
5619 | */ |
5620 | |
5621 | typedef enum HPD_INT_CONTROL_ACK { |
5622 | HPD_INT_CONTROL_ACK_0 = 0x00000000, |
5623 | HPD_INT_CONTROL_ACK_1 = 0x00000001, |
5624 | } HPD_INT_CONTROL_ACK; |
5625 | |
5626 | /* |
5627 | * HPD_INT_CONTROL_POLARITY enum |
5628 | */ |
5629 | |
5630 | typedef enum HPD_INT_CONTROL_POLARITY { |
5631 | HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000, |
5632 | HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001, |
5633 | } HPD_INT_CONTROL_POLARITY; |
5634 | |
5635 | /* |
5636 | * HPD_INT_CONTROL_RX_INT_ACK enum |
5637 | */ |
5638 | |
5639 | typedef enum HPD_INT_CONTROL_RX_INT_ACK { |
5640 | HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000, |
5641 | HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001, |
5642 | } HPD_INT_CONTROL_RX_INT_ACK; |
5643 | |
5644 | /******************************************************* |
5645 | * DP Enums |
5646 | *******************************************************/ |
5647 | |
5648 | /* |
5649 | * DP_MSO_NUM_OF_SST_LINKS enum |
5650 | */ |
5651 | |
5652 | typedef enum DP_MSO_NUM_OF_SST_LINKS { |
5653 | DP_MSO_ONE_SSTLINK = 0x00000000, |
5654 | DP_MSO_TWO_SSTLINK = 0x00000001, |
5655 | DP_MSO_FOUR_SSTLINK = 0x00000002, |
5656 | } DP_MSO_NUM_OF_SST_LINKS; |
5657 | |
5658 | /* |
5659 | * DP_SYNC_POLARITY enum |
5660 | */ |
5661 | |
5662 | typedef enum DP_SYNC_POLARITY { |
5663 | DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000, |
5664 | DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001, |
5665 | } DP_SYNC_POLARITY; |
5666 | |
5667 | /* |
5668 | * DP_COMBINE_PIXEL_NUM enum |
5669 | */ |
5670 | |
5671 | typedef enum DP_COMBINE_PIXEL_NUM { |
5672 | DP_COMBINE_ONE_PIXEL = 0x00000000, |
5673 | DP_COMBINE_TWO_PIXEL = 0x00000001, |
5674 | DP_COMBINE_FOUR_PIXEL = 0x00000002, |
5675 | } DP_COMBINE_PIXEL_NUM; |
5676 | |
5677 | /* |
5678 | * DP_LINK_TRAINING_COMPLETE enum |
5679 | */ |
5680 | |
5681 | typedef enum DP_LINK_TRAINING_COMPLETE { |
5682 | DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000, |
5683 | DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001, |
5684 | } DP_LINK_TRAINING_COMPLETE; |
5685 | |
5686 | /* |
5687 | * DP_EMBEDDED_PANEL_MODE enum |
5688 | */ |
5689 | |
5690 | typedef enum DP_EMBEDDED_PANEL_MODE { |
5691 | DP_EXTERNAL_PANEL = 0x00000000, |
5692 | DP_EMBEDDED_PANEL = 0x00000001, |
5693 | } DP_EMBEDDED_PANEL_MODE; |
5694 | |
5695 | /* |
5696 | * DP_PIXEL_ENCODING enum |
5697 | */ |
5698 | |
5699 | typedef enum DP_PIXEL_ENCODING { |
5700 | DP_PIXEL_ENCODING_RGB444 = 0x00000000, |
5701 | DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, |
5702 | DP_PIXEL_ENCODING_YCBCR444 = 0x00000002, |
5703 | DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003, |
5704 | DP_PIXEL_ENCODING_Y_ONLY = 0x00000004, |
5705 | DP_PIXEL_ENCODING_YCBCR420 = 0x00000005, |
5706 | DP_PIXEL_ENCODING_RESERVED = 0x00000006, |
5707 | } DP_PIXEL_ENCODING; |
5708 | |
5709 | /* |
5710 | * DP_COMPONENT_DEPTH enum |
5711 | */ |
5712 | |
5713 | typedef enum DP_COMPONENT_DEPTH { |
5714 | DP_COMPONENT_DEPTH_6BPC = 0x00000000, |
5715 | DP_COMPONENT_DEPTH_8BPC = 0x00000001, |
5716 | DP_COMPONENT_DEPTH_10BPC = 0x00000002, |
5717 | DP_COMPONENT_DEPTH_12BPC = 0x00000003, |
5718 | DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004, |
5719 | DP_COMPONENT_DEPTH_RESERVED = 0x00000005, |
5720 | } DP_COMPONENT_DEPTH; |
5721 | |
5722 | /* |
5723 | * DP_UDI_LANES enum |
5724 | */ |
5725 | |
5726 | typedef enum DP_UDI_LANES { |
5727 | DP_UDI_1_LANE = 0x00000000, |
5728 | DP_UDI_2_LANES = 0x00000001, |
5729 | DP_UDI_LANES_RESERVED = 0x00000002, |
5730 | DP_UDI_4_LANES = 0x00000003, |
5731 | } DP_UDI_LANES; |
5732 | |
5733 | /* |
5734 | * DP_VID_STREAM_DIS_DEFER enum |
5735 | */ |
5736 | |
5737 | typedef enum DP_VID_STREAM_DIS_DEFER { |
5738 | DP_VID_STREAM_DIS_NO_DEFER = 0x00000000, |
5739 | DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001, |
5740 | DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002, |
5741 | } DP_VID_STREAM_DIS_DEFER; |
5742 | |
5743 | /* |
5744 | * DP_STEER_OVERFLOW_ACK enum |
5745 | */ |
5746 | |
5747 | typedef enum DP_STEER_OVERFLOW_ACK { |
5748 | DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000, |
5749 | DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, |
5750 | } DP_STEER_OVERFLOW_ACK; |
5751 | |
5752 | /* |
5753 | * DP_STEER_OVERFLOW_MASK enum |
5754 | */ |
5755 | |
5756 | typedef enum DP_STEER_OVERFLOW_MASK { |
5757 | DP_STEER_OVERFLOW_MASKED = 0x00000000, |
5758 | DP_STEER_OVERFLOW_UNMASK = 0x00000001, |
5759 | } DP_STEER_OVERFLOW_MASK; |
5760 | |
5761 | /* |
5762 | * DP_TU_OVERFLOW_ACK enum |
5763 | */ |
5764 | |
5765 | typedef enum DP_TU_OVERFLOW_ACK { |
5766 | DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000, |
5767 | DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, |
5768 | } DP_TU_OVERFLOW_ACK; |
5769 | |
5770 | /* |
5771 | * DP_VID_M_N_DOUBLE_BUFFER_MODE enum |
5772 | */ |
5773 | |
5774 | typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { |
5775 | DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000, |
5776 | DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001, |
5777 | } DP_VID_M_N_DOUBLE_BUFFER_MODE; |
5778 | |
5779 | /* |
5780 | * DP_VID_M_N_GEN_EN enum |
5781 | */ |
5782 | |
5783 | typedef enum DP_VID_M_N_GEN_EN { |
5784 | DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000, |
5785 | DP_VID_M_N_CALC_AUTO = 0x00000001, |
5786 | } DP_VID_M_N_GEN_EN; |
5787 | |
5788 | /* |
5789 | * DP_VID_N_MUL enum |
5790 | */ |
5791 | |
5792 | typedef enum DP_VID_N_MUL { |
5793 | DP_VID_M_1X_INPUT_PIXEL_RATE = 0x00000000, |
5794 | DP_VID_M_2X_INPUT_PIXEL_RATE = 0x00000001, |
5795 | DP_VID_M_4X_INPUT_PIXEL_RATE = 0x00000002, |
5796 | DP_VID_M_8X_INPUT_PIXEL_RATE = 0x00000003, |
5797 | } DP_VID_N_MUL; |
5798 | |
5799 | /* |
5800 | * DP_VID_ENHANCED_FRAME_MODE enum |
5801 | */ |
5802 | |
5803 | typedef enum DP_VID_ENHANCED_FRAME_MODE { |
5804 | VID_NORMAL_FRAME_MODE = 0x00000000, |
5805 | VID_ENHANCED_MODE = 0x00000001, |
5806 | } DP_VID_ENHANCED_FRAME_MODE; |
5807 | |
5808 | /* |
5809 | * DP_VID_VBID_FIELD_POL enum |
5810 | */ |
5811 | |
5812 | typedef enum DP_VID_VBID_FIELD_POL { |
5813 | DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000, |
5814 | DP_VID_VBID_FIELD_POL_INV = 0x00000001, |
5815 | } DP_VID_VBID_FIELD_POL; |
5816 | |
5817 | /* |
5818 | * DP_VID_STREAM_DISABLE_ACK enum |
5819 | */ |
5820 | |
5821 | typedef enum DP_VID_STREAM_DISABLE_ACK { |
5822 | ID_STREAM_DISABLE_NO_ACK = 0x00000000, |
5823 | ID_STREAM_DISABLE_ACKED = 0x00000001, |
5824 | } DP_VID_STREAM_DISABLE_ACK; |
5825 | |
5826 | /* |
5827 | * DP_VID_STREAM_DISABLE_MASK enum |
5828 | */ |
5829 | |
5830 | typedef enum DP_VID_STREAM_DISABLE_MASK { |
5831 | VID_STREAM_DISABLE_MASKED = 0x00000000, |
5832 | VID_STREAM_DISABLE_UNMASK = 0x00000001, |
5833 | } DP_VID_STREAM_DISABLE_MASK; |
5834 | |
5835 | /* |
5836 | * DPHY_ATEST_SEL_LANE0 enum |
5837 | */ |
5838 | |
5839 | typedef enum DPHY_ATEST_SEL_LANE0 { |
5840 | DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000, |
5841 | DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001, |
5842 | } DPHY_ATEST_SEL_LANE0; |
5843 | |
5844 | /* |
5845 | * DPHY_ATEST_SEL_LANE1 enum |
5846 | */ |
5847 | |
5848 | typedef enum DPHY_ATEST_SEL_LANE1 { |
5849 | DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000, |
5850 | DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001, |
5851 | } DPHY_ATEST_SEL_LANE1; |
5852 | |
5853 | /* |
5854 | * DPHY_ATEST_SEL_LANE2 enum |
5855 | */ |
5856 | |
5857 | typedef enum DPHY_ATEST_SEL_LANE2 { |
5858 | DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000, |
5859 | DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001, |
5860 | } DPHY_ATEST_SEL_LANE2; |
5861 | |
5862 | /* |
5863 | * DPHY_ATEST_SEL_LANE3 enum |
5864 | */ |
5865 | |
5866 | typedef enum DPHY_ATEST_SEL_LANE3 { |
5867 | DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000, |
5868 | DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001, |
5869 | } DPHY_ATEST_SEL_LANE3; |
5870 | |
5871 | /* |
5872 | * DPHY_BYPASS enum |
5873 | */ |
5874 | |
5875 | typedef enum DPHY_BYPASS { |
5876 | DPHY_8B10B_OUTPUT = 0x00000000, |
5877 | DPHY_DBG_OUTPUT = 0x00000001, |
5878 | } DPHY_BYPASS; |
5879 | |
5880 | /* |
5881 | * DPHY_SKEW_BYPASS enum |
5882 | */ |
5883 | |
5884 | typedef enum DPHY_SKEW_BYPASS { |
5885 | DPHY_WITH_SKEW = 0x00000000, |
5886 | DPHY_NO_SKEW = 0x00000001, |
5887 | } DPHY_SKEW_BYPASS; |
5888 | |
5889 | /* |
5890 | * DPHY_TRAINING_PATTERN_SEL enum |
5891 | */ |
5892 | |
5893 | typedef enum DPHY_TRAINING_PATTERN_SEL { |
5894 | DPHY_TRAINING_PATTERN_1 = 0x00000000, |
5895 | DPHY_TRAINING_PATTERN_2 = 0x00000001, |
5896 | DPHY_TRAINING_PATTERN_3 = 0x00000002, |
5897 | DPHY_TRAINING_PATTERN_4 = 0x00000003, |
5898 | } |
---|